diff options
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp')
3 files changed, 93 insertions, 21 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index a47e5e15d..f048ede7e 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -460,9 +460,8 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[0] [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -483,9 +482,8 @@ zero=false port=system.membus.master[0] [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index ab456df4c..7edc0f615 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:05 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:23 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index e871b4c6b..a670e1cab 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,22 +4,59 @@ sim_seconds 0.000088 # Nu sim_ticks 87713500 # Number of ticks simulated final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 523852 # Simulator instruction rate (inst/s) -host_op_rate 523839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67834135 # Simulator tick rate (ticks/s) -host_mem_usage 1149444 # Number of bytes of host memory used -host_seconds 1.29 # Real time elapsed on the host +host_inst_rate 1597903 # Simulator instruction rate (inst/s) +host_op_rate 1597833 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 206906108 # Simulator tick rate (ticks/s) +host_mem_usage 1149840 # Number of bytes of host memory used +host_seconds 0.42 # Real time elapsed on the host sim_insts 677340 # Number of instructions simulated sim_ops 677340 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 35776 # Number of bytes read from this memory -system.physmem.bytes_inst_read 22272 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 559 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 407873360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 253917584 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 407873360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::total 35776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::total 559 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 205760801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 120391958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 45238190 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 14592965 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1459296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 9485427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1459296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 9485427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 407873360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205760801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 45238190 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1459296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1459296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 253917584 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205760801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 120391958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 45238190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 14592965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1459296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 9485427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1459296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 9485427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 407873360 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 175428 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started @@ -71,8 +108,11 @@ system.cpu0.icache.demand_accesses::total 175401 # n system.cpu0.icache.overall_accesses::cpu0.inst 175401 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002662 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002662 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002662 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -122,10 +162,15 @@ system.cpu0.dcache.demand_accesses::total 82337 # n system.cpu0.dcache.overall_accesses::cpu0.data 82337 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 82337 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002766 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.002766 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,8 +232,11 @@ system.cpu1.icache.demand_accesses::total 167430 # n system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -238,10 +286,15 @@ system.cpu1.dcache.demand_accesses::total 53313 # n system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004330 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004330 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005290 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005290 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,8 +356,11 @@ system.cpu2.icache.demand_accesses::total 167366 # n system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,10 +410,15 @@ system.cpu2.dcache.demand_accesses::total 58461 # n system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003825 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003825 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004636 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004636 # miss rate for overall accesses system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,8 +480,11 @@ system.cpu3.icache.demand_accesses::total 167301 # n system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,10 +534,15 @@ system.cpu3.dcache.demand_accesses::total 55820 # n system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003835 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003835 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004676 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004676 # miss rate for overall accesses system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -625,14 +694,17 @@ system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # mi system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.256519 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.977528 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses @@ -641,6 +713,7 @@ system.l2c.demand_miss_rate::cpu2.inst 0.005587 # mi system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.313165 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses @@ -649,6 +722,7 @@ system.l2c.overall_miss_rate::cpu2.inst 0.005587 # mi system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.313165 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked |