diff options
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini')
-rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini | 53 |
1 files changed, 28 insertions, 25 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index c00589f53..7658e05d6 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[1] +system_port=system.membus.slave[1] [system.cpu0] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=4 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.port[2] +mem_side=system.toL2Bus.slave[1] [system.cpu0.dtb] type=SparcTLB @@ -88,7 +87,7 @@ size=64 [system.cpu0.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=1 block_size=64 forward_snoops=true @@ -109,7 +108,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.port[1] +mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=SparcInterrupts @@ -171,7 +170,7 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=4 block_size=64 forward_snoops=true @@ -192,7 +191,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.port[4] +mem_side=system.toL2Bus.slave[3] [system.cpu1.dtb] type=SparcTLB @@ -200,7 +199,7 @@ size=64 [system.cpu1.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=1 block_size=64 forward_snoops=true @@ -221,7 +220,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.port[3] +mem_side=system.toL2Bus.slave[2] [system.cpu1.interrupts] type=SparcInterrupts @@ -264,7 +263,7 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=4 block_size=64 forward_snoops=true @@ -285,7 +284,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port -mem_side=system.toL2Bus.port[6] +mem_side=system.toL2Bus.slave[5] [system.cpu2.dtb] type=SparcTLB @@ -293,7 +292,7 @@ size=64 [system.cpu2.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=1 block_size=64 forward_snoops=true @@ -314,7 +313,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port -mem_side=system.toL2Bus.port[5] +mem_side=system.toL2Bus.slave[4] [system.cpu2.interrupts] type=SparcInterrupts @@ -357,7 +356,7 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=4 block_size=64 forward_snoops=true @@ -378,7 +377,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port -mem_side=system.toL2Bus.port[8] +mem_side=system.toL2Bus.slave[7] [system.cpu3.dtb] type=SparcTLB @@ -386,7 +385,7 @@ size=64 [system.cpu3.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=1 block_size=64 forward_snoops=true @@ -407,7 +406,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port -mem_side=system.toL2Bus.port[7] +mem_side=system.toL2Bus.slave[6] [system.cpu3.interrupts] type=SparcInterrupts @@ -421,7 +420,7 @@ type=ExeTracer [system.l2c] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=8 block_size=64 forward_snoops=true @@ -441,8 +440,8 @@ tgts_per_mshr=16 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.toL2Bus.port[0] -mem_side=system.membus.port[0] +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[0] [system.membus] type=Bus @@ -452,17 +451,20 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.l2c.mem_side system.system_port system.physmem.port[0] +master=system.physmem.port[0] +slave=system.l2c.mem_side system.system_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[2] +port=system.membus.master[0] [system.toL2Bus] type=Bus @@ -472,5 +474,6 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side |