diff options
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt')
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt | 1242 |
1 files changed, 614 insertions, 628 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 36b8c656f..c654a221f 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000262 # Number of seconds simulated -sim_ticks 262298000 # Number of ticks simulated -final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 262299000 # Number of ticks simulated +final_tick 262299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1070900 # Simulator instruction rate (inst/s) -host_op_rate 1070867 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 424091073 # Simulator tick rate (ticks/s) -host_mem_usage 232420 # Number of bytes of host memory used -host_seconds 0.62 # Real time elapsed on the host -sim_insts 662307 # Number of instructions simulated -sim_ops 662307 # Number of ops (including micro ops) simulated +host_inst_rate 1271827 # Simulator instruction rate (inst/s) +host_op_rate 1271784 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 503510999 # Simulator tick rate (ticks/s) +host_mem_usage 230932 # Number of bytes of host memory used +host_seconds 0.52 # Real time elapsed on the host +sim_insts 662502 # Number of instructions simulated +sim_ops 662502 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory @@ -34,31 +34,31 @@ system.physmem.num_reads::cpu2.data 16 # Nu system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69539226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40259552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14395840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5367940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2195976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3903957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 243997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3659959 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139566447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69539226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14395840 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2195976 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 243997 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86375039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69539226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40259552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14395840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5367940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2195976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3903957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 243997 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3659959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139566447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69538961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40259399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14395785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5367920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2195967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3903942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 243996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3659945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139565915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69538961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14395785 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2195967 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 243996 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86374710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69538961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40259399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14395785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5367920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2195967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3903942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 243996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3659945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139565915 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 524596 # number of cpu cycles simulated +system.cpu0.numCycles 524598 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 158353 # Number of instructions committed @@ -77,18 +77,18 @@ system.cpu0.num_mem_refs 73905 # nu system.cpu0.num_load_insts 48930 # Number of load instructions system.cpu0.num_store_insts 24975 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 524596 # Number of busy cycles +system.cpu0.num_busy_cycles 524598 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.479188 # Cycle average of tags in use +system.cpu0.icache.tagsinuse 212.479251 # Cycle average of tags in use system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.479188 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414998 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414998 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 212.479251 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414999 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414999 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits @@ -158,15 +158,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 36665.952891 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use -system.cpu0.dcache.total_refs 56009 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 2 # number of replacements +system.cpu0.dcache.tagsinuse 145.603716 # Cycle average of tags in use +system.cpu0.dcache.total_refs 73381 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 439.407186 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 141.233342 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.275846 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.275846 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 145.603716 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284382 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284382 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits @@ -187,16 +187,16 @@ system.cpu0.dcache.demand_misses::cpu0.data 345 # system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses system.cpu0.dcache.overall_misses::total 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4749000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4749000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7175000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7175000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 387000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 387000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11924000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11924000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11924000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11924000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4747000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4747000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7176000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7176000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 389000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 389000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11923000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11923000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11923000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11923000 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses) @@ -217,16 +217,16 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 system.cpu0.dcache.demand_miss_rate::total 0.004672 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.004672 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 29314.814815 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39207.650273 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 14884.615385 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34562.318841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34562.318841 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29302.469136 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 29302.469136 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39213.114754 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39213.114754 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14961.538462 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 14961.538462 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34559.420290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34559.420290 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,8 +235,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks -system.cpu0.dcache.writebacks::total 6 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses @@ -247,16 +247,16 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4263000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4263000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6626000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 309000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 309000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10889000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10889000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10889000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4261000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4261000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6627000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6627000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10888000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10888000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10888000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10888000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003312 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses @@ -267,84 +267,84 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 system.cpu0.dcache.demand_mshr_miss_rate::total 0.004672 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.004672 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26314.814815 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36207.650273 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11884.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26302.469136 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26302.469136 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36213.114754 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36213.114754 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11961.538462 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11961.538462 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 524596 # number of cpu cycles simulated +system.cpu1.numCycles 524598 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 172325 # Number of instructions committed -system.cpu1.committedOps 172325 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses +system.cpu1.committedInsts 172389 # Number of instructions committed +system.cpu1.committedOps 172389 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 107964 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 36203 # number of instructions that are conditional controls -system.cpu1.num_int_insts 107932 # number of integer instructions +system.cpu1.num_conditional_control_insts 36219 # number of instructions that are conditional controls +system.cpu1.num_int_insts 107964 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 249091 # number of times the integer registers were read -system.cpu1.num_int_register_writes 92744 # number of times the integer registers were written +system.cpu1.num_int_register_reads 249169 # number of times the integer registers were read +system.cpu1.num_int_register_writes 92792 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 47898 # number of memory refs -system.cpu1.num_load_insts 39616 # Number of load instructions +system.cpu1.num_mem_refs 47914 # number of memory refs +system.cpu1.num_load_insts 39632 # Number of load instructions system.cpu1.num_store_insts 8282 # Number of store instructions -system.cpu1.num_idle_cycles 68578.001739 # Number of idle cycles -system.cpu1.num_busy_cycles 456017.998261 # Number of busy cycles -system.cpu1.not_idle_fraction 0.869275 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.130725 # Percentage of idle cycles +system.cpu1.num_idle_cycles 68732.001738 # Number of idle cycles +system.cpu1.num_busy_cycles 455865.998262 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868982 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131018 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 70.076133 # Cycle average of tags in use -system.cpu1.icache.total_refs 171992 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 70.077944 # Cycle average of tags in use +system.cpu1.icache.total_refs 172056 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 469.923497 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 470.098361 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 70.076133 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136867 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136867 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 171992 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 171992 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 171992 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 171992 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 171992 # number of overall hits -system.cpu1.icache.overall_hits::total 171992 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 70.077944 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.136871 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.136871 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 172056 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 172056 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 172056 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 172056 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 172056 # number of overall hits +system.cpu1.icache.overall_hits::total 172056 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7920500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7920500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7920500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7920500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7920500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7920500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 172358 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 172358 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 172358 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 172358 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 172358 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 172358 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7921500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7921500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7921500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7921500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7921500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7921500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 172422 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 172422 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 172422 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 172422 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 172422 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 172422 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.002123 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.002123 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.002123 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21640.710383 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21640.710383 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21640.710383 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21643.442623 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 21643.442623 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 21643.442623 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 21643.442623 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,94 +359,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6822000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6822000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6822000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6822000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6822000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6822000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6823000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6823000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6823000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6823000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6823000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6823000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002123 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.002123 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.002123 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18639.344262 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18639.344262 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18639.344262 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18642.076503 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 26.693562 # Cycle average of tags in use -system.cpu1.dcache.total_refs 18908 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 609.935484 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 0 # number of replacements +system.cpu1.dcache.tagsinuse 27.731444 # Cycle average of tags in use +system.cpu1.dcache.total_refs 18765 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 647.068966 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 26.693562 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.052136 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.052136 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 39428 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39428 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 27.731444 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.054163 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.054163 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 39445 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 39445 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 8099 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 8099 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 18 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 18 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 47527 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 47527 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 47527 # number of overall hits -system.cpu1.dcache.overall_hits::total 47527 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 181 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 181 # number of ReadReq misses +system.cpu1.dcache.demand_hits::cpu1.data 47544 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 47544 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 47544 # number of overall hits +system.cpu1.dcache.overall_hits::total 47544 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 179 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 179 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 98 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 98 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 279 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 279 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 279 # number of overall misses -system.cpu1.dcache.overall_misses::total 279 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3713000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3713000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1889000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1889000 # number of WriteReq miss cycles +system.cpu1.dcache.demand_misses::cpu1.data 277 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 277 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 277 # number of overall misses +system.cpu1.dcache.overall_misses::total 277 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3683000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3683000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1838000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1838000 # number of WriteReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 415000 # number of SwapReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::total 415000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5602000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5602000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5602000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5602000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 39609 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 39609 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.demand_miss_latency::cpu1.data 5521000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5521000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5521000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5521000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 39624 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 39624 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 8197 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 47806 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 47806 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 47806 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 47806 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004570 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004570 # miss rate for ReadReq accesses +system.cpu1.dcache.demand_accesses::cpu1.data 47821 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 47821 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 47821 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 47821 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004517 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004517 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.011956 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_miss_rate::total 0.783133 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005836 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005836 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005836 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005836 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20513.812155 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19275.510204 # average WriteReq miss latency +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005792 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005792 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005792 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005792 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20575.418994 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20575.418994 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18755.102041 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18755.102041 # average WriteReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::total 6384.615385 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20078.853047 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20078.853047 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19931.407942 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19931.407942 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -455,86 +455,84 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu1.dcache.writebacks::total 1 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 179 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3170000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3170000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1595000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1595000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_misses::cpu1.data 277 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 277 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3146000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3146000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1544000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1544000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4765000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004570 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4690000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4690000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4690000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4690000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004517 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004517 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.011956 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.783133 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005836 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005836 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17513.812155 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16275.510204 # average WriteReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005792 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005792 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17575.418994 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17575.418994 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15755.102041 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15755.102041 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3384.615385 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 524596 # number of cpu cycles simulated +system.cpu2.numCycles 524598 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165499 # Number of instructions committed -system.cpu2.committedOps 165499 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses +system.cpu2.committedInsts 165564 # Number of instructions committed +system.cpu2.committedOps 165564 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 112387 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 30582 # number of instructions that are conditional controls -system.cpu2.num_int_insts 112355 # number of integer instructions +system.cpu2.num_conditional_control_insts 30599 # number of instructions that are conditional controls +system.cpu2.num_int_insts 112387 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 289268 # number of times the integer registers were read -system.cpu2.num_int_register_writes 110631 # number of times the integer registers were written +system.cpu2.num_int_register_reads 289349 # number of times the integer registers were read +system.cpu2.num_int_register_writes 110679 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 57941 # number of memory refs -system.cpu2.num_load_insts 41852 # Number of load instructions +system.cpu2.num_mem_refs 57957 # number of memory refs +system.cpu2.num_load_insts 41868 # Number of load instructions system.cpu2.num_store_insts 16089 # Number of store instructions -system.cpu2.num_idle_cycles 68840.001738 # Number of idle cycles -system.cpu2.num_busy_cycles 455755.998262 # Number of busy cycles -system.cpu2.not_idle_fraction 0.868775 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.131225 # Percentage of idle cycles +system.cpu2.num_idle_cycles 68998.001737 # Number of idle cycles +system.cpu2.num_busy_cycles 455599.998263 # Number of busy cycles +system.cpu2.not_idle_fraction 0.868475 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.131525 # Percentage of idle cycles system.cpu2.icache.replacements 280 # number of replacements -system.cpu2.icache.tagsinuse 65.601019 # Cycle average of tags in use -system.cpu2.icache.total_refs 165166 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 65.602896 # Cycle average of tags in use +system.cpu2.icache.total_refs 165231 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 451.273224 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 451.450820 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 65.601019 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.128127 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.128127 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 165166 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 165166 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 165166 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 165166 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 165166 # number of overall hits -system.cpu2.icache.overall_hits::total 165166 # number of overall hits +system.cpu2.icache.occ_blocks::cpu2.inst 65.602896 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.128131 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.128131 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 165231 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 165231 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 165231 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 165231 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 165231 # number of overall hits +system.cpu2.icache.overall_hits::total 165231 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses @@ -547,18 +545,18 @@ system.cpu2.icache.demand_miss_latency::cpu2.inst 5648500 system.cpu2.icache.demand_miss_latency::total 5648500 # number of demand (read+write) miss cycles system.cpu2.icache.overall_miss_latency::cpu2.inst 5648500 # number of overall miss cycles system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165532 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165532 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165532 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165532 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165532 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165532 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002211 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002211 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002211 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002211 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002211 # miss rate for overall accesses +system.cpu2.icache.ReadReq_accesses::cpu2.inst 165597 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 165597 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 165597 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 165597 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 165597 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 165597 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002210 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002210 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002210 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency system.cpu2.icache.ReadReq_avg_miss_latency::total 15433.060109 # average ReadReq miss latency system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency @@ -585,12 +583,12 @@ system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002211 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002211 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002211 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12433.060109 # average ReadReq mshr miss latency system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency @@ -598,75 +596,75 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 12433.060109 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 24.943438 # Cycle average of tags in use -system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1115.419355 # Average number of references to valid blocks. +system.cpu2.dcache.replacements 0 # number of replacements +system.cpu2.dcache.tagsinuse 25.974144 # Cycle average of tags in use +system.cpu2.dcache.total_refs 34436 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1187.448276 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.943438 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.048718 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.048718 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 41688 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 41688 # number of ReadReq hits +system.cpu2.dcache.occ_blocks::cpu2.data 25.974144 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.050731 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.050731 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 41706 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 41706 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15916 # number of WriteReq hits system.cpu2.dcache.WriteReq_hits::total 15916 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 57604 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 57604 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 57604 # number of overall hits -system.cpu2.dcache.overall_hits::total 57604 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 156 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 156 # number of ReadReq misses +system.cpu2.dcache.demand_hits::cpu2.data 57622 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 57622 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 57622 # number of overall hits +system.cpu2.dcache.overall_hits::total 57622 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 154 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 154 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 265 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 265 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 265 # number of overall misses -system.cpu2.dcache.overall_misses::total 265 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2527000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2527000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2084000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2084000 # number of WriteReq miss cycles +system.cpu2.dcache.demand_misses::cpu2.data 263 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 263 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 263 # number of overall misses +system.cpu2.dcache.overall_misses::total 263 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2498000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2498000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2031000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2031000 # number of WriteReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 305000 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::total 305000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4611000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4611000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4611000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4611000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 41844 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 41844 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.demand_miss_latency::cpu2.data 4529000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4529000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4529000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4529000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 41860 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 41860 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 16025 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 57869 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 57869 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003728 # miss rate for ReadReq accesses +system.cpu2.dcache.demand_accesses::cpu2.data 57885 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 57885 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 57885 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 57885 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003679 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003679 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_miss_rate::total 0.006802 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004579 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004579 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16198.717949 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 19119.266055 # average WriteReq miss latency +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004543 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004543 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004543 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004543 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16220.779221 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16220.779221 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18633.027523 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 18633.027523 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::total 5980.392157 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17400 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17400 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17220.532319 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17220.532319 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -675,116 +673,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu2.dcache.writebacks::total 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 156 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 154 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2059000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2059000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1757000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1757000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_misses::cpu2.data 263 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 263 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2036000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2036000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1704000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1704000 # number of WriteReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3816000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003728 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3740000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3740000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3740000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3740000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003679 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003679 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006802 # mshr miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004579 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004579 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13198.717949 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16119.266055 # average WriteReq mshr miss latency +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004543 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004543 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13220.779221 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13220.779221 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15633.027523 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15633.027523 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2980.392157 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 524596 # number of cpu cycles simulated +system.cpu3.numCycles 524598 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 166130 # Number of instructions committed -system.cpu3.committedOps 166130 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses +system.cpu3.committedInsts 166196 # Number of instructions committed +system.cpu3.committedOps 166196 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 112131 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 31024 # number of instructions that are conditional controls -system.cpu3.num_int_insts 112098 # number of integer instructions +system.cpu3.num_conditional_control_insts 31040 # number of instructions that are conditional controls +system.cpu3.num_int_insts 112131 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 286475 # number of times the integer registers were read -system.cpu3.num_int_register_writes 109360 # number of times the integer registers were written +system.cpu3.num_int_register_reads 286557 # number of times the integer registers were read +system.cpu3.num_int_register_writes 109409 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 57243 # number of memory refs -system.cpu3.num_load_insts 41720 # Number of load instructions +system.cpu3.num_mem_refs 57260 # number of memory refs +system.cpu3.num_load_insts 41737 # Number of load instructions system.cpu3.num_store_insts 15523 # Number of store instructions -system.cpu3.num_idle_cycles 69090.001737 # Number of idle cycles -system.cpu3.num_busy_cycles 455505.998263 # Number of busy cycles -system.cpu3.not_idle_fraction 0.868299 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.131701 # Percentage of idle cycles +system.cpu3.num_idle_cycles 69252.001736 # Number of idle cycles +system.cpu3.num_busy_cycles 455345.998264 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867990 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132010 # Percentage of idle cycles system.cpu3.icache.replacements 281 # number of replacements -system.cpu3.icache.tagsinuse 67.737646 # Cycle average of tags in use -system.cpu3.icache.total_refs 165796 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 67.739564 # Cycle average of tags in use +system.cpu3.icache.total_refs 165862 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 451.760218 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 451.940054 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 67.737646 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.132300 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.132300 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 165796 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 165796 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 165796 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 165796 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 165796 # number of overall hits -system.cpu3.icache.overall_hits::total 165796 # number of overall hits +system.cpu3.icache.occ_blocks::cpu3.inst 67.739564 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.132304 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.132304 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 165862 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 165862 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 165862 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 165862 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 165862 # number of overall hits +system.cpu3.icache.overall_hits::total 165862 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5531500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5531500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5531500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5531500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5531500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5531500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 166163 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 166163 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 166163 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 166163 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 166163 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 166163 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002209 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002209 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002209 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002209 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002209 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 15072.207084 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 15072.207084 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 15072.207084 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5533500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5533500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5533500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5533500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5533500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5533500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 166229 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 166229 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 166229 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 166229 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 166229 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 166229 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002208 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002208 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002208 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002208 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002208 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002208 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15077.656676 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 15077.656676 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 15077.656676 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 15077.656676 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,94 +795,94 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4430500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4430500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4430500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4430500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4430500 # 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average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::total 6037.037037 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17543.396226 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17543.396226 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 17349.809886 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 17349.809886 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -895,65 +891,63 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu3.dcache.writebacks::total 1 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 157 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 155 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # 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number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3854000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3854000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3854000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003764 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3774000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3774000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3774000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3774000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003714 # 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number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses @@ -1004,10 +998,10 @@ system.l2c.ReadReq_misses::cpu3.inst 9 # nu system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 450 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 12 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 72 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 11 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 69 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses @@ -1033,56 +1027,52 @@ system.l2c.overall_misses::cpu3.data 16 # nu system.l2c.overall_misses::total 592 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.inst 14822000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 3432000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3416000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 413000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 3402000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 411000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.inst 615000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 429000 # 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number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 12 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 11 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 71 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) @@ -1091,35 +1081,35 @@ system.l2c.ReadExReq_accesses::total 142 # nu system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 28 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 27 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1818 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 25 # 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miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.268496 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.972973 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.971831 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -1128,57 +1118,53 @@ system.l2c.ReadExReq_miss_rate::total 1 # mi system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.821429 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.592593 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.592593 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.325633 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.326711 # 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miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51757.575758 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 51625 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51545.454545 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 51375 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51250 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 47666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 49500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 51844.444444 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4333.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3250 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 3250 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2166.666667 # average UpgradeReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49555.555556 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 50500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 51851.111111 # average ReadReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52066.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52007.042254 # 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average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 49555.555556 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 51812.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51886.824324 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51545.454545 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 51782.608696 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.inst 51250 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51883.445946 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 49555.555556 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 51812.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51886.824324 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1215,10 +1201,10 @@ system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # n system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 12 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 72 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 11 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 69 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses @@ -1252,47 +1238,47 @@ system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 17203000 # 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number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.data 640000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 600000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22884000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22883000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.538462 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.256563 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.972973 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.971831 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -1301,21 +1287,21 @@ system.l2c.ReadExReq_mshr_miss_rate::total 1 # system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.314631 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.314631 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency @@ -1331,28 +1317,28 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.042254 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |