diff options
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc')
3 files changed, 15 insertions, 96 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index a8bc405b3..d612f6415 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000126 # Nu sim_ticks 125889000 # Number of ticks simulated final_tick 125889000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271253 # Simulator instruction rate (inst/s) -host_op_rate 271253 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29155299 # Simulator tick rate (ticks/s) -host_mem_usage 267160 # Number of bytes of host memory used -host_seconds 4.32 # Real time elapsed on the host +host_inst_rate 196054 # Simulator instruction rate (inst/s) +host_op_rate 196054 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21072637 # Simulator tick rate (ticks/s) +host_mem_usage 267156 # Number of bytes of host memory used +host_seconds 5.97 # Real time elapsed on the host sim_insts 1171234 # Number of instructions simulated sim_ops 1171234 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -666,8 +666,6 @@ system.cpu0.dcache.blocked::no_mshrs 22 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.181818 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 380 # number of ReadReq MSHR hits @@ -718,7 +716,6 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 44680.939227 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 44680.939227 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 403 # number of replacements system.cpu0.icache.tags.tagsinuse 251.059263 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 7130 # Total number of references to valid blocks. @@ -777,8 +774,6 @@ system.cpu0.icache.blocked::no_mshrs 4 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.250000 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 403 # number of writebacks system.cpu0.icache.writebacks::total 403 # number of writebacks system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 215 # number of ReadReq MSHR hits @@ -811,7 +806,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47802.407932 system.cpu0.icache.demand_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.branchPred.lookups 75929 # Number of BP lookups system.cpu1.branchPred.condPredicted 68631 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 2222 # Number of conditional branches incorrect @@ -1193,8 +1187,6 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 362 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 362 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 43 # number of WriteReq MSHR hits @@ -1243,7 +1235,6 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11369.402985 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11369.402985 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 548 # number of replacements system.cpu1.icache.tags.tagsinuse 97.609803 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 21265 # Total number of references to valid blocks. @@ -1302,8 +1293,6 @@ system.cpu1.icache.blocked::no_mshrs 1 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 548 # number of writebacks system.cpu1.icache.writebacks::total 548 # number of writebacks system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 144 # number of ReadReq MSHR hits @@ -1336,7 +1325,6 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 15868.035191 system.cpu1.icache.demand_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.branchPred.lookups 65577 # Number of BP lookups system.cpu2.branchPred.condPredicted 57724 # Number of conditional branches predicted system.cpu2.branchPred.condIncorrect 2464 # Number of conditional branches incorrect @@ -1721,8 +1709,6 @@ system.cpu2.dcache.blocked::no_mshrs 0 # nu system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 298 # number of ReadReq MSHR hits system.cpu2.dcache.ReadReq_mshr_hits::total 298 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 47 # number of WriteReq MSHR hits @@ -1773,7 +1759,6 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13924.074074 system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13924.074074 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 555 # number of replacements system.cpu2.icache.tags.tagsinuse 101.261159 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 26702 # Total number of references to valid blocks. @@ -1832,8 +1817,6 @@ system.cpu2.icache.blocked::no_mshrs 7 # nu system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.avg_blocked_cycles::no_mshrs 31.428571 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.writebacks::writebacks 555 # number of writebacks system.cpu2.icache.writebacks::total 555 # number of writebacks system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 149 # number of ReadReq MSHR hits @@ -1866,7 +1849,6 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 22336.455331 system.cpu2.icache.demand_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.branchPred.lookups 57182 # Number of BP lookups system.cpu3.branchPred.condPredicted 48797 # Number of conditional branches predicted system.cpu3.branchPred.condIncorrect 2586 # Number of conditional branches incorrect @@ -2248,8 +2230,6 @@ system.cpu3.dcache.blocked::no_mshrs 0 # nu system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 291 # number of ReadReq MSHR hits system.cpu3.dcache.ReadReq_mshr_hits::total 291 # number of ReadReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits @@ -2300,7 +2280,6 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12388.489209 system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12388.489209 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 608 # number of replacements system.cpu3.icache.tags.tagsinuse 93.738869 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 33506 # Total number of references to valid blocks. @@ -2359,8 +2338,6 @@ system.cpu3.icache.blocked::no_mshrs 0 # nu system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.writebacks::writebacks 608 # number of writebacks system.cpu3.icache.writebacks::total 608 # number of writebacks system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 128 # number of ReadReq MSHR hits @@ -2393,7 +2370,6 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13532.974428 system.cpu3.icache.demand_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 458.562207 # Cycle average of tags in use system.l2c.tags.total_refs 3097 # Total number of references to valid blocks. @@ -2650,8 +2626,6 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 8 # number of ReadCleanReq MSHR hits @@ -2819,7 +2793,6 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70119.047619 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 77375 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69266.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 70071.328671 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 583 # Transaction distribution system.membus.trans_dist::UpgradeReq 286 # Transaction distribution system.membus.trans_dist::ReadExReq 182 # Transaction distribution diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 1d3cbd064..f2280533e 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1830828 # Simulator instruction rate (inst/s) -host_op_rate 1830758 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 237054275 # Simulator tick rate (ticks/s) -host_mem_usage 306784 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host +host_inst_rate 1039500 # Simulator instruction rate (inst/s) +host_op_rate 1039462 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 134594380 # Simulator tick rate (ticks/s) +host_mem_usage 262812 # Number of bytes of host memory used +host_seconds 0.65 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -180,11 +180,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 215 # number of replacements system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. @@ -230,11 +227,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 215 # number of writebacks system.cpu0.icache.writebacks::total 215 # number of writebacks -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 173297 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -353,9 +347,6 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 278 # number of replacements system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. @@ -401,11 +392,8 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 278 # number of writebacks system.cpu1.icache.writebacks::total 278 # number of writebacks -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 173296 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -525,9 +513,6 @@ system.cpu2.dcache.blocked::no_mshrs 0 # nu system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 278 # number of replacements system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. @@ -573,11 +558,8 @@ system.cpu2.icache.blocked::no_mshrs 0 # nu system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.writebacks::writebacks 278 # number of writebacks system.cpu2.icache.writebacks::total 278 # number of writebacks -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 173297 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -696,9 +678,6 @@ system.cpu3.dcache.blocked::no_mshrs 0 # nu system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 279 # number of replacements system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. @@ -744,11 +723,8 @@ system.cpu3.icache.blocked::no_mshrs 0 # nu system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.writebacks::writebacks 279 # number of writebacks system.cpu3.icache.writebacks::total 279 # number of writebacks -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. @@ -938,9 +914,6 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 423 # Transaction distribution system.membus.trans_dist::UpgradeReq 273 # Transaction distribution system.membus.trans_dist::UpgradeResp 80 # Transaction distribution diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index eb0bc0573..22d94928b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000264 # Nu sim_ticks 263565500 # Number of ticks simulated final_tick 263565500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 798172 # Simulator instruction rate (inst/s) -host_op_rate 798158 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 317271660 # Simulator tick rate (ticks/s) -host_mem_usage 306776 # Number of bytes of host memory used -host_seconds 0.83 # Real time elapsed on the host +host_inst_rate 821706 # Simulator instruction rate (inst/s) +host_op_rate 821692 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 326627282 # Simulator tick rate (ticks/s) +host_mem_usage 262816 # Number of bytes of host memory used +host_seconds 0.81 # Real time elapsed on the host sim_insts 663039 # Number of instructions simulated sim_ops 663039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,8 +200,6 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 168 # number of ReadReq MSHR misses @@ -244,7 +242,6 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32626.780627 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 215 # number of replacements system.cpu0.icache.tags.tagsinuse 211.380247 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 157792 # Total number of references to valid blocks. @@ -302,8 +299,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 215 # number of writebacks system.cpu0.icache.writebacks::total 215 # number of writebacks system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses @@ -330,7 +325,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42127.408994 system.cpu0.icache.demand_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 527130 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -470,8 +464,6 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses @@ -512,7 +504,6 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11992.647059 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 280 # number of replacements system.cpu1.icache.tags.tagsinuse 66.953040 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 170457 # Total number of references to valid blocks. @@ -571,8 +562,6 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 280 # number of writebacks system.cpu1.icache.writebacks::total 280 # number of writebacks system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses @@ -599,7 +588,6 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14542.349727 system.cpu1.icache.demand_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 527130 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -739,8 +727,6 @@ system.cpu2.dcache.blocked::no_mshrs 0 # nu system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses @@ -781,7 +767,6 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13317.518248 system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 280 # number of replacements system.cpu2.icache.tags.tagsinuse 69.363893 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 167911 # Total number of references to valid blocks. @@ -840,8 +825,6 @@ system.cpu2.icache.blocked::no_mshrs 0 # nu system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.writebacks::writebacks 280 # number of writebacks system.cpu2.icache.writebacks::total 280 # number of writebacks system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses @@ -868,7 +851,6 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21099.726776 system.cpu2.icache.demand_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 527131 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1008,8 +990,6 @@ system.cpu3.dcache.blocked::no_mshrs 0 # nu system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 150 # number of ReadReq MSHR misses system.cpu3.dcache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses @@ -1050,7 +1030,6 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11945.945946 system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 281 # number of replacements system.cpu3.icache.tags.tagsinuse 64.942208 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 165475 # Total number of references to valid blocks. @@ -1109,8 +1088,6 @@ system.cpu3.icache.blocked::no_mshrs 0 # nu system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.writebacks::writebacks 281 # number of writebacks system.cpu3.icache.writebacks::total 281 # number of writebacks system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses @@ -1137,7 +1114,6 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937 system.cpu3.icache.demand_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 347.185045 # Cycle average of tags in use system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. @@ -1393,8 +1369,6 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 11 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 5 # number of ReadCleanReq MSHR hits @@ -1566,7 +1540,6 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50068.181818 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49687.500000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 49562.937063 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 271 # Transaction distribution system.membus.trans_dist::ReadExReq 208 # Transaction distribution |