diff options
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc')
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 985 | ||||
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt | 982 |
2 files changed, 984 insertions, 983 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index aa46bcce7..53e641a1b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000111 # Nu sim_ticks 110804500 # Number of ticks simulated final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110530 # Simulator instruction rate (inst/s) -host_op_rate 110530 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11745373 # Simulator tick rate (ticks/s) -host_mem_usage 249508 # Number of bytes of host memory used -host_seconds 9.43 # Real time elapsed on the host +host_inst_rate 170931 # Simulator instruction rate (inst/s) +host_op_rate 170931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18163832 # Simulator tick rate (ticks/s) +host_mem_usage 247816 # Number of bytes of host memory used +host_seconds 6.10 # Real time elapsed on the host sim_insts 1042724 # Number of instructions simulated sim_ops 1042724 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory @@ -57,14 +57,15 @@ system.physmem.bw_total::cpu2.data 11551877 # To system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 660 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 736 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 660 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 660 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 42176 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis @@ -229,16 +230,421 @@ system.membus.trans_dist::UpgradeReq 287 # Tr system.membus.trans_dist::UpgradeResp 76 # Transaction distribution system.membus.trans_dist::ReadExReq 163 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side 1714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks) system.membus.respLayer1.utilization 5.7 # Layer utilization (%) +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use +system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3 # 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miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.037383 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.178824 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.020930 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.273414 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.962025 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # 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miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.037383 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.020930 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67862.116992 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 76662.162162 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75343.750000 # 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Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 135488 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks) @@ -548,15 +954,15 @@ system.cpu0.int_regfile_writes 325227 # nu system.cpu0.fp_regfile_reads 192 # number of floating regfile reads system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.tags.replacements 297 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 297 # number of replacements +system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits @@ -632,15 +1038,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.869283 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277088 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 78995 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 78995 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 76703 # number of WriteReq hits @@ -1025,15 +1431,15 @@ system.cpu1.int_regfile_writes 148477 # nu system.cpu1.fp_regfile_writes 64 # number of floating regfile writes system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.icache.tags.replacements 318 # number of replacements -system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 318 # number of replacements +system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits @@ -1109,15 +1515,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits @@ -1500,15 +1906,15 @@ system.cpu2.int_regfile_writes 188531 # nu system.cpu2.fp_regfile_writes 64 # number of floating regfile writes system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.icache.tags.replacements 317 # number of replacements -system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.replacements 317 # number of replacements +system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits @@ -1584,15 +1990,15 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 21651.185882 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.191522 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051155 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 45549 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 45549 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 35887 # number of WriteReq hits @@ -1975,15 +2381,15 @@ system.cpu3.int_regfile_writes 211087 # nu system.cpu3.fp_regfile_writes 64 # number of floating regfile writes system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.icache.tags.replacements 319 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.replacements 319 # number of replacements +system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits @@ -2059,15 +2465,15 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits @@ -2185,410 +2591,5 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use -system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 421 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1443 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 229 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 4a2827ac8..8ba84a629 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000263 # Nu sim_ticks 262794500 # Number of ticks simulated final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146225 # Simulator instruction rate (inst/s) -host_op_rate 146224 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57909206 # Simulator tick rate (ticks/s) -host_mem_usage 244388 # Number of bytes of host memory used -host_seconds 4.54 # Real time elapsed on the host +host_inst_rate 681070 # Simulator instruction rate (inst/s) +host_op_rate 681053 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 269712940 # Simulator tick rate (ticks/s) +host_mem_usage 243700 # Number of bytes of host memory used +host_seconds 0.97 # Real time elapsed on the host sim_insts 663567 # Number of instructions simulated sim_ops 663567 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory @@ -64,16 +64,424 @@ system.membus.trans_dist::UpgradeReq 272 # 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mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 646588875 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution @@ -82,24 +490,24 @@ system.toL2Bus.trans_dist::UpgradeReq 274 # Tr system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 580 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 355 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 352 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 401 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 4820 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 23488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 116032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 116032 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) @@ -143,15 +551,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 525589 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits @@ -221,15 +629,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits @@ -363,15 +771,15 @@ system.cpu1.num_idle_cycles 69347.869793 # Nu system.cpu1.num_busy_cycles 456240.130207 # Number of busy cycles system.cpu1.not_idle_fraction 0.868057 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.131943 # Percentage of idle cycles -system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 280 # number of replacements +system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017506 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits @@ -441,15 +849,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits @@ -581,15 +989,15 @@ system.cpu2.num_idle_cycles 69604.869303 # Nu system.cpu2.num_busy_cycles 455983.130697 # Number of busy cycles system.cpu2.not_idle_fraction 0.867568 # Percentage of non-idle cycles system.cpu2.idle_fraction 0.132432 # Percentage of idle cycles -system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.replacements 280 # number of replacements +system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624969 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits @@ -659,15 +1067,15 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 12332 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.763892 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 26.763892 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763892 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 16865 # number of WriteReq hits @@ -799,15 +1207,15 @@ system.cpu3.num_idle_cycles 69869.868798 # Nu system.cpu3.num_busy_cycles 455718.131202 # Number of busy cycles system.cpu3.not_idle_fraction 0.867063 # Percentage of non-idle cycles system.cpu3.idle_fraction 0.132937 # Percentage of idle cycles -system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.replacements 281 # number of replacements +system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598437 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits @@ -877,15 +1285,15 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915086 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050615 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits @@ -995,413 +1403,5 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use -system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 182 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 300 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 354 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 358 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses -system.l2c.ReadReq_misses::total 450 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses -system.l2c.demand_misses::total 592 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 285 # number of overall misses -system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 66 # number of overall misses -system.l2c.overall_misses::cpu1.data 23 # number of overall misses -system.l2c.overall_misses::cpu2.inst 12 # number of overall misses -system.l2c.overall_misses::cpu2.data 16 # number of overall misses -system.l2c.overall_misses::cpu3.inst 9 # number of overall misses -system.l2c.overall_misses::cpu3.data 16 # number of overall misses -system.l2c.overall_misses::total 592 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3436500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 418500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 597500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 103500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 23504000 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 801000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 747000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7452000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3436500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1219500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 597500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 850500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 30956000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3436500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1219500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 597500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 850500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30956000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.640000 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |