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-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini142
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout6
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt1589
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini138
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout6
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt848
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini138
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout6
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt1512
9 files changed, 2497 insertions, 1888 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index eb497bb90..bb8df191a 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[2]
[system.cpu0]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb tracer workload
+children=dcache dtb fuPool icache interrupts itb tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu0.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu0.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.port[1]
+[system.cpu0.interrupts]
+type=SparcInterrupts
+
[system.cpu0.itb]
type=SparcTLB
size=64
@@ -473,7 +473,7 @@ uid=100
[system.cpu1]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb tracer
+children=dcache dtb fuPool icache interrupts itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -502,6 +502,7 @@ decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
fetchToDecodeDelay=1
@@ -519,6 +520,7 @@ iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu1.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu1.itb
@@ -530,6 +532,7 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
@@ -538,6 +541,7 @@ numRobs=1
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
@@ -575,20 +579,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -874,20 +871,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -895,6 +885,9 @@ write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.port[3]
+[system.cpu1.interrupts]
+type=SparcInterrupts
+
[system.cpu1.itb]
type=SparcTLB
size=64
@@ -904,7 +897,7 @@ type=ExeTracer
[system.cpu2]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb tracer
+children=dcache dtb fuPool icache interrupts itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -933,6 +926,7 @@ decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
fetchToDecodeDelay=1
@@ -950,6 +944,7 @@ iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu2.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu2.itb
@@ -961,6 +956,7 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
@@ -969,6 +965,7 @@ numRobs=1
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
@@ -1006,20 +1003,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -1305,20 +1295,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -1326,6 +1309,9 @@ write_buffers=8
cpu_side=system.cpu2.icache_port
mem_side=system.toL2Bus.port[5]
+[system.cpu2.interrupts]
+type=SparcInterrupts
+
[system.cpu2.itb]
type=SparcTLB
size=64
@@ -1335,7 +1321,7 @@ type=ExeTracer
[system.cpu3]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb tracer
+children=dcache dtb fuPool icache interrupts itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -1364,6 +1350,7 @@ decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu3.dtb
fetchToDecodeDelay=1
@@ -1381,6 +1368,7 @@ iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu3.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu3.itb
@@ -1392,6 +1380,7 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
@@ -1400,6 +1389,7 @@ numRobs=1
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
@@ -1437,20 +1427,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -1736,20 +1719,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -1757,6 +1733,9 @@ write_buffers=8
cpu_side=system.cpu3.icache_port
mem_side=system.toL2Bus.port[7]
+[system.cpu3.interrupts]
+type=SparcInterrupts
+
[system.cpu3.itb]
type=SparcTLB
size=64
@@ -1775,20 +1754,13 @@ is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=4
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 0491d5141..2bb2951e2 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:31
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:55
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 191a42060..befe09ef8 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.000104 # Nu
sim_ticks 104317500 # Number of ticks simulated
final_tick 104317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 132902 # Simulator instruction rate (inst/s)
-host_tick_rate 13605540 # Simulator tick rate (ticks/s)
-host_mem_usage 226920 # Number of bytes of host memory used
-host_seconds 7.67 # Real time elapsed on the host
+host_inst_rate 190796 # Simulator instruction rate (inst/s)
+host_op_rate 190795 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 19532213 # Simulator tick rate (ticks/s)
+host_mem_usage 225896 # Number of bytes of host memory used
+host_seconds 5.34 # Real time elapsed on the host
sim_insts 1018993 # Number of instructions simulated
+sim_ops 1018993 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 41984 # Number of bytes read from this memory
system.physmem.bytes_inst_read 28224 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
@@ -234,6 +236,7 @@ system.cpu0.iew.wb_rate 1.886424 # in
system.cpu0.iew.wb_fanout 0.991039 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts 462799 # The number of committed instructions
+system.cpu0.commit.commitCommittedOps 462799 # The number of committed instructions
system.cpu0.commit.commitSquashedInsts 9535 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 1043 # The number of times a branch was mispredicted
@@ -254,7 +257,8 @@ system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 188840 # Number of insts commited each cycle
-system.cpu0.commit.count 462799 # Number of instructions committed
+system.cpu0.commit.committedInsts 462799 # Number of instructions committed
+system.cpu0.commit.committedOps 462799 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 226109 # Number of memory references committed
system.cpu0.commit.loads 150402 # Number of loads committed
@@ -270,6 +274,7 @@ system.cpu0.rob.rob_writes 946703 # Th
system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 17790 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts 388389 # Number of Instructions Simulated
+system.cpu0.committedOps 388389 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 388389 # Number of Instructions Simulated
system.cpu0.cpi 0.537183 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 0.537183 # CPI: Total CPI of All Threads
@@ -286,26 +291,39 @@ system.cpu0.icache.total_refs 4810 # To
system.cpu0.icache.sampled_refs 581 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 8.278830 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0 244.353680 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.477253 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits 4810 # number of ReadReq hits
-system.cpu0.icache.demand_hits 4810 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits 4810 # number of overall hits
-system.cpu0.icache.ReadReq_misses 705 # number of ReadReq misses
-system.cpu0.icache.demand_misses 705 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses 705 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency 27622000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency 27622000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency 27622000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses 5515 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses 5515 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses 5515 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate 0.127833 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate 0.127833 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate 0.127833 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency 39180.141844 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency 39180.141844 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency 39180.141844 # average overall miss latency
+system.cpu0.icache.occ_blocks::cpu0.inst 244.353680 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.477253 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.477253 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 4810 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 4810 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 4810 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 4810 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 4810 # number of overall hits
+system.cpu0.icache.overall_hits::total 4810 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 705 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 705 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 705 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 705 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 705 # number of overall misses
+system.cpu0.icache.overall_misses::total 705 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 27622000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 27622000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 27622000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 27622000 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 27622000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 27622000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 5515 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 5515 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 5515 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 5515 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 5515 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 5515 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.127833 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.127833 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.127833 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39180.141844 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39180.141844 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39180.141844 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
@@ -314,68 +332,90 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits 123 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits 123 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses 582 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses 582 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses 582 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 21369000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency 21369000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency 21369000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.105530 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate 0.105530 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate 0.105530 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36716.494845 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 36716.494845 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 36716.494845 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 123 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 123 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 123 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 123 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 123 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 123 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 582 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 582 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 582 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 582 # number of demand (read+write) MSHR misses
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+system.cpu0.icache.overall_mshr_misses::total 582 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21369000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 21369000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21369000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 21369000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21369000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 21369000 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 9 # number of replacements
-system.cpu0.dcache.tagsinuse 138.901719 # Cycle average of tags in use
+system.cpu0.dcache.tagsinuse 140.432794 # Cycle average of tags in use
system.cpu0.dcache.total_refs 97328 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 559.356322 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0 140.432794 # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1 -1.531076 # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0 0.274283 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::1 -0.002990 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits 77005 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits 75125 # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits 23 # number of SwapReq hits
-system.cpu0.dcache.demand_hits 152130 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits 152130 # number of overall hits
-system.cpu0.dcache.ReadReq_misses 517 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses 19 # number of SwapReq misses
-system.cpu0.dcache.demand_misses 1057 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses 1057 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency 14734500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency 24692984 # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency 371000 # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency 39427484 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency 39427484 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses 77522 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses 75665 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses 153187 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses 153187 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate 0.006669 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate 0.007137 # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate 0.452381 # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate 0.006900 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate 0.006900 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency 28500 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency 45727.748148 # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency 19526.315789 # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency 37301.309366 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency 37301.309366 # average overall miss latency
+system.cpu0.dcache.occ_blocks::cpu0.data 140.432794 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.274283 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.274283 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 77005 # number of ReadReq hits
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+system.cpu0.dcache.overall_hits::total 152130 # number of overall hits
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+system.cpu0.dcache.ReadReq_misses::total 517 # number of ReadReq misses
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+system.cpu0.dcache.SwapReq_misses::total 19 # number of SwapReq misses
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+system.cpu0.dcache.overall_misses::total 1057 # number of overall misses
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+system.cpu0.dcache.ReadReq_miss_latency::total 14734500 # number of ReadReq miss cycles
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+system.cpu0.dcache.WriteReq_miss_latency::total 24692984 # number of WriteReq miss cycles
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+system.cpu0.dcache.SwapReq_miss_latency::total 371000 # number of SwapReq miss cycles
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+system.cpu0.dcache.demand_miss_latency::total 39427484 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 39427484 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 39427484 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 77522 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 77522 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 75665 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 75665 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
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+system.cpu0.dcache.demand_accesses::total 153187 # number of demand (read+write) accesses
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+system.cpu0.dcache.overall_accesses::total 153187 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006669 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007137 # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.452381 # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006900 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006900 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28500 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45727.748148 # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19526.315789 # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37301.309366 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37301.309366 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
@@ -384,36 +424,46 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8595.238095
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks 6 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits 327 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits 368 # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits 695 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits 695 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses 190 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses 172 # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses 19 # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses 362 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses 362 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 5255000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency 6251500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency 314000 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency 11506500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency 11506500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002451 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002273 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate 0.452381 # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate 0.002363 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate 0.002363 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27657.894737 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36345.930233 # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 16526.315789 # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 31785.911602 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 31785.911602 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks
+system.cpu0.dcache.writebacks::total 6 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 327 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 327 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 368 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 368 # number of WriteReq MSHR hits
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+system.cpu0.dcache.demand_mshr_hits::total 695 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 695 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 695 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 190 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 190 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 19 # number of SwapReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::total 19 # number of SwapReq MSHR misses
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+system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses
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+system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5255000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5255000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6251500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6251500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 314000 # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total 314000 # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11506500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 11506500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11506500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 11506500 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002451 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002273 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.452381 # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002363 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002363 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27657.894737 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36345.930233 # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16526.315789 # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31785.911602 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31785.911602 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.numCycles 174305 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
@@ -631,6 +681,7 @@ system.cpu1.iew.wb_rate 1.379140 # in
system.cpu1.iew.wb_fanout 0.968192 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts 275667 # The number of committed instructions
+system.cpu1.commit.commitCommittedOps 275667 # The number of committed instructions
system.cpu1.commit.commitSquashedInsts 9533 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 5427 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 1085 # The number of times a branch was mispredicted
@@ -651,7 +702,8 @@ system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 163203 # Number of insts commited each cycle
-system.cpu1.commit.count 275667 # Number of instructions committed
+system.cpu1.commit.committedInsts 275667 # Number of instructions committed
+system.cpu1.commit.committedOps 275667 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 118493 # Number of memory references committed
system.cpu1.commit.loads 80399 # Number of loads committed
@@ -668,6 +720,7 @@ system.cpu1.timesIdled 225 # Nu
system.cpu1.idleCycles 2707 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 34329 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 231385 # Number of Instructions Simulated
+system.cpu1.committedOps 231385 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 231385 # Number of Instructions Simulated
system.cpu1.cpi 0.753312 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 0.753312 # CPI: Total CPI of All Threads
@@ -684,26 +737,39 @@ system.cpu1.icache.total_refs 17870 # To
system.cpu1.icache.sampled_refs 427 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 41.850117 # Average number of references to valid blocks.
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@@ -712,68 +778,90 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value
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@@ -782,36 +870,46 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 993500 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total 993500 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3696000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 3696000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3696000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 3696000 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003288 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002787 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003065 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003065 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13412.903226 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15254.716981 # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 19105.769231 # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14160.919540 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14160.919540 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.numCycles 174018 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
@@ -1029,6 +1127,7 @@ system.cpu2.iew.wb_rate 1.290855 # in
system.cpu2.iew.wb_fanout 0.966435 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitCommittedInsts 256708 # The number of committed instructions
+system.cpu2.commit.commitCommittedOps 256708 # The number of committed instructions
system.cpu2.commit.commitSquashedInsts 10074 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 5686 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 1149 # The number of times a branch was mispredicted
@@ -1049,7 +1148,8 @@ system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 160519 # Number of insts commited each cycle
-system.cpu2.commit.count 256708 # Number of instructions committed
+system.cpu2.commit.committedInsts 256708 # Number of instructions committed
+system.cpu2.commit.committedOps 256708 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 108759 # Number of memory references committed
system.cpu2.commit.loads 73984 # Number of loads committed
@@ -1066,6 +1166,7 @@ system.cpu2.timesIdled 232 # Nu
system.cpu2.idleCycles 5048 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 34616 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 215254 # Number of Instructions Simulated
+system.cpu2.committedOps 215254 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 215254 # Number of Instructions Simulated
system.cpu2.cpi 0.808431 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 0.808431 # CPI: Total CPI of All Threads
@@ -1082,26 +1183,39 @@ system.cpu2.icache.total_refs 18578 # To
system.cpu2.icache.sampled_refs 427 # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs 43.508197 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::0 85.227474 # Average occupied blocks per context
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-system.cpu2.icache.ReadReq_misses 481 # number of ReadReq misses
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-system.cpu2.icache.ReadReq_miss_latency 10446500 # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency 10446500 # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency 10446500 # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses 19059 # number of ReadReq accesses(hits+misses)
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-system.cpu2.icache.overall_accesses 19059 # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate 0.025237 # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate 0.025237 # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate 0.025237 # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency 21718.295218 # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency 21718.295218 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency 21718.295218 # average overall miss latency
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+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21718.295218 # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21718.295218 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21718.295218 # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
@@ -1110,68 +1224,90 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
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-system.cpu2.icache.overall_mshr_miss_latency 8026500 # number of overall MSHR miss cycles
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-system.cpu2.icache.overall_avg_mshr_miss_latency 18797.423888 # average overall mshr miss latency
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-system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 2 # number of replacements
-system.cpu2.dcache.tagsinuse 19.370911 # Cycle average of tags in use
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system.cpu2.dcache.total_refs 40686 # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs 1356.200000 # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu2.dcache.WriteReq_miss_rate 0.003458 # miss rate for WriteReq accesses
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-system.cpu2.dcache.ReadReq_avg_miss_latency 23964.052288 # average ReadReq miss latency
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+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23964.052288 # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24837.500000 # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 22024.590164 # average SwapReq miss latency
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+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 24145.077720 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1180,36 +1316,46 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.writebacks 1 # number of writebacks
-system.cpu2.dcache.ReadReq_mshr_hits 297 # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits 315 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits 315 # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses 61 # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses 264 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency 2380000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency 1660000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency 1160500 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency 4040000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency 4040000 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003679 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002939 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate 0.824324 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate 0.003353 # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate 0.003353 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14691.358025 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16274.509804 # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19024.590164 # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency 15303.030303 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency 15303.030303 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks
+system.cpu2.dcache.writebacks::total 1 # number of writebacks
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 297 # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total 297 # number of ReadReq MSHR hits
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+system.cpu2.dcache.overall_mshr_hits::total 315 # number of overall MSHR hits
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+system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
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+system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 61 # number of SwapReq MSHR misses
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+system.cpu2.dcache.overall_mshr_misses::cpu2.data 264 # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses
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+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1660000 # number of WriteReq MSHR miss cycles
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+system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1160500 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4040000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total 4040000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4040000 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 4040000 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003679 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002939 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.824324 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003353 # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003353 # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14691.358025 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16274.509804 # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 19024.590164 # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 15303.030303 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 15303.030303 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.numCycles 173752 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
@@ -1427,6 +1573,7 @@ system.cpu3.iew.wb_rate 1.121909 # in
system.cpu3.iew.wb_fanout 0.961453 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitCommittedInsts 222296 # The number of committed instructions
+system.cpu3.commit.commitCommittedOps 222296 # The number of committed instructions
system.cpu3.commit.commitSquashedInsts 9409 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 7641 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 1065 # The number of times a branch was mispredicted
@@ -1447,7 +1594,8 @@ system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total 162652 # Number of insts commited each cycle
-system.cpu3.commit.count 222296 # Number of instructions committed
+system.cpu3.commit.committedInsts 222296 # Number of instructions committed
+system.cpu3.commit.committedOps 222296 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu3.commit.refs 89597 # Number of memory references committed
system.cpu3.commit.loads 61865 # Number of loads committed
@@ -1464,6 +1612,7 @@ system.cpu3.timesIdled 234 # Nu
system.cpu3.idleCycles 2770 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 34882 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 183965 # Number of Instructions Simulated
+system.cpu3.committedOps 183965 # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total 183965 # Number of Instructions Simulated
system.cpu3.cpi 0.944484 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 0.944484 # CPI: Total CPI of All Threads
@@ -1480,26 +1629,39 @@ system.cpu3.icache.total_refs 22493 # To
system.cpu3.icache.sampled_refs 426 # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs 52.800469 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::0 80.006059 # Average occupied blocks per context
-system.cpu3.icache.occ_percent::0 0.156262 # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits 22493 # number of ReadReq hits
-system.cpu3.icache.demand_hits 22493 # number of demand (read+write) hits
-system.cpu3.icache.overall_hits 22493 # number of overall hits
-system.cpu3.icache.ReadReq_misses 466 # number of ReadReq misses
-system.cpu3.icache.demand_misses 466 # number of demand (read+write) misses
-system.cpu3.icache.overall_misses 466 # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency 6527000 # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency 6527000 # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency 6527000 # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses 22959 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses 22959 # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses 22959 # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate 0.020297 # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate 0.020297 # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate 0.020297 # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency 14006.437768 # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency 14006.437768 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency 14006.437768 # average overall miss latency
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+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6527000 # number of ReadReq miss cycles
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+system.cpu3.icache.overall_accesses::total 22959 # number of overall (read+write) accesses
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+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14006.437768 # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14006.437768 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14006.437768 # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1508,68 +1670,90 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
-system.cpu3.icache.writebacks 0 # number of writebacks
-system.cpu3.icache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits
-system.cpu3.icache.demand_mshr_hits 40 # number of demand (read+write) MSHR hits
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-system.cpu3.icache.ReadReq_mshr_misses 426 # number of ReadReq MSHR misses
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-system.cpu3.icache.overall_mshr_misses 426 # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu3.icache.ReadReq_mshr_miss_latency 4833500 # number of ReadReq MSHR miss cycles
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-system.cpu3.icache.overall_mshr_miss_latency 4833500 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate 0.018555 # mshr miss rate for ReadReq accesses
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-system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11346.244131 # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency 11346.244131 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency 11346.244131 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11346.244131 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.replacements 2 # number of replacements
-system.cpu3.dcache.tagsinuse 13.455705 # Cycle average of tags in use
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system.cpu3.dcache.total_refs 33584 # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs 1158.068966 # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.dcache.WriteReq_miss_rate 0.004519 # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate 0.800000 # miss rate for SwapReq accesses
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-system.cpu3.dcache.ReadReq_avg_miss_latency 20888.392857 # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency 23288 # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency 24116.071429 # average SwapReq miss latency
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-system.cpu3.dcache.overall_avg_miss_latency 21411.867365 # average overall miss latency
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system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1578,36 +1762,46 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
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system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.replacements 0 # number of replacements
system.l2c.tagsinuse 428.231635 # Cycle average of tags in use
@@ -1615,142 +1809,231 @@ system.l2c.total_refs 1446 # To
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@@ -1759,55 +2042,159 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av
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+system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 525 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 21 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 22 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data 22 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data 22 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 87 # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 353 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 14 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst 73 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 656 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst 353 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst 73 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 656 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14091500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3019000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 561000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 2922000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data 280000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 20993500 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 840000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 880000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 880000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 880000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 3480000 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3792000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 481000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 524500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 481500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 5279000 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 14091500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 6811000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 561000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 521000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 2922000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 804500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data 521500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 26272500 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 14091500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 6811000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 561000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 521000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 2922000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 804500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data 521500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 26272500 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.875000 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.520000 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data 0.520000 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.520000 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data 0.520000 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40253.333333 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40340.425532 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40083.333333 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40346.153846 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40301.775148 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40076.923077 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40225 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40301.775148 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40076.923077 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40225 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index 65fcae2f7..90b4c4184 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[2]
[system.cpu0]
type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu0.interrupts
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -61,20 +71,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -97,20 +100,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -118,6 +114,9 @@ write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.port[1]
+[system.cpu0.interrupts]
+type=SparcInterrupts
+
[system.cpu0.itb]
type=SparcTLB
size=64
@@ -146,16 +145,18 @@ uid=100
[system.cpu1]
type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
checker=Null
clock=500
cpu_id=1
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu1.interrupts
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -163,6 +164,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -184,20 +186,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -220,20 +215,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -241,6 +229,9 @@ write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.port[3]
+[system.cpu1.interrupts]
+type=SparcInterrupts
+
[system.cpu1.itb]
type=SparcTLB
size=64
@@ -250,16 +241,18 @@ type=ExeTracer
[system.cpu2]
type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
checker=Null
clock=500
cpu_id=2
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu2.interrupts
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -267,6 +260,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -288,20 +282,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -324,20 +311,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -345,6 +325,9 @@ write_buffers=8
cpu_side=system.cpu2.icache_port
mem_side=system.toL2Bus.port[5]
+[system.cpu2.interrupts]
+type=SparcInterrupts
+
[system.cpu2.itb]
type=SparcTLB
size=64
@@ -354,16 +337,18 @@ type=ExeTracer
[system.cpu3]
type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
checker=Null
clock=500
cpu_id=3
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu3.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu3.interrupts
itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -371,6 +356,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -392,20 +378,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -428,20 +407,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -449,6 +421,9 @@ write_buffers=8
cpu_side=system.cpu3.icache_port
mem_side=system.toL2Bus.port[7]
+[system.cpu3.interrupts]
+type=SparcInterrupts
+
[system.cpu3.itb]
type=SparcTLB
size=64
@@ -467,20 +442,13 @@ is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=4
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index 8daa6c894..4d44fa6f6 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:32
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:56
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 0cc0a830c..71dd904a3 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.000088 # Nu
sim_ticks 87713500 # Number of ticks simulated
final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1650324 # Simulator instruction rate (inst/s)
-host_tick_rate 213702670 # Simulator tick rate (ticks/s)
-host_mem_usage 1140448 # Number of bytes of host memory used
+host_inst_rate 1664146 # Simulator instruction rate (inst/s)
+host_op_rate 1664073 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 215483439 # Simulator tick rate (ticks/s)
+host_mem_usage 1139232 # Number of bytes of host memory used
host_seconds 0.41 # Real time elapsed on the host
sim_insts 677340 # Number of instructions simulated
+sim_ops 677340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 35776 # Number of bytes read from this memory
system.physmem.bytes_inst_read 22272 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
@@ -22,7 +24,8 @@ system.cpu0.workload.num_syscalls 89 # Nu
system.cpu0.numCycles 175428 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.num_insts 175339 # Number of instructions executed
+system.cpu0.committedInsts 175339 # Number of instructions committed
+system.cpu0.committedOps 175339 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 120388 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
@@ -46,24 +49,30 @@ system.cpu0.icache.total_refs 174934 # To
system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 374.591006 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0 222.757301 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.435073 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits 174934 # number of ReadReq hits
-system.cpu0.icache.demand_hits 174934 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits 174934 # number of overall hits
-system.cpu0.icache.ReadReq_misses 467 # number of ReadReq misses
-system.cpu0.icache.demand_misses 467 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses 467 # number of overall misses
-system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses 175401 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses 175401 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses 175401 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate 0.002662 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate 0.002662 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate 0.002662 # miss rate for overall accesses
-system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu0.icache.occ_blocks::cpu0.inst 222.757301 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.435073 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.435073 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 174934 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 174934 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 174934 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 174934 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 174934 # number of overall hits
+system.cpu0.icache.overall_hits::total 174934 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
+system.cpu0.icache.overall_misses::total 467 # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 175401 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 175401 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 175401 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 175401 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 175401 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -72,22 +81,6 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 9 # number of replacements
system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use
@@ -95,32 +88,44 @@ system.cpu0.dcache.total_refs 61599 # To
system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0 145.712770 # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0 0.284595 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits 54431 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits 27578 # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits 15 # number of SwapReq hits
-system.cpu0.dcache.demand_hits 82009 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits 82009 # number of overall hits
-system.cpu0.dcache.ReadReq_misses 151 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses 177 # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses 27 # number of SwapReq misses
-system.cpu0.dcache.demand_misses 328 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses 328 # number of overall misses
-system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses 54582 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses 27755 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses 82337 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses 82337 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate 0.002766 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate 0.006377 # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate 0.642857 # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate 0.003984 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate 0.003984 # miss rate for overall accesses
-system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu0.dcache.occ_blocks::cpu0.data 145.712770 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.284595 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.284595 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 54431 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 54431 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits
+system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 82009 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 82009 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 82009 # number of overall hits
+system.cpu0.dcache.overall_hits::total 82009 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses
+system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses
+system.cpu0.dcache.overall_misses::total 328 # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 54582 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 54582 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 82337 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 82337 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 82337 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 82337 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002766 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -129,27 +134,14 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks 6 # number of writebacks
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks
+system.cpu0.dcache.writebacks::total 6 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.numCycles 173308 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.num_insts 167398 # Number of instructions executed
+system.cpu1.committedInsts 167398 # Number of instructions committed
+system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 633 # number of times a function call or return occured
@@ -173,24 +165,30 @@ system.cpu1.icache.total_refs 167072 # To
system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0 76.746014 # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0 0.149895 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits 167072 # number of ReadReq hits
-system.cpu1.icache.demand_hits 167072 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits 167072 # number of overall hits
-system.cpu1.icache.ReadReq_misses 358 # number of ReadReq misses
-system.cpu1.icache.demand_misses 358 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses 358 # number of overall misses
-system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses 167430 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses 167430 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses 167430 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate 0.002138 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate 0.002138 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate 0.002138 # miss rate for overall accesses
-system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu1.icache.occ_blocks::cpu1.inst 76.746014 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.149895 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.149895 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits
+system.cpu1.icache.overall_hits::total 167072 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses
+system.cpu1.icache.overall_misses::total 358 # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -199,22 +197,6 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks 0 # number of writebacks
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
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-system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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-system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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-system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 2 # number of replacements
system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use
@@ -222,32 +204,44 @@ system.cpu1.dcache.total_refs 26889 # To
system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu1.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses
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-system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -256,27 +250,14 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks 1 # number of writebacks
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-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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-system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.numCycles 173308 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.num_insts 167334 # Number of instructions executed
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system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu2.num_func_calls 633 # number of times a function call or return occured
@@ -300,24 +281,30 @@ system.cpu2.icache.total_refs 167008 # To
system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -326,22 +313,6 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
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-system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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-system.cpu2.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 2 # number of replacements
system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use
@@ -349,32 +320,44 @@ system.cpu2.dcache.total_refs 33771 # To
system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency
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system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -383,27 +366,14 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
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system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.numCycles 173307 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu3.num_func_calls 633 # number of times a function call or return occured
@@ -427,24 +397,30 @@ system.cpu3.icache.total_refs 166942 # To
system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks.
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@@ -453,22 +429,6 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
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system.cpu3.dcache.replacements 2 # number of replacements
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@@ -476,32 +436,44 @@ system.cpu3.dcache.total_refs 30309 # To
system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks.
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@@ -510,22 +482,8 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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@@ -533,124 +491,164 @@ system.l2c.total_refs 1223 # To
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system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
-system.l2c.demand_misses::0 447 # number of demand (read+write) misses
-system.l2c.demand_misses::1 82 # number of demand (read+write) misses
-system.l2c.demand_misses::2 15 # number of demand (read+write) misses
-system.l2c.demand_misses::3 15 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::total 559 # number of demand (read+write) misses
-system.l2c.overall_misses::0 447 # number of overall misses
-system.l2c.overall_misses::1 82 # number of overall misses
-system.l2c.overall_misses::2 15 # number of overall misses
-system.l2c.overall_misses::3 15 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
+system.l2c.overall_misses::cpu0.data 165 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
+system.l2c.overall_misses::cpu1.data 20 # number of overall misses
+system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
+system.l2c.overall_misses::cpu2.data 13 # number of overall misses
+system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
+system.l2c.overall_misses::cpu3.data 13 # number of overall misses
system.l2c.overall_misses::total 559 # number of overall misses
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 538 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 370 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2 370 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::3 371 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 31 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 19 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::2 20 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::3 19 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 89 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1 13 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::2 12 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 637 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 383 # number of demand (read+write) accesses
-system.l2c.demand_accesses::2 382 # number of demand (read+write) accesses
-system.l2c.demand_accesses::3 383 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 637 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 383 # number of overall (read+write) accesses
-system.l2c.overall_accesses::2 382 # number of overall (read+write) accesses
-system.l2c.overall_accesses::3 383 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.646840 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.186486 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2 0.008108 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::3 0.008086 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.849521 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.935484 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 3.935484 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.701727 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.214099 # miss rate for demand accesses
-system.l2c.demand_miss_rate::2 0.039267 # miss rate for demand accesses
-system.l2c.demand_miss_rate::3 0.039164 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.994258 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.701727 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.214099 # miss rate for overall accesses
-system.l2c.overall_miss_rate::2 0.039267 # miss rate for overall accesses
-system.l2c.overall_miss_rate::3 0.039164 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.994258 # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::3 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -659,30 +657,6 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 0 # number of writebacks
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::3 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::3 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index ae7e021b5..c00589f53 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[1]
[system.cpu0]
type=TimingSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu0.interrupts
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu0.tracer
@@ -58,20 +68,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.port[1]
+[system.cpu0.interrupts]
+type=SparcInterrupts
+
[system.cpu0.itb]
type=SparcTLB
size=64
@@ -143,16 +142,18 @@ uid=100
[system.cpu1]
type=TimingSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
checker=Null
clock=500
cpu_id=1
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu1.interrupts
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -160,6 +161,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu1.tracer
@@ -178,20 +180,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -214,20 +209,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -235,6 +223,9 @@ write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.port[3]
+[system.cpu1.interrupts]
+type=SparcInterrupts
+
[system.cpu1.itb]
type=SparcTLB
size=64
@@ -244,16 +235,18 @@ type=ExeTracer
[system.cpu2]
type=TimingSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
checker=Null
clock=500
cpu_id=2
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu2.interrupts
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -261,6 +254,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu2.tracer
@@ -279,20 +273,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -315,20 +302,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -336,6 +316,9 @@ write_buffers=8
cpu_side=system.cpu2.icache_port
mem_side=system.toL2Bus.port[5]
+[system.cpu2.interrupts]
+type=SparcInterrupts
+
[system.cpu2.itb]
type=SparcTLB
size=64
@@ -345,16 +328,18 @@ type=ExeTracer
[system.cpu3]
type=TimingSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
checker=Null
clock=500
cpu_id=3
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu3.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu3.interrupts
itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -362,6 +347,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu3.tracer
@@ -380,20 +366,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -416,20 +395,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -437,6 +409,9 @@ write_buffers=8
cpu_side=system.cpu3.icache_port
mem_side=system.toL2Bus.port[7]
+[system.cpu3.interrupts]
+type=SparcInterrupts
+
[system.cpu3.itb]
type=SparcTLB
size=64
@@ -455,20 +430,13 @@ is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=4
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index 6f90c0dd1..bd048d482 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:33
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:56:07
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 0ce3fe3af..fcff65a90 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.000262 # Nu
sim_ticks 262298000 # Number of ticks simulated
final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1158712 # Simulator instruction rate (inst/s)
-host_tick_rate 458877844 # Simulator tick rate (ticks/s)
-host_mem_usage 222944 # Number of bytes of host memory used
-host_seconds 0.57 # Real time elapsed on the host
+host_inst_rate 1330969 # Simulator instruction rate (inst/s)
+host_op_rate 1330920 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 527074583 # Simulator tick rate (ticks/s)
+host_mem_usage 221728 # Number of bytes of host memory used
+host_seconds 0.50 # Real time elapsed on the host
sim_insts 662307 # Number of instructions simulated
+sim_ops 662307 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 36608 # Number of bytes read from this memory
system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
@@ -22,7 +24,8 @@ system.cpu0.workload.num_syscalls 89 # Nu
system.cpu0.numCycles 524596 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.num_insts 158353 # Number of instructions executed
+system.cpu0.committedInsts 158353 # Number of instructions committed
+system.cpu0.committedOps 158353 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
@@ -46,26 +49,39 @@ system.cpu0.icache.total_refs 157949 # To
system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0 212.479188 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.414998 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits 157949 # number of ReadReq hits
-system.cpu0.icache.demand_hits 157949 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits 157949 # number of overall hits
-system.cpu0.icache.ReadReq_misses 467 # number of ReadReq misses
-system.cpu0.icache.demand_misses 467 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses 467 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency 18524000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency 18524000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency 18524000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses 158416 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses 158416 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses 158416 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate 0.002948 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate 0.002948 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate 0.002948 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency 39665.952891 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency 39665.952891 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency 39665.952891 # average overall miss latency
+system.cpu0.icache.occ_blocks::cpu0.inst 212.479188 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.414998 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.414998 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 157949 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 157949 # number of overall hits
+system.cpu0.icache.overall_hits::total 157949 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
+system.cpu0.icache.overall_misses::total 467 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18524000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 18524000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 18524000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 18524000 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 18524000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 18524000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 158416 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 158416 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 158416 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 158416 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -74,26 +90,24 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses 467 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses 467 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 17123000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency 17123000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency 17123000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.002948 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate 0.002948 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate 0.002948 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36665.952891 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17123000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17123000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 17123000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 9 # number of replacements
system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use
@@ -101,38 +115,59 @@ system.cpu0.dcache.total_refs 56009 # To
system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0 141.233342 # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0 0.275846 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits 48758 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits 24741 # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits
-system.cpu0.dcache.demand_hits 73499 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits 73499 # number of overall hits
-system.cpu0.dcache.ReadReq_misses 162 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses 183 # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses
-system.cpu0.dcache.demand_misses 345 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses 345 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency 4749000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency 7175000 # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency 387000 # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency 11924000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency 11924000 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses 48920 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses 24924 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses 73844 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses 73844 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate 0.003312 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate 0.007342 # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate 0.004672 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate 0.004672 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency 29314.814815 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency 39207.650273 # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency 14884.615385 # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency 34562.318841 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency 34562.318841 # average overall miss latency
+system.cpu0.dcache.occ_blocks::cpu0.data 141.233342 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.275846 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.275846 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 24741 # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
+system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 73499 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 73499 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 73499 # number of overall hits
+system.cpu0.dcache.overall_hits::total 73499 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
+system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 345 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses
+system.cpu0.dcache.overall_misses::total 345 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4749000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 4749000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7175000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 7175000 # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 387000 # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::total 387000 # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 11924000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 11924000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 11924000 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 11924000 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 73844 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 73844 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -141,39 +176,44 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks 6 # number of writebacks
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses 183 # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses 345 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses 345 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 4263000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency 6626000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency 309000 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency 10889000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency 10889000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate 0.003312 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.007342 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate 0.004672 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate 0.004672 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26314.814815 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36207.650273 # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 11884.615385 # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 31562.318841 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 31562.318841 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu0.dcache.writebacks::total 6 # number of writebacks
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+system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4263000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4263000 # number of ReadReq MSHR miss cycles
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+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626000 # number of WriteReq MSHR miss cycles
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+system.cpu0.dcache.SwapReq_mshr_miss_latency::total 309000 # number of SwapReq MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
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+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency
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+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.numCycles 524596 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.num_insts 172325 # Number of instructions executed
+system.cpu1.committedInsts 172325 # Number of instructions committed
+system.cpu1.committedOps 172325 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 637 # number of times a function call or return occured
@@ -197,26 +237,39 @@ system.cpu1.icache.total_refs 171992 # To
system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 469.923497 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0 70.076133 # Average occupied blocks per context
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-system.cpu1.icache.ReadReq_miss_latency 7920500 # number of ReadReq miss cycles
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-system.cpu1.icache.overall_miss_latency 7920500 # number of overall miss cycles
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-system.cpu1.icache.ReadReq_miss_rate 0.002123 # miss rate for ReadReq accesses
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-system.cpu1.icache.overall_miss_rate 0.002123 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency 21640.710383 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency 21640.710383 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency 21640.710383 # average overall miss latency
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+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -225,67 +278,84 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
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+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency
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+system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 47806 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 47806 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 47806 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 47806 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004570 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005836 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005836 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -294,39 +364,44 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks 1 # number of writebacks
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses 65 # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses 279 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 3170000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency 1595000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency 220000 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency 4765000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency 4765000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate 0.004570 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate 0.011956 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate 0.783133 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate 0.005836 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate 0.005836 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 17513.812155 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 16275.510204 # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 3384.615385 # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 17078.853047 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 17078.853047 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks
+system.cpu1.dcache.writebacks::total 1 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses
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+system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
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+system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3170000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3170000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1595000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1595000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4765000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.numCycles 524596 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.num_insts 165499 # Number of instructions executed
+system.cpu2.committedInsts 165499 # Number of instructions committed
+system.cpu2.committedOps 165499 # Number of ops (including micro ops) committed
system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu2.num_func_calls 637 # number of times a function call or return occured
@@ -350,26 +425,39 @@ system.cpu2.icache.total_refs 165166 # To
system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs 451.273224 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::0 65.601019 # Average occupied blocks per context
-system.cpu2.icache.occ_percent::0 0.128127 # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits 165166 # number of ReadReq hits
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-system.cpu2.icache.overall_hits 165166 # number of overall hits
-system.cpu2.icache.ReadReq_misses 366 # number of ReadReq misses
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-system.cpu2.icache.ReadReq_miss_latency 5648500 # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency 5648500 # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency 5648500 # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses 165532 # number of ReadReq accesses(hits+misses)
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-system.cpu2.icache.overall_accesses 165532 # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate 0.002211 # miss rate for ReadReq accesses
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-system.cpu2.icache.overall_miss_rate 0.002211 # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency 15433.060109 # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency 15433.060109 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency 15433.060109 # average overall miss latency
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+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -378,67 +466,84 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
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-system.cpu2.icache.overall_avg_mshr_miss_latency 12433.060109 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 2 # number of replacements
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system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks.
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system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu2.dcache.WriteReq_miss_latency::total 2084000 # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 305000 # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total 305000 # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data 4611000 # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total 4611000 # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data 4611000 # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total 4611000 # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data 41844 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total 41844 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data 16025 # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data 57869 # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total 57869 # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -447,39 +552,44 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.writebacks 1 # number of writebacks
-system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses 156 # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses 109 # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses 51 # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses 265 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses 265 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency 2059000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency 1757000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency 152000 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency 3816000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency 3816000 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003728 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate 0.006802 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate 0.822581 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate 0.004579 # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate 0.004579 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 13198.717949 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16119.266055 # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 2980.392157 # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency 14400 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency 14400 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks
+system.cpu2.dcache.writebacks::total 1 # number of writebacks
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 156 # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses
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+system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
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+system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2059000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2059000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1757000 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1757000 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3816000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.numCycles 524596 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.num_insts 166130 # Number of instructions executed
+system.cpu3.committedInsts 166130 # Number of instructions committed
+system.cpu3.committedOps 166130 # Number of ops (including micro ops) committed
system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu3.num_func_calls 637 # number of times a function call or return occured
@@ -503,26 +613,39 @@ system.cpu3.icache.total_refs 165796 # To
system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs 451.760218 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::0 67.737646 # Average occupied blocks per context
-system.cpu3.icache.occ_percent::0 0.132300 # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits 165796 # number of ReadReq hits
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-system.cpu3.icache.overall_hits 165796 # number of overall hits
-system.cpu3.icache.ReadReq_misses 367 # number of ReadReq misses
-system.cpu3.icache.demand_misses 367 # number of demand (read+write) misses
-system.cpu3.icache.overall_misses 367 # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency 5531500 # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency 5531500 # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency 5531500 # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses 166163 # number of ReadReq accesses(hits+misses)
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-system.cpu3.icache.overall_accesses 166163 # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate 0.002209 # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate 0.002209 # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate 0.002209 # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency 15072.207084 # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency 15072.207084 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency 15072.207084 # average overall miss latency
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+system.cpu3.icache.occ_percent::total 0.132300 # Average percentage of cache occupancy
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+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5531500 # number of ReadReq miss cycles
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+system.cpu3.icache.overall_miss_latency::total 5531500 # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst 166163 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total 166163 # number of ReadReq accesses(hits+misses)
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+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -531,67 +654,84 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
-system.cpu3.icache.writebacks 0 # number of writebacks
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-system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
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-system.cpu3.icache.demand_mshr_misses 367 # number of demand (read+write) MSHR misses
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-system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu3.icache.ReadReq_mshr_miss_latency 4430500 # number of ReadReq MSHR miss cycles
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-system.cpu3.icache.overall_mshr_miss_latency 4430500 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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-system.cpu3.icache.ReadReq_avg_mshr_miss_latency 12072.207084 # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency 12072.207084 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency 12072.207084 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.replacements 2 # number of replacements
-system.cpu3.dcache.tagsinuse 22.083417 # Cycle average of tags in use
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system.cpu3.dcache.total_refs 33474 # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs 32 # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs 1046.062500 # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.dcache.ReadReq_miss_latency 2569000 # number of ReadReq miss cycles
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-system.cpu3.dcache.ReadReq_miss_rate 0.003764 # miss rate for ReadReq accesses
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-system.cpu3.dcache.ReadReq_avg_miss_latency 16363.057325 # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency 19259.259259 # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency 6037.037037 # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency 17543.396226 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency 17543.396226 # average overall miss latency
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system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -600,34 +740,38 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
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system.l2c.replacements 0 # number of replacements
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@@ -635,142 +779,231 @@ system.l2c.total_refs 1223 # To
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@@ -779,55 +1012,162 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------