diff options
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref')
6 files changed, 2768 insertions, 2802 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 51784eba5..b2cdd54e1 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,82 +1,82 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:14 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:10 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done -[Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 1, Thread 2] Got lock +[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 Iteration 1 completed -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 Iteration 2 completed -[Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 3, Thread 2] Got lock [Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 Iteration 3 completed +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 4, Thread 2] Got lock [Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 Iteration 4 completed +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 5, Thread 1] Got lock [Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 Iteration 5 completed -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 Iteration 6 completed [Iteration 7, Thread 1] Got lock [Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 Iteration 7 completed [Iteration 8, Thread 2] Got lock [Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed -[Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 1] Got lock [Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 9, Thread 3] Got lock +[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 Iteration 9 completed -[Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 10, Thread 2] Got lock [Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 111402500 because target called exit() +Exiting @ tick 111594500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 1590e3eee..ea1876230 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,191 +1,191 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000111 # Number of seconds simulated -sim_ticks 111402500 # Number of ticks simulated -final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000112 # Number of seconds simulated +sim_ticks 111594500 # Number of ticks simulated +final_tick 111594500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133234 # Simulator instruction rate (inst/s) -host_op_rate 133234 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13628365 # Simulator tick rate (ticks/s) -host_mem_usage 236536 # Number of bytes of host memory used -host_seconds 8.17 # Real time elapsed on the host -sim_insts 1089093 # Number of instructions simulated -sim_ops 1089093 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 23232 # Number of bytes read from this memory +host_inst_rate 200629 # Simulator instruction rate (inst/s) +host_op_rate 200629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20568067 # Simulator tick rate (ticks/s) +host_mem_usage 235024 # Number of bytes of host memory used +host_seconds 5.43 # Real time elapsed on the host +sim_insts 1088531 # Number of instructions simulated +sim_ops 1088531 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 5120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 43072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 5120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29312 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 363 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29120 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 80 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 88 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 673 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 208541101 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 97089383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 8042907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7468414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 45959471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 11489868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 574493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7468414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 386634052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 208541101 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 8042907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 45959471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 574493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 263117973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 208541101 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 97089383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 8042907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7468414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 45959471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 11489868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 574493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7468414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 386634052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 670 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 207035293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 96922339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50468437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11470099 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1147010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7455565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2294020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7455565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 384248328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 207035293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50468437 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1147010 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2294020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 260944760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 207035293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 96922339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50468437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11470099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1147010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7455565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2294020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7455565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 384248328 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 222806 # number of cpu cycles simulated +system.cpu0.numCycles 223190 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 87253 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 84917 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1303 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 84794 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 82358 # Number of BTB hits +system.cpu0.BPredUnit.lookups 87370 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 85036 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1313 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 84895 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 82517 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 518 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 17579 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 517995 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 87253 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 82876 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 170053 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3992 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13261 # Number of cycles fetch has spent blocked +system.cpu0.BPredUnit.usedRAS 514 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 17415 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 518858 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 87370 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 83031 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 170328 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 4037 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13330 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1318 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6218 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 521 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 204756 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.529816 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.210666 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1404 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6152 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 508 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 205057 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.530311 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.210840 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34703 16.95% 16.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 84234 41.14% 58.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 594 0.29% 58.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 959 0.47% 58.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 591 0.29% 59.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 80169 39.15% 98.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 594 0.29% 98.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 373 0.18% 98.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2539 1.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34729 16.94% 16.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 84380 41.15% 58.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 595 0.29% 58.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 973 0.47% 58.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 523 0.26% 59.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 80298 39.16% 98.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 656 0.32% 98.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 373 0.18% 98.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2530 1.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 204756 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.391610 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.324870 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18003 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14874 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 169024 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 315 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2540 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 515001 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2540 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18709 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 1371 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12822 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 168665 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 649 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 511590 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 205057 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.391460 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.324737 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18107 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14779 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 169274 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 322 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2575 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 515764 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2575 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18814 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1415 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12654 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 168925 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 674 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 512400 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 235 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 349678 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1020456 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 1020456 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 335896 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13782 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 911 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 939 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4054 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 163918 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 82754 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 79985 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 79744 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 427655 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 948 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 424795 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 156 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11264 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 10234 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 204756 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.074640 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.085274 # Number of insts issued each cycle +system.cpu0.rename.LSQFullEvents 252 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 350257 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1022076 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 1022076 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 336320 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13937 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 921 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 951 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4116 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 164196 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 82879 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 80125 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 79869 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 428350 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 958 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 425359 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 176 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11411 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 10569 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 399 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 205057 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.074345 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.084750 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33869 16.54% 16.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5212 2.55% 19.09% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 81806 39.95% 59.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 81161 39.64% 98.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1586 0.77% 99.45% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 710 0.35% 99.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 306 0.15% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33897 16.53% 16.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5266 2.57% 19.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 81920 39.95% 59.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 81274 39.63% 98.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1599 0.78% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 693 0.34% 99.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 302 0.15% 99.95% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 90 0.04% 99.99% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 204756 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 205057 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 53 21.81% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 78 32.10% 53.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 46.09% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 54 22.69% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 72 30.25% 52.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 47.06% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 179222 42.19% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 179447 42.19% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued @@ -214,159 +214,159 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 163383 38.46% 80.65% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82190 19.35% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 163633 38.47% 80.66% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82279 19.34% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 424795 # Type of FU issued -system.cpu0.iq.rate 1.906569 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 243 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000572 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1054745 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 439928 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 422836 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 425359 # Type of FU issued +system.cpu0.iq.rate 1.905816 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 238 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000560 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1056189 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 440777 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 423418 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 425038 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 425597 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 79492 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 79599 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2386 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2452 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 61 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 58 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2540 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 996 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 509141 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 346 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 163918 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 82754 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 837 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2575 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1020 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 509980 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 329 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 164196 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 82879 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 61 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 382 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1141 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1523 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 423658 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 163081 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1137 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 368 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1157 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1525 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 424238 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 163317 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1121 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 80538 # number of nop insts executed -system.cpu0.iew.exec_refs 245123 # number of memory reference insts executed -system.cpu0.iew.exec_branches 84187 # Number of branches executed -system.cpu0.iew.exec_stores 82042 # Number of stores executed -system.cpu0.iew.exec_rate 1.901466 # Inst execution rate -system.cpu0.iew.wb_sent 423189 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 422836 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 250585 # num instructions producing a value -system.cpu0.iew.wb_consumers 253105 # num instructions consuming a value +system.cpu0.iew.exec_nop 80672 # number of nop insts executed +system.cpu0.iew.exec_refs 245449 # number of memory reference insts executed +system.cpu0.iew.exec_branches 84313 # Number of branches executed +system.cpu0.iew.exec_stores 82132 # Number of stores executed +system.cpu0.iew.exec_rate 1.900793 # Inst execution rate +system.cpu0.iew.wb_sent 423777 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 423418 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 250898 # num instructions producing a value +system.cpu0.iew.wb_consumers 253433 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.897777 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.990044 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.897119 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989997 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 496189 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 496189 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 12929 # The number of squashed insts skipped by commit +system.cpu0.commit.commitCommittedInsts 496825 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 496825 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 13135 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1303 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 202233 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.453551 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.134267 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1313 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 202499 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.453469 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.133222 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34442 17.03% 17.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 83893 41.48% 58.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2396 1.18% 59.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 690 0.34% 60.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 548 0.27% 60.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 79225 39.18% 99.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 480 0.24% 99.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 235 0.12% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 324 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34446 17.01% 17.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 84010 41.49% 58.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2422 1.20% 59.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 711 0.35% 60.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 562 0.28% 60.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 79343 39.18% 99.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 465 0.23% 99.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 235 0.12% 99.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 305 0.15% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 202233 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 496189 # Number of instructions committed -system.cpu0.commit.committedOps 496189 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 202499 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 496825 # Number of instructions committed +system.cpu0.commit.committedOps 496825 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 242804 # Number of memory references committed -system.cpu0.commit.loads 161532 # Number of loads committed +system.cpu0.commit.refs 243122 # Number of memory references committed +system.cpu0.commit.loads 161744 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 83160 # Number of branches committed +system.cpu0.commit.branches 83266 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 334226 # Number of committed integer instructions. +system.cpu0.commit.int_insts 334650 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 324 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 305 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 709866 # The number of ROB reads -system.cpu0.rob.rob_writes 1020791 # The number of ROB writes -system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 18050 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 416214 # Number of Instructions Simulated -system.cpu0.committedOps 416214 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 416214 # Number of Instructions Simulated -system.cpu0.cpi 0.535316 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.535316 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.868056 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.868056 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 757980 # number of integer regfile reads -system.cpu0.int_regfile_writes 341432 # number of integer regfile writes +system.cpu0.rob.rob_reads 710993 # The number of ROB reads +system.cpu0.rob.rob_writes 1022511 # The number of ROB writes +system.cpu0.timesIdled 324 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 18133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 416744 # Number of Instructions Simulated +system.cpu0.committedOps 416744 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 416744 # Number of Instructions Simulated +system.cpu0.cpi 0.535557 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.535557 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.867216 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.867216 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 758967 # number of integer regfile reads +system.cpu0.int_regfile_writes 341941 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 246952 # number of misc regfile reads +system.cpu0.misc_regfile_reads 247293 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 300 # number of replacements -system.cpu0.icache.tagsinuse 248.673809 # Cycle average of tags in use -system.cpu0.icache.total_refs 5459 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 593 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.205734 # Average number of references to valid blocks. +system.cpu0.icache.replacements 307 # number of replacements +system.cpu0.icache.tagsinuse 248.147409 # Cycle average of tags in use +system.cpu0.icache.total_refs 5393 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 598 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.018395 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 248.673809 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.485691 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.485691 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5459 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5459 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5459 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5459 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5459 # number of overall hits -system.cpu0.icache.overall_hits::total 5459 # number of overall hits +system.cpu0.icache.occ_blocks::cpu0.inst 248.147409 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.484663 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.484663 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5393 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5393 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5393 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5393 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5393 # number of overall hits +system.cpu0.icache.overall_hits::total 5393 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 759 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 759 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 759 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 759 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 759 # number of overall misses system.cpu0.icache.overall_misses::total 759 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29159500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 29159500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 29159500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 29159500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 29159500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 29159500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6218 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6218 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6218 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6218 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6218 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6218 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122065 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.122065 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122065 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.122065 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122065 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.122065 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38418.313570 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38418.313570 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38418.313570 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 28913000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28913000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 28913000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28913000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 28913000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28913000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6152 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6152 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6152 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6152 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6152 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6152 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123375 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.123375 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123375 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.123375 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123375 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.123375 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38093.544137 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38093.544137 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38093.544137 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38093.544137 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38093.544137 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38093.544137 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -375,106 +375,106 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 594 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 594 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 594 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 594 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 594 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 594 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21891000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21891000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21891000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21891000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21891000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21891000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.095529 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.095529 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.095529 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36853.535354 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 160 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 160 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 160 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 160 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 160 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 160 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 599 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 599 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 599 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 599 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21855500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21855500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21855500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21855500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21855500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21855500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097367 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.097367 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.097367 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36486.644407 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36486.644407 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36486.644407 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 8 # number of replacements -system.cpu0.dcache.tagsinuse 141.285775 # Cycle average of tags in use -system.cpu0.dcache.total_refs 100453 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 577.316092 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 2 # number of replacements +system.cpu0.dcache.tagsinuse 144.541703 # Cycle average of tags in use +system.cpu0.dcache.total_refs 163878 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 171 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 958.350877 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 141.285775 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.275949 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.275949 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 83026 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83026 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80684 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80684 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 163710 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 163710 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 163710 # number of overall hits -system.cpu0.dcache.overall_hits::total 163710 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 495 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 495 # number of ReadReq misses +system.cpu0.dcache.occ_blocks::cpu0.data 144.541703 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.282308 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.282308 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 83150 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 83150 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80790 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80790 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 163940 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 163940 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 163940 # number of overall hits +system.cpu0.dcache.overall_hits::total 163940 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 500 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 500 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1041 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1041 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1041 # number of overall misses -system.cpu0.dcache.overall_misses::total 1041 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13976000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13976000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24361986 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24361986 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 380500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 380500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38337986 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38337986 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38337986 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38337986 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83521 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83521 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81230 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81230 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1046 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1046 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1046 # number of overall misses +system.cpu0.dcache.overall_misses::total 1046 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13780500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13780500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24368986 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24368986 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 390500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 38149486 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 38149486 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 38149486 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 38149486 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 83650 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 83650 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81336 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81336 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 164751 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 164751 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164751 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 164751 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005927 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005927 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006722 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006722 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006319 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006319 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006319 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006319 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28234.343434 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28234.343434 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44619.021978 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44619.021978 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19025 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36828.036503 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36828.036503 # average overall miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 164986 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 164986 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 164986 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 164986 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005977 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005977 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006713 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006713 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006340 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006340 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006340 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006340 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27561 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27561 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44631.842491 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44631.842491 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18595.238095 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 18595.238095 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36471.783939 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36471.783939 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36471.783939 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36471.783939 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -483,476 +483,476 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks -system.cpu0.dcache.writebacks::total 6 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 313 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 683 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 683 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 176 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4954500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4954500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6250000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6250000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11204500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11204500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11204500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11204500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002179 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002179 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002167 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002167 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002173 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002173 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27222.527473 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27222.527473 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35511.363636 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35511.363636 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16025 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16025 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 320 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 320 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 371 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 371 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 691 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 691 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 691 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 691 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 180 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 355 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 355 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6275500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6275500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 327500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 327500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11208500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11208500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11208500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11208500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002152 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002152 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002152 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002152 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27405.555556 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27405.555556 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35860 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35860 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 15595.238095 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15595.238095 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31573.239437 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31573.239437 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31573.239437 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31573.239437 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 187393 # number of cpu cycles simulated +system.cpu1.numCycles 187839 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 57495 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 54509 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1432 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 50945 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 49902 # Number of BTB hits +system.cpu1.BPredUnit.lookups 50940 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 47890 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1510 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 44289 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 43310 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 759 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 829 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 28506 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 323137 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 57495 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 50661 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 112599 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4204 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 33253 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 31688 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 280910 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 50940 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 44139 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 100869 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4392 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 39081 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6513 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 19809 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 184628 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.750206 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.168540 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 6575 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1045 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 22757 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 182067 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.542894 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.098462 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 72029 39.01% 39.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 57027 30.89% 69.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6026 3.26% 73.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3313 1.79% 74.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 681 0.37% 75.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 39928 21.63% 96.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1176 0.64% 97.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 885 0.48% 98.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3563 1.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 81198 44.60% 44.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 51887 28.50% 73.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7438 4.09% 77.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3280 1.80% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 684 0.38% 79.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 31924 17.53% 96.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1209 0.66% 97.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 879 0.48% 98.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3568 1.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 184628 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.306815 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.724381 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 34082 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 29678 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 106549 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 5112 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2694 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 318863 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2694 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 34823 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 15756 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13064 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 101771 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 10007 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 316589 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 26 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 63 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 221379 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 610170 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 610170 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 206274 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15105 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1171 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1292 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 12551 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 90746 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 43396 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 43483 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 38230 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 262560 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6300 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 264126 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12570 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11522 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 184628 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.430585 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.313833 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 182067 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.271190 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.495483 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 38413 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 34373 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 93637 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 6265 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2804 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 276803 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2804 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 39183 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19194 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14318 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 87661 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 12332 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 274424 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 52 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 191179 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 520245 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 520245 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 175779 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15400 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1221 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1348 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 15085 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 76182 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 35431 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 36807 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 30214 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 225638 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 7711 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 228522 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12774 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11561 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 762 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 182067 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.255153 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.306407 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 69552 37.67% 37.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 22561 12.22% 49.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43412 23.51% 73.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 44019 23.84% 97.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3358 1.82% 99.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1272 0.69% 99.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 343 0.19% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 78861 43.31% 43.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 26436 14.52% 57.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 35607 19.56% 77.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 36159 19.86% 97.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3279 1.80% 99.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1252 0.69% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 353 0.19% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 59 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 184628 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 182067 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 21 6.65% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 85 26.90% 33.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 66.46% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 20 6.62% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 72 23.84% 30.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 69.54% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 126488 47.89% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 94921 35.94% 83.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 42717 16.17% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 112122 49.06% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 81642 35.73% 84.79% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 34758 15.21% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 264126 # Type of FU issued -system.cpu1.iq.rate 1.409476 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 316 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 713260 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 281477 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 262161 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 228522 # Type of FU issued +system.cpu1.iq.rate 1.216584 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 302 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001322 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 639493 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 246163 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 226488 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 264442 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 228824 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 37998 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 30049 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2692 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1591 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2733 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1566 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2694 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1681 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 313238 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 386 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 90746 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 43396 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2804 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1582 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 271136 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 377 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 76182 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 35431 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1144 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 47 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1109 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1593 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 262830 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 89694 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1296 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 494 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1182 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1676 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 227186 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 75112 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1336 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 44378 # number of nop insts executed -system.cpu1.iew.exec_refs 132319 # number of memory reference insts executed -system.cpu1.iew.exec_branches 53738 # Number of branches executed -system.cpu1.iew.exec_stores 42625 # Number of stores executed -system.cpu1.iew.exec_rate 1.402560 # Inst execution rate -system.cpu1.iew.wb_sent 262446 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 262161 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 149144 # num instructions producing a value -system.cpu1.iew.wb_consumers 154061 # num instructions consuming a value +system.cpu1.iew.exec_nop 37787 # number of nop insts executed +system.cpu1.iew.exec_refs 109780 # number of memory reference insts executed +system.cpu1.iew.exec_branches 47145 # Number of branches executed +system.cpu1.iew.exec_stores 34668 # Number of stores executed +system.cpu1.iew.exec_rate 1.209472 # Inst execution rate +system.cpu1.iew.wb_sent 226789 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 226488 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 126631 # num instructions producing a value +system.cpu1.iew.wb_consumers 131515 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.398990 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.968084 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.205756 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.962864 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 298843 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 298843 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 14389 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5646 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1432 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 175422 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.703566 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.044466 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 256347 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 256347 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 14788 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 6949 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1510 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 172689 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.484443 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.966336 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 68710 39.17% 39.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 51651 29.44% 68.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6180 3.52% 72.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6549 3.73% 75.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1541 0.88% 76.75% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 38344 21.86% 98.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 640 0.36% 98.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 812 0.46% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 79222 45.88% 45.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 45065 26.10% 71.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6173 3.57% 75.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 7849 4.55% 80.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1517 0.88% 80.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 30495 17.66% 98.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 550 0.32% 98.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 998 0.58% 99.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 820 0.47% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 175422 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 298843 # Number of instructions committed -system.cpu1.commit.committedOps 298843 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 172689 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 256347 # Number of instructions committed +system.cpu1.commit.committedOps 256347 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 129859 # Number of memory references committed -system.cpu1.commit.loads 88054 # Number of loads committed -system.cpu1.commit.membars 4938 # Number of memory barriers committed -system.cpu1.commit.branches 52708 # Number of branches committed +system.cpu1.commit.refs 107314 # Number of memory references committed +system.cpu1.commit.loads 73449 # Number of loads committed +system.cpu1.commit.membars 6235 # Number of memory barriers committed +system.cpu1.commit.branches 46061 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 204694 # Number of committed integer instructions. +system.cpu1.commit.int_insts 175498 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 820 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 487255 # The number of ROB reads -system.cpu1.rob.rob_writes 629168 # The number of ROB writes +system.cpu1.rob.rob_reads 442417 # The number of ROB reads +system.cpu1.rob.rob_writes 545088 # The number of ROB writes system.cpu1.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2765 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 35411 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 250401 # Number of Instructions Simulated -system.cpu1.committedOps 250401 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 250401 # Number of Instructions Simulated -system.cpu1.cpi 0.748372 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.748372 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.336235 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.336235 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 456552 # number of integer regfile reads -system.cpu1.int_regfile_writes 212248 # number of integer regfile writes +system.cpu1.idleCycles 5772 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 35349 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 213261 # Number of Instructions Simulated +system.cpu1.committedOps 213261 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 213261 # Number of Instructions Simulated +system.cpu1.cpi 0.880794 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.880794 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.135339 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.135339 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 389025 # number of integer regfile reads +system.cpu1.int_regfile_writes 181950 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 133945 # number of misc regfile reads +system.cpu1.misc_regfile_reads 111436 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 322 # number of replacements -system.cpu1.icache.tagsinuse 82.769076 # Cycle average of tags in use -system.cpu1.icache.total_refs 19304 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 435 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 44.377011 # Average number of references to valid blocks. +system.cpu1.icache.replacements 321 # number of replacements +system.cpu1.icache.tagsinuse 92.166456 # Cycle average of tags in use +system.cpu1.icache.total_refs 22247 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 51.025229 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 82.769076 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.161658 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.161658 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19304 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19304 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19304 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19304 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19304 # number of overall hits -system.cpu1.icache.overall_hits::total 19304 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 505 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 505 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 505 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 505 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 505 # number of overall misses -system.cpu1.icache.overall_misses::total 505 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7500500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7500500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7500500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7500500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7500500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7500500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19809 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19809 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19809 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19809 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19809 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19809 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025493 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.025493 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025493 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.025493 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.025493 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14852.475248 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14852.475248 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14852.475248 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 92.166456 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.180013 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.180013 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 22247 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22247 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22247 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22247 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22247 # number of overall hits +system.cpu1.icache.overall_hits::total 22247 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 510 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 510 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 510 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 510 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 510 # number of overall misses +system.cpu1.icache.overall_misses::total 510 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11347500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 11347500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 11347500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 11347500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 11347500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 11347500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 22757 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 22757 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 22757 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 22757 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 22757 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 22757 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022411 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022411 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022411 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022411 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022411 # miss rate for overall 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70 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 435 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 435 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 435 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 435 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 435 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 435 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5474500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5474500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5474500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5474500 # number of demand (read+write) MSHR miss cycles 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-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 319 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 364 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 364 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2052000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2052000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1523500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1523500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 888500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 888500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3575500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3575500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3575500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3575500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003019 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003019 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002611 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002837 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002837 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13153.846154 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13153.846154 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13977.064220 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13977.064220 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17770 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17770 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 266 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 47 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 313 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 313 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 313 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 313 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 159 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2405000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2405000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1693500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1693500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1063000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1063000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4098500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4098500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4098500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4098500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003530 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003166 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003166 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.764706 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.764706 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003374 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003374 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003374 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003374 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15125.786164 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15125.786164 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15827.102804 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15827.102804 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20442.307692 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20442.307692 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15407.894737 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15407.894737 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15407.894737 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15407.894737 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 187102 # number of cpu cycles simulated +system.cpu2.numCycles 187552 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 52366 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 49346 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1501 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 45884 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 44697 # Number of BTB hits +system.cpu2.BPredUnit.lookups 49236 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 46105 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1532 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 42466 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 41429 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 764 # Number of times the RAS was used to get a target. -system.cpu2.BPredUnit.RASInCorrect 230 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 30829 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 289891 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 52366 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 45461 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 103159 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4491 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 37226 # Number of cycles fetch has spent blocked +system.cpu2.BPredUnit.usedRAS 825 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. +system.cpu2.fetch.icacheStallCycles 33274 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 268508 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 49236 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 42254 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 98143 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4464 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 42536 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6501 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1096 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 21870 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 331 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 181728 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.595192 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.120038 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6571 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1082 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 24716 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 184466 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.455596 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.059567 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 78569 43.23% 43.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 52779 29.04% 72.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6971 3.84% 76.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3518 1.94% 78.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 702 0.39% 78.44% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 33444 18.40% 96.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1229 0.68% 97.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 914 0.50% 98.02% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3602 1.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 86323 46.80% 46.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 50944 27.62% 74.41% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8337 4.52% 78.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3301 1.79% 80.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 755 0.41% 81.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 29086 15.77% 96.90% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1170 0.63% 97.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 883 0.48% 98.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3667 1.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 181728 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.279879 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.549374 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 37176 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 32970 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 96308 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5861 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2912 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 285362 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2912 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 37970 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 18336 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13742 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 90714 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 11553 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 283108 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 197373 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 538438 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 538438 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 181356 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 16017 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1308 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 14181 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 79045 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 36977 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 38155 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 31746 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 233020 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 7475 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 234915 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13691 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12875 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 913 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 181728 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.292674 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.310296 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 184466 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.262519 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.431646 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 41063 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 36807 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 89946 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 7224 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2855 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 264281 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2855 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 41843 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 22202 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13743 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 82992 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14260 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 261668 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 57 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 181221 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 490993 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 490993 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 165322 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 15899 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1233 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1350 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 17036 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 71489 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 32632 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 34884 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 27362 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 213682 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 8649 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 217360 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13263 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11908 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 765 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 184466 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.178320 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.292872 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 76657 42.18% 42.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 25237 13.89% 56.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 37132 20.43% 76.50% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 37732 20.76% 97.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3274 1.80% 99.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1229 0.68% 99.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 84063 45.57% 45.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 29277 15.87% 61.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 32764 17.76% 79.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 33297 18.05% 97.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3312 1.80% 99.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1277 0.69% 99.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 362 0.20% 99.94% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 181728 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 184466 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 21 6.69% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 83 26.43% 33.12% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 66.88% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 20 6.64% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 71 23.59% 30.23% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 114779 48.86% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 83862 35.70% 84.56% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 36274 15.44% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 107542 49.48% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 77871 35.83% 85.30% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 31947 14.70% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 234915 # Type of FU issued -system.cpu2.iq.rate 1.255545 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 314 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001337 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 651945 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 254231 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 232815 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 217360 # Type of FU issued +system.cpu2.iq.rate 1.158932 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001385 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 619541 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 235636 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 215243 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 235229 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 217661 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 31545 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 27206 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 3013 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2801 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1611 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1615 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2912 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1924 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 279572 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 79045 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 36977 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1114 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 62 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2855 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1726 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 258195 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 386 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 71489 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 32632 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 517 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1138 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1655 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 233532 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 77718 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1383 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1199 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1712 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 215982 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 70400 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1378 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 39077 # number of nop insts executed -system.cpu2.iew.exec_refs 113896 # number of memory reference insts executed -system.cpu2.iew.exec_branches 48223 # Number of branches executed -system.cpu2.iew.exec_stores 36178 # Number of stores executed -system.cpu2.iew.exec_rate 1.248153 # Inst execution rate -system.cpu2.iew.wb_sent 233124 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 232815 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 130712 # num instructions producing a value -system.cpu2.iew.wb_consumers 135609 # num instructions consuming a value +system.cpu2.iew.exec_nop 35864 # number of nop insts executed +system.cpu2.iew.exec_refs 102255 # number of memory reference insts executed +system.cpu2.iew.exec_branches 45260 # Number of branches executed +system.cpu2.iew.exec_stores 31855 # Number of stores executed +system.cpu2.iew.exec_rate 1.151585 # Inst execution rate +system.cpu2.iew.wb_sent 215555 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 215243 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 119078 # num instructions producing a value +system.cpu2.iew.wb_consumers 124002 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.244321 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.963889 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.147644 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.960291 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitCommittedInsts 263733 # The number of committed instructions -system.cpu2.commit.commitCommittedOps 263733 # The number of committed instructions -system.cpu2.commit.commitSquashedInsts 15844 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 6562 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1501 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 172316 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.530520 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.983884 # Number of insts commited each cycle +system.cpu2.commit.commitCommittedInsts 242999 # The number of committed instructions +system.cpu2.commit.commitCommittedOps 242999 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 15188 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7884 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1532 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 175041 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.388240 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.921152 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 76563 44.43% 44.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 46194 26.81% 71.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6230 3.62% 74.85% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 7466 4.33% 79.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1536 0.89% 80.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 32043 18.60% 98.67% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 480 0.28% 98.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 990 0.57% 99.53% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 85384 48.78% 48.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 43145 24.65% 73.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6226 3.56% 76.98% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 8763 5.01% 81.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1523 0.87% 82.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 27601 15.77% 98.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 589 0.34% 98.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 998 0.57% 99.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 812 0.46% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 172316 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 263733 # Number of instructions committed -system.cpu2.commit.committedOps 263733 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 175041 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 242999 # Number of instructions committed +system.cpu2.commit.committedOps 242999 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 111398 # Number of memory references committed -system.cpu2.commit.loads 76032 # Number of loads committed -system.cpu2.commit.membars 5840 # Number of memory barriers committed -system.cpu2.commit.branches 47167 # Number of branches committed +system.cpu2.commit.refs 99705 # Number of memory references committed +system.cpu2.commit.loads 68688 # Number of loads committed +system.cpu2.commit.membars 7170 # Number of memory barriers committed +system.cpu2.commit.branches 44148 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 180680 # Number of committed integer instructions. +system.cpu2.commit.int_insts 165976 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 814 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 450492 # The number of ROB reads -system.cpu2.rob.rob_writes 562082 # The number of ROB writes -system.cpu2.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5374 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 35702 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 219944 # Number of Instructions Simulated -system.cpu2.committedOps 219944 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 219944 # Number of Instructions Simulated -system.cpu2.cpi 0.850680 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.850680 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.175530 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.175530 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 401453 # number of integer regfile reads -system.cpu2.int_regfile_writes 187612 # number of integer regfile writes +system.cpu2.rob.rob_reads 431829 # The number of ROB reads +system.cpu2.rob.rob_writes 519243 # The number of ROB writes +system.cpu2.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3086 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 35636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 200891 # Number of Instructions Simulated +system.cpu2.committedOps 200891 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 200891 # Number of Instructions Simulated +system.cpu2.cpi 0.933601 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.933601 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.071122 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.071122 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 366578 # number of integer regfile reads +system.cpu2.int_regfile_writes 171642 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 115545 # number of misc regfile reads +system.cpu2.misc_regfile_reads 103931 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 325 # number of replacements -system.cpu2.icache.tagsinuse 91.851117 # Cycle average of tags in use -system.cpu2.icache.total_refs 21358 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 440 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 48.540909 # Average number of references to valid blocks. +system.cpu2.icache.replacements 324 # number of replacements +system.cpu2.icache.tagsinuse 83.306019 # Cycle average of tags in use +system.cpu2.icache.total_refs 24210 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 55.273973 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 91.851117 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.179397 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.179397 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 21358 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 21358 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 21358 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 21358 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 21358 # number of overall hits -system.cpu2.icache.overall_hits::total 21358 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 512 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 512 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 512 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 512 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 512 # number of overall misses -system.cpu2.icache.overall_misses::total 512 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11141500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 11141500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 11141500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 11141500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 11141500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 11141500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 21870 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 21870 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 21870 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 21870 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 21870 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 21870 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023411 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.023411 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023411 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.023411 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023411 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.023411 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 21760.742188 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 21760.742188 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 21760.742188 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked +system.cpu2.icache.occ_blocks::cpu2.inst 83.306019 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.162707 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.162707 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 24210 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 24210 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 24210 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 24210 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 24210 # number of overall hits +system.cpu2.icache.overall_hits::total 24210 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 506 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 506 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 506 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 506 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 506 # number of overall misses +system.cpu2.icache.overall_misses::total 506 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7060500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7060500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7060500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7060500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7060500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7060500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 24716 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 24716 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 24716 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 24716 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 24716 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 24716 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.020473 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.020473 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.020473 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.020473 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.020473 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.020473 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13953.557312 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13953.557312 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13953.557312 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13953.557312 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13953.557312 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13953.557312 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 72 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 72 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 72 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 72 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 440 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 440 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 440 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 440 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 440 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 440 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 8467000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 8467000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 8467000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 8467000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8467000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 8467000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.020119 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.020119 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.020119 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19243.181818 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 19243.181818 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 19243.181818 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 438 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 438 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5136000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5136000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5136000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5136000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5136000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5136000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017721 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.017721 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.017721 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11726.027397 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 11726.027397 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 11726.027397 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 26.720433 # Cycle average of tags in use -system.cpu2.dcache.total_refs 41712 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1345.548387 # Average number of references to valid blocks. +system.cpu2.dcache.replacements 0 # number of replacements +system.cpu2.dcache.tagsinuse 24.973314 # Cycle average of tags in use +system.cpu2.dcache.total_refs 37203 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1328.678571 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 26.720433 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.052188 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.052188 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 45716 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 45716 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 35144 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 35144 # number of WriteReq hits +system.cpu2.dcache.occ_blocks::cpu2.data 24.973314 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.048776 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.048776 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42731 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42731 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 30798 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 30798 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 80860 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 80860 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 80860 # number of overall hits -system.cpu2.dcache.overall_hits::total 80860 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 438 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 438 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 146 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 146 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 62 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 62 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 584 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 584 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 584 # number of overall misses -system.cpu2.dcache.overall_misses::total 584 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10255000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 10255000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2937000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2937000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1181000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 1181000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 13192000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 13192000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 46154 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 46154 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 35290 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 35290 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 76 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 81444 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 81444 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 81444 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 81444 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009490 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009490 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004137 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004137 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.815789 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.815789 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007171 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007171 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007171 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007171 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23413.242009 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 23413.242009 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 20116.438356 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 19048.387097 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 22589.041096 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 22589.041096 # average overall miss latency +system.cpu2.dcache.demand_hits::cpu2.data 73529 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 73529 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 73529 # number of overall hits +system.cpu2.dcache.overall_hits::total 73529 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 443 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 443 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 151 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 151 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 594 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 594 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 594 # number of overall misses +system.cpu2.dcache.overall_misses::total 594 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9862000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 9862000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2806000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2806000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1173500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 1173500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 12668000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 12668000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 12668000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 12668000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 43174 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 43174 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 30949 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 30949 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 74123 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 74123 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 74123 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 74123 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010261 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010261 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004879 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004879 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794118 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008014 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.008014 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008014 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.008014 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22261.851016 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 22261.851016 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18582.781457 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 18582.781457 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21731.481481 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 21731.481481 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 21326.599327 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 21326.599327 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 21326.599327 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 21326.599327 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1439,368 +1437,366 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu2.dcache.writebacks::total 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 267 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 45 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 312 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 312 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 312 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 312 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 171 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 62 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 62 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 272 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 272 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2480000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2480000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1516500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1516500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 995000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 995000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3996500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3996500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3996500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3996500 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003705 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003705 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002862 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002862 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.815789 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.815789 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003340 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003340 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14502.923977 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14502.923977 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15014.851485 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15014.851485 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 16048.387097 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 16048.387097 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 279 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 47 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 326 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 326 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 164 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2336000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2336000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1419000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1419000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1011500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1011500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3755000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3755000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3755000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3755000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003799 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003799 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003360 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003360 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794118 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003616 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003616 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003616 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003616 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14243.902439 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14243.902439 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13644.230769 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13644.230769 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18731.481481 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18731.481481 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14011.194030 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14011.194030 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14011.194030 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14011.194030 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 186832 # number of cpu cycles simulated +system.cpu3.numCycles 187286 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 49447 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 46344 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 42752 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 41712 # Number of BTB hits +system.cpu3.BPredUnit.lookups 59110 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 55955 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1573 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 52456 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 51388 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 813 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 831 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 32933 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 270157 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 49447 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 42525 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 98584 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4439 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 41922 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 27555 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 332776 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 59110 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 52219 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 115081 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4575 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 31846 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6509 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24454 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 183862 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.469347 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.064581 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6567 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 1060 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 19062 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 185045 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.798352 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.183167 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 85278 46.38% 46.38% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 51117 27.80% 74.18% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8231 4.48% 78.66% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3382 1.84% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 704 0.38% 80.88% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 29457 16.02% 96.90% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1168 0.64% 97.54% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 877 0.48% 98.02% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3648 1.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 69964 37.81% 37.81% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 58012 31.35% 69.16% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 5498 2.97% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3553 1.92% 74.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 717 0.39% 74.44% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 41629 22.50% 96.93% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1211 0.65% 97.59% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 858 0.46% 98.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3603 1.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 183862 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.264660 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.445989 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 40520 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 36424 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 90525 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7045 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2839 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 265643 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2839 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 41308 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 21637 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13915 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 83785 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 13869 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 263122 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 51 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 182223 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 494224 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 494224 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 166723 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 15500 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1230 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1367 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 16602 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 72088 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 32971 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 35168 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 27743 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 215022 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8560 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 218529 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12998 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11805 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 824 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 183862 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.188549 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.293380 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 185045 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.315614 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.776833 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 32638 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 28853 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 109537 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4519 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2931 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 328437 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2931 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 33475 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 14026 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13970 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 105232 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 8844 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 325744 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 59 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 228226 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 629601 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 629601 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 212325 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 15901 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1261 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1383 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 11670 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 93735 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 45116 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 44692 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 39822 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 270564 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6038 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 271349 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 13410 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 12382 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 838 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 185045 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.466395 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.313251 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 83207 45.26% 45.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 28783 15.65% 60.91% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 33187 18.05% 78.96% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 33716 18.34% 97.30% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3245 1.76% 99.06% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1264 0.69% 99.75% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 67828 36.65% 36.65% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 21223 11.47% 48.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 45218 24.44% 72.56% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 45760 24.73% 97.29% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3300 1.78% 99.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1261 0.68% 99.75% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 183862 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 185045 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 21 7.02% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 68 22.74% 29.77% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 21 6.80% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 78 25.24% 32.04% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 67.96% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 107929 49.39% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 78286 35.82% 85.21% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 32314 14.79% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 129621 47.77% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 97351 35.88% 83.65% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 44377 16.35% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 218529 # Type of FU issued -system.cpu3.iq.rate 1.169655 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 299 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001368 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 621265 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 236621 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 216530 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 271349 # Type of FU issued +system.cpu3.iq.rate 1.448848 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001139 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 728169 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 290051 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 269261 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 218828 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 271658 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 27592 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 39639 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2778 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2895 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1562 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1672 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2839 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1746 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 259780 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 72088 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 32971 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2931 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1690 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 322365 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 93735 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 45116 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1181 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 62 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1186 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1699 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 217228 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 70964 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1301 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 528 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1218 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1746 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 269989 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 92559 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1360 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 36198 # number of nop insts executed -system.cpu3.iew.exec_refs 103196 # number of memory reference insts executed -system.cpu3.iew.exec_branches 45494 # Number of branches executed -system.cpu3.iew.exec_stores 32232 # Number of stores executed -system.cpu3.iew.exec_rate 1.162692 # Inst execution rate -system.cpu3.iew.wb_sent 216841 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 216530 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 119982 # num instructions producing a value -system.cpu3.iew.wb_consumers 124874 # num instructions consuming a value +system.cpu3.iew.exec_nop 45763 # number of nop insts executed +system.cpu3.iew.exec_refs 136843 # number of memory reference insts executed +system.cpu3.iew.exec_branches 55022 # Number of branches executed +system.cpu3.iew.exec_stores 44284 # Number of stores executed +system.cpu3.iew.exec_rate 1.441587 # Inst execution rate +system.cpu3.iew.wb_sent 269584 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 269261 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 153664 # num instructions producing a value +system.cpu3.iew.wb_consumers 158539 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.158956 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.960825 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.437700 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.969250 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitCommittedInsts 244729 # The number of committed instructions -system.cpu3.commit.commitCommittedOps 244729 # The number of committed instructions -system.cpu3.commit.commitSquashedInsts 15046 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7736 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1525 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 174515 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.402338 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.927125 # Number of insts commited each cycle +system.cpu3.commit.commitCommittedInsts 306791 # The number of committed instructions +system.cpu3.commit.commitCommittedOps 306791 # The number of committed instructions +system.cpu3.commit.commitSquashedInsts 15574 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 5200 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1573 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 175548 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.747619 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.056560 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 84328 48.32% 48.32% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 43439 24.89% 73.21% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6199 3.55% 76.76% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8632 4.95% 81.71% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1540 0.88% 82.59% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 28042 16.07% 98.66% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 531 0.30% 98.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 992 0.57% 99.53% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 812 0.47% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 66312 37.77% 37.77% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 53003 30.19% 67.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6220 3.54% 71.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 6065 3.45% 74.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1526 0.87% 75.83% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 40098 22.84% 98.68% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 522 0.30% 98.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 989 0.56% 99.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 174515 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 244729 # Number of instructions committed -system.cpu3.commit.committedOps 244729 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 175548 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 306791 # Number of instructions committed +system.cpu3.commit.committedOps 306791 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 100719 # Number of memory references committed -system.cpu3.commit.loads 69310 # Number of loads committed -system.cpu3.commit.membars 7019 # Number of memory barriers committed -system.cpu3.commit.branches 44389 # Number of branches committed +system.cpu3.commit.refs 134284 # Number of memory references committed +system.cpu3.commit.loads 90840 # Number of loads committed +system.cpu3.commit.membars 4481 # Number of memory barriers committed +system.cpu3.commit.branches 53890 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 167227 # Number of committed integer instructions. +system.cpu3.commit.int_insts 210289 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 432891 # The number of ROB reads -system.cpu3.rob.rob_writes 522404 # The number of ROB writes -system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 2970 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 35972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 202534 # Number of Instructions Simulated -system.cpu3.committedOps 202534 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 202534 # Number of Instructions Simulated -system.cpu3.cpi 0.922472 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.922472 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.084043 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.084043 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 369217 # number of integer regfile reads -system.cpu3.int_regfile_writes 172842 # number of integer regfile writes +system.cpu3.rob.rob_reads 496513 # The number of ROB reads +system.cpu3.rob.rob_writes 647676 # The number of ROB writes +system.cpu3.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 2241 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 35902 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 257635 # Number of Instructions Simulated +system.cpu3.committedOps 257635 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 257635 # Number of Instructions Simulated +system.cpu3.cpi 0.726943 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.726943 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.375623 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.375623 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 470214 # number of integer regfile reads +system.cpu3.int_regfile_writes 218594 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 104868 # number of misc regfile reads +system.cpu3.misc_regfile_reads 138505 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 320 # number of replacements -system.cpu3.icache.tagsinuse 85.923076 # Cycle average of tags in use -system.cpu3.icache.total_refs 23951 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 432 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 55.442130 # Average number of references to valid blocks. +system.cpu3.icache.replacements 322 # number of replacements +system.cpu3.icache.tagsinuse 87.207959 # Cycle average of tags in use +system.cpu3.icache.total_refs 18566 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 42.582569 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 85.923076 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.167819 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.167819 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 23951 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 23951 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 23951 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 23951 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 23951 # number of overall hits -system.cpu3.icache.overall_hits::total 23951 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 503 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 503 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 503 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 503 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 503 # number of overall misses -system.cpu3.icache.overall_misses::total 503 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6843000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6843000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6843000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6843000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6843000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6843000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 24454 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 24454 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 24454 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 24454 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 24454 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 24454 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020569 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.020569 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020569 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.020569 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.020569 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13604.373757 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13604.373757 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13604.373757 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 87.207959 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.170328 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.170328 # Average percentage of cache occupancy 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of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6966500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6966500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6966500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6966500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6966500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 19062 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 19062 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 19062 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 19062 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 19062 # number of overall (read+write) accesses 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miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14045.362903 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14045.362903 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1809,106 +1805,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 71 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 71 # number of 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0.003760 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003319 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003319 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003575 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003575 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13196.319018 # average ReadReq mshr miss latency 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-system.l2c.ReadReq_avg_mshr_miss_latency::total 39979.704797 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39981.447124 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40351.063830 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40125 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40192.307692 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40026.315789 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40006.172840 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40335.106383 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40192.307692 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40291.666667 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40293.893130 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40297.709924 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40286.982249 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40125 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40269.230769 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40043.283582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40286.982249 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40125 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40269.230769 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40043.283582 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index 7edc0f615..4b3a2eb90 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:23 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:10 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index a670e1cab..382c1c71b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87713500 # Number of ticks simulated final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1597903 # Simulator instruction rate (inst/s) -host_op_rate 1597833 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 206906108 # Simulator tick rate (ticks/s) -host_mem_usage 1149840 # Number of bytes of host memory used -host_seconds 0.42 # Real time elapsed on the host +host_inst_rate 1588944 # Simulator instruction rate (inst/s) +host_op_rate 1588869 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 205745598 # Simulator tick rate (ticks/s) +host_mem_usage 1148436 # Number of bytes of host memory used +host_seconds 0.43 # Real time elapsed on the host sim_insts 677340 # Number of instructions simulated sim_ops 677340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory @@ -122,15 +122,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use -system.cpu0.dcache.total_refs 61599 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 2 # number of replacements +system.cpu0.dcache.tagsinuse 150.735434 # Cycle average of tags in use +system.cpu0.dcache.total_refs 81884 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 490.323353 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.712770 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284595 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284595 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 150.735434 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.294405 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.294405 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 54431 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 54431 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits @@ -179,8 +179,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks -system.cpu0.dcache.writebacks::total 6 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 173308 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started @@ -246,35 +246,35 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use -system.cpu1.dcache.total_refs 26889 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 0 # number of replacements +system.cpu1.dcache.tagsinuse 30.314752 # Cycle average of tags in use +system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 29.073016 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.056783 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.056783 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 40468 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 40468 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 30.314752 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.059208 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.059208 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 53031 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 53031 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 53031 # number of overall hits -system.cpu1.dcache.overall_hits::total 53031 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 176 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 176 # number of ReadReq misses +system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits +system.cpu1.dcache.overall_hits::total 53033 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses -system.cpu1.dcache.overall_misses::total 282 # number of overall misses +system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses +system.cpu1.dcache.overall_misses::total 280 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) @@ -285,16 +285,16 @@ system.cpu1.dcache.demand_accesses::cpu1.data 53313 system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004330 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004330 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005290 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005290 # miss rate for overall accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,8 +303,6 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu1.dcache.writebacks::total 1 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 173308 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started @@ -370,35 +368,35 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use -system.cpu2.dcache.total_refs 33771 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. +system.cpu2.dcache.replacements 0 # number of replacements +system.cpu2.dcache.tagsinuse 29.603311 # Cycle average of tags in use +system.cpu2.dcache.total_refs 33613 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1292.807692 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 28.420699 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.055509 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.055509 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 42192 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42192 # number of ReadReq hits +system.cpu2.dcache.occ_blocks::cpu2.data 29.603311 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.057819 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.057819 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 58190 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 58190 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 58190 # number of overall hits -system.cpu2.dcache.overall_hits::total 58190 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses +system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits +system.cpu2.dcache.overall_hits::total 58192 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses -system.cpu2.dcache.overall_misses::total 271 # number of overall misses +system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses +system.cpu2.dcache.overall_misses::total 269 # number of overall misses system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) @@ -409,16 +407,16 @@ system.cpu2.dcache.demand_accesses::cpu2.data 58461 system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003825 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003825 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004636 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004636 # miss rate for overall accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -427,8 +425,6 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu2.dcache.writebacks::total 1 # number of writebacks system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 173307 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started @@ -494,35 +490,35 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 27.588376 # Cycle average of tags in use -system.cpu3.dcache.total_refs 30309 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. +system.cpu3.dcache.replacements 0 # number of replacements +system.cpu3.dcache.tagsinuse 28.793270 # Cycle average of tags in use +system.cpu3.dcache.total_refs 30236 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 27 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 1119.851852 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 27.588376 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.053884 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.053884 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 41299 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41299 # number of ReadReq hits +system.cpu3.dcache.occ_blocks::cpu3.data 28.793270 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.056237 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.056237 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 55559 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 55559 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 55559 # number of overall hits -system.cpu3.dcache.overall_hits::total 55559 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 159 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 159 # number of ReadReq misses +system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits +system.cpu3.dcache.overall_hits::total 55561 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 261 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 261 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 261 # number of overall misses -system.cpu3.dcache.overall_misses::total 261 # number of overall misses +system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses +system.cpu3.dcache.overall_misses::total 259 # number of overall misses system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) @@ -533,16 +529,16 @@ system.cpu3.dcache.demand_accesses::cpu3.data 55820 system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003835 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003835 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004676 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004676 # miss rate for overall accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -551,16 +547,14 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu3.dcache.writebacks::total 1 # number of writebacks system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 371.980910 # Cycle average of tags in use -system.l2c.total_refs 1223 # Total number of references to valid blocks. -system.l2c.sampled_refs 426 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.870892 # Average number of references to valid blocks. +system.l2c.tagsinuse 366.557230 # Cycle average of tags in use +system.l2c.total_refs 1220 # Total number of references to valid blocks. +system.l2c.sampled_refs 421 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.897862 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 6.390048 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.966368 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.inst 239.409595 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.data 55.204245 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.inst 59.507442 # Average occupied blocks per requestor @@ -569,7 +563,7 @@ system.l2c.occ_blocks::cpu2.inst 1.930518 # Av system.l2c.occ_blocks::cpu2.data 0.935341 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.inst 0.977501 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.data 0.905573 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000098 # Average percentage of cache occupancy +system.l2c.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy @@ -578,38 +572,38 @@ system.l2c.occ_percent::cpu2.inst 0.000029 # Av system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.005676 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.005593 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits -system.l2c.Writeback_hits::total 9 # number of Writeback hits +system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1226 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 1220 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 185 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits system.l2c.overall_hits::cpu1.inst 296 # number of overall hits -system.l2c.overall_hits::cpu1.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.data 3 # number of overall hits system.l2c.overall_hits::cpu2.inst 356 # number of overall hits -system.l2c.overall_hits::cpu2.data 11 # number of overall hits +system.l2c.overall_hits::cpu2.data 9 # number of overall hits system.l2c.overall_hits::cpu3.inst 357 # number of overall hits -system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1226 # number of overall hits +system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::total 1220 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses @@ -620,10 +614,10 @@ system.l2c.ReadReq_misses::cpu3.inst 2 # nu system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 423 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses @@ -650,19 +644,19 @@ system.l2c.overall_misses::total 559 # nu system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 89 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) @@ -671,35 +665,35 @@ system.l2c.ReadExReq_accesses::total 136 # nu system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.256519 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.977528 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -708,21 +702,21 @@ system.l2c.ReadExReq_miss_rate::total 1 # mi system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.313165 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.313165 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 3d54c9924..145ab230c 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:33 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:12 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done @@ -79,4 +79,4 @@ Iteration 9 completed [Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 262298000 because target called exit() +Exiting @ tick 262299000 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 36b8c656f..c654a221f 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000262 # Number of seconds simulated -sim_ticks 262298000 # Number of ticks simulated -final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 262299000 # Number of ticks simulated +final_tick 262299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1070900 # Simulator instruction rate (inst/s) -host_op_rate 1070867 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 424091073 # Simulator tick rate (ticks/s) -host_mem_usage 232420 # Number of bytes of host memory used -host_seconds 0.62 # Real time elapsed on the host -sim_insts 662307 # Number of instructions simulated -sim_ops 662307 # Number of ops (including micro ops) simulated +host_inst_rate 1271827 # Simulator instruction rate (inst/s) +host_op_rate 1271784 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 503510999 # Simulator tick rate (ticks/s) +host_mem_usage 230932 # Number of bytes of host memory used +host_seconds 0.52 # Real time elapsed on the host +sim_insts 662502 # Number of instructions simulated +sim_ops 662502 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory @@ -34,31 +34,31 @@ system.physmem.num_reads::cpu2.data 16 # Nu system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69539226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40259552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14395840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5367940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2195976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3903957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 243997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3659959 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139566447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69539226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14395840 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2195976 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 243997 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86375039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69539226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40259552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14395840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5367940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2195976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3903957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 243997 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3659959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139566447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69538961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40259399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14395785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5367920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2195967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3903942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 243996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3659945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139565915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69538961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14395785 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2195967 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 243996 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86374710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69538961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40259399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14395785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5367920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2195967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3903942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 243996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3659945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139565915 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 524596 # number of cpu cycles simulated +system.cpu0.numCycles 524598 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 158353 # Number of instructions committed @@ -77,18 +77,18 @@ system.cpu0.num_mem_refs 73905 # nu system.cpu0.num_load_insts 48930 # Number of load instructions system.cpu0.num_store_insts 24975 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 524596 # Number of busy cycles +system.cpu0.num_busy_cycles 524598 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.479188 # Cycle average of tags in use +system.cpu0.icache.tagsinuse 212.479251 # Cycle average of tags in use system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.479188 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414998 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414998 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 212.479251 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414999 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414999 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits @@ -158,15 +158,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 36665.952891 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use -system.cpu0.dcache.total_refs 56009 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 2 # number of replacements +system.cpu0.dcache.tagsinuse 145.603716 # Cycle average of tags in use +system.cpu0.dcache.total_refs 73381 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 439.407186 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 141.233342 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.275846 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.275846 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 145.603716 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284382 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284382 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits @@ -187,16 +187,16 @@ system.cpu0.dcache.demand_misses::cpu0.data 345 # system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses system.cpu0.dcache.overall_misses::total 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4749000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4749000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7175000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7175000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 387000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 387000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11924000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11924000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11924000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11924000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4747000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4747000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7176000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7176000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 389000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 389000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11923000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11923000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11923000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11923000 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses) @@ -217,16 +217,16 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 system.cpu0.dcache.demand_miss_rate::total 0.004672 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.004672 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 29314.814815 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39207.650273 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 14884.615385 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34562.318841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34562.318841 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29302.469136 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 29302.469136 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39213.114754 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39213.114754 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14961.538462 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 14961.538462 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34559.420290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34559.420290 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,8 +235,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks -system.cpu0.dcache.writebacks::total 6 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses @@ -247,16 +247,16 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4263000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4263000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6626000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 309000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 309000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10889000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10889000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10889000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4261000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4261000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6627000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6627000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10888000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10888000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10888000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10888000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003312 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses @@ -267,84 +267,84 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 system.cpu0.dcache.demand_mshr_miss_rate::total 0.004672 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.004672 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26314.814815 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36207.650273 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11884.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26302.469136 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26302.469136 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36213.114754 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36213.114754 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11961.538462 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11961.538462 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 524596 # number of cpu cycles simulated +system.cpu1.numCycles 524598 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 172325 # Number of instructions committed -system.cpu1.committedOps 172325 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses +system.cpu1.committedInsts 172389 # Number of instructions committed +system.cpu1.committedOps 172389 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 107964 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 36203 # number of instructions that are conditional controls -system.cpu1.num_int_insts 107932 # number of integer instructions +system.cpu1.num_conditional_control_insts 36219 # number of instructions that are conditional controls +system.cpu1.num_int_insts 107964 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 249091 # number of times the integer registers were read -system.cpu1.num_int_register_writes 92744 # number of times the integer registers were written +system.cpu1.num_int_register_reads 249169 # number of times the integer registers were read +system.cpu1.num_int_register_writes 92792 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 47898 # number of memory refs -system.cpu1.num_load_insts 39616 # Number of load instructions +system.cpu1.num_mem_refs 47914 # number of memory refs +system.cpu1.num_load_insts 39632 # Number of load instructions system.cpu1.num_store_insts 8282 # Number of store instructions -system.cpu1.num_idle_cycles 68578.001739 # Number of idle cycles -system.cpu1.num_busy_cycles 456017.998261 # Number of busy cycles -system.cpu1.not_idle_fraction 0.869275 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.130725 # Percentage of idle cycles +system.cpu1.num_idle_cycles 68732.001738 # Number of idle cycles +system.cpu1.num_busy_cycles 455865.998262 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868982 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131018 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 70.076133 # Cycle average of tags in use -system.cpu1.icache.total_refs 171992 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 70.077944 # Cycle average of tags in use +system.cpu1.icache.total_refs 172056 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 469.923497 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 470.098361 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 70.076133 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136867 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136867 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 171992 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 171992 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 171992 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 171992 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 171992 # number of overall hits -system.cpu1.icache.overall_hits::total 171992 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 70.077944 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.136871 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.136871 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 172056 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 172056 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 172056 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 172056 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 172056 # number of overall hits +system.cpu1.icache.overall_hits::total 172056 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7920500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7920500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7920500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7920500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7920500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7920500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 172358 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 172358 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 172358 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 172358 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 172358 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 172358 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7921500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7921500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7921500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7921500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7921500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7921500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 172422 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 172422 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 172422 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 172422 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 172422 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 172422 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.002123 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.002123 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.002123 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21640.710383 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21640.710383 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21640.710383 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21643.442623 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 21643.442623 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 21643.442623 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 21643.442623 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,94 +359,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6822000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6822000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6822000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6822000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6822000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6822000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6823000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6823000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6823000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6823000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6823000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6823000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002123 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.002123 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.002123 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18639.344262 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18639.344262 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18639.344262 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18642.076503 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 26.693562 # Cycle average of tags in use -system.cpu1.dcache.total_refs 18908 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 609.935484 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 0 # number of replacements +system.cpu1.dcache.tagsinuse 27.731444 # Cycle average of tags in use +system.cpu1.dcache.total_refs 18765 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 647.068966 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 26.693562 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.052136 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.052136 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 39428 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39428 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 27.731444 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.054163 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.054163 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 39445 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 39445 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 8099 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 8099 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 18 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 18 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 47527 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 47527 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 47527 # number of overall hits -system.cpu1.dcache.overall_hits::total 47527 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 181 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 181 # number of ReadReq misses +system.cpu1.dcache.demand_hits::cpu1.data 47544 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 47544 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 47544 # number of overall hits +system.cpu1.dcache.overall_hits::total 47544 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 179 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 179 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 98 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 98 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 279 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 279 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 279 # number of overall misses -system.cpu1.dcache.overall_misses::total 279 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3713000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3713000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1889000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1889000 # number of WriteReq miss cycles +system.cpu1.dcache.demand_misses::cpu1.data 277 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 277 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 277 # number of overall misses +system.cpu1.dcache.overall_misses::total 277 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3683000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3683000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1838000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1838000 # number of WriteReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 415000 # number of SwapReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::total 415000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5602000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5602000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5602000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5602000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 39609 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 39609 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.demand_miss_latency::cpu1.data 5521000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5521000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5521000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5521000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 39624 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 39624 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 8197 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 47806 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 47806 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 47806 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 47806 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004570 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004570 # miss rate for ReadReq accesses +system.cpu1.dcache.demand_accesses::cpu1.data 47821 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 47821 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 47821 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 47821 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004517 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004517 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.011956 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_miss_rate::total 0.783133 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005836 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005836 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005836 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005836 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20513.812155 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19275.510204 # average WriteReq miss latency +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005792 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005792 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005792 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005792 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20575.418994 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20575.418994 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18755.102041 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18755.102041 # average WriteReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::total 6384.615385 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20078.853047 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20078.853047 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19931.407942 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19931.407942 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -455,86 +455,84 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu1.dcache.writebacks::total 1 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 179 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3170000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3170000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1595000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1595000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_misses::cpu1.data 277 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 277 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3146000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3146000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1544000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1544000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4765000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004570 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4690000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4690000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4690000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4690000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004517 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004517 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.011956 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.783133 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005836 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005836 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17513.812155 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16275.510204 # average WriteReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005792 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005792 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17575.418994 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17575.418994 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15755.102041 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15755.102041 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3384.615385 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 524596 # number of cpu cycles simulated +system.cpu2.numCycles 524598 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165499 # Number of instructions committed -system.cpu2.committedOps 165499 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses +system.cpu2.committedInsts 165564 # Number of instructions committed +system.cpu2.committedOps 165564 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 112387 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 30582 # number of instructions that are conditional controls -system.cpu2.num_int_insts 112355 # number of integer instructions +system.cpu2.num_conditional_control_insts 30599 # number of instructions that are conditional controls +system.cpu2.num_int_insts 112387 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 289268 # number of times the integer registers were read -system.cpu2.num_int_register_writes 110631 # number of times the integer registers were written +system.cpu2.num_int_register_reads 289349 # number of times the integer registers were read +system.cpu2.num_int_register_writes 110679 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 57941 # number of memory refs -system.cpu2.num_load_insts 41852 # Number of load instructions +system.cpu2.num_mem_refs 57957 # number of memory refs +system.cpu2.num_load_insts 41868 # Number of load instructions system.cpu2.num_store_insts 16089 # Number of store instructions -system.cpu2.num_idle_cycles 68840.001738 # Number of idle cycles -system.cpu2.num_busy_cycles 455755.998262 # Number of busy cycles -system.cpu2.not_idle_fraction 0.868775 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.131225 # Percentage of idle cycles +system.cpu2.num_idle_cycles 68998.001737 # Number of idle cycles +system.cpu2.num_busy_cycles 455599.998263 # Number of busy cycles +system.cpu2.not_idle_fraction 0.868475 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.131525 # Percentage of idle cycles system.cpu2.icache.replacements 280 # number of replacements -system.cpu2.icache.tagsinuse 65.601019 # Cycle average of tags in use -system.cpu2.icache.total_refs 165166 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 65.602896 # Cycle average of tags in use +system.cpu2.icache.total_refs 165231 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 451.273224 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 451.450820 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 65.601019 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.128127 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.128127 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 165166 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 165166 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 165166 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 165166 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 165166 # number of overall hits -system.cpu2.icache.overall_hits::total 165166 # number of overall hits +system.cpu2.icache.occ_blocks::cpu2.inst 65.602896 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.128131 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.128131 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 165231 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 165231 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 165231 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 165231 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 165231 # number of overall hits +system.cpu2.icache.overall_hits::total 165231 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses @@ -547,18 +545,18 @@ system.cpu2.icache.demand_miss_latency::cpu2.inst 5648500 system.cpu2.icache.demand_miss_latency::total 5648500 # number of demand (read+write) miss cycles system.cpu2.icache.overall_miss_latency::cpu2.inst 5648500 # number of overall miss cycles system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165532 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165532 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165532 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165532 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165532 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165532 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002211 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002211 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002211 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002211 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002211 # miss rate for overall accesses +system.cpu2.icache.ReadReq_accesses::cpu2.inst 165597 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 165597 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 165597 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 165597 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 165597 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 165597 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002210 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002210 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002210 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency system.cpu2.icache.ReadReq_avg_miss_latency::total 15433.060109 # average ReadReq miss latency system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency @@ -585,12 +583,12 @@ system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002211 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002211 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002211 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12433.060109 # average ReadReq mshr miss latency system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency @@ -598,75 +596,75 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 12433.060109 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 24.943438 # Cycle average of tags in use -system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1115.419355 # Average number of references to valid blocks. +system.cpu2.dcache.replacements 0 # number of replacements +system.cpu2.dcache.tagsinuse 25.974144 # Cycle average of tags in use +system.cpu2.dcache.total_refs 34436 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1187.448276 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.943438 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.048718 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.048718 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 41688 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 41688 # number of ReadReq hits +system.cpu2.dcache.occ_blocks::cpu2.data 25.974144 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.050731 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.050731 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 41706 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 41706 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15916 # number of WriteReq hits system.cpu2.dcache.WriteReq_hits::total 15916 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 57604 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 57604 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 57604 # number of overall hits -system.cpu2.dcache.overall_hits::total 57604 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 156 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 156 # number of ReadReq misses +system.cpu2.dcache.demand_hits::cpu2.data 57622 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 57622 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 57622 # number of overall hits +system.cpu2.dcache.overall_hits::total 57622 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 154 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 154 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 265 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 265 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 265 # number of overall misses -system.cpu2.dcache.overall_misses::total 265 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2527000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2527000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2084000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2084000 # number of WriteReq miss cycles +system.cpu2.dcache.demand_misses::cpu2.data 263 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 263 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 263 # number of overall misses +system.cpu2.dcache.overall_misses::total 263 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2498000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2498000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2031000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2031000 # number of WriteReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 305000 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::total 305000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4611000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4611000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4611000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4611000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 41844 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 41844 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.demand_miss_latency::cpu2.data 4529000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4529000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4529000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4529000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 41860 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 41860 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 16025 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 57869 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 57869 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003728 # miss rate for ReadReq accesses +system.cpu2.dcache.demand_accesses::cpu2.data 57885 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 57885 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 57885 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 57885 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003679 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003679 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_miss_rate::total 0.006802 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004579 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004579 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16198.717949 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 19119.266055 # average WriteReq miss latency +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004543 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004543 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004543 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004543 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16220.779221 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16220.779221 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18633.027523 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 18633.027523 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::total 5980.392157 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17400 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17400 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17220.532319 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17220.532319 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -675,116 +673,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu2.dcache.writebacks::total 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 156 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 154 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2059000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2059000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1757000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1757000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_misses::cpu2.data 263 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 263 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2036000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2036000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1704000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1704000 # number of WriteReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3816000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003728 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3740000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3740000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3740000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3740000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003679 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003679 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006802 # mshr miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004579 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004579 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13198.717949 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16119.266055 # average WriteReq mshr miss latency +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004543 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004543 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13220.779221 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13220.779221 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15633.027523 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15633.027523 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2980.392157 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 524596 # number of cpu cycles simulated +system.cpu3.numCycles 524598 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 166130 # Number of instructions committed -system.cpu3.committedOps 166130 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses +system.cpu3.committedInsts 166196 # Number of instructions committed +system.cpu3.committedOps 166196 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 112131 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 31024 # number of instructions that are conditional controls -system.cpu3.num_int_insts 112098 # number of integer instructions +system.cpu3.num_conditional_control_insts 31040 # number of instructions that are conditional controls +system.cpu3.num_int_insts 112131 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 286475 # number of times the integer registers were read -system.cpu3.num_int_register_writes 109360 # number of times the integer registers were written +system.cpu3.num_int_register_reads 286557 # number of times the integer registers were read +system.cpu3.num_int_register_writes 109409 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 57243 # number of memory refs -system.cpu3.num_load_insts 41720 # Number of load instructions +system.cpu3.num_mem_refs 57260 # number of memory refs +system.cpu3.num_load_insts 41737 # Number of load instructions system.cpu3.num_store_insts 15523 # Number of store instructions -system.cpu3.num_idle_cycles 69090.001737 # Number of idle cycles -system.cpu3.num_busy_cycles 455505.998263 # Number of busy cycles -system.cpu3.not_idle_fraction 0.868299 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.131701 # Percentage of idle cycles +system.cpu3.num_idle_cycles 69252.001736 # Number of idle cycles +system.cpu3.num_busy_cycles 455345.998264 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867990 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132010 # Percentage of idle cycles system.cpu3.icache.replacements 281 # number of replacements -system.cpu3.icache.tagsinuse 67.737646 # Cycle average of tags in use -system.cpu3.icache.total_refs 165796 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 67.739564 # Cycle average of tags in use +system.cpu3.icache.total_refs 165862 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 451.760218 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 451.940054 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 67.737646 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.132300 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.132300 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 165796 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 165796 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 165796 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 165796 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 165796 # number of overall hits -system.cpu3.icache.overall_hits::total 165796 # number of overall hits +system.cpu3.icache.occ_blocks::cpu3.inst 67.739564 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.132304 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.132304 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 165862 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 165862 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 165862 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 165862 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 165862 # number of overall hits +system.cpu3.icache.overall_hits::total 165862 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5531500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5531500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5531500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5531500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5531500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5531500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 166163 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 166163 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 166163 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 166163 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 166163 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 166163 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002209 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002209 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002209 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002209 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002209 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 15072.207084 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 15072.207084 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 15072.207084 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5533500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5533500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5533500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5533500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5533500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5533500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 166229 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 166229 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 166229 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 166229 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 166229 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 166229 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002208 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002208 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002208 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002208 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002208 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002208 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15077.656676 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 15077.656676 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 15077.656676 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 15077.656676 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,94 +795,94 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4430500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4430500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4430500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4430500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4430500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4430500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002209 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12072.207084 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12072.207084 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12072.207084 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4432500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4432500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4432500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4432500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4432500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4432500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002208 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002208 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002208 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12077.656676 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12077.656676 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12077.656676 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 25.684916 # Cycle average of tags in use -system.cpu3.dcache.total_refs 33474 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 32 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1046.062500 # Average number of references to valid blocks. +system.cpu3.dcache.replacements 0 # number of replacements +system.cpu3.dcache.tagsinuse 26.774212 # Cycle average of tags in use +system.cpu3.dcache.total_refs 33417 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 1113.900000 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 25.684916 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.050166 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.050166 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 41555 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41555 # number of ReadReq hits +system.cpu3.dcache.occ_blocks::cpu3.data 26.774212 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.052293 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.052293 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41574 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41574 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 15348 # number of WriteReq hits system.cpu3.dcache.WriteReq_hits::total 15348 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 56903 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 56903 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 56903 # number of overall hits -system.cpu3.dcache.overall_hits::total 56903 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses +system.cpu3.dcache.demand_hits::cpu3.data 56922 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 56922 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 56922 # number of overall hits +system.cpu3.dcache.overall_hits::total 56922 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 155 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 155 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 265 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 265 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 265 # number of overall misses -system.cpu3.dcache.overall_misses::total 265 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2569000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 2569000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2080000 # 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number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 4649000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 4649000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 4649000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41712 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41712 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.demand_miss_latency::cpu3.data 4563000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 4563000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 4563000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 4563000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41729 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41729 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::cpu3.data 15456 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::total 15456 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::cpu3.data 65 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 57168 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 57168 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 57168 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 57168 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003764 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses +system.cpu3.dcache.demand_accesses::cpu3.data 57185 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 57185 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 57185 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 57185 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003714 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003714 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_miss_rate::total 0.006988 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses system.cpu3.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004635 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004635 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004635 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004635 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16363.057325 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 16363.057325 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 19259.259259 # average WriteReq miss latency +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004599 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004599 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004599 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004599 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16367.741935 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 16367.741935 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18759.259259 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 18759.259259 # average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::total 6037.037037 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17543.396226 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17543.396226 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 17349.809886 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 17349.809886 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -895,65 +891,63 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu3.dcache.writebacks::total 1 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 157 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 155 # 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number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3854000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3854000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3854000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3854000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003764 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3774000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3774000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3774000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3774000 # 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Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 54.220360 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 51.601293 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 6.129067 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.914986 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.831600 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.889759 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 231.859241 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 54.220371 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 51.601321 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 6.129070 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1.917102 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.831909 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.inst 0.887228 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.844646 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000085 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu3.data 0.844647 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.003538 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy @@ -962,38 +956,38 @@ system.l2c.occ_percent::cpu2.inst 0.000029 # Av system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.005400 # 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number of overall miss cycles system.l2c.overall_miss_latency::cpu2.inst 615000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.data 832000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 429000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 827000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30715000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 446000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 829000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30717000 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 13 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 13 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 13 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1676 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 12 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 11 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 71 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) @@ -1091,35 +1081,35 @@ system.l2c.ReadExReq_accesses::total 142 # nu system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 28 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 27 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1818 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 28 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 27 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 27 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1818 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.615385 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.153846 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.268496 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.972973 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.971831 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -1128,57 +1118,53 @@ system.l2c.ReadExReq_miss_rate::total 1 # mi system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.821429 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.592593 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.592593 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.325633 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.821429 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.592593 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.592593 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.325633 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51757.575758 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 51625 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51545.454545 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 51375 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51250 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 47666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 49500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 51844.444444 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4333.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3250 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 3250 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2166.666667 # average UpgradeReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49555.555556 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 50500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 51851.111111 # average ReadReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52066.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52007.042254 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 51545.454545 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 51782.608696 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.inst 51250 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.data 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51883.445946 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 49555.555556 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 51812.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51886.824324 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51545.454545 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 51782.608696 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.inst 51250 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51883.445946 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 49555.555556 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 51812.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51886.824324 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1215,10 +1201,10 @@ system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # n system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 12 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 72 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 11 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 69 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses @@ -1252,47 +1238,47 @@ system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 17203000 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 480000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 640000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 640000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 2880000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 440000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 600000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 2760000 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3960000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 601000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 600000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 560000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5681000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5680000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 11402000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 6600000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 2360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 881000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 880000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.inst 361000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.data 640000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.data 600000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22884000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22883000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 11402000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 6600000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 2360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 881000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 880000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.inst 361000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.data 640000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 600000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22884000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22883000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.538462 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.256563 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.972973 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.971831 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -1301,21 +1287,21 @@ system.l2c.ReadExReq_mshr_miss_rate::total 1 # system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.314631 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.314631 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency @@ -1331,28 +1317,28 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.042254 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |