diff options
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic')
6 files changed, 2843 insertions, 2841 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index adca0d63f..49d73401e 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -1779,6 +1779,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -1789,6 +1790,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true @@ -1817,6 +1819,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 9fd6655b7..3c88e0e72 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 16:01:12 +gem5 compiled Mar 26 2013 15:04:14 +gem5 started Mar 26 2013 15:04:37 gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second @@ -12,38 +12,38 @@ info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 1] Got lock [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 Iteration 1 completed -[Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 Iteration 2 completed -[Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 3, Thread 3] Got lock +[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 Iteration 3 completed -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 Iteration 4 completed -[Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 1] Got lock [Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 Iteration 5 completed [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 @@ -52,19 +52,19 @@ Iteration 5 completed [Iteration 6, Thread 3] Got lock [Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 Iteration 6 completed +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 7, Thread 3] Got lock [Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1 Iteration 7 completed -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 Iteration 8 completed [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 @@ -73,12 +73,12 @@ Iteration 8 completed [Iteration 9, Thread 2] Got lock [Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 Iteration 9 completed -[Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 104832500 because target called exit() +Exiting @ tick 105945500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 3eb29c400..f2f028686 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,71 +1,71 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000106 # Number of seconds simulated -sim_ticks 105801500 # Number of ticks simulated -final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 105945500 # Number of ticks simulated +final_tick 105945500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173787 # Simulator instruction rate (inst/s) -host_op_rate 173787 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17750545 # Simulator tick rate (ticks/s) -host_mem_usage 247480 # Number of bytes of host memory used -host_seconds 5.96 # Real time elapsed on the host -sim_insts 1035849 # Number of instructions simulated -sim_ops 1035849 # Number of ops (including micro ops) simulated +host_inst_rate 48441 # Simulator instruction rate (inst/s) +host_op_rate 48441 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4953275 # Simulator tick rate (ticks/s) +host_mem_usage 291288 # Number of bytes of host memory used +host_seconds 21.39 # Real time elapsed on the host +sim_insts 1036095 # Number of instructions simulated +sim_ops 1036095 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 4992 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42240 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 22848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 4992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 512 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28544 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 357 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 78 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 660 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 215951570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 101624268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 48392509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 12098127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 3629438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7863783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1814719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7863783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 399238196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 215951570 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 48392509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 3629438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1814719 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269788236 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 215951570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 101624268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 48392509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 12098127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 3629438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7863783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1814719 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7863783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 215658051 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 101486141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47118566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 12081684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 4832673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7853094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1812253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7853094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 398695556 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 215658051 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47118566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 4832673 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1812253 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269421542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 215658051 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 101486141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47118566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 12081684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 4832673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7853094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1812253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7853094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 398695556 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 661 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 732 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 735 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 42240 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 71 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 74 # Reqs where no action is needed system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 74 # Track reads on a per bank basis @@ -100,7 +100,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 105773500 # Total gap between requests +system.physmem.totGap 105917500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -115,8 +115,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see @@ -179,157 +179,157 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 4076500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 20691500 # Sum of mem lat for all requests +system.physmem.totQLat 4080500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 20695500 # Sum of mem lat for all requests system.physmem.totBusLat 3305000 # Total cycles spent in databus access system.physmem.totBankLat 13310000 # Total cycles spent in bank access -system.physmem.avgQLat 6167.17 # Average queueing delay per request +system.physmem.avgQLat 6173.22 # Average queueing delay per request system.physmem.avgBankLat 20136.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31303.33 # Average memory access latency -system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 31309.38 # Average memory access latency +system.physmem.avgRdBW 398.70 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 398.70 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.12 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.20 # Average read queue length over time +system.physmem.busUtil 3.11 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.19 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 465 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 70.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 160020.42 # Average gap between requests -system.cpu0.branchPred.lookups 82232 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80005 # Number of conditional branches predicted +system.physmem.avgGap 160238.28 # Average gap between requests +system.cpu0.branchPred.lookups 82343 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80122 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1236 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 79512 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 77444 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 79627 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 77569 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.399135 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 97.415450 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 525 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 211604 # number of cpu cycles simulated +system.cpu0.numCycles 211892 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 16980 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 488068 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82232 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 77969 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 160105 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3869 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13032 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17012 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 488761 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 82343 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 78094 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 160351 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3870 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13040 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1378 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5906 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 485 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 193984 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.516022 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.216359 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1377 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5901 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 194270 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.515885 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.216000 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33879 17.46% 17.46% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 79263 40.86% 58.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33919 17.46% 17.46% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 79392 40.87% 58.33% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 605 0.31% 58.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 997 0.51% 59.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 996 0.51% 59.15% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::4 467 0.24% 59.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 75310 38.82% 98.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 571 0.29% 98.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 376 0.19% 98.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2516 1.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 75436 38.83% 98.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 571 0.29% 98.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 375 0.19% 98.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2509 1.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 193984 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.388613 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.306516 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17628 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14487 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 159104 # Number of cycles decode is running +system.cpu0.fetch.rateDist::total 194270 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.388608 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.306652 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17669 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14482 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 159353 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 281 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2484 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 484973 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2484 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18279 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 710 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13181 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 158767 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 563 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 482144 # Number of instructions processed by rename +system.cpu0.decode.SquashCycles 2485 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 485695 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2485 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18316 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 722 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13165 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 159020 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 562 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 482913 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full system.cpu0.rename.LSQFullEvents 156 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 329947 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 961518 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 961518 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 316491 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13456 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 888 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3585 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 154112 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 77863 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 75108 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 74923 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 403093 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 921 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 400275 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11012 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9891 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 362 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 193984 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.063443 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.093968 # Number of insts issued each cycle +system.cpu0.rename.RenamedOperands 330456 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 963041 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 963041 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 316991 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13465 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 886 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 906 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3563 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 154365 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 77987 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 75234 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 75049 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 403722 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 919 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 400870 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11014 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 10026 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 360 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 194270 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.063468 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.094328 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33040 17.03% 17.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4899 2.53% 19.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 76941 39.66% 59.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 76443 39.41% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1604 0.83% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 703 0.36% 99.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 261 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 76 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33101 17.04% 17.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4910 2.53% 19.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 77039 39.66% 59.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 76515 39.39% 98.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1655 0.85% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 696 0.36% 99.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 259 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 77 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 193984 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 194270 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 51 22.67% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 62 27.56% 50.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 49.78% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 50 22.22% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 62 27.56% 49.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 113 50.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 169361 42.31% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 169604 42.31% 42.31% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.31% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.31% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.31% # Type of FU issued @@ -358,157 +358,157 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.31% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.31% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.31% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 153636 38.38% 80.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 77278 19.31% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 153865 38.38% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 77401 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 400275 # Type of FU issued -system.cpu0.iq.rate 1.891623 # Inst issue rate +system.cpu0.iq.FU_type_0::total 400870 # Type of FU issued +system.cpu0.iq.rate 1.891860 # Inst issue rate system.cpu0.iq.fu_busy_cnt 225 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000562 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 994851 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 415081 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 398443 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 996359 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 415710 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 399019 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 400500 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 401095 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 74634 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 74761 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2277 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2280 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1438 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2484 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 441 # Number of cycles IEW is blocking +system.cpu0.iew.iewSquashCycles 2485 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 453 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 479665 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 154112 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 77863 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 809 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispatchedInsts 480419 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 309 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 154365 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 77987 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 807 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 346 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 1112 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1458 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 399178 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 153293 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 399786 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 153534 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1084 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 75651 # number of nop insts executed -system.cpu0.iew.exec_refs 230462 # number of memory reference insts executed -system.cpu0.iew.exec_branches 79264 # Number of branches executed -system.cpu0.iew.exec_stores 77169 # Number of stores executed -system.cpu0.iew.exec_rate 1.886439 # Inst execution rate -system.cpu0.iew.wb_sent 398782 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 398443 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 236156 # num instructions producing a value -system.cpu0.iew.wb_consumers 238721 # num instructions consuming a value +system.cpu0.iew.exec_nop 75778 # number of nop insts executed +system.cpu0.iew.exec_refs 230828 # number of memory reference insts executed +system.cpu0.iew.exec_branches 79388 # Number of branches executed +system.cpu0.iew.exec_stores 77294 # Number of stores executed +system.cpu0.iew.exec_rate 1.886744 # Inst execution rate +system.cpu0.iew.wb_sent 399367 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 399019 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 236486 # num instructions producing a value +system.cpu0.iew.wb_consumers 239045 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.882965 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989255 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.883124 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989295 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12542 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12546 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1236 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 191500 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.439102 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136121 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 191785 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.439388 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136415 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33551 17.52% 17.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 78896 41.20% 58.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2340 1.22% 59.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 696 0.36% 60.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 545 0.28% 60.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 74448 38.88% 99.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 466 0.24% 99.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 256 0.13% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33586 17.51% 17.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 79020 41.20% 58.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2366 1.23% 59.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 689 0.36% 60.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 531 0.28% 60.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 74531 38.86% 99.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 504 0.26% 99.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 248 0.13% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 310 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 191500 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 467088 # Number of instructions committed -system.cpu0.commit.committedOps 467088 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 191785 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 467838 # Number of instructions committed +system.cpu0.commit.committedOps 467838 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 228259 # Number of memory references committed -system.cpu0.commit.loads 151835 # Number of loads committed +system.cpu0.commit.refs 228634 # Number of memory references committed +system.cpu0.commit.loads 152085 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 78311 # Number of branches committed +system.cpu0.commit.branches 78436 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 314822 # Number of committed integer instructions. +system.cpu0.commit.int_insts 315322 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 310 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 669667 # The number of ROB reads -system.cpu0.rob.rob_writes 961765 # The number of ROB writes +system.cpu0.rob.rob_reads 670698 # The number of ROB reads +system.cpu0.rob.rob_writes 963274 # The number of ROB writes system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 17620 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 391961 # Number of Instructions Simulated -system.cpu0.committedOps 391961 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 391961 # Number of Instructions Simulated -system.cpu0.cpi 0.539860 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.539860 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.852333 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.852333 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 714059 # number of integer regfile reads -system.cpu0.int_regfile_writes 321926 # number of integer regfile writes +system.cpu0.idleCycles 17622 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 392586 # Number of Instructions Simulated +system.cpu0.committedOps 392586 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 392586 # Number of Instructions Simulated +system.cpu0.cpi 0.539734 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.539734 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.852765 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.852765 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 715161 # number of integer regfile reads +system.cpu0.int_regfile_writes 322387 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 232286 # number of misc regfile reads +system.cpu0.misc_regfile_reads 232651 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.replacements 298 # number of replacements -system.cpu0.icache.tagsinuse 245.557795 # Cycle average of tags in use -system.cpu0.icache.total_refs 5162 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 245.594499 # Cycle average of tags in use +system.cpu0.icache.total_refs 5155 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 589 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.764007 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 8.752122 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 245.557795 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.479605 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.479605 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5162 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5162 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5162 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5162 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5162 # number of overall hits -system.cpu0.icache.overall_hits::total 5162 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 744 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 744 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 744 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 744 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 744 # number of overall misses -system.cpu0.icache.overall_misses::total 744 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26547500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 26547500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 26547500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 26547500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 26547500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 26547500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5906 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5906 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5906 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5906 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5906 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5906 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125974 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125974 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125974 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125974 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125974 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125974 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35682.123656 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 35682.123656 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 35682.123656 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 35682.123656 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 245.594499 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.479677 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.479677 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5155 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5155 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5155 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5155 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5155 # number of overall hits +system.cpu0.icache.overall_hits::total 5155 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 746 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 746 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 746 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 746 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 746 # number of overall misses +system.cpu0.icache.overall_misses::total 746 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26567000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 26567000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 26567000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 26567000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 26567000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 26567000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5901 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5901 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5901 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5901 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5901 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5901 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.126419 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.126419 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126419 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.126419 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126419 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.126419 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35612.600536 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 35612.600536 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35612.600536 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 35612.600536 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35612.600536 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 35612.600536 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -517,106 +517,106 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 154 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 154 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 154 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 154 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 156 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 156 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 156 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 156 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 156 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 590 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 590 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 590 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 590 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 590 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21154500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21154500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21154500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21154500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21154500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21154500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.099898 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.099898 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.099898 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 35855.084746 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21166500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21166500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21166500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21166500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21166500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21166500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.099983 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.099983 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.099983 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 35875.423729 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 35875.423729 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 35875.423729 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 143.429999 # Cycle average of tags in use -system.cpu0.dcache.total_refs 153854 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 143.449906 # Cycle average of tags in use +system.cpu0.dcache.total_refs 154093 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 905.023529 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 906.429412 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 143.429999 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.280137 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.280137 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 78105 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 78105 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 75839 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 75839 # number of WriteReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 143.449906 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.280176 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.280176 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 78219 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 78219 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75963 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75963 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153944 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153944 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153944 # number of overall hits -system.cpu0.dcache.overall_hits::total 153944 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 154182 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 154182 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 154182 # number of overall hits +system.cpu0.dcache.overall_hits::total 154182 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 475 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 543 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 543 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1018 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1018 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1018 # number of overall misses -system.cpu0.dcache.overall_misses::total 1018 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11909000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11909000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24675495 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24675495 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 605500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 605500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 36584495 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 36584495 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 36584495 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 36584495 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 78580 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 78580 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 76382 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 76382 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1019 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1019 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1019 # number of overall misses +system.cpu0.dcache.overall_misses::total 1019 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11954500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11954500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24681495 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24681495 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 599500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 599500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 36635995 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 36635995 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 36635995 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 36635995 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78694 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78694 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 76507 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 76507 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 154962 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 154962 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 154962 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 154962 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006045 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006045 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007109 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007109 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 155201 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 155201 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 155201 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 155201 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006036 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006036 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007110 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007110 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006569 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006569 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006569 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006569 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25071.578947 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25071.578947 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45442.900552 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45442.900552 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28833.333333 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 28833.333333 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35937.617878 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35937.617878 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006566 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006566 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006566 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006566 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25167.368421 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25167.368421 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45370.395221 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45370.395221 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28547.619048 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 28547.619048 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35952.890088 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35952.890088 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked @@ -627,365 +627,365 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 286 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 660 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 660 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 660 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 660 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 170 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 170 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_hits::cpu0.data 659 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 659 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 659 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 659 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5409500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5409500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5718500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5718500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 563500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 563500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11128000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11128000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11128000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11128000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002392 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002226 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002226 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5407500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5407500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5740000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5740000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 557500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 557500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11147500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11147500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11147500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11147500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002402 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002402 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002235 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002235 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002310 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002310 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28773.936170 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28773.936170 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33638.235294 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33638.235294 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26833.333333 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26833.333333 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002320 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002320 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28611.111111 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28611.111111 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33567.251462 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33567.251462 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26547.619048 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26547.619048 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 58098 # Number of BP lookups -system.cpu1.branchPred.condPredicted 55415 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 51986 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 51313 # Number of BTB hits +system.cpu1.branchPred.lookups 56473 # Number of BP lookups +system.cpu1.branchPred.condPredicted 53777 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1278 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 50438 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 49675 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.705421 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 648 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.487252 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 680 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 174790 # number of cpu cycles simulated +system.cpu1.numCycles 175078 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 24349 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 331605 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 58098 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 51961 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 112635 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3690 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 23829 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 25485 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 320653 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 56473 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 50355 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 109933 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 25650 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6397 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.NoActiveThreadStallCycles 6381 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 795 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 15584 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 170350 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.946610 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.217345 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 16660 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 170597 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.879593 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.199930 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 57715 33.88% 33.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 56197 32.99% 66.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 4087 2.40% 69.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3199 1.88% 71.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 641 0.38% 71.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 43239 25.38% 96.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1271 0.75% 97.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 756 0.44% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 60664 35.56% 35.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 55109 32.30% 67.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 4624 2.71% 70.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3194 1.87% 72.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 685 0.40% 72.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 41191 24.15% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1119 0.66% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 783 0.46% 98.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3228 1.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 170350 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.332387 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.897162 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27574 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 22245 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 108585 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3208 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2341 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 328108 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2341 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28283 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 9804 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11660 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 105676 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 6189 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 325946 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 230320 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 636644 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 636644 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 217343 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1083 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1203 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8803 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 95013 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 46485 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 44692 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 41453 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 273191 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 4270 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 273407 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10726 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10333 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 504 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 170350 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.604972 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.301874 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 170597 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.322559 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.831487 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 29160 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 23609 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 105420 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3678 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2349 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 317245 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2349 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 29851 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 11179 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11654 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 102051 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 7132 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 315250 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 222317 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 613423 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 613423 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 209500 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12817 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 9565 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 91347 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 44397 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 43115 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 39365 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 263703 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 4783 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 264442 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10738 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10286 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 531 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 170597 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.550098 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.309842 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54964 32.27% 32.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16569 9.73% 41.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 46599 27.35% 69.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 47325 27.78% 97.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3328 1.95% 99.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1208 0.71% 99.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 245 0.14% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 57935 33.96% 33.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 18114 10.62% 44.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 44440 26.05% 70.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 45139 26.46% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3372 1.98% 99.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1210 0.71% 99.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 275 0.16% 99.93% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 170350 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 170597 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 17 5.69% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 72 24.08% 29.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17 5.80% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 66 22.53% 28.33% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 130168 47.61% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 97443 35.64% 83.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 45796 16.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 126483 47.83% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 94216 35.63% 83.46% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 43743 16.54% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 273407 # Type of FU issued -system.cpu1.iq.rate 1.564203 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 299 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001094 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 717543 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 288232 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 271609 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 264442 # Type of FU issued +system.cpu1.iq.rate 1.510424 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 293 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001108 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 699908 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 279269 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 262662 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 273706 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 264735 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 41212 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 39130 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2369 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2377 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1440 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2341 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1392 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 323061 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 370 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 95013 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 46485 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1042 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2349 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1341 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 312497 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 91347 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 44397 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 928 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1384 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 272209 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 94088 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1198 # Number of squashed instructions skipped in execute +system.cpu1.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 950 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1409 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 263311 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 90404 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1131 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 45600 # number of nop insts executed -system.cpu1.iew.exec_refs 139806 # number of memory reference insts executed -system.cpu1.iew.exec_branches 54914 # Number of branches executed -system.cpu1.iew.exec_stores 45718 # Number of stores executed -system.cpu1.iew.exec_rate 1.557349 # Inst execution rate -system.cpu1.iew.wb_sent 271881 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 271609 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 156621 # num instructions producing a value -system.cpu1.iew.wb_consumers 161297 # num instructions consuming a value +system.cpu1.iew.exec_nop 44011 # number of nop insts executed +system.cpu1.iew.exec_refs 134069 # number of memory reference insts executed +system.cpu1.iew.exec_branches 53318 # Number of branches executed +system.cpu1.iew.exec_stores 43665 # Number of stores executed +system.cpu1.iew.exec_rate 1.503964 # Inst execution rate +system.cpu1.iew.wb_sent 262943 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 262662 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 150856 # num instructions producing a value +system.cpu1.iew.wb_consumers 155566 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.553916 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.971010 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.500257 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.969723 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12317 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 3766 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 161612 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.922772 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.097017 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12295 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 4252 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1278 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 161867 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.854590 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.083667 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 52280 32.35% 32.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 52948 32.76% 65.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6058 3.75% 68.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 4700 2.91% 71.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 41692 25.80% 98.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 528 0.33% 98.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1013 0.63% 99.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 55765 34.45% 34.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 51311 31.70% 66.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6076 3.75% 69.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 5204 3.21% 73.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1553 0.96% 74.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 39486 24.39% 98.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 647 0.40% 98.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1002 0.62% 99.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 161612 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 310743 # Number of instructions committed -system.cpu1.commit.committedOps 310743 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 161867 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 300197 # Number of instructions committed +system.cpu1.commit.committedOps 300197 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 137689 # Number of memory references committed -system.cpu1.commit.loads 92644 # Number of loads committed -system.cpu1.commit.membars 3055 # Number of memory barriers committed -system.cpu1.commit.branches 54067 # Number of branches committed +system.cpu1.commit.refs 131930 # Number of memory references committed +system.cpu1.commit.loads 88970 # Number of loads committed +system.cpu1.commit.membars 3544 # Number of memory barriers committed +system.cpu1.commit.branches 52469 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 213879 # Number of committed integer instructions. +system.cpu1.commit.int_insts 206526 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 822 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 823 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 483263 # The number of ROB reads -system.cpu1.rob.rob_writes 648465 # The number of ROB writes -system.cpu1.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 4440 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.rob.rob_reads 472949 # The number of ROB reads +system.cpu1.rob.rob_writes 627337 # The number of ROB writes +system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 4481 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 36812 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 262828 # Number of Instructions Simulated -system.cpu1.committedOps 262828 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 262828 # Number of Instructions Simulated -system.cpu1.cpi 0.665036 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.665036 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.503679 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.503679 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 478110 # number of integer regfile reads -system.cpu1.int_regfile_writes 222397 # number of integer regfile writes +system.cpu1.committedInsts 253388 # Number of Instructions Simulated +system.cpu1.committedOps 253388 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 253388 # Number of Instructions Simulated +system.cpu1.cpi 0.690948 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.690948 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.447286 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.447286 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 460976 # number of integer regfile reads +system.cpu1.int_regfile_writes 214498 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 141404 # number of misc regfile reads +system.cpu1.misc_regfile_reads 135647 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 85.239071 # Cycle average of tags in use -system.cpu1.icache.total_refs 15102 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 85.226466 # Cycle average of tags in use +system.cpu1.icache.total_refs 16176 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 35.534118 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 38.061176 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 85.239071 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.166483 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.166483 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 15102 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15102 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15102 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15102 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15102 # number of overall hits -system.cpu1.icache.overall_hits::total 15102 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 482 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 482 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 482 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses -system.cpu1.icache.overall_misses::total 482 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10460500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10460500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10460500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10460500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10460500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10460500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 15584 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 15584 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 15584 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 15584 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 15584 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 15584 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030929 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030929 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030929 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030929 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030929 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030929 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21702.282158 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21702.282158 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21702.282158 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21702.282158 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 85.226466 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.166458 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.166458 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 16176 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16176 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16176 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16176 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16176 # number of overall hits +system.cpu1.icache.overall_hits::total 16176 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 484 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 484 # number of ReadReq misses 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+system.cpu1.icache.ReadReq_accesses::total 16660 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16660 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16660 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16660 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16660 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029052 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029052 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029052 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029052 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029052 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029052 # miss rate for overall accesses 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-system.cpu1.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_hits::cpu1.data 298 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 298 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 298 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 298 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 151 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1798500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1798500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1487000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1487000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 402000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 402000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3285500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3285500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3285500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3285500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002876 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002876 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002379 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002379 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.830769 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002647 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002647 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11832.236842 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11832.236842 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13897.196262 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13897.196262 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7444.444444 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7444.444444 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1741000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1741000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1514500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1514500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 414000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 414000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3255500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3255500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3255500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3255500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002946 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002946 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002518 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002518 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002751 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002751 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11529.801325 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11529.801325 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14023.148148 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14023.148148 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 8280 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 8280 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 45099 # Number of BP lookups -system.cpu2.branchPred.condPredicted 42400 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1262 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 39025 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 38304 # Number of BTB hits +system.cpu2.branchPred.lookups 48435 # Number of BP lookups +system.cpu2.branchPred.condPredicted 45756 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1281 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 42366 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 41626 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.152466 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 646 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 98.253316 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 643 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 174459 # number of cpu cycles simulated +system.cpu2.numCycles 174747 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 32669 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 244823 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 45099 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 38950 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 90929 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 39674 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 30691 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 266889 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 48435 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 42269 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 96584 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3759 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 36275 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6379 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.NoActiveThreadStallCycles 6390 # Number of stall cycles due to no active thread to fetch from system.cpu2.fetch.PendingTrapStallCycles 712 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 24269 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 265 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 172730 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.417374 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.028063 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.CacheLines 22267 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 173057 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.542203 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.085998 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 81801 47.36% 47.36% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 47495 27.50% 74.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8404 4.87% 79.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3201 1.85% 81.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 675 0.39% 81.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 25947 15.02% 96.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1207 0.70% 97.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 760 0.44% 98.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3240 1.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 76473 44.19% 44.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 49798 28.78% 72.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 7404 4.28% 77.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3211 1.86% 79.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 674 0.39% 79.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 30262 17.49% 96.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1242 0.72% 97.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 752 0.43% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3241 1.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 172730 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.258508 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.403327 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 39762 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 34129 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 82888 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 7209 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2363 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 241309 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2363 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 40462 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 21352 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11989 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 75976 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14209 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 239275 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 36 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 165256 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 446077 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 446077 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 152520 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12736 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1091 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1215 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 16777 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 64738 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 29196 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 31698 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 24168 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 195168 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8612 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 199473 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 10767 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10430 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 172730 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.154825 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.283743 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 173057 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.277172 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.527288 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 36897 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 31644 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 89441 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 6284 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2401 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 263319 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2401 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 37621 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 18625 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12236 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 83428 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12356 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 261093 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 181374 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 493566 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 493566 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 168473 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12901 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1100 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 15080 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 72313 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 33498 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 35025 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 28444 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 214608 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 7657 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 217768 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 10976 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11107 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 637 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 173057 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.258360 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.300957 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 79387 45.96% 45.96% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 29099 16.85% 62.81% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 29295 16.96% 79.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 30090 17.42% 97.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3300 1.91% 99.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1204 0.70% 99.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 247 0.14% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 56 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 74099 42.82% 42.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 26214 15.15% 57.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 33561 19.39% 77.36% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 34357 19.85% 97.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3304 1.91% 99.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1156 0.67% 99.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 172730 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 173057 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 16 5.67% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 56 19.86% 25.53% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 74.47% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 17 5.65% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 74 24.58% 30.23% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 99688 49.98% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 71251 35.72% 85.70% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 28534 14.30% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 107188 49.22% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 77805 35.73% 84.95% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 32775 15.05% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 199473 # Type of FU issued -system.cpu2.iq.rate 1.143380 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 282 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001414 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 572030 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 214590 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 197726 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 217768 # Type of FU issued +system.cpu2.iq.rate 1.246190 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 609024 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 233287 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 215963 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 199755 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 218069 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 23953 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 28178 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2414 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2489 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1398 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1471 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2363 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 870 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 236415 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 392 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 64738 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 29196 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2401 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 915 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 258202 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 343 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 72313 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 33498 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1067 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 66 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 913 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1372 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 198312 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 63718 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1161 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 926 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1391 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 216605 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 71227 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1163 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 32635 # number of nop insts executed -system.cpu2.iew.exec_refs 92179 # number of memory reference insts executed -system.cpu2.iew.exec_branches 41831 # Number of branches executed -system.cpu2.iew.exec_stores 28461 # Number of stores executed -system.cpu2.iew.exec_rate 1.136726 # Inst execution rate -system.cpu2.iew.wb_sent 197998 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 197726 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 108943 # num instructions producing a value -system.cpu2.iew.wb_consumers 113613 # num instructions consuming a value +system.cpu2.iew.exec_nop 35937 # number of nop insts executed +system.cpu2.iew.exec_refs 103922 # number of memory reference insts executed +system.cpu2.iew.exec_branches 45106 # Number of branches executed +system.cpu2.iew.exec_stores 32695 # Number of stores executed +system.cpu2.iew.exec_rate 1.239535 # Inst execution rate +system.cpu2.iew.wb_sent 216253 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 215963 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 120625 # num instructions producing a value +system.cpu2.iew.wb_consumers 125288 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.133367 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.958896 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.235861 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.962782 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12414 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7958 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1262 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 163988 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.365838 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.905647 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12625 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7020 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1281 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 164266 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.494880 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.964665 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 80806 49.28% 49.28% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 39854 24.30% 73.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6054 3.69% 77.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 8882 5.42% 82.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1574 0.96% 83.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 24481 14.93% 98.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 507 0.31% 98.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1010 0.62% 99.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 820 0.50% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 74448 45.32% 45.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 43200 26.30% 71.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6076 3.70% 75.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7927 4.83% 80.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1577 0.96% 81.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 28745 17.50% 98.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 476 0.29% 98.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1000 0.61% 99.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 817 0.50% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 163988 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 223981 # Number of instructions committed -system.cpu2.commit.committedOps 223981 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 164266 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 245558 # Number of instructions committed +system.cpu2.commit.committedOps 245558 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 90122 # Number of memory references committed -system.cpu2.commit.loads 62324 # Number of loads committed -system.cpu2.commit.membars 7244 # Number of memory barriers committed -system.cpu2.commit.branches 41003 # Number of branches committed +system.cpu2.commit.refs 101851 # Number of memory references committed +system.cpu2.commit.loads 69824 # Number of loads committed +system.cpu2.commit.membars 6301 # Number of memory barriers committed +system.cpu2.commit.branches 44289 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 153248 # Number of committed integer instructions. +system.cpu2.commit.int_insts 168258 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 820 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 398976 # The number of ROB reads -system.cpu2.rob.rob_writes 475157 # The number of ROB writes -system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1729 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.rob.rob_reads 421045 # The number of ROB reads +system.cpu2.rob.rob_writes 518771 # The number of ROB writes +system.cpu2.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1690 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 37143 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 184944 # Number of Instructions Simulated -system.cpu2.committedOps 184944 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 184944 # Number of Instructions Simulated -system.cpu2.cpi 0.943307 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.943307 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.060100 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.060100 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 335090 # number of integer regfile reads -system.cpu2.int_regfile_writes 157371 # number of integer regfile writes +system.cpu2.committedInsts 204183 # Number of Instructions Simulated +system.cpu2.committedOps 204183 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 204183 # Number of Instructions Simulated +system.cpu2.cpi 0.855835 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.855835 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.168449 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.168449 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 370277 # number of integer regfile reads +system.cpu2.int_regfile_writes 173276 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 93758 # number of misc regfile reads +system.cpu2.misc_regfile_reads 105484 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.replacements 319 # number of replacements -system.cpu2.icache.tagsinuse 83.416337 # Cycle average of tags in use -system.cpu2.icache.total_refs 23791 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 83.493778 # Cycle average of tags in use +system.cpu2.icache.total_refs 21789 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 55.327907 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 50.672093 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 83.416337 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.162923 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.162923 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 23791 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 23791 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 23791 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 23791 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 23791 # number of overall hits -system.cpu2.icache.overall_hits::total 23791 # number of overall hits +system.cpu2.icache.occ_blocks::cpu2.inst 83.493778 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.163074 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 21789 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 21789 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 21789 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 21789 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 21789 # number of overall hits +system.cpu2.icache.overall_hits::total 21789 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 478 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 478 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 478 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 478 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 478 # number of overall misses system.cpu2.icache.overall_misses::total 478 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6751000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6751000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6751000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6751000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6751000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6751000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 24269 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 24269 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 24269 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 24269 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 24269 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 24269 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.019696 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.019696 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.019696 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.019696 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.019696 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.019696 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14123.430962 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14123.430962 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14123.430962 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14123.430962 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6833500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6833500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6833500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6833500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6833500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6833500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 22267 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 22267 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 22267 # number of demand (read+write) accesses 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latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14296.025105 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14296.025105 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14296.025105 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14296.025105 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1481,94 +1481,94 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 430 system.cpu2.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 430 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5435000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5435000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5435000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5435000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5435000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5435000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017718 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.017718 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.017718 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12639.534884 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5518500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5518500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5518500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5518500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5518500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5518500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.019311 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.019311 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12833.720930 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12833.720930 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12833.720930 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 25.649065 # Cycle average of tags in use -system.cpu2.dcache.total_refs 33911 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1169.344828 # Average number of references to valid blocks. +system.cpu2.dcache.tagsinuse 25.660288 # Cycle average of tags in use +system.cpu2.dcache.total_refs 38032 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1358.285714 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 25.649065 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.050096 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.050096 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 39345 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 39345 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 27592 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 27592 # number of WriteReq hits +system.cpu2.dcache.occ_blocks::cpu2.data 25.660288 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.050118 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.050118 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42624 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42624 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 31820 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 31820 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 66937 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 66937 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 66937 # number of overall hits -system.cpu2.dcache.overall_hits::total 66937 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 402 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 402 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 138 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 138 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 540 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 540 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 540 # number of overall misses -system.cpu2.dcache.overall_misses::total 540 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5276000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5276000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2759500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2759500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 558000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 558000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 8035500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 8035500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 8035500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 8035500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 39747 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 39747 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 27730 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 27730 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 67477 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 67477 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 67477 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 67477 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010114 # miss rate for ReadReq accesses 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-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19996.376812 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 19996.376812 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10528.301887 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 10528.301887 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 14880.555556 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 14880.555556 # average overall miss latency +system.cpu2.dcache.demand_hits::cpu2.data 74444 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 74444 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 74444 # number of overall hits +system.cpu2.dcache.overall_hits::total 74444 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 407 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 407 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 134 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 134 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 541 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 541 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 541 # number of overall misses +system.cpu2.dcache.overall_misses::total 541 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5612500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5612500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2750000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 572000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 572000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 8362500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 8362500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 8362500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 8362500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 43031 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 43031 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 31954 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 31954 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 74985 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 74985 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 74985 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 74985 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009458 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.009458 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004194 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004194 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794521 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.794521 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007215 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007215 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007215 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007215 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13789.926290 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 13789.926290 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20522.388060 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20522.388060 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9862.068966 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 9862.068966 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15457.486137 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 15457.486137 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15457.486137 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 15457.486137 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1577,365 +1577,365 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 241 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 241 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 246 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 274 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 274 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 274 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 274 # number of overall MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 279 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 279 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 53 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 266 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 266 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1358500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1358500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1350500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1350500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 452000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 452000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2709000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2709000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2709000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2709000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004051 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004051 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003787 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003787 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.779412 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.779412 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003942 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003942 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8437.888199 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8437.888199 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 12861.904762 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 12861.904762 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8528.301887 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8528.301887 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1373500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1373500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1349000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1349000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2722500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2722500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2722500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2722500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003741 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003741 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003161 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003161 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794521 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794521 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003494 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003494 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8531.055901 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8531.055901 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13356.435644 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13356.435644 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7862.068966 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7862.068966 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 47073 # Number of BP lookups -system.cpu3.branchPred.condPredicted 44334 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1289 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 40998 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 40129 # Number of BTB hits +system.cpu3.branchPred.lookups 45379 # Number of BP lookups +system.cpu3.branchPred.condPredicted 42609 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1294 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 39317 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 38445 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.880384 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.782130 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 651 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 174149 # number of cpu cycles simulated +system.cpu3.numCycles 174437 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 31334 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 257802 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 47073 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 40794 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 94093 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3784 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 37693 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 32466 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 246453 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 45379 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 39096 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 91198 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3791 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 39692 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6388 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 691 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 23091 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 172622 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.493448 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.066617 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6399 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 24152 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 172879 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.425581 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.034525 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 78529 45.49% 45.49% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 48697 28.21% 73.70% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 7780 4.51% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3181 1.84% 80.05% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 739 0.43% 80.48% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 28510 16.52% 97.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1109 0.64% 97.64% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 774 0.45% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3303 1.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 81681 47.25% 47.25% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 47531 27.49% 74.74% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8280 4.79% 79.53% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3183 1.84% 81.37% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 751 0.43% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 26265 15.19% 97.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1130 0.65% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 760 0.44% 98.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3298 1.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 172622 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.270303 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.480353 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 38095 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 32492 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 86590 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 6639 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2418 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 254216 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2418 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 38798 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 19631 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12074 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 80231 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 13082 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 251848 # Number of instructions processed by rename +system.cpu3.fetch.rateDist::total 172879 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.260145 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.412848 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 39667 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 34044 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 83244 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7105 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2420 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 242894 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2420 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 40390 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 21128 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12127 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 76402 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 14013 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 240516 # Number of instructions processed by rename system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 33 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 174600 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 473869 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 473869 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 161804 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 12796 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1100 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1222 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 15769 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 69165 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 31749 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 33643 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 26714 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 206536 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7999 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 210100 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10964 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10853 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 623 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 172622 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.217110 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.294923 # Number of insts issued each cycle +system.cpu3.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 166179 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 449032 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 449032 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 153365 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12814 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1105 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1221 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 16705 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 65194 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 29511 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 31885 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 24466 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 196370 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8514 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 200412 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10978 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11006 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 643 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 172879 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.159262 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.284832 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 76068 44.07% 44.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 27297 15.81% 59.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 31861 18.46% 78.34% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 32569 18.87% 97.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3286 1.90% 99.11% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1177 0.68% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 258 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 79312 45.88% 45.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 28822 16.67% 62.55% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 29551 17.09% 79.64% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 30339 17.55% 97.19% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3334 1.93% 99.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1154 0.67% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 172622 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 172879 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 11 3.79% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 69 23.79% 27.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 72.41% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 12 4.07% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 73 24.75% 28.81% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 104024 49.51% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 75016 35.70% 85.22% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 31060 14.78% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 100076 49.94% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 71520 35.69% 85.62% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 28816 14.38% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 210100 # Type of FU issued -system.cpu3.iq.rate 1.206438 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 290 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001380 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 593222 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 225545 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 208328 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 200412 # Type of FU issued +system.cpu3.iq.rate 1.148908 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 295 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001472 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 574125 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 215907 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 198595 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 210390 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 200707 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 26418 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 24188 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2499 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2497 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1475 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2418 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 854 # Number of cycles IEW is blocking +system.cpu3.iew.iewSquashCycles 2420 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 942 # Number of cycles IEW is blocking system.cpu3.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 249047 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 69165 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 31749 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1065 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewDispatchedInsts 237691 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 65194 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 29511 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1069 # Number of dispatched non-speculative instructions system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 473 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1408 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 208934 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 68077 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1166 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 475 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1407 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 199248 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 64095 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1164 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 34512 # number of nop insts executed -system.cpu3.iew.exec_refs 99056 # number of memory reference insts executed -system.cpu3.iew.exec_branches 43690 # Number of branches executed -system.cpu3.iew.exec_stores 30979 # Number of stores executed -system.cpu3.iew.exec_rate 1.199743 # Inst execution rate -system.cpu3.iew.wb_sent 208597 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 208328 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 115832 # num instructions producing a value -system.cpu3.iew.wb_consumers 120507 # num instructions consuming a value +system.cpu3.iew.exec_nop 32807 # number of nop insts executed +system.cpu3.iew.exec_refs 92831 # number of memory reference insts executed +system.cpu3.iew.exec_branches 41971 # Number of branches executed +system.cpu3.iew.exec_stores 28736 # Number of stores executed +system.cpu3.iew.exec_rate 1.142235 # Inst execution rate +system.cpu3.iew.wb_sent 198881 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 198595 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 109565 # num instructions producing a value +system.cpu3.iew.wb_consumers 114222 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.196263 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.961206 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.138491 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.959229 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 12582 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7376 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1289 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 163816 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.443357 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.942306 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 12643 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7871 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1294 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 164060 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.371620 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.908371 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 76810 46.89% 46.89% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 41800 25.52% 72.40% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6086 3.72% 76.12% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8257 5.04% 81.16% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1545 0.94% 82.10% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 27022 16.50% 98.60% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 472 0.29% 98.89% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1012 0.62% 99.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 80528 49.08% 49.08% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 40048 24.41% 73.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6110 3.72% 77.22% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8758 5.34% 82.56% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1552 0.95% 83.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 24728 15.07% 98.58% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 520 0.32% 98.89% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1010 0.62% 99.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 806 0.49% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 163816 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 236445 # Number of instructions committed -system.cpu3.commit.committedOps 236445 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 164060 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 225028 # Number of instructions committed +system.cpu3.commit.committedOps 225028 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 96940 # Number of memory references committed -system.cpu3.commit.loads 66666 # Number of loads committed -system.cpu3.commit.membars 6656 # Number of memory barriers committed -system.cpu3.commit.branches 42889 # Number of branches committed +system.cpu3.commit.refs 90734 # Number of memory references committed +system.cpu3.commit.loads 62697 # Number of loads committed +system.cpu3.commit.membars 7153 # Number of memory barriers committed +system.cpu3.commit.branches 41151 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 161946 # Number of committed integer instructions. +system.cpu3.commit.int_insts 154003 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 806 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 411444 # The number of ROB reads -system.cpu3.rob.rob_writes 500477 # The number of ROB writes -system.cpu3.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1527 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.rob.rob_reads 400338 # The number of ROB reads +system.cpu3.rob.rob_writes 477767 # The number of ROB writes +system.cpu3.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1558 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu3.quiesceCycles 37453 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 196116 # Number of Instructions Simulated -system.cpu3.committedOps 196116 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 196116 # Number of Instructions Simulated -system.cpu3.cpi 0.887990 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.887990 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.126139 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.126139 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 355696 # number of integer regfile reads -system.cpu3.int_regfile_writes 166589 # number of integer regfile writes +system.cpu3.committedInsts 185938 # Number of Instructions Simulated +system.cpu3.committedOps 185938 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 185938 # Number of Instructions Simulated +system.cpu3.cpi 0.938146 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.938146 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.065932 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.065932 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 337021 # number of integer regfile reads +system.cpu3.int_regfile_writes 158120 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 100584 # number of misc regfile reads +system.cpu3.misc_regfile_reads 94371 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.replacements 318 # number of replacements -system.cpu3.icache.tagsinuse 80.204482 # Cycle average of tags in use -system.cpu3.icache.total_refs 22614 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 80.241223 # Cycle average of tags in use +system.cpu3.icache.total_refs 23677 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 429 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 52.713287 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 55.191142 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 80.204482 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.156649 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.156649 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 22614 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 22614 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 22614 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 22614 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 22614 # number of overall hits -system.cpu3.icache.overall_hits::total 22614 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 477 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 477 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 477 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 477 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 477 # number of overall misses -system.cpu3.icache.overall_misses::total 477 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6252000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6252000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6252000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6252000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6252000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6252000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 23091 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 23091 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 23091 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 23091 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 23091 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 23091 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020657 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.020657 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020657 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.020657 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020657 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.020657 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13106.918239 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13106.918239 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13106.918239 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13106.918239 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 80.241223 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.156721 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.156721 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 23677 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 23677 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 23677 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 23677 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 23677 # number of overall hits +system.cpu3.icache.overall_hits::total 23677 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses +system.cpu3.icache.overall_misses::total 475 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6195500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6195500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6195500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6195500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6195500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6195500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 24152 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 24152 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 24152 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 24152 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 24152 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 24152 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.019667 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.019667 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.019667 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.019667 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.019667 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.019667 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13043.157895 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13043.157895 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13043.157895 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13043.157895 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13043.157895 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13043.157895 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1944,106 +1944,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 48 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 48 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 48 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 48 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4992500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4992500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4992500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4992500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4992500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4992500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.018579 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.018579 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.018579 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11637.529138 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11637.529138 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11637.529138 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 11637.529138 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11637.529138 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 11637.529138 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4977500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4977500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4977500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4977500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4977500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4977500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017763 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017763 # 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occupancy system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000035 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000025 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006489 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.006490 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 230 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 342 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 343 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 418 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 416 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 11 # number 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UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 71 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 74 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses @@ -2178,54 +2178,54 @@ system.l2c.ReadExReq_misses::cpu3.data 12 # nu system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses system.l2c.demand_misses::cpu0.inst 360 # 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demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 216500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 825500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 37064500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 18249500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 10005500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4327000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1663000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 840500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 937000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 216500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 825500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 37064500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 590 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses) @@ -2238,10 +2238,10 @@ system.l2c.ReadReq_accesses::total 1989 # nu system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 77 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) @@ -2267,18 +2267,18 @@ system.l2c.overall_accesses::cpu3.data 24 # nu system.l2c.overall_accesses::total 2120 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.610169 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.195294 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.192941 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.027907 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.032558 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.013986 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.011655 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.273504 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.857143 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.959459 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.961039 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -2286,54 +2286,54 @@ system.l2c.ReadExReq_miss_rate::cpu3.data 1 # m system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.610169 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.195294 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 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cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 86253 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 663761 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 28135994 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 113753 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 664761 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 28141994 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses @@ -2444,7 +2444,7 @@ system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.857143 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.959459 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.961039 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -2452,59 +2452,59 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.311792 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.162162 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49906 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28751 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.152830 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40993.700000 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10639.500000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10247.211268 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10050.900000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10118.411765 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10553.368421 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10237.229730 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45181.468085 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64519.615385 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64596.538462 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60000.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50625.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 48956.740458 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50709.166667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 48972.007634 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47262.511905 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70900.550000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47262.511905 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70900.550000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index c755fbf49..b4eef5d4b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -439,6 +439,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -462,6 +463,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index d217747b2..adbb7069b 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -3,33 +3,33 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 15:51:52 +gem5 compiled Mar 26 2013 15:04:14 +gem5 started Mar 26 2013 15:04:37 gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 -[Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 Iteration 1 completed -[Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 Iteration 2 completed -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 Iteration 3 completed [Iteration 4, Thread 2] Got lock [Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 @@ -38,12 +38,12 @@ Iteration 3 completed [Iteration 4, Thread 1] Got lock [Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 Iteration 4 completed -[Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 Iteration 5 completed [Iteration 6, Thread 2] Got lock [Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 @@ -52,12 +52,12 @@ Iteration 5 completed [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 Iteration 6 completed -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 7, Thread 3] Got lock [Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 Iteration 7 completed [Iteration 8, Thread 2] Got lock [Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 @@ -66,12 +66,12 @@ Iteration 7 completed [Iteration 8, Thread 1] Got lock [Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 Iteration 9 completed [Iteration 10, Thread 2] Got lock [Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 @@ -81,4 +81,4 @@ Iteration 9 completed [Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 261623500 because target called exit() +Exiting @ tick 262970500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 03a5c597b..f34b8a118 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000262 # Number of seconds simulated -sim_ticks 261623500 # Number of ticks simulated -final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000263 # Number of seconds simulated +sim_ticks 262970500 # Number of ticks simulated +final_tick 262970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226128 # Simulator instruction rate (inst/s) -host_op_rate 226126 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89603226 # Simulator tick rate (ticks/s) -host_mem_usage 289396 # Number of bytes of host memory used -host_seconds 2.92 # Real time elapsed on the host -sim_insts 660239 # Number of instructions simulated -sim_ops 660239 # Number of ops (including micro ops) simulated +host_inst_rate 110323 # Simulator instruction rate (inst/s) +host_op_rate 110323 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43749084 # Simulator tick rate (ticks/s) +host_mem_usage 287188 # Number of bytes of host memory used +host_seconds 6.01 # Real time elapsed on the host +sim_insts 663135 # Number of instructions simulated +sim_ops 663135 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 3392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 4224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 3392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 4224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 53 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 66 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69718508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40363347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 1712384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3669395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2201637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3914021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 12965196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 5381780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139926268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69718508 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 1712384 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2201637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 12965196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86597725 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69718508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40363347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1712384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3669395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2201637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3914021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 12965196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 5381780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139926268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69361392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40156596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16062638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5597586 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 486747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3650600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 243373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3650600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139209531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69361392 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16062638 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 486747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 243373 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86154150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69361392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40156596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16062638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5597586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 486747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3650600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 243373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3650600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139209531 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 523247 # number of cpu cycles simulated +system.cpu0.numCycles 525941 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158010 # Number of instructions committed -system.cpu0.committedOps 158010 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108832 # Number of integer alu accesses +system.cpu0.committedInsts 158580 # Number of instructions committed +system.cpu0.committedOps 158580 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 109212 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25938 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108832 # number of integer instructions +system.cpu0.num_conditional_control_insts 26033 # number of instructions that are conditional controls +system.cpu0.num_int_insts 109212 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 314654 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110438 # number of times the integer registers were written +system.cpu0.num_int_register_reads 315794 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110818 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73739 # number of memory refs -system.cpu0.num_load_insts 48819 # Number of load instructions -system.cpu0.num_store_insts 24920 # Number of store instructions +system.cpu0.num_mem_refs 74024 # number of memory refs +system.cpu0.num_load_insts 49009 # Number of load instructions +system.cpu0.num_store_insts 25015 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 523247 # Number of busy cycles +system.cpu0.num_busy_cycles 525941 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.464540 # Cycle average of tags in use -system.cpu0.icache.total_refs 157606 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 212.410852 # Cycle average of tags in use +system.cpu0.icache.total_refs 158176 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 337.486081 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 338.706638 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.464540 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414970 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414970 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 157606 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157606 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157606 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157606 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157606 # number of overall hits -system.cpu0.icache.overall_hits::total 157606 # number of overall hits +system.cpu0.icache.occ_blocks::cpu0.inst 212.410852 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414865 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414865 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 158176 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 158176 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 158176 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 158176 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 158176 # number of overall hits +system.cpu0.icache.overall_hits::total 158176 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18144000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18144000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18144000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18144000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18144000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18144000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158073 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158073 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158073 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158073 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158073 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158073 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002954 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002954 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002954 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002954 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002954 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002954 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38852.248394 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38852.248394 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38852.248394 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38852.248394 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18143000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18143000 # number of ReadReq miss cycles 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0.002944 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38850.107066 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38850.107066 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38850.107066 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38850.107066 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -139,94 +139,94 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17210000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17210000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17210000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17210000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17210000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17210000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002954 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002954 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002954 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36852.248394 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17209000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17209000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17209000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17209000 # number of demand (read+write) MSHR miss cycles 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latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36850.107066 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36850.107066 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 145.601248 # Cycle average of tags in use -system.cpu0.dcache.total_refs 73215 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 145.568014 # Cycle average of tags in use +system.cpu0.dcache.total_refs 73491 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 438.413174 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 440.065868 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.601248 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284377 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284377 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 48647 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48647 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24686 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24686 # number of WriteReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 145.568014 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284313 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284313 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 48828 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48828 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73333 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73333 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73333 # number of overall hits -system.cpu0.dcache.overall_hits::total 73333 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses 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misses -system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses -system.cpu0.dcache.overall_misses::total 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4649500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7005000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7005000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 363500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 363500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11654500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11654500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11654500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11654500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48809 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48809 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24869 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24869 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 355 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 355 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 355 # number of overall misses +system.cpu0.dcache.overall_misses::total 355 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4683500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4683500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7047500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7047500 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 364500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 364500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11731000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11731000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11731000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11731000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48999 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48999 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24964 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24964 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73678 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73678 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73678 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73678 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003319 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003319 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007359 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007359 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73963 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73963 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73963 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73963 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003490 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003490 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007371 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007371 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004683 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004683 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004683 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004683 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28700.617284 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28700.617284 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38278.688525 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38278.688525 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13980.769231 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 13980.769231 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33781.159420 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33781.159420 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004800 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004800 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004800 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004800 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27388.888889 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27388.888889 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38301.630435 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38301.630435 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14019.230769 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 14019.230769 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33045.070423 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33045.070423 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -237,114 +237,114 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 171 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 184 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 184 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4325500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4325500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6639000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6639000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10964500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10964500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10964500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10964500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003319 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003319 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007359 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 355 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 355 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4341500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4341500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6679500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6679500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 312500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 312500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11021000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11021000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11021000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11021000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003490 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003490 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007371 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007371 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004683 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004683 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26700.617284 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26700.617284 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36278.688525 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36278.688525 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11980.769231 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11980.769231 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004800 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004800 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004800 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004800 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25388.888889 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25388.888889 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36301.630435 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36301.630435 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12019.230769 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12019.230769 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31045.070423 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31045.070423 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31045.070423 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31045.070423 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 523247 # number of cpu cycles simulated +system.cpu1.numCycles 525940 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 173283 # Number of instructions committed -system.cpu1.committedOps 173283 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 108736 # Number of integer alu accesses +system.cpu1.committedInsts 166746 # Number of instructions committed +system.cpu1.committedOps 166746 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 110403 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 36284 # number of instructions that are conditional controls -system.cpu1.num_int_insts 108736 # number of integer instructions +system.cpu1.num_conditional_control_insts 32184 # number of instructions that are conditional controls +system.cpu1.num_int_insts 110403 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 252002 # number of times the integer registers were read -system.cpu1.num_int_register_writes 93825 # number of times the integer registers were written +system.cpu1.num_int_register_reads 275077 # number of times the integer registers were read +system.cpu1.num_int_register_writes 104543 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 48621 # number of memory refs -system.cpu1.num_load_insts 40031 # Number of load instructions -system.cpu1.num_store_insts 8590 # Number of store instructions -system.cpu1.num_idle_cycles 68750.001737 # Number of idle cycles -system.cpu1.num_busy_cycles 454496.998263 # Number of busy cycles -system.cpu1.not_idle_fraction 0.868609 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.131391 # Percentage of idle cycles +system.cpu1.num_mem_refs 54388 # number of memory refs +system.cpu1.num_load_insts 40871 # Number of load instructions +system.cpu1.num_store_insts 13517 # Number of store instructions +system.cpu1.num_idle_cycles 69336.869902 # Number of idle cycles +system.cpu1.num_busy_cycles 456603.130098 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868166 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131834 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 65.593035 # Cycle average of tags in use -system.cpu1.icache.total_refs 172950 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 70.021877 # Cycle average of tags in use +system.cpu1.icache.total_refs 166413 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 472.540984 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 454.680328 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 65.593035 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.128111 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.128111 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 172950 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 172950 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 172950 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 172950 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 172950 # number of overall hits -system.cpu1.icache.overall_hits::total 172950 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 70.021877 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.136761 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.136761 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 166413 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 166413 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 166413 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 166413 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 166413 # number of overall hits +system.cpu1.icache.overall_hits::total 166413 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5373500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5373500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5373500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5373500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5373500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5373500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 173316 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 173316 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 173316 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 173316 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 173316 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 173316 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002112 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002112 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002112 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002112 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002112 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002112 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14681.693989 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14681.693989 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14681.693989 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14681.693989 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7565000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7565000 # number of ReadReq miss cycles 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0.002195 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002195 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002195 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002195 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002195 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002195 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20669.398907 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20669.398907 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20669.398907 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20669.398907 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20669.398907 # average overall miss latency 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of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 54313 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 54313 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 54313 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 54313 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003744 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003744 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007881 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.007881 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.769231 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.769231 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004769 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004769 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004769 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004769 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19310.457516 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19310.457516 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18509.433962 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18509.433962 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 5480 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 5480 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18982.625483 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18982.625483 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -455,114 +455,114 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 177 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 282 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 282 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 282 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 282 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2962000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2962000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1665500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1665500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 549500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 549500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4627500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4627500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4627500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4627500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004422 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004422 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012328 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012328 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.774648 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.774648 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005810 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005810 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16734.463277 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16734.463277 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15861.904762 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15861.904762 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 9990.909091 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 9990.909091 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency 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+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2648500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1750000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1750000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 174000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 174000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4398500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4398500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4398500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4398500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003744 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003744 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007881 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007881 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.769231 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.769231 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004769 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004769 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004769 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004769 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17310.457516 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17310.457516 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16509.433962 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16509.433962 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3480 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3480 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency 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27518 # number of instructions that are conditional controls -system.cpu2.num_int_insts 113639 # number of integer instructions +system.cpu2.num_conditional_control_insts 33551 # number of instructions that are conditional controls +system.cpu2.num_int_insts 110917 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 306682 # number of times the integer registers were read -system.cpu2.num_int_register_writes 118721 # number of times the integer registers were written +system.cpu2.num_int_register_reads 271666 # number of times the integer registers were read +system.cpu2.num_int_register_writes 102578 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 62290 # number of memory refs -system.cpu2.num_load_insts 42488 # Number of load instructions -system.cpu2.num_store_insts 19802 # Number of store instructions -system.cpu2.num_idle_cycles 69015.869837 # Number of idle cycles -system.cpu2.num_busy_cycles 454230.130163 # Number of busy cycles -system.cpu2.not_idle_fraction 0.868101 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.131899 # Percentage of idle cycles -system.cpu2.icache.replacements 281 # number of replacements -system.cpu2.icache.tagsinuse 67.731754 # Cycle average of tags in use -system.cpu2.icache.total_refs 160331 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 436.869210 # Average number of references to valid blocks. +system.cpu2.num_mem_refs 53535 # number of memory refs +system.cpu2.num_load_insts 41127 # Number of load instructions +system.cpu2.num_store_insts 12408 # Number of store instructions +system.cpu2.num_idle_cycles 69585.001735 # Number of idle cycles +system.cpu2.num_busy_cycles 456355.998265 # Number of busy cycles +system.cpu2.not_idle_fraction 0.867694 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.132306 # Percentage of idle cycles +system.cpu2.icache.replacements 280 # number of replacements +system.cpu2.icache.tagsinuse 65.527396 # Cycle average of tags in use +system.cpu2.icache.total_refs 169662 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 463.557377 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 67.731754 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.132289 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.132289 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 160331 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 160331 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 160331 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 160331 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 160331 # number of overall hits -system.cpu2.icache.overall_hits::total 160331 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 367 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 367 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 367 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 367 # number of overall misses -system.cpu2.icache.overall_misses::total 367 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5321500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5321500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5321500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5321500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5321500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5321500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 160698 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 160698 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 160698 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 160698 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 160698 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 160698 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002284 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002284 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002284 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002284 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002284 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002284 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14500 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14500 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14500 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14500 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14500 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14500 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 65.527396 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.127983 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.127983 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 169662 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 169662 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 169662 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 169662 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 169662 # number of overall hits +system.cpu2.icache.overall_hits::total 169662 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses +system.cpu2.icache.overall_misses::total 366 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5281000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5281000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5281000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5281000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5281000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5281000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 170028 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 170028 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 170028 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 170028 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 170028 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 170028 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002153 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002153 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002153 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14428.961749 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14428.961749 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14428.961749 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14428.961749 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14428.961749 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14428.961749 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -571,100 +571,100 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 367 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 367 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 367 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4587500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4587500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4587500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4587500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4587500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4587500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002284 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12500 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12500 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4549000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 4549000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4549000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 4549000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4549000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 4549000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12428.961749 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12428.961749 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12428.961749 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 26.833050 # Cycle average of tags in use -system.cpu2.dcache.total_refs 41851 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 25.908378 # Cycle average of tags in use +system.cpu2.dcache.total_refs 27066 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1443.137931 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 933.310345 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 26.833050 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.052408 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.052408 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 42328 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42328 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 19626 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 19626 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 61954 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 61954 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 61954 # number of overall hits -system.cpu2.dcache.overall_hits::total 61954 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 106 # number of WriteReq misses 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SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 62212 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 62212 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 62212 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 62212 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003578 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003578 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005372 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.005372 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.852941 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.852941 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004147 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004147 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004147 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004147 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12750 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 12750 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20330.188679 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 20330.188679 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10560.344828 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 10560.344828 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 15864.341085 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 15864.341085 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 25.908378 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.050602 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.050602 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 40963 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40963 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 12235 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 12235 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits 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overall misses +system.cpu2.dcache.overall_misses::total 262 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2754500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2754500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1914500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 1914500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 286000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 286000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4669000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4669000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4669000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4669000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 41120 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 41120 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 12340 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 12340 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 53460 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 53460 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 53460 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 53460 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003818 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003818 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008509 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.008509 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.772727 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.772727 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004901 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004901 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004901 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004901 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17544.585987 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 17544.585987 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18233.333333 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 18233.333333 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5607.843137 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 5607.843137 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17820.610687 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17820.610687 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17820.610687 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17820.610687 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,114 +673,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 258 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 258 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 258 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 258 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1634000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1634000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1943000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1943000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 496500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 496500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3577000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3577000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3577000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3577000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003578 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003578 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.005372 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.005372 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.852941 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.852941 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004147 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004147 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10750 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10750 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 18330.188679 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 18330.188679 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8560.344828 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8560.344828 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 157 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses 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+system.cpu2.dcache.demand_mshr_miss_latency::total 4145000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4145000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 4145000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003818 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003818 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.008509 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.008509 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.772727 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.772727 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004901 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004901 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004901 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004901 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15544.585987 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15544.585987 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16233.333333 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16233.333333 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3607.843137 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3607.843137 # average SwapReq mshr miss latency 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alu accesses +system.cpu3.committedInsts 167814 # Number of instructions committed +system.cpu3.committedOps 167814 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 111369 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 33752 # number of instructions that are conditional controls -system.cpu3.num_int_insts 108796 # number of integer instructions +system.cpu3.num_conditional_control_insts 32222 # number of instructions that are conditional controls +system.cpu3.num_int_insts 111369 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 262371 # number of times the integer registers were read -system.cpu3.num_int_register_writes 98980 # number of times the integer registers were written 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Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 458.874317 # Average number of references to valid blocks. +system.cpu3.num_mem_refs 55316 # number of memory refs +system.cpu3.num_load_insts 41342 # Number of load instructions +system.cpu3.num_store_insts 13974 # Number of store instructions +system.cpu3.num_idle_cycles 69844.868934 # Number of idle cycles +system.cpu3.num_busy_cycles 456095.131066 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867200 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132800 # Percentage of idle cycles +system.cpu3.icache.replacements 281 # number of replacements +system.cpu3.icache.tagsinuse 67.672766 # Cycle average of tags in use +system.cpu3.icache.total_refs 167480 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 456.348774 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 70.063196 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.136842 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.136842 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 167948 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 167948 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 167948 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 167948 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 167948 # number of overall hits -system.cpu3.icache.overall_hits::total 167948 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 366 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 366 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 366 # number of overall misses -system.cpu3.icache.overall_misses::total 366 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7343000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7343000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7343000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7343000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7343000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7343000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 168314 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 168314 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 168314 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 168314 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 168314 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 168314 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002175 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002175 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002175 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002175 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002175 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002175 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 20062.841530 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 20062.841530 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 20062.841530 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 20062.841530 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 67.672766 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.132173 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.132173 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 167480 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 167480 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 167480 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 167480 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 167480 # number of overall hits +system.cpu3.icache.overall_hits::total 167480 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses +system.cpu3.icache.overall_misses::total 367 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5162000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5162000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5162000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5162000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5162000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5162000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 167847 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 167847 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 167847 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 167847 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 167847 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 167847 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002187 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002187 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002187 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002187 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002187 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002187 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14065.395095 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14065.395095 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14065.395095 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14065.395095 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14065.395095 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14065.395095 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -789,100 +789,100 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 366 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 366 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 366 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6611000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 6611000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6611000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 6611000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6611000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 6611000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002175 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002175 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 18062.841530 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4428000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4428000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4428000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4428000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4428000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4428000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002187 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002187 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002187 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12065.395095 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12065.395095 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12065.395095 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 27.713697 # Cycle average of tags in use -system.cpu3.dcache.total_refs 24536 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 26.814972 # Cycle average of tags in use +system.cpu3.dcache.total_refs 30179 # Total number of references to valid blocks. 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WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 79 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 79 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 55228 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 55228 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 55228 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 55228 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004137 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.004137 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007630 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.007630 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.873418 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.873418 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005016 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005016 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005016 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005016 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16394.736842 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 16394.736842 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20768.867925 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20768.867925 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 5333.333333 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 5333.333333 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18068.592058 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18068.592058 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18068.592058 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18068.592058 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -891,225 +891,225 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 172 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 55 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 276 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 276 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 276 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3061000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3061000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1763500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1763500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 543500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 543500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4824500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4824500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4824500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4824500 # number of overall MSHR miss cycles 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overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004137 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004137 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.007630 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.007630 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.873418 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.873418 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005016 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.005016 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005016 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.005016 # mshr miss rate for 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-system.l2c.occ_blocks::cpu0.data 54.217473 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 6.219466 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 0.812784 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.917796 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.863537 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 46.262373 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 6.128563 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.889079 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 231.800504 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 54.209816 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 51.703511 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 6.143370 # Average occupied blocks per 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for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.180328 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.884615 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 41250 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.930233 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40018.604651 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40160.392857 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40138.611111 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40105.052632 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40105.670588 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40357.142857 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40464.285714 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40633.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40147.887324 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40099.800000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40187.187500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40112.287500 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40821.428571 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40678.571429 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40176.056338 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 41250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40766.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40633.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40057.692308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 41250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40766.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40633.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40057.692308 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |