diff options
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic')
3 files changed, 2988 insertions, 2833 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index f2f028686..6295c2feb 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,87 +1,87 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000106 # Number of seconds simulated -sim_ticks 105945500 # Number of ticks simulated -final_tick 105945500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000110 # Number of seconds simulated +sim_ticks 110344500 # Number of ticks simulated +final_tick 110344500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48441 # Simulator instruction rate (inst/s) -host_op_rate 48441 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4953275 # Simulator tick rate (ticks/s) -host_mem_usage 291288 # Number of bytes of host memory used -host_seconds 21.39 # Real time elapsed on the host -sim_insts 1036095 # Number of instructions simulated -sim_ops 1036095 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory +host_inst_rate 97195 # Simulator instruction rate (inst/s) +host_op_rate 97194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10306929 # Simulator tick rate (ticks/s) +host_mem_usage 249456 # Number of bytes of host memory used +host_seconds 10.71 # Real time elapsed on the host +sim_insts 1040548 # Number of instructions simulated +sim_ops 1040548 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 4992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 22848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 4992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 28544 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 357 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 78 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 660 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 215658051 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 101486141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47118566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 12081684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 4832673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7853094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1812253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7853094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 398695556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 215658051 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47118566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 4832673 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1812253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269421542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 215658051 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 101486141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47118566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 12081684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 4832673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7853094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1812253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7853094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 398695556 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 661 # Total number of read requests seen +system.physmem.num_reads::total 659 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 206480613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 97440289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 46400138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11600034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1740005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7540022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 3480010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7540022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 382221135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 206480613 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 46400138 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1740005 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 3480010 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 258100766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 206480613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 97440289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 46400138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11600034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1740005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7540022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 3480010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7540022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 382221135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 660 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 735 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 42240 # Total number of bytes read from memory +system.physmem.bytesRead 42176 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 74 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 75 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 69 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 58 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 13 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 65 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 98 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -100,14 +100,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 105917500 # Total gap between requests +system.physmem.totGap 110316500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 661 # Categorize read packet sizes +system.physmem.readPktSize::6 660 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -115,11 +115,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -179,336 +179,420 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 4080500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 20695500 # Sum of mem lat for all requests -system.physmem.totBusLat 3305000 # Total cycles spent in databus access -system.physmem.totBankLat 13310000 # Total cycles spent in bank access -system.physmem.avgQLat 6173.22 # Average queueing delay per request -system.physmem.avgBankLat 20136.16 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 282 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.796288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 318.984215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 9 7.03% 67.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 10 7.81% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 5 3.91% 78.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3 2.34% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 4 3.12% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 3 2.34% 86.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 4 3.12% 89.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.56% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 0.78% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation +system.physmem.totQLat 3607500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 17921250 # Sum of mem lat for all requests +system.physmem.totBusLat 3300000 # Total cycles spent in databus access +system.physmem.totBankLat 11013750 # Total cycles spent in bank access +system.physmem.avgQLat 5465.91 # Average queueing delay per request +system.physmem.avgBankLat 16687.50 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31309.38 # Average memory access latency -system.physmem.avgRdBW 398.70 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27153.41 # Average memory access latency +system.physmem.avgRdBW 382.22 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 398.70 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 382.22 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.11 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.19 # Average read queue length over time +system.physmem.busUtil 2.99 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.16 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 465 # Number of row buffer hits during reads +system.physmem.readRowHits 532 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.35 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 160238.28 # Average gap between requests -system.cpu0.branchPred.lookups 82343 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80122 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1236 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 79627 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 77569 # Number of BTB hits +system.physmem.avgGap 167146.21 # Average gap between requests +system.membus.throughput 382221135 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 529 # Transaction distribution +system.membus.trans_dist::ReadResp 528 # Transaction distribution +system.membus.trans_dist::UpgradeReq 284 # Transaction distribution +system.membus.trans_dist::UpgradeResp 75 # Transaction distribution +system.membus.trans_dist::ReadExReq 164 # Transaction distribution +system.membus.trans_dist::ReadExResp 131 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side 1711 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1711 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 42176 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 906000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer0.occupancy 6286926 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 5.7 # Layer utilization (%) +system.toL2Bus.throughput 1697085038 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2531 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2530 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 287 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 287 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 395 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 395 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 585 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 850 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 363 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 356 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 363 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5408 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 135488 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 51776 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 1621980 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2642498 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1437498 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1913498 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 1155972 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1929492 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 1158481 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 1.0 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1936496 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 1.8 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1165479 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) +system.cpu0.branchPred.lookups 82851 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80650 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 80180 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 78131 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.415450 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 525 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 97.444500 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 211892 # number of cpu cycles simulated +system.cpu0.numCycles 220690 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17012 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 488761 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82343 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 78094 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 160351 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3870 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13040 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17257 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 491686 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 82851 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 78643 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 161395 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13763 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1377 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5901 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 194270 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.515885 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.216000 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1562 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 494 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 196421 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.503225 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.215279 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33919 17.46% 17.46% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 79392 40.87% 58.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 605 0.31% 58.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 996 0.51% 59.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 467 0.24% 59.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 75436 38.83% 98.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 571 0.29% 98.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 375 0.19% 98.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2509 1.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35026 17.83% 17.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 79943 40.70% 58.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 973 0.50% 59.32% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 76047 38.72% 98.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2457 1.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 194270 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.388608 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.306652 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17669 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14482 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 159353 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 281 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2485 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 485695 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2485 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18316 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 722 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13165 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 159020 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 562 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 482913 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 156 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 330456 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 963041 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 963041 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 316991 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13465 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 886 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 906 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3563 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 154365 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 77987 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 75234 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 75049 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 403722 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 919 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 400870 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11014 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 10026 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 360 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 194270 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.063468 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.094328 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 196421 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.375418 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.227949 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17908 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15370 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 160419 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 285 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2439 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 488842 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2439 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18575 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 759 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14008 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 160070 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 570 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 485981 # Number of instructions processed by rename +system.cpu0.rename.LSQFullEvents 199 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 332328 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 969157 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 969157 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 319407 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3600 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 155469 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 78571 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 75822 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 75638 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 406410 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 403726 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 135 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10718 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9636 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 196421 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.055412 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097532 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33101 17.04% 17.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4910 2.53% 19.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 77039 39.66% 59.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 76515 39.39% 98.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1655 0.85% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 696 0.36% 99.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 259 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 77 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34004 17.31% 17.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4909 2.50% 19.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 77804 39.61% 59.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 77117 39.26% 98.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1569 0.80% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 649 0.33% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 194270 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 196421 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 50 22.22% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 62 27.56% 49.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 113 50.22% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 57 25.68% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 53 23.87% 49.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 50.45% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 169604 42.31% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 153865 38.38% 80.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 77401 19.31% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 170720 42.29% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 155014 38.40% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 77992 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 400870 # Type of FU issued -system.cpu0.iq.rate 1.891860 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 225 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 996359 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 415710 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 399019 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 403726 # Type of FU issued +system.cpu0.iq.rate 1.829381 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 222 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000550 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1004230 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 418093 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 401910 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 401095 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 403948 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 74761 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 75361 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2280 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1438 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2176 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2485 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 453 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 480419 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 309 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 154365 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 77987 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 807 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2439 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 333 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 32 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 483693 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 155469 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 78571 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 346 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1112 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1458 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 399786 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 153534 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1084 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 342 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1448 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 402662 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 154684 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1064 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 75778 # number of nop insts executed -system.cpu0.iew.exec_refs 230828 # number of memory reference insts executed -system.cpu0.iew.exec_branches 79388 # Number of branches executed -system.cpu0.iew.exec_stores 77294 # Number of stores executed -system.cpu0.iew.exec_rate 1.886744 # Inst execution rate -system.cpu0.iew.wb_sent 399367 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 399019 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 236486 # num instructions producing a value -system.cpu0.iew.wb_consumers 239045 # num instructions consuming a value +system.cpu0.iew.exec_nop 76372 # number of nop insts executed +system.cpu0.iew.exec_refs 232577 # number of memory reference insts executed +system.cpu0.iew.exec_branches 79993 # Number of branches executed +system.cpu0.iew.exec_stores 77893 # Number of stores executed +system.cpu0.iew.exec_rate 1.824559 # Inst execution rate +system.cpu0.iew.wb_sent 402239 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 401910 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 238133 # num instructions producing a value +system.cpu0.iew.wb_consumers 240585 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.883124 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989295 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.821152 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989808 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12546 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12210 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1236 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 191785 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.439388 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136415 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 193982 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430442 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136125 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33586 17.51% 17.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 79020 41.20% 58.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2366 1.23% 59.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 689 0.36% 60.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 531 0.28% 60.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 74531 38.86% 99.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 504 0.26% 99.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 248 0.13% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 310 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34427 17.75% 17.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 79760 41.12% 58.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2402 1.24% 60.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 529 0.27% 60.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 75180 38.76% 99.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 442 0.23% 99.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 241 0.12% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 308 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 191785 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 467838 # Number of instructions committed -system.cpu0.commit.committedOps 467838 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 193982 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 471462 # Number of instructions committed +system.cpu0.commit.committedOps 471462 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 228634 # Number of memory references committed -system.cpu0.commit.loads 152085 # Number of loads committed +system.cpu0.commit.refs 230446 # Number of memory references committed +system.cpu0.commit.loads 153293 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 78436 # Number of branches committed +system.cpu0.commit.branches 79040 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 315322 # Number of committed integer instructions. +system.cpu0.commit.int_insts 317738 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 310 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 308 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 670698 # The number of ROB reads -system.cpu0.rob.rob_writes 963274 # The number of ROB writes -system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 17622 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 392586 # Number of Instructions Simulated -system.cpu0.committedOps 392586 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 392586 # Number of Instructions Simulated -system.cpu0.cpi 0.539734 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.539734 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.852765 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.852765 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 715161 # number of integer regfile reads -system.cpu0.int_regfile_writes 322387 # number of integer regfile writes +system.cpu0.rob.rob_reads 676185 # The number of ROB reads +system.cpu0.rob.rob_writes 969800 # The number of ROB writes +system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 24269 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 395606 # Number of Instructions Simulated +system.cpu0.committedOps 395606 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 395606 # Number of Instructions Simulated +system.cpu0.cpi 0.557853 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.557853 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.792587 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.792587 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 720352 # number of integer regfile reads +system.cpu0.int_regfile_writes 324661 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 232651 # number of misc regfile reads +system.cpu0.misc_regfile_reads 234400 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 298 # number of replacements -system.cpu0.icache.tagsinuse 245.594499 # Cycle average of tags in use -system.cpu0.icache.total_refs 5155 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 589 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.752122 # Average number of references to valid blocks. +system.cpu0.icache.replacements 297 # number of replacements +system.cpu0.icache.tagsinuse 241.066229 # Cycle average of tags in use +system.cpu0.icache.total_refs 5081 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.655877 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 245.594499 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.479677 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.479677 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5155 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5155 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5155 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5155 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5155 # number of overall hits -system.cpu0.icache.overall_hits::total 5155 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 746 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 746 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 746 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 746 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 746 # number of overall misses -system.cpu0.icache.overall_misses::total 746 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26567000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 26567000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 26567000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 26567000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 26567000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 26567000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5901 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5901 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5901 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5901 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5901 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5901 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.126419 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.126419 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126419 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.126419 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126419 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.126419 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35612.600536 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 35612.600536 # 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number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 34643000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129220 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.129220 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129220 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.129220 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129220 # 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mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45925.173469 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 45925.173469 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 45925.173469 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 143.449906 # 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miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007068 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006566 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006566 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006566 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006566 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25167.368421 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25167.368421 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45370.395221 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45370.395221 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28547.619048 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 28547.619048 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35952.890088 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35952.890088 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006082 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006082 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006082 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006082 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31405.172414 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31405.172414 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65129.324771 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 65129.324771 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19833.333333 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19833.333333 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50731.842271 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50731.842271 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 499 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.142857 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.761905 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 286 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 659 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 659 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 659 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 659 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 220 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 590 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 590 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 590 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 590 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 186 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5407500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5407500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5740000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5740000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 557500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 557500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11147500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11147500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11147500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11147500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002402 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002402 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002235 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002235 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6035502 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6035502 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7873000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7873000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13908502 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13908502 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13908502 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13908502 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002347 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002347 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002269 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002269 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002320 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002320 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28611.111111 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28611.111111 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33567.251462 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33567.251462 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26547.619048 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26547.619048 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002309 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002309 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32448.935484 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32448.935484 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44988.571429 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44988.571429 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17833.333333 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17833.333333 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 56473 # Number of BP lookups -system.cpu1.branchPred.condPredicted 53777 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1278 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 50438 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 49675 # Number of BTB hits +system.cpu1.branchPred.lookups 58259 # Number of BP lookups +system.cpu1.branchPred.condPredicted 55591 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 52252 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 51480 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.487252 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 680 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.522545 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 650 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 175078 # number of cpu cycles simulated +system.cpu1.numCycles 176870 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 25485 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 320653 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 56473 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 50355 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 109933 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 25650 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 24483 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 332703 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 58259 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 52130 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 112942 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3669 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 23224 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6381 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 795 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 16660 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 170597 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.879593 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.199930 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 755 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 15523 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 171052 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.945040 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.217476 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 60664 35.56% 35.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 55109 32.30% 67.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 4624 2.71% 70.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3194 1.87% 72.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 685 0.40% 72.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 41191 24.15% 96.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1119 0.66% 97.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 783 0.46% 98.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3228 1.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 58110 33.97% 33.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 56330 32.93% 66.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 4061 2.37% 69.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3192 1.87% 71.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 642 0.38% 71.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 43436 25.39% 96.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1285 0.75% 97.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 751 0.44% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 170597 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.322559 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.831487 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 29160 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 23609 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 105420 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3678 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2349 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 317245 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2349 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 29851 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 11179 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11654 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 102051 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 7132 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 315250 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 222317 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 613423 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 613423 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 209500 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12817 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 9565 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 91347 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 44397 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 43115 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 39365 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 263703 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 4783 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 264442 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10738 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10286 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 531 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 170597 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.550098 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.309842 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 171052 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.329389 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.881060 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27575 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 21737 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 108940 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3156 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2318 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 329200 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2318 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28271 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 9057 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11940 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 106039 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 6101 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 326983 # Number of instructions processed by rename +system.cpu1.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 231035 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 638817 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 638817 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 218174 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12861 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1086 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1205 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8759 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 95375 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 46677 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 44840 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 41648 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 274055 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 4247 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 274319 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 86 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10569 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10360 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 171052 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.603717 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.300528 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 57935 33.96% 33.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 18114 10.62% 44.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 44440 26.05% 70.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 45139 26.46% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3372 1.98% 99.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1210 0.71% 99.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 275 0.16% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 55274 32.31% 32.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16462 9.62% 41.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 46955 27.45% 69.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 47561 27.80% 97.19% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3274 1.91% 99.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1158 0.68% 99.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 170597 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 171052 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 17 5.80% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 66 22.53% 28.33% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17 6.05% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 54 19.22% 25.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 74.73% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 126483 47.83% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 94216 35.63% 83.46% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 43743 16.54% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 130533 47.58% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 97787 35.65% 83.23% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 45999 16.77% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 264442 # Type of FU issued -system.cpu1.iq.rate 1.510424 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 293 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001108 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 699908 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 279269 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 262662 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 274319 # Type of FU issued +system.cpu1.iq.rate 1.550964 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 281 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001024 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 720057 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 288914 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 272470 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 264735 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 274600 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 39130 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 41423 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2377 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2326 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2349 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1341 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 312497 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 91347 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 44397 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2318 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 743 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 324068 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 95375 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 46677 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1041 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 950 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1409 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 263311 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 90404 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1131 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 924 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1387 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 273134 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 94466 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1185 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 44011 # number of nop insts executed -system.cpu1.iew.exec_refs 134069 # number of memory reference insts executed -system.cpu1.iew.exec_branches 53318 # Number of branches executed -system.cpu1.iew.exec_stores 43665 # Number of stores executed -system.cpu1.iew.exec_rate 1.503964 # Inst execution rate -system.cpu1.iew.wb_sent 262943 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 262662 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 150856 # num instructions producing a value -system.cpu1.iew.wb_consumers 155566 # num instructions consuming a value +system.cpu1.iew.exec_nop 45766 # number of nop insts executed +system.cpu1.iew.exec_refs 140389 # number of memory reference insts executed +system.cpu1.iew.exec_branches 55097 # Number of branches executed +system.cpu1.iew.exec_stores 45923 # Number of stores executed +system.cpu1.iew.exec_rate 1.544264 # Inst execution rate +system.cpu1.iew.wb_sent 272765 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 272470 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 157153 # num instructions producing a value +system.cpu1.iew.wb_consumers 161823 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.500257 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.969723 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.540510 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.971141 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12295 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 4252 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1278 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 161867 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.854590 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.083667 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12117 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 3751 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 161408 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.932674 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.096378 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 55765 34.45% 34.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 51311 31.70% 66.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6076 3.75% 69.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5204 3.21% 73.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1553 0.96% 74.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 39486 24.39% 98.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 647 0.40% 98.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1002 0.62% 99.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 51564 31.95% 31.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 53244 32.99% 64.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6086 3.77% 68.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 4696 2.91% 71.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 41954 25.99% 98.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 476 0.29% 98.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 816 0.51% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 161867 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 300197 # Number of instructions committed -system.cpu1.commit.committedOps 300197 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 161408 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 311949 # Number of instructions committed +system.cpu1.commit.committedOps 311949 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 131930 # Number of memory references committed -system.cpu1.commit.loads 88970 # Number of loads committed -system.cpu1.commit.membars 3544 # Number of memory barriers committed -system.cpu1.commit.branches 52469 # Number of branches committed +system.cpu1.commit.refs 138308 # Number of memory references committed +system.cpu1.commit.loads 93049 # Number of loads committed +system.cpu1.commit.membars 3038 # Number of memory barriers committed +system.cpu1.commit.branches 54264 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 206526 # Number of committed integer instructions. +system.cpu1.commit.int_insts 214693 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 823 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 816 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 472949 # The number of ROB reads -system.cpu1.rob.rob_writes 627337 # The number of ROB writes -system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 4481 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 36812 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 253388 # Number of Instructions Simulated -system.cpu1.committedOps 253388 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 253388 # Number of Instructions Simulated -system.cpu1.cpi 0.690948 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.690948 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.447286 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.447286 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 460976 # number of integer regfile reads -system.cpu1.int_regfile_writes 214498 # number of integer regfile writes +system.cpu1.rob.rob_reads 484071 # The number of ROB reads +system.cpu1.rob.rob_writes 650455 # The number of ROB writes +system.cpu1.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 5818 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 43818 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 263856 # Number of Instructions Simulated +system.cpu1.committedOps 263856 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 263856 # Number of Instructions Simulated +system.cpu1.cpi 0.670328 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.670328 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.491808 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.491808 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 479823 # number of integer regfile reads +system.cpu1.int_regfile_writes 223101 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 135647 # number of misc regfile reads +system.cpu1.misc_regfile_reads 141972 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 85.226466 # Cycle average of tags in use -system.cpu1.icache.total_refs 16176 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 82.334562 # Cycle average of tags in use +system.cpu1.icache.total_refs 15036 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 38.061176 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 35.378824 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 85.226466 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.166458 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.166458 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 16176 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16176 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16176 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16176 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16176 # number of overall hits -system.cpu1.icache.overall_hits::total 16176 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 484 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 484 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 484 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 484 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 484 # number of overall misses -system.cpu1.icache.overall_misses::total 484 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10452000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10452000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10452000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10452000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10452000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10452000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16660 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16660 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16660 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16660 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16660 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16660 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029052 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029052 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029052 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029052 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029052 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029052 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21595.041322 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21595.041322 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21595.041322 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21595.041322 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 82.334562 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.160810 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.160810 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 15036 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15036 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15036 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15036 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15036 # number of overall hits +system.cpu1.icache.overall_hits::total 15036 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 487 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 487 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 487 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 487 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 487 # number of overall misses +system.cpu1.icache.overall_misses::total 487 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 12109000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 12109000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 12109000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 12109000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 12109000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 12109000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 15523 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 15523 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 15523 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 15523 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 15523 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 15523 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031373 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.031373 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031373 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.031373 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031373 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.031373 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24864.476386 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24864.476386 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24864.476386 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24864.476386 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 84 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 59 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 59 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 59 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 59 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 62 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 62 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 62 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 62 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8244000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8244000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8244000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8244000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8244000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8244000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.025510 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.025510 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.025510 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.025510 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.025510 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.025510 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19397.647059 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 19397.647059 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 19397.647059 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9721502 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 9721502 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9721502 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 9721502 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9721502 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 9721502 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027379 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027379 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027379 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22874.122353 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 22874.122353 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 22874.122353 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.077196 # Cycle average of tags in use -system.cpu1.dcache.total_refs 49103 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1693.206897 # Average number of references to valid blocks. +system.cpu1.dcache.tagsinuse 26.168894 # Cycle average of tags in use +system.cpu1.dcache.total_refs 51272 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 1831.142857 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.077196 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.052885 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.052885 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 50842 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 50842 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 42756 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 42756 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 93598 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 93598 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 93598 # number of overall hits -system.cpu1.dcache.overall_hits::total 93598 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 415 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 415 # number of ReadReq misses +system.cpu1.dcache.occ_blocks::cpu1.data 26.168894 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.051111 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.051111 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 52686 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 52686 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 45050 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 45050 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 97736 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 97736 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 97736 # number of overall hits +system.cpu1.dcache.overall_hits::total 97736 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 340 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 340 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 142 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 142 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 557 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 557 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 557 # number of overall misses -system.cpu1.dcache.overall_misses::total 557 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8012000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8012000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3190500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3190500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 514000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 514000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 11202500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 11202500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 11202500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 11202500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 51257 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 51257 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 42898 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 42898 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 94155 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 94155 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 94155 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 94155 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008096 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.008096 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003310 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003310 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.806452 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005916 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005916 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005916 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005916 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19306.024096 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19306.024096 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22468.309859 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22468.309859 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 10280 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 10280 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20112.208259 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20112.208259 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20112.208259 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20112.208259 # average overall miss latency +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 482 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 482 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 482 # number of overall misses +system.cpu1.dcache.overall_misses::total 482 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5254500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5254500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3040000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3040000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 532000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 532000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8294500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8294500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8294500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8294500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 53026 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 53026 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 45192 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 45192 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 98218 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 98218 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 98218 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 98218 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.006412 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.006412 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003142 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003142 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.835821 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004907 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004907 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004907 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004907 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15454.411765 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15454.411765 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21408.450704 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21408.450704 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9500 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9500 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17208.506224 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17208.506224 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1102,473 +1185,473 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 264 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 264 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 185 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 185 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 298 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 298 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 298 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 298 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 151 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses +system.cpu1.dcache.demand_mshr_hits::cpu1.data 219 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 219 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1741000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1741000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1514500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1514500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 414000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 414000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3255500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3255500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3255500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3255500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002946 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002946 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002518 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002518 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002751 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002751 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11529.801325 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11529.801325 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14023.148148 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14023.148148 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 8280 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 8280 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1346027 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1346027 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1452501 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1452501 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 420000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 420000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2798528 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2798528 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2798528 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2798528 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002923 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002923 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002390 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002390 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.835821 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002678 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002678 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 8684.045161 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 8684.045161 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13449.083333 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13449.083333 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7500 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7500 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 48435 # Number of BP lookups -system.cpu2.branchPred.condPredicted 45756 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1281 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 42366 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 41626 # Number of BTB hits +system.cpu2.branchPred.lookups 40256 # Number of BP lookups +system.cpu2.branchPred.condPredicted 37554 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1244 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 34216 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 33404 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.253316 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 643 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 97.626841 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 656 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 174747 # number of cpu cycles simulated +system.cpu2.numCycles 176505 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 30691 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 266889 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 48435 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 42269 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 96584 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3759 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 36275 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6390 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 712 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 22267 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 173057 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.542203 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.085998 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 35945 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 212693 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 40256 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 34060 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 82824 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3666 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 45362 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 778 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 27473 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 251 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 174585 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.218278 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 1.916616 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 76473 44.19% 44.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 49798 28.78% 72.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 7404 4.28% 77.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3211 1.86% 79.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 674 0.39% 79.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 30262 17.49% 96.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1242 0.72% 97.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 752 0.43% 98.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3241 1.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 91761 52.56% 52.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 44191 25.31% 77.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 10007 5.73% 83.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3161 1.81% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 734 0.42% 85.83% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 19642 11.25% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1038 0.59% 97.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 777 0.45% 98.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3274 1.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 173057 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.277172 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.527288 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 36897 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 31644 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 89441 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 6284 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2401 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 263319 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2401 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 37621 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 18625 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12236 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 83428 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 12356 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 261093 # Number of instructions processed by rename +system.cpu2.fetch.rateDist::total 174585 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.228073 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.205025 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 44684 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 38236 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 73287 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 8707 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2345 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 209159 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2345 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 45347 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 25711 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11752 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 64880 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 17224 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 207132 # Number of instructions processed by rename system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 181374 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 493566 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 493566 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 168473 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12901 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1100 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 15080 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 72313 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 33498 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 35025 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 28444 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 214608 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 7657 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 217768 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 10976 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11107 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 637 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 173057 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.258360 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.300957 # Number of insts issued each cycle +system.cpu2.rename.LSQFullEvents 18 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 141115 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 375802 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 375802 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 128666 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12449 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1089 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1217 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 19740 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 53610 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 22854 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 26965 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 17848 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 166370 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 10183 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 172186 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 129 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 10670 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10572 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 174585 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.986259 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.235789 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 74099 42.82% 42.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 26214 15.15% 57.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 33561 19.39% 77.36% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 34357 19.85% 97.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3304 1.91% 99.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1156 0.67% 99.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 89355 51.18% 51.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 33684 19.29% 70.48% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 23026 13.19% 83.66% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 23727 13.59% 97.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3246 1.86% 99.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1164 0.67% 99.78% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 273 0.16% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 173057 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 174585 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 17 5.65% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 74 24.58% 30.23% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 12 4.35% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 54 19.57% 23.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 76.09% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 107188 49.22% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 77805 35.73% 84.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 32775 15.05% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 88373 51.32% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 61586 35.77% 87.09% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 22227 12.91% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 217768 # Type of FU issued -system.cpu2.iq.rate 1.246190 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 609024 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 233287 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 215963 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 172186 # Type of FU issued +system.cpu2.iq.rate 0.975530 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 276 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001603 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 519362 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 187269 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 170462 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 218069 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 172462 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 28178 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 17592 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2489 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2439 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1471 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedStores 1401 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2401 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 915 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 258202 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 343 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 72313 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 33498 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1067 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 66 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2345 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 684 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 204373 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 344 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 53610 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 22854 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 926 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1391 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 216605 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 71227 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1163 # Number of squashed instructions skipped in execute +system.cpu2.iew.predictedTakenIncorrect 451 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 900 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1351 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 171090 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 52536 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1096 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 35937 # number of nop insts executed -system.cpu2.iew.exec_refs 103922 # number of memory reference insts executed -system.cpu2.iew.exec_branches 45106 # Number of branches executed -system.cpu2.iew.exec_stores 32695 # Number of stores executed -system.cpu2.iew.exec_rate 1.239535 # Inst execution rate -system.cpu2.iew.wb_sent 216253 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 215963 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 120625 # num instructions producing a value -system.cpu2.iew.wb_consumers 125288 # num instructions consuming a value +system.cpu2.iew.exec_nop 27820 # number of nop insts executed +system.cpu2.iew.exec_refs 74679 # number of memory reference insts executed +system.cpu2.iew.exec_branches 36982 # Number of branches executed +system.cpu2.iew.exec_stores 22143 # Number of stores executed +system.cpu2.iew.exec_rate 0.969321 # Inst execution rate +system.cpu2.iew.wb_sent 170734 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 170462 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 91387 # num instructions producing a value +system.cpu2.iew.wb_consumers 96059 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.235861 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.962782 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.965763 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.951363 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12625 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7020 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1281 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 164266 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.494880 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.964665 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12267 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 9515 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1244 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 164914 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.164777 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.788510 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 74448 45.32% 45.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 43200 26.30% 71.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6076 3.70% 75.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 7927 4.83% 80.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1577 0.96% 81.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 28745 17.50% 98.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 476 0.29% 98.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1000 0.61% 99.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 817 0.50% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 91274 55.35% 55.35% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 35097 21.28% 76.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6075 3.68% 80.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 10441 6.33% 86.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1560 0.95% 87.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 18154 11.01% 98.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 495 0.30% 98.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 812 0.49% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 164266 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 245558 # Number of instructions committed -system.cpu2.commit.committedOps 245558 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 164914 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 192088 # Number of instructions committed +system.cpu2.commit.committedOps 192088 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 101851 # Number of memory references committed -system.cpu2.commit.loads 69824 # Number of loads committed -system.cpu2.commit.membars 6301 # Number of memory barriers committed -system.cpu2.commit.branches 44289 # Number of branches committed +system.cpu2.commit.refs 72624 # Number of memory references committed +system.cpu2.commit.loads 51171 # Number of loads committed +system.cpu2.commit.membars 8798 # Number of memory barriers committed +system.cpu2.commit.branches 36206 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 168258 # Number of committed integer instructions. +system.cpu2.commit.int_insts 130952 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 421045 # The number of ROB reads -system.cpu2.rob.rob_writes 518771 # The number of ROB writes -system.cpu2.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1690 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 37143 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 204183 # Number of Instructions Simulated -system.cpu2.committedOps 204183 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 204183 # Number of Instructions Simulated -system.cpu2.cpi 0.855835 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.855835 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.168449 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.168449 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 370277 # number of integer regfile reads -system.cpu2.int_regfile_writes 173276 # number of integer regfile writes +system.cpu2.rob.rob_reads 367870 # The number of ROB reads +system.cpu2.rob.rob_writes 411061 # The number of ROB writes +system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1920 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 44183 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 156297 # Number of Instructions Simulated +system.cpu2.committedOps 156297 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 156297 # Number of Instructions Simulated +system.cpu2.cpi 1.129292 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.129292 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.885510 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.885510 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 282509 # number of integer regfile reads +system.cpu2.int_regfile_writes 133289 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 105484 # number of misc regfile reads +system.cpu2.misc_regfile_reads 76201 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.icache.replacements 319 # number of replacements -system.cpu2.icache.tagsinuse 83.493778 # Cycle average of tags in use -system.cpu2.icache.total_refs 21789 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 50.672093 # Average number of references to valid blocks. +system.cpu2.icache.replacements 318 # number of replacements +system.cpu2.icache.tagsinuse 76.657940 # Cycle average of tags in use +system.cpu2.icache.total_refs 26999 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 428 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 63.081776 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 83.493778 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.163074 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 21789 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 21789 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 21789 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 21789 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 21789 # number of overall hits -system.cpu2.icache.overall_hits::total 21789 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 478 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 478 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 478 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 478 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 478 # number of overall misses -system.cpu2.icache.overall_misses::total 478 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6833500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6833500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6833500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6833500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6833500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6833500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 22267 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 22267 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 22267 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 22267 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 22267 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 22267 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.021467 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.021467 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.021467 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.021467 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.021467 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.021467 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14296.025105 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14296.025105 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14296.025105 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14296.025105 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14296.025105 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14296.025105 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.occ_blocks::cpu2.inst 76.657940 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.149723 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.149723 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 26999 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 26999 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 26999 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 26999 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 26999 # number of overall hits +system.cpu2.icache.overall_hits::total 26999 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 474 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 474 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 474 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 474 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 474 # 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miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 11711.356467 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 11711.356467 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20705.223881 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20705.223881 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9870.370370 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 9870.370370 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14383.592018 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14383.592018 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14383.592018 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14383.592018 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1577,365 +1660,365 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 246 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 156 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 279 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 279 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 189 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 189 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 189 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 189 # number of overall MSHR hits system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1373500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1373500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1349000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1349000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2722500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2722500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2722500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2722500 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003741 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003741 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003161 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003161 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794521 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794521 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003494 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003494 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8531.055901 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8531.055901 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13356.435644 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13356.435644 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7862.068966 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7862.068966 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1142519 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1142519 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1333500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1333500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 425000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 425000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2476019 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2476019 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2476019 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2476019 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004609 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004609 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.004724 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.004724 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.760563 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.760563 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004653 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004653 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7096.391304 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7096.391304 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13202.970297 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13202.970297 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7870.370370 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7870.370370 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 45379 # Number of BP lookups -system.cpu3.branchPred.condPredicted 42609 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1294 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 39317 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 38445 # Number of BTB hits +system.cpu3.branchPred.lookups 52069 # Number of BP lookups +system.cpu3.branchPred.condPredicted 49356 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1283 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 46005 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 45233 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.782130 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 651 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 98.321922 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 642 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 174437 # number of cpu cycles simulated +system.cpu3.numCycles 176161 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 32466 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 246453 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 45379 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 39096 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 91198 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3791 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 39692 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 28821 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 290359 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 52069 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45875 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 102938 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3745 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 32453 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6399 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24152 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 172879 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.425581 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.034525 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 7327 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 20536 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 174715 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.661901 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.131946 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 81681 47.25% 47.25% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 47531 27.49% 74.74% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8280 4.79% 79.53% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3183 1.84% 81.37% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 751 0.43% 81.81% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 26265 15.19% 97.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1130 0.65% 97.65% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 760 0.44% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3298 1.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 71777 41.08% 41.08% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 52540 30.07% 71.15% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 6531 3.74% 74.89% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3210 1.84% 76.73% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 677 0.39% 77.12% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 34730 19.88% 97.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1243 0.71% 97.71% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 745 0.43% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3262 1.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 172879 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.260145 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.412848 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 39667 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 34044 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 83244 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7105 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2420 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 242894 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2420 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 40390 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 21128 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12127 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 76402 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 14013 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 240516 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 166179 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 449032 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 449032 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 153365 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 12814 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1105 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1221 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 16705 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 65194 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 29511 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 31885 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 24466 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 196370 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8514 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 200412 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10978 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11006 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 643 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 172879 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.159262 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.284832 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 174715 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.295576 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.648259 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 34404 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 28518 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 96588 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5492 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2386 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 286754 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2386 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 35116 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 15951 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 11812 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 91334 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 10789 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 284513 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 198512 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 543834 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 543834 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 185460 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 13052 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1098 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1218 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 13448 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 80352 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 37945 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 38583 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 32886 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 235223 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6760 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 237671 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10910 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10900 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 576 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 174715 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.360335 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.308190 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 79312 45.88% 45.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 28822 16.67% 62.55% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 29551 17.09% 79.64% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 30339 17.55% 97.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3334 1.93% 99.12% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1154 0.67% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 69245 39.63% 39.63% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 23718 13.58% 53.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 38151 21.84% 75.04% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 38808 22.21% 97.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3275 1.87% 99.13% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1152 0.66% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 254 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 172879 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 174715 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 12 4.07% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 73 24.75% 28.81% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 17 5.94% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 59 20.63% 26.57% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 73.43% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 100076 49.94% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 71520 35.69% 85.62% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 28816 14.38% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 115348 48.53% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 85085 35.80% 84.33% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 37238 15.67% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 200412 # Type of FU issued -system.cpu3.iq.rate 1.148908 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 295 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001472 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 574125 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 215907 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 198595 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 237671 # Type of FU issued +system.cpu3.iq.rate 1.349169 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 286 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001203 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 650461 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 252939 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 235820 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 200707 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 237957 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 24188 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 32638 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2497 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2448 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2420 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 942 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 237691 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 65194 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 29511 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1069 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2386 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 609 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 281506 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 80352 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 37945 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 475 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1407 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 199248 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 64095 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1164 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 925 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 236476 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 79331 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 32807 # number of nop insts executed -system.cpu3.iew.exec_refs 92831 # number of memory reference insts executed -system.cpu3.iew.exec_branches 41971 # Number of branches executed -system.cpu3.iew.exec_stores 28736 # Number of stores executed -system.cpu3.iew.exec_rate 1.142235 # Inst execution rate -system.cpu3.iew.wb_sent 198881 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 198595 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 109565 # num instructions producing a value -system.cpu3.iew.wb_consumers 114222 # num instructions consuming a value +system.cpu3.iew.exec_nop 39523 # number of nop insts executed +system.cpu3.iew.exec_refs 116486 # number of memory reference insts executed +system.cpu3.iew.exec_branches 48746 # Number of branches executed +system.cpu3.iew.exec_stores 37155 # Number of stores executed +system.cpu3.iew.exec_rate 1.342386 # Inst execution rate +system.cpu3.iew.wb_sent 236114 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 235820 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 133214 # num instructions producing a value +system.cpu3.iew.wb_consumers 137877 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.138491 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.959229 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.338662 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.966180 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 12643 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7871 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1294 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 164060 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.371620 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.908371 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 12531 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6184 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1283 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 165002 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.630011 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.014402 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 80528 49.08% 49.08% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 40048 24.41% 73.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6110 3.72% 77.22% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8758 5.34% 82.56% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1552 0.95% 83.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 24728 15.07% 98.58% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 520 0.32% 98.89% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1010 0.62% 99.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 806 0.49% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 67849 41.12% 41.12% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 46915 28.43% 69.55% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6084 3.69% 73.24% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7112 4.31% 77.55% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1576 0.96% 78.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 33196 20.12% 98.62% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 454 0.28% 98.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1000 0.61% 99.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 816 0.49% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 164060 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 225028 # Number of instructions committed -system.cpu3.commit.committedOps 225028 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 165002 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 268955 # Number of instructions committed +system.cpu3.commit.committedOps 268955 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 90734 # Number of memory references committed -system.cpu3.commit.loads 62697 # Number of loads committed -system.cpu3.commit.membars 7153 # Number of memory barriers committed -system.cpu3.commit.branches 41151 # Number of branches committed +system.cpu3.commit.refs 114381 # Number of memory references committed +system.cpu3.commit.loads 77904 # Number of loads committed +system.cpu3.commit.membars 5468 # Number of memory barriers committed +system.cpu3.commit.branches 47910 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 154003 # Number of committed integer instructions. +system.cpu3.commit.int_insts 184410 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 806 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 816 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 400338 # The number of ROB reads -system.cpu3.rob.rob_writes 477767 # The number of ROB writes -system.cpu3.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1558 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 37453 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 185938 # Number of Instructions Simulated -system.cpu3.committedOps 185938 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 185938 # Number of Instructions Simulated -system.cpu3.cpi 0.938146 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.938146 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.065932 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.065932 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 337021 # number of integer regfile reads -system.cpu3.int_regfile_writes 158120 # number of integer regfile writes +system.cpu3.rob.rob_reads 445085 # The number of ROB reads +system.cpu3.rob.rob_writes 565364 # The number of ROB writes +system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1446 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 44527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 224789 # Number of Instructions Simulated +system.cpu3.committedOps 224789 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 224789 # Number of Instructions Simulated +system.cpu3.cpi 0.783673 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.783673 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.276043 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.276043 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 408025 # number of integer regfile reads +system.cpu3.int_regfile_writes 190344 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 94371 # number of misc regfile reads +system.cpu3.misc_regfile_reads 118055 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.icache.replacements 318 # number of replacements -system.cpu3.icache.tagsinuse 80.241223 # Cycle average of tags in use -system.cpu3.icache.total_refs 23677 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 429 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 55.191142 # Average number of references to valid blocks. +system.cpu3.icache.replacements 319 # number of replacements +system.cpu3.icache.tagsinuse 80.505037 # Cycle average of tags in use +system.cpu3.icache.total_refs 20059 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 46.648837 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 80.241223 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.156721 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.156721 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 23677 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 23677 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 23677 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 23677 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 23677 # number of overall hits -system.cpu3.icache.overall_hits::total 23677 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses -system.cpu3.icache.overall_misses::total 475 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6195500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6195500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6195500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6195500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6195500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6195500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 24152 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 24152 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 24152 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 24152 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 24152 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 24152 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.019667 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.019667 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.019667 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.019667 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.019667 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.019667 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13043.157895 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13043.157895 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13043.157895 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13043.157895 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13043.157895 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13043.157895 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 80.505037 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.157236 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.157236 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 20059 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 20059 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 20059 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 20059 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 20059 # number of overall hits +system.cpu3.icache.overall_hits::total 20059 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 477 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 477 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 477 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 477 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 477 # number of overall misses +system.cpu3.icache.overall_misses::total 477 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6428500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6428500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6428500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6428500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6428500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6428500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 20536 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 20536 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 20536 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 20536 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 20536 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 20536 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023228 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.023228 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023228 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.023228 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023228 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023228 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13476.939203 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13476.939203 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13476.939203 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13476.939203 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13476.939203 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13476.939203 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1944,106 +2027,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4977500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4977500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4977500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4977500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4977500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4977500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017763 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017763 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017763 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.017763 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017763 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.017763 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11602.564103 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11602.564103 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11602.564103 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 11602.564103 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11602.564103 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 11602.564103 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 47 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 47 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 47 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 47 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 47 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 47 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5181004 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5181004 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5181004 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5181004 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5181004 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5181004 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020939 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.020939 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.020939 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12048.846512 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12048.846512 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12048.846512 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 24.570062 # Cycle average of tags in use -system.cpu3.dcache.total_refs 34044 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 24.780818 # Cycle average of tags in use +system.cpu3.dcache.total_refs 42491 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1215.857143 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1517.535714 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 24.570062 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.047988 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.047988 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 39468 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 39468 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 27827 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 27827 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 67295 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 67295 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 67295 # number of overall hits -system.cpu3.dcache.overall_hits::total 67295 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 421 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 421 # number of ReadReq misses +system.cpu3.dcache.occ_blocks::cpu3.data 24.780818 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.048400 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.048400 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 46335 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 46335 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 36269 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 36269 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 82604 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 82604 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 82604 # number of overall hits +system.cpu3.dcache.overall_hits::total 82604 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 340 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 340 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # 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number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 8188000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 8188000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 8188000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 39889 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 39889 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 27965 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 27965 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 67854 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 67854 # 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number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 478 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 478 # number of overall misses +system.cpu3.dcache.overall_misses::total 478 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4247000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 4247000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2709000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2709000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 548500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 548500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 6956000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 6956000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 6956000 # 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number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007284 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.007284 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003790 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003790 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.828571 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.828571 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005753 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005753 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005753 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005753 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12491.176471 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12491.176471 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19630.434783 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19630.434783 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9456.896552 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9456.896552 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14552.301255 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 14552.301255 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14552.301255 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 14552.301255 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2052,288 +2135,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 258 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 258 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 290 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 290 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 290 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 290 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 182 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 215 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 215 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 269 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 269 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1447000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1447000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1250000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1250000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 487500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 487500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2697000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2697000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2697000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2697000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004086 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004086 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003790 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003790 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003964 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003964 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003964 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003964 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8877.300613 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8877.300613 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 11792.452830 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 11792.452830 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 8405.172414 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 8405.172414 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 10026.022305 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 10026.022305 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 10026.022305 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 10026.022305 # average overall mshr miss latency +system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1065020 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1065020 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1284501 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1284501 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 432500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 432500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2349521 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2349521 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2349521 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2349521 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003385 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003385 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002884 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002884 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.828571 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.828571 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003166 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003166 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6740.632911 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6740.632911 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12233.342857 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12233.342857 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7456.896552 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7456.896552 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8933.539924 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8933.539924 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8933.539924 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8933.539924 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 425.302863 # Cycle average of tags in use -system.l2c.total_refs 1445 # Total number of references to valid blocks. -system.l2c.sampled_refs 527 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.741935 # Average number of references to valid blocks. +system.l2c.tagsinuse 416.873465 # Cycle average of tags in use +system.l2c.total_refs 1443 # Total number of references to valid blocks. +system.l2c.sampled_refs 526 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.743346 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.824834 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 289.870828 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.081037 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 62.204312 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.605545 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 4.564656 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.760691 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 1.668516 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.722445 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004423 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000902 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000949 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000070 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 779500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 38596500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.266466 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.857143 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.961039 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.961538 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.311792 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49906 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40993.700000 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10050.900000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10118.411765 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10553.368421 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10237.229730 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45181.468085 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64596.538462 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60000.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50709.166667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 48972.007634 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47262.511905 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70900.550000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47262.511905 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70900.550000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61550.675676 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 56749.527410 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10563.437500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.986667 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66630.319149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65711.538462 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62937.500000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58604.166667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 65465.648855 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 45b73a0af..3469c3943 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205117 # Simulator instruction rate (inst/s) -host_op_rate 205116 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26560282 # Simulator tick rate (ticks/s) -host_mem_usage 1206900 # Number of bytes of host memory used -host_seconds 3.30 # Real time elapsed on the host +host_inst_rate 1256528 # Simulator instruction rate (inst/s) +host_op_rate 1256465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 162691956 # Simulator tick rate (ticks/s) +host_mem_usage 1160656 # Number of bytes of host memory used +host_seconds 0.54 # Real time elapsed on the host sim_insts 677327 # Number of instructions simulated sim_ops 677327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory @@ -57,6 +57,12 @@ system.physmem.bw_total::cpu2.data 9486130 # To system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 407903588 # Throughput (bytes/s) +system.membus.data_through_bus 35776 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.toL2Bus.throughput 1893577480 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 166080 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 175415 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index f34b8a118..a78d037d9 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,130 +1,193 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 262970500 # Number of ticks simulated -final_tick 262970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 262793500 # Number of ticks simulated +final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110323 # Simulator instruction rate (inst/s) -host_op_rate 110323 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43749084 # Simulator tick rate (ticks/s) -host_mem_usage 287188 # Number of bytes of host memory used -host_seconds 6.01 # Real time elapsed on the host -sim_insts 663135 # Number of instructions simulated -sim_ops 663135 # Number of ops (including micro ops) simulated +host_inst_rate 1490059 # Simulator instruction rate (inst/s) +host_op_rate 1490014 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 590046557 # Simulator tick rate (ticks/s) +host_mem_usage 244196 # Number of bytes of host memory used +host_seconds 0.45 # Real time elapsed on the host +sim_insts 663601 # Number of instructions simulated +sim_ops 663601 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 4224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 4224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 66 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69361392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40156596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16062638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5597586 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 486747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3650600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 243373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3650600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139209531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69361392 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16062638 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 486747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 243373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86154150 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69361392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40156596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16062638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5597586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 486747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3650600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 243373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3650600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139209531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 139303293 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 430 # Transaction distribution +system.membus.trans_dist::ReadResp 430 # Transaction distribution +system.membus.trans_dist::UpgradeReq 272 # Transaction distribution +system.membus.trans_dist::UpgradeResp 77 # Transaction distribution +system.membus.trans_dist::ReadExReq 208 # Transaction distribution +system.membus.trans_dist::ReadExResp 142 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side 1559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1559 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36608 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 855296 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer0.occupancy 5423500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 2.1 # Layer utilization (%) +system.toL2Bus.throughput 646591335 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 934 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 580 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 388 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 359 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 734 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 361 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 4820 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 10944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 23488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 116032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 116032 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 1474488 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1650489 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 1281961 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.5 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1651987 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 1173486 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1177490 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 525941 # number of cpu cycles simulated +system.cpu0.numCycles 525587 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158580 # Number of instructions committed -system.cpu0.committedOps 158580 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 109212 # Number of integer alu accesses +system.cpu0.committedInsts 158574 # Number of instructions committed +system.cpu0.committedOps 158574 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 109208 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 26033 # number of instructions that are conditional controls -system.cpu0.num_int_insts 109212 # number of integer instructions +system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls +system.cpu0.num_int_insts 109208 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315794 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110818 # number of times the integer registers were written +system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 74024 # number of memory refs -system.cpu0.num_load_insts 49009 # Number of load instructions -system.cpu0.num_store_insts 25015 # Number of store instructions +system.cpu0.num_mem_refs 74021 # number of memory refs +system.cpu0.num_load_insts 49007 # Number of load instructions +system.cpu0.num_store_insts 25014 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 525941 # Number of busy cycles +system.cpu0.num_busy_cycles 525587 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.410852 # Cycle average of tags in use -system.cpu0.icache.total_refs 158176 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 212.401760 # Cycle average of tags in use +system.cpu0.icache.total_refs 158170 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 338.706638 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 338.693790 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.410852 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414865 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414865 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 158176 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 158176 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 158176 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 158176 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 158176 # number of overall hits -system.cpu0.icache.overall_hits::total 158176 # number of overall hits +system.cpu0.icache.occ_blocks::cpu0.inst 212.401760 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 158170 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 158170 # number of overall hits +system.cpu0.icache.overall_hits::total 158170 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18143000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18143000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18143000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18143000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18143000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18143000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158643 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158643 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158643 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158643 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158643 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158643 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18147500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18147500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18147500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18147500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18147500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18147500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158637 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158637 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158637 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38850.107066 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38850.107066 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38850.107066 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38850.107066 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38859.743041 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38859.743041 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38859.743041 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38859.743041 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38859.743041 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38859.743041 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -139,94 +202,94 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17209000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17209000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17209000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17209000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17209000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17209000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17213500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17213500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17213500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17213500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17213500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17213500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36850.107066 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36850.107066 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36850.107066 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36859.743041 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36859.743041 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36859.743041 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 145.568014 # Cycle average of tags in use -system.cpu0.dcache.total_refs 73491 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 145.572033 # Cycle average of tags in use +system.cpu0.dcache.total_refs 73489 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 440.065868 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 440.053892 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.568014 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284313 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284313 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 48828 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48828 # number of ReadReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 145.572033 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73608 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73608 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73608 # number of overall hits -system.cpu0.dcache.overall_hits::total 73608 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 171 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 171 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 184 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 184 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 73607 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73607 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73607 # number of overall hits +system.cpu0.dcache.overall_hits::total 73607 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 355 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 355 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 355 # number of overall misses -system.cpu0.dcache.overall_misses::total 355 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4683500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4683500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7047500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7047500 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 364500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 364500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11731000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11731000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11731000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11731000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48999 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48999 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24964 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24964 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses +system.cpu0.dcache.overall_misses::total 353 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4582500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4582500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6978000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6978000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11560500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11560500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11560500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11560500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24963 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73963 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73963 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73963 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73963 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003490 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003490 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007371 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007371 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73960 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73960 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73960 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73960 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003470 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003470 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007331 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007331 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004800 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004800 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004800 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004800 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27388.888889 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27388.888889 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38301.630435 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38301.630435 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14019.230769 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 14019.230769 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33045.070423 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33045.070423 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26955.882353 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26955.882353 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38131.147541 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38131.147541 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32749.291785 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32749.291785 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32749.291785 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32749.291785 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -237,114 +300,114 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 171 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 184 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 184 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 355 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 355 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4341500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4341500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6679500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6679500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 312500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 312500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11021000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11021000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003490 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003490 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007371 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007371 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237519 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237519 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6612000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6612000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10849519 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10849519 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10849519 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10849519 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007331 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004800 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004800 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004800 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004800 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25388.888889 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25388.888889 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36301.630435 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36301.630435 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12019.230769 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12019.230769 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31045.070423 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31045.070423 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31045.070423 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31045.070423 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24926.582353 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24926.582353 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36131.147541 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36131.147541 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30735.181303 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30735.181303 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30735.181303 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30735.181303 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 525940 # number of cpu cycles simulated +system.cpu1.numCycles 525587 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 166746 # Number of instructions committed -system.cpu1.committedOps 166746 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 110403 # Number of integer alu accesses +system.cpu1.committedInsts 173389 # Number of instructions committed +system.cpu1.committedOps 173389 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 107707 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 32184 # number of instructions that are conditional controls -system.cpu1.num_int_insts 110403 # number of integer instructions +system.cpu1.num_conditional_control_insts 36848 # number of instructions that are conditional controls +system.cpu1.num_int_insts 107707 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 275077 # number of times the integer registers were read -system.cpu1.num_int_register_writes 104543 # number of times the integer registers were written +system.cpu1.num_int_register_reads 245634 # number of times the integer registers were read +system.cpu1.num_int_register_writes 91167 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 54388 # number of memory refs -system.cpu1.num_load_insts 40871 # Number of load instructions -system.cpu1.num_store_insts 13517 # Number of store instructions -system.cpu1.num_idle_cycles 69336.869902 # Number of idle cycles -system.cpu1.num_busy_cycles 456603.130098 # Number of busy cycles -system.cpu1.not_idle_fraction 0.868166 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.131834 # Percentage of idle cycles +system.cpu1.num_mem_refs 47028 # number of memory refs +system.cpu1.num_load_insts 39502 # Number of load instructions +system.cpu1.num_store_insts 7526 # Number of store instructions +system.cpu1.num_idle_cycles 69346.001736 # Number of idle cycles +system.cpu1.num_busy_cycles 456240.998264 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868060 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131940 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 70.021877 # Cycle average of tags in use -system.cpu1.icache.total_refs 166413 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 70.017443 # Cycle average of tags in use +system.cpu1.icache.total_refs 173056 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 454.680328 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 472.830601 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 70.021877 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136761 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136761 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 166413 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 166413 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 166413 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 166413 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 166413 # number of overall hits -system.cpu1.icache.overall_hits::total 166413 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 70.017443 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 173056 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 173056 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 173056 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 173056 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 173056 # number of overall hits +system.cpu1.icache.overall_hits::total 173056 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7565000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7565000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7565000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7565000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7565000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7565000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 166779 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 166779 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 166779 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 166779 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 166779 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 166779 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002195 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002195 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002195 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002195 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002195 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002195 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20669.398907 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20669.398907 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20669.398907 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20669.398907 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20669.398907 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20669.398907 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7542000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7542000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7542000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7542000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7542000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7542000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 173422 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 173422 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 173422 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 173422 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 173422 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 173422 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002110 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002110 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002110 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002110 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002110 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002110 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20606.557377 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20606.557377 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20606.557377 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20606.557377 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20606.557377 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20606.557377 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,94 +422,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6833000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6833000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6833000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6833000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6833000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6833000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002195 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002195 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002195 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18669.398907 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18669.398907 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18669.398907 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806511 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806511 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806511 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6806511 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806511 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6806511 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002110 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002110 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002110 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18597.024590 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18597.024590 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18597.024590 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.686467 # Cycle average of tags in use -system.cpu1.dcache.total_refs 29411 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.692937 # Cycle average of tags in use +system.cpu1.dcache.total_refs 17380 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 980.366667 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 579.333333 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.686467 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.054075 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.054075 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 40710 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 40710 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 13344 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 13344 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 54054 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 54054 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 54054 # number of overall hits -system.cpu1.dcache.overall_hits::total 54054 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 153 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 153 # number of ReadReq misses +system.cpu1.dcache.occ_blocks::cpu1.data 27.692937 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.054088 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.054088 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 39322 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 39322 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7334 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7334 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 19 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 19 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 46656 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 46656 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 46656 # number of overall hits +system.cpu1.dcache.overall_hits::total 46656 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 172 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 172 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 259 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 259 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259 # number of overall misses -system.cpu1.dcache.overall_misses::total 259 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2954500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2954500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1962000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1962000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 274000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 274000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4916500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4916500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4916500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4916500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 40863 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 40863 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 13450 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 13450 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 65 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 54313 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 54313 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 54313 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 54313 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003744 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003744 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007881 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.007881 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.769231 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.769231 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004769 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004769 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004769 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004769 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19310.457516 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19310.457516 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18509.433962 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18509.433962 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 5480 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 5480 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18982.625483 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18982.625483 # average overall miss latency +system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 278 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 278 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 278 # number of overall misses +system.cpu1.dcache.overall_misses::total 278 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3331000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3331000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2174000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2174000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 282000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 282000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5505000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5505000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5505000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5505000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 39494 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 39494 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7440 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7440 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 84 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 84 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 46934 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 46934 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 46934 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 46934 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004355 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004355 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014247 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.014247 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.773810 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.773810 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005923 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005923 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005923 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005923 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19366.279070 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19366.279070 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20509.433962 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20509.433962 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4338.461538 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4338.461538 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19802.158273 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19802.158273 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19802.158273 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19802.158273 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -455,114 +518,114 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 153 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2648500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2648500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1750000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1750000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 174000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 174000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4398500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4398500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4398500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4398500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003744 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003744 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007881 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007881 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.769231 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.769231 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004769 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004769 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004769 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004769 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17310.457516 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17310.457516 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16509.433962 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16509.433962 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3480 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3480 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 278 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 278 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2972539 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2972539 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 152000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4934539 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4934539 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4934539 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4934539 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004355 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004355 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014247 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014247 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.773810 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.773810 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005923 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005923 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005923 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005923 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17282.203488 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17282.203488 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18509.433962 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18509.433962 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2338.461538 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2338.461538 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17750.140288 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17750.140288 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 525941 # number of cpu cycles simulated +system.cpu2.numCycles 525587 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 169995 # Number of instructions committed -system.cpu2.committedOps 169995 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 110917 # Number of integer alu accesses +system.cpu2.committedInsts 164870 # Number of instructions committed +system.cpu2.committedOps 164870 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 112982 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 33551 # number of instructions that are conditional controls -system.cpu2.num_int_insts 110917 # number of integer instructions +system.cpu2.num_conditional_control_insts 29953 # number of instructions that are conditional controls +system.cpu2.num_int_insts 112982 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 271666 # number of times the integer registers were read -system.cpu2.num_int_register_writes 102578 # number of times the integer registers were written +system.cpu2.num_int_register_reads 294323 # number of times the integer registers were read +system.cpu2.num_int_register_writes 112883 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 53535 # number of memory refs -system.cpu2.num_load_insts 41127 # Number of load instructions -system.cpu2.num_store_insts 12408 # Number of store instructions -system.cpu2.num_idle_cycles 69585.001735 # Number of idle cycles -system.cpu2.num_busy_cycles 456355.998265 # Number of busy cycles -system.cpu2.not_idle_fraction 0.867694 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.132306 # Percentage of idle cycles +system.cpu2.num_mem_refs 59198 # number of memory refs +system.cpu2.num_load_insts 42166 # Number of load instructions +system.cpu2.num_store_insts 17032 # Number of store instructions +system.cpu2.num_idle_cycles 69603.001735 # Number of idle cycles +system.cpu2.num_busy_cycles 455983.998265 # Number of busy cycles +system.cpu2.not_idle_fraction 0.867571 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.132429 # Percentage of idle cycles system.cpu2.icache.replacements 280 # number of replacements -system.cpu2.icache.tagsinuse 65.527396 # Cycle average of tags in use -system.cpu2.icache.total_refs 169662 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 67.624903 # Cycle average of tags in use +system.cpu2.icache.total_refs 164537 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 463.557377 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 449.554645 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 65.527396 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.127983 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.127983 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 169662 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 169662 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 169662 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 169662 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 169662 # number of overall hits -system.cpu2.icache.overall_hits::total 169662 # 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average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14428.961749 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14428.961749 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14428.961749 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5251500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5251500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5251500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5251500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5251500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5251500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 164903 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 164903 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 164903 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 164903 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 164903 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 164903 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002219 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002219 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002219 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002219 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002219 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002219 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14348.360656 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14348.360656 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14348.360656 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14348.360656 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14348.360656 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14348.360656 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,94 +640,94 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4549000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4549000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4549000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4549000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4549000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4549000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12428.961749 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12428.961749 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12428.961749 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4514513 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 4514513 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4514513 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 4514513 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4514513 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 4514513 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002219 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002219 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002219 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002219 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002219 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002219 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12334.734973 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12334.734973 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12334.734973 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12334.734973 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12334.734973 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12334.734973 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 25.908378 # Cycle average of tags in use -system.cpu2.dcache.total_refs 27066 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 26.764140 # Cycle average of tags in use +system.cpu2.dcache.total_refs 36333 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 933.310345 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1252.862069 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 25.908378 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.050602 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.050602 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 40963 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40963 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 12235 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 12235 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 53198 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 53198 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 53198 # number of overall hits -system.cpu2.dcache.overall_hits::total 53198 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 157 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 157 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 262 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses -system.cpu2.dcache.overall_misses::total 262 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2754500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2754500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1914500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 1914500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 286000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 286000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4669000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4669000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4669000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4669000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 41120 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 41120 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 12340 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 12340 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 53460 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 53460 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 53460 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 53460 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003818 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003818 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008509 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.008509 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.772727 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.772727 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004901 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004901 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004901 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004901 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17544.585987 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 17544.585987 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18233.333333 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 18233.333333 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5607.843137 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 5607.843137 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17820.610687 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17820.610687 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17820.610687 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17820.610687 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 26.764140 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.052274 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.052274 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42000 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42000 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 16859 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 16859 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 58859 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 58859 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 58859 # number of overall hits +system.cpu2.dcache.overall_hits::total 58859 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 158 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 158 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 52 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 52 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses +system.cpu2.dcache.overall_misses::total 267 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2136000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2136000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1926500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 1926500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 214000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 214000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4062500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4062500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4062500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4062500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42158 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42158 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 16968 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 16968 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 59126 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 59126 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 59126 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 59126 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003748 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003748 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006424 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.006424 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.838710 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.838710 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004516 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004516 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004516 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004516 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13518.987342 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 13518.987342 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17674.311927 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 17674.311927 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4115.384615 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4115.384615 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15215.355805 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 15215.355805 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15215.355805 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 15215.355805 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,114 +736,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 157 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2440500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2440500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1704500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1704500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 184000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 184000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4145000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 4145000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4145000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 4145000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003818 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003818 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.008509 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.008509 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.772727 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.772727 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004901 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004901 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004901 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004901 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15544.585987 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15544.585987 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16233.333333 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16233.333333 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3607.843137 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3607.843137 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 15820.610687 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 15820.610687 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 15820.610687 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 15820.610687 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 158 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1814014 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1814014 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1708500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1708500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 110000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 110000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3522514 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3522514 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3522514 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3522514 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003748 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003748 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006424 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.838710 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.838710 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004516 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004516 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004516 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004516 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11481.101266 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11481.101266 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15674.311927 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15674.311927 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2115.384615 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2115.384615 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13192.936330 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13192.936330 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13192.936330 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13192.936330 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 525940 # number of cpu cycles simulated +system.cpu3.numCycles 525586 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 167814 # Number of instructions committed -system.cpu3.committedOps 167814 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 111369 # Number of integer alu accesses +system.cpu3.committedInsts 166768 # Number of instructions committed +system.cpu3.committedOps 166768 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 112266 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 32222 # number of instructions that are conditional controls -system.cpu3.num_int_insts 111369 # number of integer instructions +system.cpu3.num_conditional_control_insts 31259 # number of instructions that are conditional controls +system.cpu3.num_int_insts 112266 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 278793 # number of times the integer registers were read -system.cpu3.num_int_register_writes 105918 # number of times the integer registers were written +system.cpu3.num_int_register_reads 286233 # number of times the integer registers were read +system.cpu3.num_int_register_writes 109194 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 55316 # number of memory refs -system.cpu3.num_load_insts 41342 # Number of load instructions -system.cpu3.num_store_insts 13974 # Number of store instructions -system.cpu3.num_idle_cycles 69844.868934 # Number of idle cycles -system.cpu3.num_busy_cycles 456095.131066 # Number of busy cycles -system.cpu3.not_idle_fraction 0.867200 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.132800 # Percentage of idle cycles +system.cpu3.num_mem_refs 57176 # number of memory refs +system.cpu3.num_load_insts 41805 # Number of load instructions +system.cpu3.num_store_insts 15371 # Number of store instructions +system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles +system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles system.cpu3.icache.replacements 281 # number of replacements -system.cpu3.icache.tagsinuse 67.672766 # Cycle average of tags in use -system.cpu3.icache.total_refs 167480 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 65.598360 # Cycle average of tags in use +system.cpu3.icache.total_refs 166434 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 456.348774 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 453.498638 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 67.672766 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.132173 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.132173 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 167480 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 167480 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 167480 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 167480 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 167480 # number of overall hits -system.cpu3.icache.overall_hits::total 167480 # number of overall hits +system.cpu3.icache.occ_blocks::cpu3.inst 65.598360 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 166434 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 166434 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 166434 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 166434 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 166434 # number of overall hits +system.cpu3.icache.overall_hits::total 166434 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5162000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5162000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5162000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5162000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5162000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5162000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 167847 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 167847 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 167847 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 167847 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 167847 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 167847 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002187 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002187 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002187 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002187 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002187 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002187 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14065.395095 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14065.395095 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14065.395095 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14065.395095 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14065.395095 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14065.395095 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5149000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5149000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5149000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5149000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5149000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5149000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 166801 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 166801 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 166801 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 166801 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 166801 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 166801 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002200 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002200 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002200 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002200 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002200 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002200 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14029.972752 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14029.972752 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14029.972752 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14029.972752 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14029.972752 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14029.972752 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -795,94 +858,94 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4428000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4428000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4428000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4428000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4428000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4428000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002187 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002187 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002187 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12065.395095 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12065.395095 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12065.395095 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4414501 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4414501 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4414501 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4414501 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4414501 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4414501 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002200 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002200 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002200 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12028.613079 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12028.613079 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12028.613079 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 26.814972 # Cycle average of tags in use -system.cpu3.dcache.total_refs 30179 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 25.941840 # Cycle average of tags in use +system.cpu3.dcache.total_refs 33003 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1040.655172 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1138.034483 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 26.814972 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.052373 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.052373 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 41164 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41164 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 13787 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 13787 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 10 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 10 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 54951 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 54951 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 54951 # number of overall hits -system.cpu3.dcache.overall_hits::total 54951 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 171 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 171 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 106 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 106 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 277 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 277 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 277 # number of overall misses -system.cpu3.dcache.overall_misses::total 277 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2803500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 2803500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2201500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2201500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 368000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 368000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 5005000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 5005000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 5005000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 5005000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41335 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41335 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 13893 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 13893 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 79 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 79 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 55228 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 55228 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 55228 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 55228 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004137 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.004137 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007630 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.007630 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.873418 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.873418 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005016 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005016 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005016 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005016 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16394.736842 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 16394.736842 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20768.867925 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 20768.867925 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 5333.333333 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 5333.333333 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18068.592058 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 18068.592058 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18068.592058 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 18068.592058 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 25.941840 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.050668 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.050668 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41638 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41638 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 15196 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 15196 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 56834 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 56834 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 56834 # number of overall hits +system.cpu3.dcache.overall_hits::total 56834 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 159 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 159 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 53 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses +system.cpu3.dcache.overall_misses::total 268 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2247500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 2247500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1908500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1908500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 217500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 217500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 4156000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 4156000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 4156000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 4156000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41797 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41797 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 15305 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 15305 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 64 # 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average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15507.462687 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 15507.462687 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -891,70 +954,70 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 171 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # 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number of ReadReq accesses(hits+misses) @@ -1069,10 +1132,10 @@ system.l2c.ReadReq_accesses::total 1670 # nu system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) @@ -1109,7 +1172,7 @@ system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -1133,38 +1196,38 @@ system.l2c.overall_miss_rate::cpu2.data 0.640000 # mi system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52342.105263 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52373.684211 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52348.484848 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52375 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 47375 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 50000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 42833.333333 # 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average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40678.571429 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40176.056338 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40035.642857 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40278.161972 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40031.187500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40109.263986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 41250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40766.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40633.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40057.692308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40031.187500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40109.263986 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |