diff options
Diffstat (limited to 'tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt')
| -rw-r--r-- | tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 076c105ad..9e326e98d 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.019665 # Number of seconds simulated -sim_ticks 19665440 # Number of ticks simulated -final_tick 19665440 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.006104 # Number of seconds simulated +sim_ticks 6103915 # Number of ticks simulated +final_tick 6103915 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 178903 # Simulator tick rate (ticks/s) -host_mem_usage 378856 # Number of bytes of host memory used -host_seconds 109.92 # Real time elapsed on the host +host_tick_rate 78453 # Simulator tick rate (ticks/s) +host_mem_usage 374396 # Number of bytes of host memory used +host_seconds 77.80 # Real time elapsed on the host system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.num_reads 99534 # number of read accesses completed -system.cpu0.num_writes 53920 # number of write accesses completed +system.cpu0.num_reads 99027 # number of read accesses completed +system.cpu0.num_writes 53493 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99604 # number of read accesses completed -system.cpu1.num_writes 53779 # number of write accesses completed +system.cpu1.num_reads 98254 # number of read accesses completed +system.cpu1.num_writes 52787 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99103 # number of read accesses completed -system.cpu2.num_writes 53314 # number of write accesses completed +system.cpu2.num_reads 99047 # number of read accesses completed +system.cpu2.num_writes 53306 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99223 # number of read accesses completed -system.cpu3.num_writes 53188 # number of write accesses completed +system.cpu3.num_reads 98414 # number of read accesses completed +system.cpu3.num_writes 53420 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 53373 # number of write accesses completed +system.cpu4.num_writes 53741 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99316 # number of read accesses completed -system.cpu5.num_writes 53693 # number of write accesses completed +system.cpu5.num_reads 98111 # number of read accesses completed +system.cpu5.num_writes 53002 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99832 # number of read accesses completed -system.cpu6.num_writes 53341 # number of write accesses completed +system.cpu6.num_reads 99154 # number of read accesses completed +system.cpu6.num_writes 52587 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99257 # number of read accesses completed -system.cpu7.num_writes 53656 # number of write accesses completed +system.cpu7.num_reads 99215 # number of read accesses completed +system.cpu7.num_writes 53364 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- |