diff options
Diffstat (limited to 'tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats')
| -rw-r--r-- | tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats | 783 |
1 files changed, 17 insertions, 766 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats index 75d9d7cf6..393b22366 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats @@ -1,26 +1,24 @@ -Real time: Apr/09/2013 02:01:53 +Real time: Jun/08/2013 13:30:00 Profiler Stats -------------- -Elapsed_time_in_seconds: 168 -Elapsed_time_in_minutes: 2.8 -Elapsed_time_in_hours: 0.0466667 -Elapsed_time_in_days: 0.00194444 +Elapsed_time_in_seconds: 99 +Elapsed_time_in_minutes: 1.65 +Elapsed_time_in_hours: 0.0275 +Elapsed_time_in_days: 0.00114583 -Virtual_time_in_seconds: 167.14 -Virtual_time_in_minutes: 2.78567 -Virtual_time_in_hours: 0.0464278 -Virtual_time_in_days: 0.00193449 +Virtual_time_in_seconds: 96.67 +Virtual_time_in_minutes: 1.61117 +Virtual_time_in_hours: 0.0268528 +Virtual_time_in_days: 0.00111887 Ruby_current_time: 5795833 Ruby_start_time: 0 Ruby_cycles: 5795833 -mbytes_resident: 64.7773 -mbytes_total: 244.449 -resident_ratio: 0.264993 - -ruby_cycles_executed: [ 5795834 5795834 5795834 5795834 5795834 5795834 5795834 5795834 ] +mbytes_resident: 69.8828 +mbytes_total: 285.598 +resident_ratio: 0.244717 Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -68,7 +66,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -87,13 +84,13 @@ Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation Resource Usage -------------- page_size: 4096 -user_time: 166 +user_time: 96 system_time: 0 -page_reclaims: 17148 -page_faults: 3 +page_reclaims: 19166 +page_faults: 0 swaps: 0 -block_inputs: 776 -block_outputs: 312 +block_inputs: 24 +block_outputs: 256 Network Stats ------------- @@ -324,749 +321,3 @@ links_utilized_percent_switch_9: 18.0864 outgoing_messages_switch_9_link_8_Writeback_Control: 950339 7602712 [ 0 0 582292 0 0 368047 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_9_link_8_Unblock_Control: 617596 4940768 [ 0 0 0 0 0 617596 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [50266 50315 50271 50212 50263 50069 50306 49970 ] 401672 -Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [26762 27215 27106 27272 27014 27080 27361 27054 ] 216864 -L2_Replacement [76877 77378 77204 77319 77135 76978 77528 76877 ] 617296 -L1_to_L2 [839684 843217 843158 840771 842565 841910 845488 839694 ] 6736487 -Trigger_L2_to_L1D [75 72 99 79 66 89 69 72 ] 621 -Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -Complete_L2_to_L1 [75 72 99 79 66 89 69 72 ] 621 -Other_GETX [189761 189309 189417 189262 189522 189457 189156 189455 ] 1515339 -Other_GETS [350360 350304 350380 350430 350354 350578 350311 350671 ] 2803388 -Merged_GETS [67 47 56 60 48 51 52 58 ] 439 -Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -Invalidate [0 0 0 0 0 0 0 0 ] 0 -Ack [535380 538939 537669 538458 537124 535993 539952 535252 ] 4298767 -Shared_Ack [61 58 61 63 51 74 50 68 ] 486 -Data [2873 3045 2960 3027 2998 3000 2981 3082 ] 23966 -Shared_Data [1060 1048 1056 1053 1045 1094 1078 1123 ] 8557 -Exclusive_Data [72953 73296 73198 73248 73100 72896 73480 72683 ] 584854 -Writeback_Ack [72619 73022 72821 72965 72792 72564 73169 72340 ] 582292 -Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -All_acks [1114 1096 1109 1107 1091 1156 1120 1180 ] 8973 -All_acks_no_sharers [75773 76294 76104 76221 76052 75834 76419 75708 ] 608405 -Flush_line [0 0 0 0 0 0 0 0 ] 0 -Block_Ack [0 0 0 0 0 0 0 0 ] 0 - - - Transitions - -I Load [50174 50224 50155 50116 50191 49971 50219 49868 ] 400918 -I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [26713 27165 27060 27213 26955 27016 27320 27019 ] 216461 -I L2_Replacement [1339 1403 1446 1410 1437 1441 1373 1479 ] 11328 -I L1_to_L2 [263 295 253 281 292 256 261 290 ] 2191 -I Trigger_L2_to_L1D [3 0 1 2 0 4 2 3 ] 15 -I Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -I Other_GETX [188850 188385 188473 188307 188572 188504 188287 188527 ] 1507905 -I Other_GETS [348728 348598 348711 348779 348712 348887 348575 348998 ] 2789988 -I Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -I NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -I Invalidate [0 0 0 0 0 0 0 0 ] 0 -I Flush_line [0 0 0 0 0 0 0 0 ] 0 - -S Load [1 1 2 0 0 0 1 1 ] 6 -S Ifetch [0 0 0 0 0 0 0 0 ] 0 -S Store [0 0 0 0 0 0 0 0 ] 0 -S L2_Replacement [2919 2953 2937 2944 2906 2973 2984 3058 ] 23674 -S L1_to_L2 [2947 2984 2973 2971 2929 2993 3006 3086 ] 23889 -S Trigger_L2_to_L1D [2 5 4 1 0 2 3 6 ] 23 -S Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -S Other_GETX [29 31 38 33 32 28 25 31 ] 247 -S Other_GETS [57 56 59 72 52 62 79 49 ] 486 -S Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -S NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -S Invalidate [0 0 0 0 0 0 0 0 ] 0 -S Flush_line [0 0 0 0 0 0 0 0 ] 0 - -O Load [0 0 0 0 0 0 0 0 ] 0 -O Ifetch [0 0 0 0 0 0 0 0 ] 0 -O Store [1 0 0 0 0 0 0 0 ] 1 -O L2_Replacement [1037 1033 990 999 972 1001 1015 980 ] 8027 -O L1_to_L2 [204 188 202 199 190 218 217 198 ] 1616 -O Trigger_L2_to_L1D [0 2 0 1 0 1 0 2 ] 6 -O Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -O Other_GETX [7 8 8 5 3 11 9 5 ] 56 -O Other_GETS [9 14 12 12 13 9 9 13 ] 91 -O Merged_GETS [4 3 2 6 3 1 1 1 ] 21 -O Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -O NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -O Invalidate [0 0 0 0 0 0 0 0 ] 0 -O Flush_line [0 0 0 0 0 0 0 0 ] 0 - -M Load [7 3 5 6 2 11 6 2 ] 42 -M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [5 5 2 5 2 9 1 2 ] 31 -M L2_Replacement [45647 45669 45641 45593 45746 45407 45688 45251 ] 364642 -M L1_to_L2 [46941 46960 46927 46865 46980 46700 46933 46507 ] 374813 -M Trigger_L2_to_L1D [49 40 60 51 41 55 37 40 ] 373 -M Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -M Other_GETX [529 518 538 533 520 540 502 539 ] 4219 -M Other_GETS [983 999 944 950 931 962 974 928 ] 7671 -M Merged_GETS [39 27 33 31 27 27 29 42 ] 255 -M Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -M NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -M Invalidate [0 0 0 0 0 0 0 0 ] 0 -M Flush_line [0 0 0 0 0 0 0 0 ] 0 - -MM Load [4 8 2 6 6 4 3 7 ] 40 -MM Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM Store [0 5 1 2 4 4 1 2 ] 19 -MM L2_Replacement [25935 26320 26190 26373 26074 26156 26468 26109 ] 209625 -MM L1_to_L2 [26603 27029 26955 27088 26817 26905 27186 26874 ] 215457 -MM Trigger_L2_to_L1D [21 25 34 24 25 27 27 21 ] 204 -MM Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -MM Other_GETX [296 298 301 320 334 308 279 308 ] 2444 -MM Other_GETS [481 549 562 521 548 558 561 599 ] 4379 -MM Merged_GETS [23 16 21 23 18 23 21 15 ] 160 -MM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -MM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -MM Invalidate [0 0 0 0 0 0 0 0 ] 0 -MM Flush_line [0 0 0 0 0 0 0 0 ] 0 - -IR Load [1 0 1 0 0 1 1 2 ] 6 -IR Ifetch [0 0 0 0 0 0 0 0 ] 0 -IR Store [2 0 0 2 0 3 1 1 ] 9 -IR L1_to_L2 [0 0 0 0 0 11 0 2 ] 13 -IR Flush_line [0 0 0 0 0 0 0 0 ] 0 - -SR Load [2 3 4 1 0 1 2 4 ] 17 -SR Ifetch [0 0 0 0 0 0 0 0 ] 0 -SR Store [0 2 0 0 0 1 1 2 ] 6 -SR L1_to_L2 [0 3 0 0 0 0 0 13 ] 16 -SR Flush_line [0 0 0 0 0 0 0 0 ] 0 - -OR Load [0 1 0 1 0 1 0 2 ] 5 -OR Ifetch [0 0 0 0 0 0 0 0 ] 0 -OR Store [0 1 0 0 0 0 0 0 ] 1 -OR L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -OR Flush_line [0 0 0 0 0 0 0 0 ] 0 - -MR Load [32 27 42 33 20 37 27 31 ] 249 -MR Ifetch [0 0 0 0 0 0 0 0 ] 0 -MR Store [17 13 18 18 21 18 10 9 ] 124 -MR L1_to_L2 [91 56 102 86 95 89 59 56 ] 634 -MR Flush_line [0 0 0 0 0 0 0 0 ] 0 - -MMR Load [14 17 26 16 16 16 18 14 ] 137 -MMR Ifetch [0 0 0 0 0 0 0 0 ] 0 -MMR Store [7 8 8 8 9 11 9 7 ] 67 -MMR L1_to_L2 [59 75 46 41 49 33 49 34 ] 386 -MMR Flush_line [0 0 0 0 0 0 0 0 ] 0 - -IM Load [0 0 0 0 0 0 0 0 ] 0 -IM Ifetch [0 0 0 0 0 0 0 0 ] 0 -IM Store [0 0 0 0 0 0 0 0 ] 0 -IM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IM L1_to_L2 [264282 266577 267890 269848 268056 268579 269306 265306 ] 2139844 -IM Other_GETX [7 12 10 15 9 15 10 13 ] 91 -IM Other_GETS [21 19 20 24 14 14 22 16 ] 150 -IM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -IM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -IM Invalidate [0 0 0 0 0 0 0 0 ] 0 -IM Ack [183448 186647 185973 187270 185299 185768 187652 185613 ] 1487670 -IM Data [985 1103 1041 1101 1105 1091 1048 1112 ] 8586 -IM Exclusive_Data [25729 26061 26018 26114 25848 25928 26272 25907 ] 207877 -IM Flush_line [0 0 0 0 0 0 0 0 ] 0 - -SM Load [0 0 0 0 0 0 0 0 ] 0 -SM Ifetch [0 0 0 0 0 0 0 0 ] 0 -SM Store [0 0 0 0 0 0 0 0 ] 0 -SM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -SM L1_to_L2 [0 11 0 0 0 1 7 0 ] 19 -SM Other_GETX [0 0 0 0 0 0 0 0 ] 0 -SM Other_GETS [0 0 0 0 0 0 0 0 ] 0 -SM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -SM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -SM Invalidate [0 0 0 0 0 0 0 0 ] 0 -SM Ack [0 14 0 0 0 7 7 14 ] 42 -SM Data [0 2 0 0 0 1 1 2 ] 6 -SM Exclusive_Data [0 0 0 0 0 0 0 0 ] 0 -SM Flush_line [0 0 0 0 0 0 0 0 ] 0 - -OM Load [0 0 0 0 0 0 0 0 ] 0 -OM Ifetch [0 0 0 0 0 0 0 0 ] 0 -OM Store [0 0 0 0 0 0 0 0 ] 0 -OM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -OM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -OM Other_GETX [0 0 0 0 0 0 0 0 ] 0 -OM Other_GETS [0 0 0 0 0 0 0 0 ] 0 -OM Merged_GETS [0 0 0 0 0 0 0 0 ] 0 -OM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -OM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -OM Invalidate [0 0 0 0 0 0 0 0 ] 0 -OM Ack [7 7 0 0 0 0 0 0 ] 14 -OM All_acks [0 0 0 0 0 0 0 0 ] 0 -OM All_acks_no_sharers [1 1 0 0 0 0 0 0 ] 2 -OM Flush_line [0 0 0 0 0 0 0 0 ] 0 - -ISM Load [0 0 0 0 0 0 0 0 ] 0 -ISM Ifetch [0 0 0 0 0 0 0 0 ] 0 -ISM Store [0 0 0 0 0 0 0 0 ] 0 -ISM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -ISM L1_to_L2 [2 0 0 0 1 0 14 1 ] 18 -ISM Ack [104 73 108 117 100 106 115 87 ] 810 -ISM All_acks_no_sharers [985 1105 1041 1101 1105 1092 1049 1114 ] 8592 -ISM Flush_line [0 0 0 0 0 0 0 0 ] 0 - -M_W Load [0 0 0 0 0 0 0 0 ] 0 -M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -M_W Store [0 0 0 0 0 0 0 0 ] 0 -M_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -M_W L1_to_L2 [539 550 404 533 478 492 525 425 ] 3946 -M_W Ack [1618 1714 1578 1607 1665 1631 1583 1553 ] 12949 -M_W All_acks_no_sharers [47224 47235 47179 47134 47252 46968 47208 46776 ] 376976 -M_W Flush_line [0 0 0 0 0 0 0 0 ] 0 - -MM_W Load [0 0 0 0 0 0 0 0 ] 0 -MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM_W Store [0 0 0 0 0 0 0 0 ] 0 -MM_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MM_W L1_to_L2 [1079 875 817 808 798 840 931 893 ] 7041 -MM_W Ack [2578 2557 2465 2275 2427 2427 2583 2531 ] 19843 -MM_W All_acks_no_sharers [25729 26061 26018 26114 25848 25928 26272 25907 ] 207877 -MM_W Flush_line [0 0 0 0 0 0 0 0 ] 0 - -IS Load [0 0 0 0 0 0 0 0 ] 0 -IS Ifetch [0 0 0 0 0 0 0 0 ] 0 -IS Store [0 0 0 0 0 0 0 0 ] 0 -IS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IS L1_to_L2 [495283 496463 495139 490703 494908 493655 495921 494562 ] 3956634 -IS Other_GETX [18 25 17 24 21 22 15 15 ] 157 -IS Other_GETS [33 30 33 29 36 40 28 38 ] 267 -IS Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -IS NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -IS Invalidate [0 0 0 0 0 0 0 0 ] 0 -IS Ack [344673 344866 344538 344199 344619 343059 344891 342300 ] 2753145 -IS Shared_Ack [57 54 57 59 48 68 45 64 ] 452 -IS Data [1888 1940 1919 1926 1893 1908 1932 1968 ] 15374 -IS Shared_Data [1060 1048 1056 1053 1045 1094 1078 1123 ] 8557 -IS Exclusive_Data [47224 47235 47180 47134 47252 46968 47208 46776 ] 376977 -IS Flush_line [0 0 0 0 0 0 0 0 ] 0 - -SS Load [0 0 0 0 0 0 0 0 ] 0 -SS Ifetch [0 0 0 0 0 0 0 0 ] 0 -SS Store [0 0 0 0 0 0 0 0 ] 0 -SS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -SS L1_to_L2 [1116 874 1194 1064 767 881 901 1161 ] 7958 -SS Ack [2952 3061 3007 2990 3014 2995 3121 3154 ] 24294 -SS Shared_Ack [4 4 4 4 3 6 5 4 ] 34 -SS All_acks [1114 1096 1109 1107 1091 1156 1120 1180 ] 8973 -SS All_acks_no_sharers [1834 1892 1866 1872 1847 1846 1890 1911 ] 14958 -SS Flush_line [0 0 0 0 0 0 0 0 ] 0 - -OI Load [0 1 2 0 0 0 0 0 ] 3 -OI Ifetch [0 0 0 0 0 0 0 0 ] 0 -OI Store [0 0 0 0 0 0 0 0 ] 0 -OI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -OI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -OI Other_GETX [0 0 2 0 0 0 0 0 ] 2 -OI Other_GETS [1 0 0 1 0 0 0 1 ] 3 -OI Merged_GETS [0 0 0 0 0 0 1 0 ] 1 -OI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -OI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -OI Invalidate [0 0 0 0 0 0 0 0 ] 0 -OI Writeback_Ack [1085 1073 1027 1041 1020 1047 1077 1009 ] 8379 -OI Flush_line [0 0 0 0 0 0 0 0 ] 0 - -MI Load [10 11 14 12 12 8 7 12 ] 86 -MI Ifetch [0 0 0 0 0 0 0 0 ] 0 -MI Store [7 4 4 12 9 7 8 7 ] 58 -MI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -MI Other_GETX [25 32 30 25 31 29 29 17 ] 218 -MI Other_GETS [47 39 39 42 48 46 63 29 ] 353 -MI Merged_GETS [1 1 0 0 0 0 0 0 ] 2 -MI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -MI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -MI Invalidate [0 0 0 0 0 0 0 0 ] 0 -MI Writeback_Ack [71509 71917 71762 71899 71741 71488 72063 71314 ] 573693 -MI Flush_line [0 0 0 0 0 0 0 0 ] 0 - -II Load [0 0 0 0 0 0 0 0 ] 0 -II Ifetch [0 0 0 0 0 0 0 0 ] 0 -II Store [0 0 0 0 0 0 0 0 ] 0 -II L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -II L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -II Other_GETX [0 0 0 0 0 0 0 0 ] 0 -II Other_GETS [0 0 0 0 0 0 0 0 ] 0 -II Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -II NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -II Invalidate [0 0 0 0 0 0 0 0 ] 0 -II Writeback_Ack [25 32 32 25 31 29 29 17 ] 220 -II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -II Flush_line [0 0 0 0 0 0 0 0 ] 0 - -IT Load [0 0 1 0 0 0 0 2 ] 3 -IT Ifetch [0 0 0 0 0 0 0 0 ] 0 -IT Store [0 0 0 1 0 1 0 0 ] 2 -IT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IT L1_to_L2 [0 0 0 1 0 11 9 3 ] 24 -IT Complete_L2_to_L1 [3 0 1 2 0 4 2 3 ] 15 - -ST Load [0 1 0 0 0 1 0 3 ] 5 -ST Ifetch [0 0 0 0 0 0 0 0 ] 0 -ST Store [0 0 0 0 0 0 0 1 ] 1 -ST L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -ST L1_to_L2 [10 21 7 9 0 0 5 25 ] 77 -ST Complete_L2_to_L1 [2 5 4 1 0 2 3 6 ] 23 - -OT Load [0 0 0 0 0 0 0 2 ] 2 -OT Ifetch [0 0 0 0 0 0 0 0 ] 0 -OT Store [0 0 0 0 0 0 0 0 ] 0 -OT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -OT L1_to_L2 [0 0 0 6 0 0 0 0 ] 6 -OT Complete_L2_to_L1 [0 2 0 1 0 1 0 2 ] 6 - -MT Load [13 7 10 13 10 14 13 15 ] 95 -MT Ifetch [0 0 0 0 0 0 0 0 ] 0 -MT Store [6 9 9 9 9 7 5 2 ] 56 -MT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MT L1_to_L2 [179 117 164 171 115 155 80 166 ] 1147 -MT Complete_L2_to_L1 [49 40 60 51 41 55 37 40 ] 373 - -MMT Load [8 11 7 8 6 4 9 5 ] 58 -MMT Ifetch [0 0 0 0 0 0 0 0 ] 0 -MMT Store [4 3 4 2 5 3 5 2 ] 28 -MMT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MMT L1_to_L2 [86 139 85 97 90 91 78 92 ] 758 -MMT Complete_L2_to_L1 [21 25 34 24 25 27 27 21 ] 204 - -MI_F Load [0 0 0 0 0 0 0 0 ] 0 -MI_F Ifetch [0 0 0 0 0 0 0 0 ] 0 -MI_F Store [0 0 0 0 0 0 0 0 ] 0 -MI_F L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -MI_F Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -MI_F Flush_line [0 0 0 0 0 0 0 0 ] 0 - -MM_F Load [0 0 0 0 0 0 0 0 ] 0 -MM_F Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM_F Store [0 0 0 0 0 0 0 0 ] 0 -MM_F L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -MM_F Other_GETX [0 0 0 0 0 0 0 0 ] 0 -MM_F Other_GETS [0 0 0 0 0 0 0 0 ] 0 -MM_F Merged_GETS [0 0 0 0 0 0 0 0 ] 0 -MM_F Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -MM_F NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -MM_F Invalidate [0 0 0 0 0 0 0 0 ] 0 -MM_F Ack [0 0 0 0 0 0 0 0 ] 0 -MM_F All_acks [0 0 0 0 0 0 0 0 ] 0 -MM_F All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0 -MM_F Flush_line [0 0 0 0 0 0 0 0 ] 0 -MM_F Block_Ack [0 0 0 0 0 0 0 0 ] 0 - -IM_F Load [0 0 0 0 0 0 0 0 ] 0 -IM_F Ifetch [0 0 0 0 0 0 0 0 ] 0 -IM_F Store [0 0 0 0 0 0 0 0 ] 0 -IM_F L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IM_F L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -IM_F Other_GETX [0 0 0 0 0 0 0 0 ] 0 -IM_F Other_GETS [0 0 0 0 0 0 0 0 ] 0 -IM_F Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -IM_F NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -IM_F Invalidate [0 0 0 0 0 0 0 0 ] 0 -IM_F Ack [0 0 0 0 0 0 0 0 ] 0 -IM_F Data [0 0 0 0 0 0 0 0 ] 0 -IM_F Exclusive_Data [0 0 0 0 0 0 0 0 ] 0 -IM_F Flush_line [0 0 0 0 0 0 0 0 ] 0 - -ISM_F Load [0 0 0 0 0 0 0 0 ] 0 -ISM_F Ifetch [0 0 0 0 0 0 0 0 ] 0 -ISM_F Store [0 0 0 0 0 0 0 0 ] 0 -ISM_F L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -ISM_F L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -ISM_F Ack [0 0 0 0 0 0 0 0 ] 0 -ISM_F All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0 -ISM_F Flush_line [0 0 0 0 0 0 0 0 ] 0 - -SM_F Load [0 0 0 0 0 0 0 0 ] 0 -SM_F Ifetch [0 0 0 0 0 0 0 0 ] 0 -SM_F Store [0 0 0 0 0 0 0 0 ] 0 -SM_F L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -SM_F L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -SM_F Other_GETX [0 0 0 0 0 0 0 0 ] 0 -SM_F Other_GETS [0 0 0 0 0 0 0 0 ] 0 -SM_F Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -SM_F NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -SM_F Invalidate [0 0 0 0 0 0 0 0 ] 0 -SM_F Ack [0 0 0 0 0 0 0 0 ] 0 -SM_F Data [0 0 0 0 0 0 0 0 ] 0 -SM_F Exclusive_Data [0 0 0 0 0 0 0 0 ] 0 -SM_F Flush_line [0 0 0 0 0 0 0 0 ] 0 - -OM_F Load [0 0 0 0 0 0 0 0 ] 0 -OM_F Ifetch [0 0 0 0 0 0 0 0 ] 0 -OM_F Store [0 0 0 0 0 0 0 0 ] 0 -OM_F L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -OM_F L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -OM_F Other_GETX [0 0 0 0 0 0 0 0 ] 0 -OM_F Other_GETS [0 0 0 0 0 0 0 0 ] 0 -OM_F Merged_GETS [0 0 0 0 0 0 0 0 ] 0 -OM_F Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -OM_F NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -OM_F Invalidate [0 0 0 0 0 0 0 0 ] 0 -OM_F Ack [0 0 0 0 0 0 0 0 ] 0 -OM_F All_acks [0 0 0 0 0 0 0 0 ] 0 -OM_F All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0 -OM_F Flush_line [0 0 0 0 0 0 0 0 ] 0 - -MM_WF Load [0 0 0 0 0 0 0 0 ] 0 -MM_WF Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM_WF Store [0 0 0 0 0 0 0 0 ] 0 -MM_WF L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MM_WF L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -MM_WF Ack [0 0 0 0 0 0 0 0 ] 0 -MM_WF All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0 -MM_WF Flush_line [0 0 0 0 0 0 0 0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 811546 - memory_reads: 597507 - memory_writes: 214013 - memory_refreshes: 40249 - memory_total_request_delays: 49147842 - memory_delays_per_request: 60.5608 - memory_delays_in_input_queue: 408038 - memory_delays_behind_head_of_bank_queue: 19549348 - memory_delays_stalled_at_head_of_bank_queue: 29190456 - memory_stalls_for_bank_busy: 4395939 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 7180359 - memory_stalls_for_arbitration: 6011646 - memory_stalls_for_bus: 8156080 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 2068734 - memory_stalls_for_read_read_turnaround: 1377698 - accesses_per_bank: 25525 25047 25485 25568 25590 25517 25716 25410 25335 25484 25540 25414 25457 25303 25416 25361 25622 25433 25171 25194 25397 25498 25175 25106 25081 25088 24820 25599 25387 25331 25290 25186 - - --- Directory --- - - Event Counts - -GETX [220023 ] 220023 -GETS [406995 ] 406995 -PUT [585083 ] 585083 -Unblock [220 ] 220 -UnblockS [23931 ] 23931 -UnblockM [593445 ] 593445 -Writeback_Clean [8030 ] 8030 -Writeback_Dirty [349 ] 349 -Writeback_Exclusive_Clean [360015 ] 360015 -Writeback_Exclusive_Dirty [213674 ] 213674 -Pf_Replacement [0 ] 0 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -Memory_Data [597503 ] 597503 -Memory_Ack [214013 ] 214013 -Ack [0 ] 0 -Shared_Ack [0 ] 0 -Shared_Data [0 ] 0 -Data [0 ] 0 -Exclusive_Data [0 ] 0 -All_acks_and_shared_data [0 ] 0 -All_acks_and_owner_data [0 ] 0 -All_acks_and_data_no_sharers [0 ] 0 -All_Unblocks [439 ] 439 -GETF [0 ] 0 -PUTF [0 ] 0 - - - Transitions - -NX GETX [61 ] 61 -NX GETS [97 ] 97 -NX PUT [8595 ] 8595 -NX Pf_Replacement [0 ] 0 -NX DMA_READ [0 ] 0 -NX DMA_WRITE [0 ] 0 -NX GETF [0 ] 0 - -NO GETX [6880 ] 6880 -NO GETS [12400 ] 12400 -NO PUT [573697 ] 573697 -NO Pf_Replacement [0 ] 0 -NO DMA_READ [0 ] 0 -NO DMA_WRITE [0 ] 0 -NO GETF [0 ] 0 - -S GETX [0 ] 0 -S GETS [0 ] 0 -S PUT [0 ] 0 -S Pf_Replacement [0 ] 0 -S DMA_READ [0 ] 0 -S DMA_WRITE [0 ] 0 -S GETF [0 ] 0 - -O GETX [8316 ] 8316 -O GETS [15375 ] 15375 -O PUT [0 ] 0 -O Pf_Replacement [0 ] 0 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 -O GETF [0 ] 0 - -E GETX [201220 ] 201220 -E GETS [372612 ] 372612 -E PUT [0 ] 0 -E DMA_READ [0 ] 0 -E DMA_WRITE [0 ] 0 -E GETF [0 ] 0 - -O_R GETX [0 ] 0 -O_R GETS [0 ] 0 -O_R PUT [0 ] 0 -O_R Pf_Replacement [0 ] 0 -O_R DMA_READ [0 ] 0 -O_R DMA_WRITE [0 ] 0 -O_R Ack [0 ] 0 -O_R All_acks_and_data_no_sharers [0 ] 0 -O_R GETF [0 ] 0 - -S_R GETX [0 ] 0 -S_R GETS [0 ] 0 -S_R PUT [0 ] 0 -S_R Pf_Replacement [0 ] 0 -S_R DMA_READ [0 ] 0 -S_R DMA_WRITE [0 ] 0 -S_R Ack [0 ] 0 -S_R Data [0 ] 0 -S_R All_acks_and_data_no_sharers [0 ] 0 -S_R GETF [0 ] 0 - -NO_R GETX [0 ] 0 -NO_R GETS [0 ] 0 -NO_R PUT [0 ] 0 -NO_R Pf_Replacement [0 ] 0 -NO_R DMA_READ [0 ] 0 -NO_R DMA_WRITE [0 ] 0 -NO_R Ack [0 ] 0 -NO_R Data [0 ] 0 -NO_R Exclusive_Data [0 ] 0 -NO_R All_acks_and_data_no_sharers [0 ] 0 -NO_R GETF [0 ] 0 - -NO_B GETX [205 ] 205 -NO_B GETS [439 ] 439 -NO_B PUT [2778 ] 2778 -NO_B UnblockS [8092 ] 8092 -NO_B UnblockM [592827 ] 592827 -NO_B Pf_Replacement [0 ] 0 -NO_B DMA_READ [0 ] 0 -NO_B DMA_WRITE [0 ] 0 -NO_B GETF [0 ] 0 - -NO_B_X GETX [0 ] 0 -NO_B_X GETS [0 ] 0 -NO_B_X PUT [0 ] 0 -NO_B_X UnblockS [4 ] 4 -NO_B_X UnblockM [201 ] 201 -NO_B_X Pf_Replacement [0 ] 0 -NO_B_X DMA_READ [0 ] 0 -NO_B_X DMA_WRITE [0 ] 0 -NO_B_X GETF [0 ] 0 - -NO_B_S GETX [0 ] 0 -NO_B_S GETS [0 ] 0 -NO_B_S PUT [2 ] 2 -NO_B_S UnblockS [22 ] 22 -NO_B_S UnblockM [417 ] 417 -NO_B_S Pf_Replacement [0 ] 0 -NO_B_S DMA_READ [0 ] 0 -NO_B_S DMA_WRITE [0 ] 0 -NO_B_S GETF [0 ] 0 - -NO_B_S_W GETX [1 ] 1 -NO_B_S_W GETS [1 ] 1 -NO_B_S_W PUT [7 ] 7 -NO_B_S_W UnblockS [439 ] 439 -NO_B_S_W Pf_Replacement [0 ] 0 -NO_B_S_W DMA_READ [0 ] 0 -NO_B_S_W DMA_WRITE [0 ] 0 -NO_B_S_W All_Unblocks [439 ] 439 -NO_B_S_W GETF [0 ] 0 - -O_B GETX [9 ] 9 -O_B GETS [6 ] 6 -O_B PUT [0 ] 0 -O_B UnblockS [15374 ] 15374 -O_B UnblockM [0 ] 0 -O_B Pf_Replacement [0 ] 0 -O_B DMA_READ [0 ] 0 -O_B DMA_WRITE [0 ] 0 -O_B GETF [0 ] 0 - -NO_B_W GETX [1957 ] 1957 -NO_B_W GETS [3492 ] 3492 -NO_B_W PUT [0 ] 0 -NO_B_W UnblockS [0 ] 0 -NO_B_W UnblockM [0 ] 0 -NO_B_W Pf_Replacement [0 ] 0 -NO_B_W DMA_READ [0 ] 0 -NO_B_W DMA_WRITE [0 ] 0 -NO_B_W Memory_Data [582129 ] 582129 -NO_B_W GETF [0 ] 0 - -O_B_W GETX [38 ] 38 -O_B_W GETS [103 ] 103 -O_B_W PUT [0 ] 0 -O_B_W UnblockS [0 ] 0 -O_B_W Pf_Replacement [0 ] 0 -O_B_W DMA_READ [0 ] 0 -O_B_W DMA_WRITE [0 ] 0 -O_B_W Memory_Data [15374 ] 15374 -O_B_W GETF [0 ] 0 - -NO_W GETX [0 ] 0 -NO_W GETS [0 ] 0 -NO_W PUT [0 ] 0 -NO_W Pf_Replacement [0 ] 0 -NO_W DMA_READ [0 ] 0 -NO_W DMA_WRITE [0 ] 0 -NO_W Memory_Data [0 ] 0 -NO_W GETF [0 ] 0 - -O_W GETX [0 ] 0 -O_W GETS [0 ] 0 -O_W PUT [0 ] 0 -O_W Pf_Replacement [0 ] 0 -O_W DMA_READ [0 ] 0 -O_W DMA_WRITE [0 ] 0 -O_W Memory_Data [0 ] 0 -O_W GETF [0 ] 0 - -NO_DW_B_W GETX [0 ] 0 -NO_DW_B_W GETS [0 ] 0 -NO_DW_B_W PUT [0 ] 0 -NO_DW_B_W Pf_Replacement [0 ] 0 -NO_DW_B_W DMA_READ [0 ] 0 -NO_DW_B_W DMA_WRITE [0 ] 0 -NO_DW_B_W Ack [0 ] 0 -NO_DW_B_W Data [0 ] 0 -NO_DW_B_W Exclusive_Data [0 ] 0 -NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 -NO_DW_B_W GETF [0 ] 0 - -NO_DR_B_W GETX [0 ] 0 -NO_DR_B_W GETS [0 ] 0 -NO_DR_B_W PUT [0 ] 0 -NO_DR_B_W Pf_Replacement [0 ] 0 -NO_DR_B_W DMA_READ [0 ] 0 -NO_DR_B_W DMA_WRITE [0 ] 0 -NO_DR_B_W Memory_Data [0 ] 0 -NO_DR_B_W Ack [0 ] 0 -NO_DR_B_W Shared_Ack [0 ] 0 -NO_DR_B_W Shared_Data [0 ] 0 -NO_DR_B_W Data [0 ] 0 -NO_DR_B_W Exclusive_Data [0 ] 0 -NO_DR_B_W GETF [0 ] 0 - -NO_DR_B_D GETX [0 ] 0 -NO_DR_B_D GETS [0 ] 0 -NO_DR_B_D PUT [0 ] 0 -NO_DR_B_D Pf_Replacement [0 ] 0 -NO_DR_B_D DMA_READ [0 ] 0 -NO_DR_B_D DMA_WRITE [0 ] 0 -NO_DR_B_D Ack [0 ] 0 -NO_DR_B_D Shared_Ack [0 ] 0 -NO_DR_B_D Shared_Data [0 ] 0 -NO_DR_B_D Data [0 ] 0 -NO_DR_B_D Exclusive_Data [0 ] 0 -NO_DR_B_D All_acks_and_shared_data [0 ] 0 -NO_DR_B_D All_acks_and_owner_data [0 ] 0 -NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 -NO_DR_B_D GETF [0 ] 0 - -NO_DR_B GETX [0 ] 0 -NO_DR_B GETS [0 ] 0 -NO_DR_B PUT [0 ] 0 -NO_DR_B Pf_Replacement [0 ] 0 -NO_DR_B DMA_READ [0 ] 0 -NO_DR_B DMA_WRITE [0 ] 0 -NO_DR_B Ack [0 ] 0 -NO_DR_B Shared_Ack [0 ] 0 -NO_DR_B Shared_Data [0 ] 0 -NO_DR_B Data [0 ] 0 -NO_DR_B Exclusive_Data [0 ] 0 -NO_DR_B All_acks_and_shared_data [0 ] 0 -NO_DR_B All_acks_and_owner_data [0 ] 0 -NO_DR_B All_acks_and_data_no_sharers [0 ] 0 -NO_DR_B GETF [0 ] 0 - -NO_DW_W GETX [0 ] 0 -NO_DW_W GETS [0 ] 0 -NO_DW_W PUT [0 ] 0 -NO_DW_W Pf_Replacement [0 ] 0 -NO_DW_W DMA_READ [0 ] 0 -NO_DW_W DMA_WRITE [0 ] 0 -NO_DW_W Memory_Ack [0 ] 0 -NO_DW_W GETF [0 ] 0 - -O_DR_B_W GETX [0 ] 0 -O_DR_B_W GETS [0 ] 0 -O_DR_B_W PUT [0 ] 0 -O_DR_B_W Pf_Replacement [0 ] 0 -O_DR_B_W DMA_READ [0 ] 0 -O_DR_B_W DMA_WRITE [0 ] 0 -O_DR_B_W Memory_Data [0 ] 0 -O_DR_B_W Ack [0 ] 0 -O_DR_B_W Shared_Ack [0 ] 0 -O_DR_B_W GETF [0 ] 0 - -O_DR_B GETX [0 ] 0 -O_DR_B GETS [0 ] 0 -O_DR_B PUT [0 ] 0 -O_DR_B Pf_Replacement [0 ] 0 -O_DR_B DMA_READ [0 ] 0 -O_DR_B DMA_WRITE [0 ] 0 -O_DR_B Ack [0 ] 0 -O_DR_B Shared_Ack [0 ] 0 -O_DR_B All_acks_and_owner_data [0 ] 0 -O_DR_B All_acks_and_data_no_sharers [0 ] 0 -O_DR_B GETF [0 ] 0 - -WB GETX [295 ] 295 -WB GETS [514 ] 514 -WB PUT [4 ] 4 -WB Unblock [220 ] 220 -WB Writeback_Clean [8030 ] 8030 -WB Writeback_Dirty [349 ] 349 -WB Writeback_Exclusive_Clean [360015 ] 360015 -WB Writeback_Exclusive_Dirty [213674 ] 213674 -WB Pf_Replacement [0 ] 0 -WB DMA_READ [0 ] 0 -WB DMA_WRITE [0 ] 0 -WB GETF [0 ] 0 - -WB_O_W GETX [0 ] 0 -WB_O_W GETS [3 ] 3 -WB_O_W PUT [0 ] 0 -WB_O_W Pf_Replacement [0 ] 0 -WB_O_W DMA_READ [0 ] 0 -WB_O_W DMA_WRITE [0 ] 0 -WB_O_W Memory_Ack [348 ] 348 -WB_O_W GETF [0 ] 0 - -WB_E_W GETX [1041 ] 1041 -WB_E_W GETS [1953 ] 1953 -WB_E_W PUT [0 ] 0 -WB_E_W Pf_Replacement [0 ] 0 -WB_E_W DMA_READ [0 ] 0 -WB_E_W DMA_WRITE [0 ] 0 -WB_E_W Memory_Ack [213665 ] 213665 -WB_E_W GETF [0 ] 0 - -NO_F GETX [0 ] 0 -NO_F GETS [0 ] 0 -NO_F PUT [0 ] 0 -NO_F UnblockM [0 ] 0 -NO_F Pf_Replacement [0 ] 0 -NO_F GETF [0 ] 0 -NO_F PUTF [0 ] 0 - -NO_F_W GETX [0 ] 0 -NO_F_W GETS [0 ] 0 -NO_F_W PUT [0 ] 0 -NO_F_W Pf_Replacement [0 ] 0 -NO_F_W DMA_READ [0 ] 0 -NO_F_W DMA_WRITE [0 ] 0 -NO_F_W Memory_Data [0 ] 0 -NO_F_W GETF [0 ] 0 - |