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-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini8
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats33
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout8
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt6
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini114
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest/simout6
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt1938
7 files changed, 1235 insertions, 878 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
index f1d5fb57f..dacf2f87f 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
@@ -41,6 +41,7 @@ percent_source_unaligned=50
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[0]
test=system.l1_cntrl0.sequencer.port[0]
@@ -58,6 +59,7 @@ percent_source_unaligned=50
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[1]
test=system.l1_cntrl1.sequencer.port[0]
@@ -75,6 +77,7 @@ percent_source_unaligned=50
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[2]
test=system.l1_cntrl2.sequencer.port[0]
@@ -92,6 +95,7 @@ percent_source_unaligned=50
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[3]
test=system.l1_cntrl3.sequencer.port[0]
@@ -109,6 +113,7 @@ percent_source_unaligned=50
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[4]
test=system.l1_cntrl4.sequencer.port[0]
@@ -126,6 +131,7 @@ percent_source_unaligned=50
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[5]
test=system.l1_cntrl5.sequencer.port[0]
@@ -143,6 +149,7 @@ percent_source_unaligned=50
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[6]
test=system.l1_cntrl6.sequencer.port[0]
@@ -160,6 +167,7 @@ percent_source_unaligned=50
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[7]
test=system.l1_cntrl7.sequencer.port[0]
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
index 64437a4e3..e8a51599b 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,26 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Feb/12/2012 12:58:05
+Real time: Feb/12/2012 15:36:31
Profiler Stats
--------------
-Elapsed_time_in_seconds: 110
-Elapsed_time_in_minutes: 1.83333
-Elapsed_time_in_hours: 0.0305556
-Elapsed_time_in_days: 0.00127315
+Elapsed_time_in_seconds: 190
+Elapsed_time_in_minutes: 3.16667
+Elapsed_time_in_hours: 0.0527778
+Elapsed_time_in_days: 0.00219907
-Virtual_time_in_seconds: 110.38
-Virtual_time_in_minutes: 1.83967
-Virtual_time_in_hours: 0.0306611
-Virtual_time_in_days: 0.00127755
+Virtual_time_in_seconds: 189.25
+Virtual_time_in_minutes: 3.15417
+Virtual_time_in_hours: 0.0525694
+Virtual_time_in_days: 0.00219039
Ruby_current_time: 22495354
Ruby_start_time: 0
Ruby_cycles: 22495354
-mbytes_resident: 41.8164
-mbytes_total: 371.512
-resident_ratio: 0.112578
+mbytes_resident: 0
+mbytes_total: 0
ruby_cycles_executed: [ 22495355 22495355 22495355 22495355 22495355 22495355 22495355 22495355 ]
@@ -116,13 +115,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 3280807 average: 0.508064 |
Resource Usage
--------------
page_size: 4096
-user_time: 110
+user_time: 188
system_time: 0
-page_reclaims: 11719
-page_faults: 18
+page_reclaims: 12571
+page_faults: 0
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 1
+block_outputs: 44
Network Stats
-------------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
index 1577dfd47..f74c8ffd6 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 12 2012 12:56:01
-gem5 started Feb 12 2012 12:56:15
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Feb 12 2012 15:33:08
+gem5 started Feb 12 2012 15:33:21
+gem5 executing on Alis-MacBook-Pro.local
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
index 04704faf4..1bc6a2ebb 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
@@ -4,9 +4,9 @@ sim_seconds 0.022495 # Nu
sim_ticks 22495354 # Number of ticks simulated
final_tick 22495354 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 204320 # Simulator tick rate (ticks/s)
-host_mem_usage 380432 # Number of bytes of host memory used
-host_seconds 110.10 # Real time elapsed on the host
+host_tick_rate 118487 # Simulator tick rate (ticks/s)
+host_mem_usage 398520 # Number of bytes of host memory used
+host_seconds 189.86 # Real time elapsed on the host
system.physmem.bytes_read 0 # Number of bytes read from this memory
system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
index ac8d82ede..1dd8fc1b6 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem system.funcmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -35,6 +42,7 @@ percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[0]
test=system.cpu0.l1c.cpu_side
@@ -50,20 +58,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -85,6 +86,7 @@ percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[1]
test=system.cpu1.l1c.cpu_side
@@ -100,20 +102,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -135,6 +130,7 @@ percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[2]
test=system.cpu2.l1c.cpu_side
@@ -150,20 +146,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -185,6 +174,7 @@ percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[3]
test=system.cpu3.l1c.cpu_side
@@ -200,20 +190,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -235,6 +218,7 @@ percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[4]
test=system.cpu4.l1c.cpu_side
@@ -250,20 +234,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -285,6 +262,7 @@ percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[5]
test=system.cpu5.l1c.cpu_side
@@ -300,20 +278,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -335,6 +306,7 @@ percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[6]
test=system.cpu6.l1c.cpu_side
@@ -350,20 +322,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -385,6 +350,7 @@ percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[7]
test=system.cpu7.l1c.cpu_side
@@ -400,20 +366,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@@ -442,20 +401,13 @@ is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=8
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=65536
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
index c76c33576..c89b62243 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:28
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:36
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 263488655 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
index 82bd7a1b0..8183eaaf7 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -4,9 +4,9 @@ sim_seconds 0.000263 # Nu
sim_ticks 263488655 # Number of ticks simulated
final_tick 263488655 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 1768401 # Simulator tick rate (ticks/s)
-host_mem_usage 335780 # Number of bytes of host memory used
-host_seconds 149.00 # Real time elapsed on the host
+host_tick_rate 1938715 # Simulator tick rate (ticks/s)
+host_mem_usage 338552 # Number of bytes of host memory used
+host_seconds 135.91 # Real time elapsed on the host
system.physmem.bytes_read 4057580 # Number of bytes read from this memory
system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2644316 # Number of bytes written to this memory
@@ -28,258 +28,289 @@ system.l2c.total_refs 139150 # To
system.l2c.sampled_refs 77525 # Sample count of references to valid blocks.
system.l2c.avg_refs 1.794905 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 24.077198 # Average occupied blocks per context
-system.l2c.occ_blocks::1 23.899612 # Average occupied blocks per context
-system.l2c.occ_blocks::2 23.566419 # Average occupied blocks per context
-system.l2c.occ_blocks::3 24.461210 # Average occupied blocks per context
-system.l2c.occ_blocks::4 24.025606 # Average occupied blocks per context
-system.l2c.occ_blocks::5 23.167376 # Average occupied blocks per context
-system.l2c.occ_blocks::6 23.494200 # Average occupied blocks per context
-system.l2c.occ_blocks::7 23.002994 # Average occupied blocks per context
-system.l2c.occ_blocks::8 468.019905 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.023513 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.023339 # Average percentage of cache occupancy
-system.l2c.occ_percent::2 0.023014 # Average percentage of cache occupancy
-system.l2c.occ_percent::3 0.023888 # Average percentage of cache occupancy
-system.l2c.occ_percent::4 0.023463 # Average percentage of cache occupancy
-system.l2c.occ_percent::5 0.022624 # Average percentage of cache occupancy
-system.l2c.occ_percent::6 0.022944 # Average percentage of cache occupancy
-system.l2c.occ_percent::7 0.022464 # Average percentage of cache occupancy
-system.l2c.occ_percent::8 0.457051 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 10466 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 10370 # number of ReadReq hits
-system.l2c.ReadReq_hits::2 10579 # number of ReadReq hits
-system.l2c.ReadReq_hits::3 10469 # number of ReadReq hits
-system.l2c.ReadReq_hits::4 10390 # number of ReadReq hits
-system.l2c.ReadReq_hits::5 10384 # number of ReadReq hits
-system.l2c.ReadReq_hits::6 10590 # number of ReadReq hits
-system.l2c.ReadReq_hits::7 10463 # number of ReadReq hits
+system.l2c.occ_blocks::writebacks 468.019905 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0 24.077198 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1 23.899612 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2 23.566419 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3 24.461210 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu4 24.025606 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu5 23.167376 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu6 23.494200 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu7 23.002994 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.457051 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0 0.023513 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1 0.023339 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2 0.023014 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu3 0.023888 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu4 0.023463 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu5 0.022624 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu6 0.022944 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu7 0.022464 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.642299 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0 10466 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1 10370 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2 10579 # number of ReadReq hits
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system.l2c.overall_accesses::total 192669 # number of overall (read+write) accesses
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-system.l2c.UpgradeReq_avg_miss_latency::1 163584.854819 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2 161662.707483 # average UpgradeReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::4 164822.571248 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::5 160767.895449 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::6 160965.885468 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::7 165239.316056 # average UpgradeReq miss latency
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system.l2c.blocked_cycles::no_mshrs 97509 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked
@@ -288,119 +319,327 @@ system.l2c.avg_blocked_cycles::no_mshrs 6964.928571 # av
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
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-system.l2c.UpgradeReq_mshr_misses 12838 # number of UpgradeReq MSHR misses
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-system.l2c.demand_mshr_misses 84625 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 84625 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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-system.l2c.ReadReq_mshr_uncacheable_latency 3189139994 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency 1723903484 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 4913043478 # number of overall MSHR uncacheable cycles
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system.cpu0.l1c.blocked::no_mshrs 69110 # number of cycles access was blocked
@@ -409,72 +648,94 @@ system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3673.059398
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+system.cpu1.l1c.overall_misses::total 60385 # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1 1301760811 # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total 1301760811 # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1 1014297005 # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total 1014297005 # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency::cpu1 2316057816 # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_latency::total 2316057816 # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1 2316057816 # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total 2316057816 # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1 44539 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total 44539 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1 24341 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total 24341 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1 68880 # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total 68880 # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1 68880 # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total 68880 # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.833202 # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956206 # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1 0.876670 # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1 0.876670 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 35078.437375 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 43578.818690 # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 38354.853291 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 38354.853291 # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs 253325402 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs 68822 # number of cycles access was blocked
@@ -483,72 +744,94 @@ system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3680.878237
system.cpu1.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks 11809 # number of writebacks
-system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.l1c.ReadReq_mshr_misses 37110 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses 23275 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses 60385 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses 60385 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency 1264508347 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency 990933889 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency 2255442236 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency 2255442236 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 877119159 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 578327433 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency 1455446592 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate 0.833202 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate 0.956206 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate 0.876670 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate 0.876670 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34074.598410 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 42575.032825 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency 37351.034793 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency 37351.034793 # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu1.l1c.writebacks::total 11809 # number of writebacks
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+system.cpu1.l1c.WriteReq_mshr_misses::total 23275 # number of WriteReq MSHR misses
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+system.cpu1.l1c.demand_mshr_misses::total 60385 # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1 60385 # number of overall MSHR misses
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+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 877119159 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 578327433 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.833202 # mshr miss rate for ReadReq accesses
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+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 34074.598410 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 42575.032825 # average WriteReq mshr miss latency
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+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.num_reads 99149 # number of read accesses completed
system.cpu2.num_writes 53185 # number of write accesses completed
system.cpu2.num_copies 0 # number of copy accesses completed
system.cpu2.l1c.replacements 27627 # number of replacements
-system.cpu2.l1c.tagsinuse 84.373112 # Cycle average of tags in use
+system.cpu2.l1c.tagsinuse 345.430231 # Cycle average of tags in use
system.cpu2.l1c.total_refs 11519 # Total number of references to valid blocks.
system.cpu2.l1c.sampled_refs 27982 # Sample count of references to valid blocks.
system.cpu2.l1c.avg_refs 0.411657 # Average number of references to valid blocks.
system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.occ_blocks::0 345.430231 # Average occupied blocks per context
-system.cpu2.l1c.occ_blocks::1 -261.057119 # Average occupied blocks per context
-system.cpu2.l1c.occ_percent::0 0.674668 # Average percentage of cache occupancy
-system.cpu2.l1c.occ_percent::1 -0.509877 # Average percentage of cache occupancy
-system.cpu2.l1c.ReadReq_hits 7576 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits 1069 # number of WriteReq hits
-system.cpu2.l1c.demand_hits 8645 # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits 8645 # number of overall hits
-system.cpu2.l1c.ReadReq_misses 37144 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses 22885 # number of WriteReq misses
-system.cpu2.l1c.demand_misses 60029 # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses 60029 # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency 1302790562 # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency 991654869 # number of WriteReq miss cycles
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-system.cpu2.l1c.ReadReq_accesses 44720 # number of ReadReq accesses(hits+misses)
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-system.cpu2.l1c.ReadReq_miss_rate 0.830590 # miss rate for ReadReq accesses
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-system.cpu2.l1c.demand_miss_rate 0.874115 # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate 0.874115 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency 35074.051314 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency 43332.089535 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency 38222.283080 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency 38222.283080 # average overall miss latency
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+system.cpu2.l1c.demand_accesses::total 68674 # number of demand (read+write) accesses
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+system.cpu2.l1c.overall_accesses::total 68674 # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.830590 # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955373 # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2 0.874115 # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2 0.874115 # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 35074.051314 # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 43332.089535 # average WriteReq miss latency
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+system.cpu2.l1c.overall_avg_miss_latency::cpu2 38222.283080 # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs 254303447 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs 68698 # number of cycles access was blocked
@@ -557,72 +840,94 @@ system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3701.759105
system.cpu2.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks 11784 # number of writebacks
-system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu2.l1c.ReadReq_mshr_misses 37144 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses 22885 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses 60029 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses 60029 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency 1265501937 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency 968684322 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency 2234186259 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency 2234186259 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 900513056 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 566349170 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency 1466862226 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate 0.830590 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate 0.955373 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate 0.874115 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate 0.874115 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34070.157684 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 42328.351409 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency 37218.448733 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency 37218.448733 # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu2.l1c.writebacks::writebacks 11784 # number of writebacks
+system.cpu2.l1c.writebacks::total 11784 # number of writebacks
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+system.cpu2.l1c.ReadReq_mshr_misses::total 37144 # number of ReadReq MSHR misses
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+system.cpu2.l1c.demand_mshr_misses::total 60029 # number of demand (read+write) MSHR misses
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+system.cpu2.l1c.overall_mshr_misses::total 60029 # number of overall MSHR misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1265501937 # number of ReadReq MSHR miss cycles
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+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 968684322 # number of WriteReq MSHR miss cycles
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+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 566349170 # number of WriteReq MSHR uncacheable cycles
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+system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1466862226 # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.830590 # mshr miss rate for ReadReq accesses
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+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 34070.157684 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 42328.351409 # average WriteReq mshr miss latency
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system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu3.l1c.blocked::no_mshrs 68939 # number of cycles access was blocked
@@ -631,72 +936,94 @@ system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3691.127910
system.cpu3.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu4.l1c.blocked_cycles::no_mshrs 254136532 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs 68868 # number of cycles access was blocked
@@ -705,72 +1032,94 @@ system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3690.197653
system.cpu4.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu5.l1c.blocked_cycles::no_mshrs 253381114 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs 68969 # number of cycles access was blocked
@@ -779,72 +1128,94 @@ system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3673.840624
system.cpu5.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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+system.cpu6.l1c.overall_hits::total 8662 # number of overall hits
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+system.cpu6.l1c.overall_misses::total 60251 # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6 1299799162 # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total 1299799162 # number of ReadReq miss cycles
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+system.cpu6.l1c.WriteReq_miss_latency::total 1015775810 # number of WriteReq miss cycles
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+system.cpu6.l1c.demand_miss_latency::total 2315574972 # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6 2315574972 # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total 2315574972 # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6 44652 # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total 44652 # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6 24261 # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total 24261 # number of WriteReq accesses(hits+misses)
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+system.cpu6.l1c.demand_accesses::total 68913 # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6 68913 # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total 68913 # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.831071 # miss rate for ReadReq accesses
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+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 35026.520844 # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 43893.173019 # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 38432.141740 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 38432.141740 # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs 253794713 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs 68612 # number of cycles access was blocked
@@ -853,72 +1224,94 @@ system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3698.984332
system.cpu6.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.writebacks 11849 # number of writebacks
-system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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-system.cpu6.l1c.ReadReq_mshr_misses 37109 # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses 23142 # number of WriteReq MSHR misses
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-system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency 1262548698 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency 992541214 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency 2255089912 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency 2255089912 # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 877981455 # number of ReadReq MSHR uncacheable cycles
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-system.cpu6.l1c.overall_mshr_uncacheable_latency 1452670464 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate 0.831071 # mshr miss rate for ReadReq accesses
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-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 34022.708723 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 42889.171809 # average WriteReq mshr miss latency
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-system.cpu6.l1c.overall_avg_mshr_miss_latency 37428.256992 # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu7.num_reads 99694 # number of read accesses completed
system.cpu7.num_writes 53501 # number of write accesses completed
system.cpu7.num_copies 0 # number of copy accesses completed
system.cpu7.l1c.replacements 27727 # number of replacements
-system.cpu7.l1c.tagsinuse 84.250612 # Cycle average of tags in use
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system.cpu7.l1c.total_refs 11534 # Total number of references to valid blocks.
system.cpu7.l1c.sampled_refs 28062 # Sample count of references to valid blocks.
system.cpu7.l1c.avg_refs 0.411018 # Average number of references to valid blocks.
system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.occ_blocks::0 346.094259 # Average occupied blocks per context
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+system.cpu7.l1c.overall_avg_miss_latency::cpu7 38046.102147 # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs 254008986 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs 69036 # number of cycles access was blocked
@@ -927,34 +1320,41 @@ system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3679.369981
system.cpu7.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu7.l1c.overall_mshr_misses 60276 # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency 1249829653 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency 982928032 # number of WriteReq MSHR miss cycles
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-system.cpu7.l1c.overall_mshr_miss_latency 2232757685 # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 901961636 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 558194703 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency 1460156339 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830316 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate 0.954152 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate 0.873818 # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate 0.873818 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 33638.262764 # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 42512.349466 # average WriteReq mshr miss latency
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-system.cpu7.l1c.overall_avg_mshr_miss_latency 37042.233808 # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
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+system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1460156339 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.830316 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954152 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 33638.262764 # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 42512.349466 # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------