diff options
Diffstat (limited to 'tests/quick/se/50.memtest/ref/alpha')
4 files changed, 1504 insertions, 1502 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini index 120840f6d..1f567a1b9 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini @@ -16,7 +16,7 @@ kernel= load_addr_mask=1099511627775 mem_mode=timing mem_ranges= -memories=system.physmem system.funcmem +memories=system.funcmem system.physmem num_work_ids=16 readfile= symbolfile= @@ -415,6 +415,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=16 master=system.physmem.port @@ -438,6 +439,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=16 master=system.l2c.cpu_side diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr index ac8f30c3e..014cde607 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr @@ -1,74 +1,74 @@ -system.cpu4: completed 10000 read, 5213 write accesses @76807500 -system.cpu7: completed 10000 read, 5302 write accesses @79251000 -system.cpu3: completed 10000 read, 5351 write accesses @81062000 -system.cpu5: completed 10000 read, 5541 write accesses @82066500 -system.cpu1: completed 10000 read, 5479 write accesses @82140500 -system.cpu2: completed 10000 read, 5270 write accesses @82209500 -system.cpu6: completed 10000 read, 5352 write accesses @82224000 -system.cpu0: completed 10000 read, 5437 write accesses @83502000 -system.cpu4: completed 20000 read, 10638 write accesses @152852500 -system.cpu7: completed 20000 read, 10671 write accesses @153245500 -system.cpu5: completed 20000 read, 10802 write accesses @155921500 -system.cpu1: completed 20000 read, 10780 write accesses @157898500 -system.cpu3: completed 20000 read, 10762 write accesses @158207000 -system.cpu2: completed 20000 read, 10562 write accesses @158441500 -system.cpu6: completed 20000 read, 10817 write accesses @160812000 -system.cpu0: completed 20000 read, 10942 write accesses @162138000 -system.cpu4: completed 30000 read, 15885 write accesses @226882500 -system.cpu7: completed 30000 read, 16162 write accesses @230488000 -system.cpu1: completed 30000 read, 15996 write accesses @231220000 -system.cpu5: completed 30000 read, 16227 write accesses @232272500 -system.cpu3: completed 30000 read, 16181 write accesses @234012000 -system.cpu6: completed 30000 read, 16285 write accesses @236458500 -system.cpu2: completed 30000 read, 16117 write accesses @236552000 -system.cpu0: completed 30000 read, 16426 write accesses @240306500 -system.cpu4: completed 40000 read, 21151 write accesses @301825500 -system.cpu7: completed 40000 read, 21649 write accesses @305825500 -system.cpu1: completed 40000 read, 21293 write accesses @308437500 -system.cpu3: completed 40000 read, 21436 write accesses @308497500 -system.cpu5: completed 40000 read, 21614 write accesses @310554000 -system.cpu2: completed 40000 read, 21323 write accesses @312243500 -system.cpu6: completed 40000 read, 21541 write accesses @312536000 -system.cpu0: completed 40000 read, 21919 write accesses @320331000 -system.cpu4: completed 50000 read, 26446 write accesses @376676500 -system.cpu7: completed 50000 read, 26971 write accesses @382643500 -system.cpu1: completed 50000 read, 26742 write accesses @382692500 -system.cpu3: completed 50000 read, 26868 write accesses @383729000 -system.cpu5: completed 50000 read, 26982 write accesses @388892000 -system.cpu2: completed 50000 read, 26690 write accesses @389746500 -system.cpu6: completed 50000 read, 26890 write accesses @390639500 -system.cpu0: completed 50000 read, 27239 write accesses @394395001 -system.cpu4: completed 60000 read, 31859 write accesses @454814000 -system.cpu3: completed 60000 read, 32157 write accesses @455574000 -system.cpu1: completed 60000 read, 32039 write accesses @458833000 -system.cpu7: completed 60000 read, 32494 write accesses @460248000 -system.cpu2: completed 60000 read, 32094 write accesses @465749500 -system.cpu5: completed 60000 read, 32378 write accesses @466634000 -system.cpu6: completed 60000 read, 32333 write accesses @468161500 -system.cpu0: completed 60000 read, 32569 write accesses @469644500 -system.cpu3: completed 70000 read, 37524 write accesses @531095000 -system.cpu4: completed 70000 read, 37387 write accesses @531724000 -system.cpu1: completed 70000 read, 37455 write accesses @534864500 -system.cpu2: completed 70000 read, 37386 write accesses @539742500 -system.cpu7: completed 70000 read, 38025 write accesses @540171500 -system.cpu5: completed 70000 read, 37779 write accesses @540661000 -system.cpu0: completed 70000 read, 37912 write accesses @543002000 -system.cpu6: completed 70000 read, 37876 write accesses @544926000 -system.cpu4: completed 80000 read, 42765 write accesses @607648000 -system.cpu3: completed 80000 read, 42947 write accesses @608627500 -system.cpu1: completed 80000 read, 42804 write accesses @612176500 -system.cpu5: completed 80000 read, 43215 write accesses @614679500 -system.cpu2: completed 80000 read, 42837 write accesses @616130500 -system.cpu7: completed 80000 read, 43372 write accesses @618251000 -system.cpu0: completed 80000 read, 43388 write accesses @620992000 -system.cpu6: completed 80000 read, 43420 write accesses @622851000 -system.cpu4: completed 90000 read, 48066 write accesses @681361000 -system.cpu3: completed 90000 read, 48251 write accesses @683201500 -system.cpu1: completed 90000 read, 48377 write accesses @690035500 -system.cpu5: completed 90000 read, 48546 write accesses @692142000 -system.cpu2: completed 90000 read, 48240 write accesses @693946000 -system.cpu7: completed 90000 read, 48816 write accesses @696757000 -system.cpu0: completed 90000 read, 48758 write accesses @697163500 -system.cpu6: completed 90000 read, 48649 write accesses @698059000 -system.cpu4: completed 100000 read, 53418 write accesses @758619000 +system.cpu6: completed 10000 read, 5435 write accesses @79021500 +system.cpu0: completed 10000 read, 5363 write accesses @79194500 +system.cpu7: completed 10000 read, 5392 write accesses @79770500 +system.cpu2: completed 10000 read, 5375 write accesses @80689500 +system.cpu1: completed 10000 read, 5373 write accesses @81623500 +system.cpu4: completed 10000 read, 5458 write accesses @81916000 +system.cpu5: completed 10000 read, 5507 write accesses @81975000 +system.cpu3: completed 10000 read, 5421 write accesses @82381000 +system.cpu2: completed 20000 read, 10678 write accesses @153864500 +system.cpu0: completed 20000 read, 10854 write accesses @154789000 +system.cpu7: completed 20000 read, 10817 write accesses @154953500 +system.cpu1: completed 20000 read, 10781 write accesses @155855500 +system.cpu3: completed 20000 read, 10799 write accesses @157033000 +system.cpu4: completed 20000 read, 10854 write accesses @157158000 +system.cpu6: completed 20000 read, 10878 write accesses @157795000 +system.cpu5: completed 20000 read, 10963 write accesses @159866500 +system.cpu0: completed 30000 read, 16180 write accesses @228385000 +system.cpu2: completed 30000 read, 15995 write accesses @229109500 +system.cpu7: completed 30000 read, 16232 write accesses @231170000 +system.cpu1: completed 30000 read, 16165 write accesses @231658500 +system.cpu4: completed 30000 read, 16252 write accesses @232783000 +system.cpu6: completed 30000 read, 16228 write accesses @233712000 +system.cpu3: completed 30000 read, 16226 write accesses @236523000 +system.cpu5: completed 30000 read, 16456 write accesses @239602000 +system.cpu0: completed 40000 read, 21598 write accesses @305262000 +system.cpu2: completed 40000 read, 21332 write accesses @306571000 +system.cpu1: completed 40000 read, 21599 write accesses @307778500 +system.cpu4: completed 40000 read, 21599 write accesses @307971000 +system.cpu7: completed 40000 read, 21551 write accesses @308441000 +system.cpu6: completed 40000 read, 21597 write accesses @310397000 +system.cpu3: completed 40000 read, 21704 write accesses @312891000 +system.cpu5: completed 40000 read, 21914 write accesses @315565000 +system.cpu4: completed 50000 read, 26891 write accesses @381925000 +system.cpu0: completed 50000 read, 26990 write accesses @382095500 +system.cpu2: completed 50000 read, 26686 write accesses @382917500 +system.cpu1: completed 50000 read, 26983 write accesses @384289000 +system.cpu6: completed 50000 read, 27066 write accesses @384539000 +system.cpu7: completed 50000 read, 26943 write accesses @385136500 +system.cpu3: completed 50000 read, 27037 write accesses @389922000 +system.cpu5: completed 50000 read, 27423 write accesses @393691500 +system.cpu6: completed 60000 read, 32353 write accesses @457634500 +system.cpu4: completed 60000 read, 32228 write accesses @457992000 +system.cpu1: completed 60000 read, 32457 write accesses @460714000 +system.cpu2: completed 60000 read, 32178 write accesses @461196500 +system.cpu0: completed 60000 read, 32542 write accesses @461690000 +system.cpu7: completed 60000 read, 32302 write accesses @462388500 +system.cpu3: completed 60000 read, 32488 write accesses @466103000 +system.cpu5: completed 60000 read, 32744 write accesses @469778000 +system.cpu6: completed 70000 read, 37747 write accesses @533745000 +system.cpu2: completed 70000 read, 37532 write accesses @535320500 +system.cpu4: completed 70000 read, 37773 write accesses @535591500 +system.cpu7: completed 70000 read, 37639 write accesses @538124500 +system.cpu0: completed 70000 read, 37909 write accesses @538334500 +system.cpu1: completed 70000 read, 37921 write accesses @541231500 +system.cpu3: completed 70000 read, 37871 write accesses @542226500 +system.cpu5: completed 70000 read, 38229 write accesses @548322500 +system.cpu4: completed 80000 read, 42983 write accesses @610769500 +system.cpu6: completed 80000 read, 43020 write accesses @610776000 +system.cpu2: completed 80000 read, 42982 write accesses @611661000 +system.cpu0: completed 80000 read, 43374 write accesses @615085500 +system.cpu1: completed 80000 read, 43250 write accesses @615627500 +system.cpu7: completed 80000 read, 43033 write accesses @615746000 +system.cpu3: completed 80000 read, 43154 write accesses @619760000 +system.cpu5: completed 80000 read, 43738 write accesses @625688001 +system.cpu6: completed 90000 read, 48339 write accesses @685422000 +system.cpu2: completed 90000 read, 48272 write accesses @687608500 +system.cpu4: completed 90000 read, 48507 write accesses @688615500 +system.cpu7: completed 90000 read, 48310 write accesses @688789000 +system.cpu0: completed 90000 read, 48650 write accesses @689991000 +system.cpu1: completed 90000 read, 48621 write accesses @693117500 +system.cpu3: completed 90000 read, 48493 write accesses @697608000 +system.cpu5: completed 90000 read, 49008 write accesses @701381500 +system.cpu6: completed 100000 read, 53851 write accesses @761435500 hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout index 86075abc3..077a1416b 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memt gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:46:00 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 14:39:12 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 758619000 because maximum number of loads reached +Exiting @ tick 761435500 because maximum number of loads reached diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 08d964bc4..5ed14465a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,633 +1,633 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000758 # Number of seconds simulated -sim_ticks 758227000 # Number of ticks simulated -final_tick 758227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000761 # Number of seconds simulated +sim_ticks 761435500 # Number of ticks simulated +final_tick 761435500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 200763174 # Simulator tick rate (ticks/s) -host_mem_usage 353776 # Number of bytes of host memory used -host_seconds 3.78 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 94296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 93084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 90684 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 91125 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 90329 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 98961 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 91564 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 94442 # Number of bytes read from this memory -system.physmem.bytes_read::total 744485 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 495744 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5338 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5288 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5371 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5302 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5445 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5231 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5370 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5430 # Number of bytes written to this memory -system.physmem.bytes_written::total 538519 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10932 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11115 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11115 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11202 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11345 # Number of read requests responded to by this memory -system.physmem.num_reads::total 89033 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7746 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5338 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5288 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5371 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5302 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5445 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5231 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5370 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5430 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50521 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 124363812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 122765346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 119600067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 120181687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 119131869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 130516323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 120760669 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 124556366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 981876140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 653820030 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7040108 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6974165 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 7083631 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 6992629 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 7181227 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 6898989 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 7082312 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 7161444 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 710234534 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 653820030 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 131403920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 129739511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 126683698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 127174316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 126313096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 137415312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 127842981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 131717810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1692110674 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 15709 # number of replacements -system.l2c.tagsinuse 802.621152 # Cycle average of tags in use -system.l2c.total_refs 152986 # Total number of references to valid blocks. -system.l2c.sampled_refs 16508 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.267386 # Average number of references to valid blocks. +host_tick_rate 112752764 # Simulator tick rate (ticks/s) +host_mem_usage 399024 # Number of bytes of host memory used +host_seconds 6.75 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 92287 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 88521 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 93126 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 92216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 93858 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 91205 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 94911 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 89917 # Number of bytes read from this memory +system.physmem.bytes_read::total 736041 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 486336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5427 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5222 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5377 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5288 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5289 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5451 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5508 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5340 # Number of bytes written to this memory +system.physmem.bytes_written::total 529238 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11206 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11157 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11261 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11265 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11258 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11247 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11104 # Number of read requests responded to by this memory +system.physmem.num_reads::total 89661 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 7599 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5427 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5222 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5377 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5288 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5289 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5451 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5508 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5340 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50501 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 121201336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 116255415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 122303202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 121108091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 123264544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 119780336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 124647459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 118088794 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 966649178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 638709385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7127327 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6858099 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 7061662 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 6944777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 6946091 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 7158847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7233705 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7013069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 695052962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 638709385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 128328663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 123113514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 129364864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 128052869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 130210635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 126939183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 131881164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 125101864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1661702140 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 15611 # number of replacements +system.l2c.tagsinuse 803.524746 # Cycle average of tags in use +system.l2c.total_refs 152738 # Total number of references to valid blocks. +system.l2c.sampled_refs 16409 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.308185 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 738.344301 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.856749 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.750709 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 7.581062 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 8.075895 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.623690 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 8.411297 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 8.326520 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 8.650930 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.721039 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.007673 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007569 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.007403 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007887 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007445 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.008214 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.008131 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.008448 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.783810 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 11060 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10905 # 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number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 371 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2982 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2017 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 2086 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1996 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2001 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 2062 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1995 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 2076 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2009 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16242 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 13077 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12991 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12913 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12909 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 13087 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12764 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 13079 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 13053 # number of demand (read+write) hits -system.l2c.demand_hits::total 103873 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 13077 # number of overall hits -system.l2c.overall_hits::cpu1 12991 # number of overall hits -system.l2c.overall_hits::cpu2 12913 # number of overall hits -system.l2c.overall_hits::cpu3 12909 # number of overall hits -system.l2c.overall_hits::cpu4 13087 # number of overall hits -system.l2c.overall_hits::cpu5 12764 # number of overall hits -system.l2c.overall_hits::cpu6 13079 # number of overall hits -system.l2c.overall_hits::cpu7 13053 # number of overall hits -system.l2c.overall_hits::total 103873 # number of overall hits -system.l2c.ReadReq_misses::cpu0 831 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 825 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 807 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 851 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 828 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 911 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 848 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 890 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6791 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1940 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1902 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1837 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1834 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1940 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1893 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1907 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1914 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15167 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4262 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4280 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4373 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4275 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4377 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4319 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4433 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4324 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34643 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5093 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5105 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5180 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5126 # 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number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 55911401 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 54499902 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 55745405 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 435303755 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 229815657 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 230400614 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 235881114 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 230703609 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 235441620 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 233239630 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 238696088 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 232987140 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11680 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11851 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11934 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 94422 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 77283 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 77283 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2321 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2226 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2246 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2275 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2240 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2282 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2285 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18149 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6279 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6366 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6369 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6276 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6439 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6314 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6509 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6333 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50885 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 18170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18096 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18093 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18035 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18292 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17994 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 18360 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18267 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 145307 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 18170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18096 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18093 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18035 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18292 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17994 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 18360 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18267 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 145307 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.069885 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.070332 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.068833 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.072370 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.069856 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.077997 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.071555 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.074577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.071922 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.835847 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.836412 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.825247 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.816563 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.852747 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.845089 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.835670 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.837637 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.835693 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.678771 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.672322 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.686607 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.681166 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.679764 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.684035 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.681057 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.682773 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.680810 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.280297 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.282107 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.286299 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.284225 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.284551 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.290652 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.287636 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.285433 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.285148 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.280297 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.282107 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.286299 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.284225 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.284551 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.290652 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.287636 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.285433 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.285148 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 60633.495788 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 60106.585455 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 60578.608426 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 59535.757932 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 61088.085749 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 59778.755214 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 60649.102594 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 59660.591011 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 60240.609778 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28790.936082 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28313.562566 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28965.924878 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 27764.952563 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28509.746392 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 29535.869519 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28578.868380 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29125.080982 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28700.715699 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53922.021821 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53831.919159 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53940.341642 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53965.756491 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53790.637423 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54003.155823 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53845.271374 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53882.317299 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53897.337759 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55017.100334 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54845.944564 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54974.527220 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54890.468006 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54951.499520 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55009.192352 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54937.800985 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54868.635596 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54936.995052 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55017.100334 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54845.944564 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54974.527220 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54890.468006 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54951.499520 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55009.192352 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54937.800985 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54868.635596 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54936.995052 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 12946 # number of cycles access was blocked +system.l2c.occ_blocks::writebacks 740.398086 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 7.878873 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 7.659983 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 8.123766 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 7.474129 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 8.226019 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 8.053219 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 8.543884 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 7.166787 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.723045 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.007694 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.007480 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.007933 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.007299 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.008033 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.007864 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.008344 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.006999 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784692 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 10900 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10939 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10998 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10816 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 11039 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10812 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 11089 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 11073 # number of ReadReq hits +system.l2c.ReadReq_hits::total 87666 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 77271 # number of Writeback hits +system.l2c.Writeback_hits::total 77271 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 347 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 357 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 381 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 350 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 354 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 346 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 406 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 354 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2895 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1978 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 2136 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 2005 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1996 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1979 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 2046 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 2087 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 2088 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16315 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12878 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 13075 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 13003 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12812 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 13018 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12858 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 13176 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 13161 # number of demand (read+write) hits +system.l2c.demand_hits::total 103981 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12878 # number of overall hits +system.l2c.overall_hits::cpu1 13075 # number of overall hits +system.l2c.overall_hits::cpu2 13003 # number of overall hits +system.l2c.overall_hits::cpu3 12812 # number of overall hits +system.l2c.overall_hits::cpu4 13018 # number of overall hits +system.l2c.overall_hits::cpu5 12858 # number of overall hits +system.l2c.overall_hits::cpu6 13176 # number of overall hits +system.l2c.overall_hits::cpu7 13161 # number of overall hits +system.l2c.overall_hits::total 103981 # number of overall hits +system.l2c.ReadReq_misses::cpu0 842 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 806 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 858 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 816 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 872 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 849 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 881 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 820 # number of ReadReq misses +system.l2c.ReadReq_misses::total 6744 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1862 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1924 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1971 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1858 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1932 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1882 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1937 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1981 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15347 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4273 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4353 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4268 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4257 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4400 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4320 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4282 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4210 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34363 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5115 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5159 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5126 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5073 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5272 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5169 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5163 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5030 # number of demand (read+write) misses +system.l2c.demand_misses::total 41107 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5115 # number of overall misses +system.l2c.overall_misses::cpu1 5159 # number of overall misses +system.l2c.overall_misses::cpu2 5126 # number of overall misses +system.l2c.overall_misses::cpu3 5073 # number of overall misses +system.l2c.overall_misses::cpu4 5272 # number of overall misses +system.l2c.overall_misses::cpu5 5169 # number of overall misses +system.l2c.overall_misses::cpu6 5163 # number of overall misses +system.l2c.overall_misses::cpu7 5030 # number of overall misses +system.l2c.overall_misses::total 41107 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 50835946 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 48414928 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 51478420 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 48581936 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 52640430 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 50070934 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 52891428 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 49101459 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 404015481 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 54966909 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 55263407 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 54925394 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 53857894 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 54541411 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 53722422 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 55425398 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 56851911 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 439554746 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 229863626 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 234328104 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 229945624 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 229282087 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 236284615 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 232406616 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 230024647 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 226955142 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1849090461 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 280699572 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 282743032 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 281424044 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 277864023 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 288925045 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 282477550 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 282916075 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 276056601 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2253105942 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 280699572 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 282743032 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 281424044 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 277864023 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 288925045 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 282477550 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 282916075 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 276056601 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2253105942 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11742 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11745 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11856 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11632 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11911 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11661 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11970 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11893 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 94410 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 77271 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77271 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2209 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2281 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2352 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2208 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2286 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2228 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2343 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2335 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18242 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6251 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6489 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6273 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6253 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6379 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6366 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6369 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6298 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50678 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17993 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18234 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18129 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17885 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18290 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18027 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18339 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18191 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 145088 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17993 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18234 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18129 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17885 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18290 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 18027 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18339 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18191 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 145088 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.071708 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.068625 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.072368 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.070151 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.073210 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.072807 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.073601 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.068948 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.071433 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.842915 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.843490 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.838010 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.841486 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.845144 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.844704 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.826718 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.848394 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.841300 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.683571 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.670828 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.680376 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.680793 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.689763 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.678605 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.672319 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.668466 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.678065 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.284277 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.282933 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.282751 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.283646 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.288245 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.286737 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.281531 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.276510 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.283325 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.284277 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.282933 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.282751 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.283646 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.288245 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.286737 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.281531 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.276510 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.283325 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 60375.232779 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 60068.148883 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 59998.158508 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 59536.686275 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 60367.465596 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 58976.365135 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 60035.673099 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 59879.828049 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 59907.396352 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 29520.359291 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28723.184511 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 27866.765094 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 28987.025834 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28230.543996 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28545.388948 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28614.041301 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 28698.592125 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28641.085945 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 53794.436227 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 53831.404549 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 53876.669166 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 53860.015739 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 53701.048864 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 53797.827778 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 53718.974078 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 53908.584798 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53810.507261 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 54877.726686 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 54805.782516 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 54901.296137 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 54773.117090 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 54803.688354 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 54648.394274 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 54796.838079 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 54882.028032 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 54810.760746 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 54877.726686 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 54805.782516 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 54901.296137 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 54773.117090 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 54803.688354 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 54648.394274 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 54796.838079 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 54882.028032 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 54810.760746 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 11382 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1808 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1550 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.160398 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.343226 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7746 # number of writebacks -system.l2c.writebacks::total 7746 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 7599 # number of writebacks +system.l2c.writebacks::total 7599 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 4 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu3 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 7 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu5 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 29 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 828 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 815 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 804 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 844 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 824 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 909 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 843 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 883 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6750 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1940 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1901 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1837 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1834 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1940 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1892 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1907 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1914 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15165 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4255 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4276 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4373 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4271 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4372 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4316 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4430 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4321 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34614 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5083 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5091 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5177 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5115 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5196 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5225 # 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number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 39357435 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 39064937 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 40158430 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 40512435 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 43385946 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 40969439 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 42146427 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 325806484 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 79643349 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 78062835 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 75255324 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 75287345 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 79635834 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 77713835 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 78284820 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 78593341 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 622476683 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 178045657 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 178454114 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 182867114 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 178794609 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 182240620 # 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number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 410453631 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 397457157 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 406979111 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 406829637 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 405432120 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 405171118 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 400882109 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 414057617 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3247262500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 226073488 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 225167477 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 228704981 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 225137481 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 230851979 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 222187990 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 228117990 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 230091986 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1816333372 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 636527119 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 622624634 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 635684092 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 631967118 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 636284099 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 627359108 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 629000099 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 644149603 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5063595872 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.069632 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.069480 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068577 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.071775 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.069518 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.077825 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.071133 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.073990 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.071488 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.835847 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.835972 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.825247 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.816563 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.852747 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.844643 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.835670 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.837637 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.835583 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.677656 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.671693 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.686607 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.680529 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.678987 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.683560 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.680596 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.682299 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.680240 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.279747 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.281333 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.286133 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.283615 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.284059 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.290375 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.287200 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.284885 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.284666 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.279747 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.281333 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.286133 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.283615 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.284059 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.290375 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.287200 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.284885 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.284666 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48564.535024 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48291.331288 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 48588.230100 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 47581.078199 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49165.576456 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 47729.313531 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 48599.571767 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47730.947905 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 48267.627259 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41053.272680 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41064.089953 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40966.425694 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41050.896947 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41049.398969 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41074.965645 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41051.295228 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41062.351620 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41046.929311 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41843.867685 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41733.890084 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41817.313972 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41862.469913 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41683.581885 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41895.187674 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41743.586682 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41776.473039 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41794.128763 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42938.637025 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42783.647417 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42868.852811 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42806.068231 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 42870.102964 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42910.158086 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42839.660156 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42786.811491 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42850.509066 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42938.637025 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42783.647417 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42868.852811 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42806.068231 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 42870.102964 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42910.158086 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42839.660156 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42786.811491 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42850.509066 # average overall mshr miss latency +system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 25 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 76 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 833 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 800 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 853 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 808 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 867 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 841 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 874 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 817 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 6693 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1862 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1924 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1970 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1858 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1932 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1881 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1937 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1981 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15345 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4271 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4350 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4264 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4253 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4393 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4317 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4280 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4210 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34338 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5104 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5150 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5117 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5061 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5260 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5158 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5154 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5027 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 41031 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5104 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5150 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5117 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5061 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5260 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5158 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5154 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5027 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 41031 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 40464447 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 38550929 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 41027920 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 38515937 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 41941930 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 39649436 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 41931428 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 39012959 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 321094986 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 76446342 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 78808343 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80788312 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 76138817 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 79209815 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 77051840 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 79478835 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 81341333 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 629263637 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 178032127 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 181508104 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 178129124 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 177575588 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 182792115 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 179941616 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 178029147 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 175952642 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1431960463 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 218496574 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 220059033 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 219157044 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 216091525 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 224734045 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 219591052 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 219960575 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 214965601 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1753055449 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 218496574 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 220059033 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 219157044 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 216091525 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 224734045 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 219591052 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 219960575 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 214965601 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1753055449 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 408840154 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 409932127 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 406697168 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 412407125 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 410618544 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 412439590 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 408986543 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 406399119 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3276320370 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 229120490 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 221422480 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 227576980 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 223709488 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 225472990 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 232298486 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 233243987 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 227452978 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1820297879 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 637960644 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 631354607 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 634274148 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 636116613 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 636091534 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 644738076 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 642230530 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 633852097 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5096618249 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.070942 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.068114 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.071947 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.069464 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.072790 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.072121 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.073016 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.068696 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.070893 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.842915 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.843490 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.837585 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.841486 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.845144 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.844255 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.826718 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.848394 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.841191 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.683251 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.670365 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.679739 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.680154 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.688666 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.678134 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.672005 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.668466 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.677572 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.283666 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.282439 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.282255 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.282975 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.287589 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.286126 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.281040 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.276345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.282801 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.283666 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.282439 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.282255 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.282975 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.287589 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.286126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.281040 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.276345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.282801 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48576.767107 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48188.661250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 48098.382181 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 47668.238861 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48375.928489 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 47145.583829 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 47976.462243 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47751.479804 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 47974.747647 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41056.037594 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40960.677235 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41009.295431 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40978.911195 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40998.869048 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40963.232323 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41031.923077 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41060.743564 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41007.731313 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41683.944509 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41726.000920 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41775.122889 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41753.018575 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41609.860005 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41682.097753 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41595.595093 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41793.976722 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41701.918079 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42808.889890 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42729.909320 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 42829.205394 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 42697.396760 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42725.103612 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42572.906553 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42677.643578 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42762.204297 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42725.145597 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42808.889890 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42729.909320 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 42829.205394 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 42697.396760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42725.103612 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42572.906553 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42677.643578 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42762.204297 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42725.145597 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -656,114 +656,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 98877 # number of read accesses completed -system.cpu0.num_writes 53303 # number of write accesses completed +system.cpu0.num_reads 99397 # number of read accesses completed +system.cpu0.num_writes 53728 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 22594 # number of replacements -system.cpu0.l1c.tagsinuse 395.326045 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13097 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 23010 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.569187 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 22406 # number of replacements +system.cpu0.l1c.tagsinuse 396.107523 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13328 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22796 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.584664 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 395.326045 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.772121 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.772121 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8525 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8525 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1042 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1042 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9567 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9567 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9567 # number of overall hits -system.cpu0.l1c.overall_hits::total 9567 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36170 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36170 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23033 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23033 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 59203 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 59203 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 59203 # number of overall misses -system.cpu0.l1c.overall_misses::total 59203 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1338428684 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1338428684 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1081120140 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1081120140 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 2419548824 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 2419548824 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 2419548824 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 2419548824 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44695 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44695 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24075 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24075 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68770 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68770 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68770 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68770 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809263 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.809263 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956719 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.956719 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.860884 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.860884 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.860884 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.860884 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37003.834227 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 37003.834227 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 46937.877827 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 46937.877827 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 40868.686114 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 40868.686114 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 40868.686114 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 40868.686114 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1431079 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 396.107523 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.773648 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.773648 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8751 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8751 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1114 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1114 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9865 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9865 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9865 # number of overall hits +system.cpu0.l1c.overall_hits::total 9865 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36190 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36190 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23005 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23005 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 59195 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 59195 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 59195 # number of overall misses +system.cpu0.l1c.overall_misses::total 59195 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1343389412 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1343389412 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1089518245 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1089518245 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 2432907657 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 2432907657 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 2432907657 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 2432907657 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44941 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44941 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24119 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24119 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 69060 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 69060 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 69060 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 69060 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805278 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.805278 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953812 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.953812 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.857153 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.857153 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.857153 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.857153 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37120.459022 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 37120.459022 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 47360.062812 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 47360.062812 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 41099.884399 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 41099.884399 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 41099.884399 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 41099.884399 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1437100 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 67309 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 67352 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.261332 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.337154 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9829 # number of writebacks -system.cpu0.l1c.writebacks::total 9829 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36170 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36170 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23033 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 59203 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 59203 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 59203 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 59203 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1266094684 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1266094684 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1035054140 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1035054140 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2301148824 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 2301148824 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2301148824 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 2301148824 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 713940998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 713940998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 425679500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 425679500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1139620498 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1139620498 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809263 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809263 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956719 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956719 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860884 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.860884 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860884 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.860884 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35004.000111 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35004.000111 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 44937.877827 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 44937.877827 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 38868.787460 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 38868.787460 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 38868.787460 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 38868.787460 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9722 # number of writebacks +system.cpu0.l1c.writebacks::total 9722 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36190 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36190 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23005 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23005 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 59195 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 59195 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 59195 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 59195 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1271011412 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1271011412 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1043514245 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1043514245 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2314525657 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 2314525657 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2314525657 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 2314525657 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 712928581 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 712928581 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 437133462 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 437133462 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1150062043 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1150062043 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805278 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805278 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953812 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953812 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857153 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.857153 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857153 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.857153 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35120.514286 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35120.514286 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 45360.323625 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 45360.323625 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 39100.019546 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 39100.019546 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 39100.019546 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 39100.019546 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -771,114 +771,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98330 # number of read accesses completed -system.cpu1.num_writes 53283 # number of write accesses completed +system.cpu1.num_reads 98684 # number of read accesses completed +system.cpu1.num_writes 53281 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 22413 # number of replacements -system.cpu1.l1c.tagsinuse 397.274781 # Cycle average of tags in use -system.cpu1.l1c.total_refs 13337 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22810 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.584700 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21834 # number of replacements +system.cpu1.l1c.tagsinuse 394.001606 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13244 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22217 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.596120 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 397.274781 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.775927 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.775927 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8758 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8758 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1087 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1087 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9845 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9845 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9845 # number of overall hits -system.cpu1.l1c.overall_hits::total 9845 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 35763 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 35763 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23060 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23060 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 58823 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 58823 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 58823 # number of overall misses -system.cpu1.l1c.overall_misses::total 58823 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1339256827 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1339256827 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1098702208 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1098702208 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 2437959035 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 2437959035 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 2437959035 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 2437959035 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44521 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44521 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24147 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24147 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 68668 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 68668 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 68668 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 68668 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.803284 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.803284 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954984 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954984 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.856629 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.856629 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.856629 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.856629 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37448.111931 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 37448.111931 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47645.368951 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 47645.368951 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 41445.676606 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 41445.676606 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 41445.676606 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 41445.676606 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1431601 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 394.001606 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.769534 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.769534 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8661 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8661 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1083 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1083 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9744 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9744 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9744 # number of overall hits +system.cpu1.l1c.overall_hits::total 9744 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35792 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35792 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23021 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23021 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58813 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58813 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58813 # number of overall misses +system.cpu1.l1c.overall_misses::total 58813 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1333175718 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1333175718 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 1095650216 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 1095650216 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 2428825934 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 2428825934 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 2428825934 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 2428825934 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44453 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44453 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24104 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24104 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68557 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68557 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68557 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68557 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805165 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805165 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955070 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.955070 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.857870 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.857870 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.857870 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.857870 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37247.868742 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 37247.868742 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47593.510968 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 47593.510968 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 41297.433119 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 41297.433119 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 41297.433119 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 41297.433119 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1437849 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 66652 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66915 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.478740 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.487693 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9847 # number of writebacks -system.cpu1.l1c.writebacks::total 9847 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35763 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 35763 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23060 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23060 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 58823 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 58823 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 58823 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 58823 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1267732827 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1267732827 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1052584208 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1052584208 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2320317035 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 2320317035 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2320317035 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 2320317035 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 694424746 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 694424746 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 428704098 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 428704098 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1123128844 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1123128844 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.803284 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.803284 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954984 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954984 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.856629 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.856629 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.856629 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.856629 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35448.167855 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35448.167855 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45645.455681 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45645.455681 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39445.744607 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39445.744607 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39445.744607 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39445.744607 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9612 # number of writebacks +system.cpu1.l1c.writebacks::total 9612 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35792 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35792 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23021 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23021 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58813 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58813 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58813 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58813 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1261597219 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1261597219 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1049610216 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1049610216 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2311207435 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 2311207435 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2311207435 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 2311207435 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 716556549 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 716556549 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 420969607 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 420969607 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1137526156 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1137526156 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805165 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805165 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955070 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955070 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857870 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.857870 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857870 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.857870 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35248.022435 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35248.022435 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45593.597845 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45593.597845 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39297.560658 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39297.560658 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39297.560658 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39297.560658 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -886,114 +886,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 98918 # number of read accesses completed -system.cpu2.num_writes 53026 # number of write accesses completed +system.cpu2.num_reads 99895 # number of read accesses completed +system.cpu2.num_writes 53724 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22091 # number of replacements -system.cpu2.l1c.tagsinuse 394.122068 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13053 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22474 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.580804 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 22670 # number of replacements +system.cpu2.l1c.tagsinuse 395.972858 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13513 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 23058 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.586044 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 394.122068 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.769770 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.769770 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1062 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1062 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9719 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9719 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9719 # number of overall hits -system.cpu2.l1c.overall_hits::total 9719 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 35792 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 35792 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22782 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22782 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 58574 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 58574 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 58574 # number of overall misses -system.cpu2.l1c.overall_misses::total 58574 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1334540137 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1334540137 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1086319531 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1086319531 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 2420859668 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 2420859668 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 2420859668 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 2420859668 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44449 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44449 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 23844 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 23844 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68293 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68293 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68293 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68293 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805237 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805237 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955460 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955460 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.857687 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.857687 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.857687 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.857687 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37285.989523 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 37285.989523 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47683.238127 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 47683.238127 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 41329.935944 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 41329.935944 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 41329.935944 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 41329.935944 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1431481 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 395.972858 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.773384 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.773384 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8816 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8816 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1120 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1120 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9936 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9936 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9936 # number of overall hits +system.cpu2.l1c.overall_hits::total 9936 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36217 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36217 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23141 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23141 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 59358 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 59358 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 59358 # number of overall misses +system.cpu2.l1c.overall_misses::total 59358 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1347141340 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1347141340 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1089667259 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1089667259 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 2436808599 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 2436808599 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 2436808599 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 2436808599 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45033 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45033 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24261 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24261 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 69294 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 69294 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 69294 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 69294 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.804232 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.804232 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953835 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953835 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.856611 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.856611 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.856611 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.856611 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37196.381257 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 37196.381257 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47088.166415 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 47088.166415 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 41052.740978 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 41052.740978 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 41052.740978 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 41052.740978 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1437012 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 66558 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 67454 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.507272 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.303585 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9590 # number of writebacks -system.cpu2.l1c.writebacks::total 9590 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35792 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 35792 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22782 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22782 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 58574 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 58574 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 58574 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 58574 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1262960137 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1262960137 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1040755531 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1040755531 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2303715668 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 2303715668 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2303715668 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 2303715668 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 710805276 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 710805276 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 431026471 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 431026471 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1141831747 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1141831747 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805237 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805237 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955460 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955460 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857687 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.857687 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857687 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.857687 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35286.101280 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35286.101280 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45683.238127 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45683.238127 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39330.004234 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39330.004234 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39330.004234 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39330.004234 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9964 # number of writebacks +system.cpu2.l1c.writebacks::total 9964 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36217 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36217 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23141 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23141 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 59358 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 59358 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 59358 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 59358 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1274713340 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1274713340 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1043385259 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1043385259 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2318098599 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 2318098599 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2318098599 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 2318098599 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 709358616 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 709358616 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 436023988 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 436023988 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1145382604 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1145382604 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.804232 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.804232 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953835 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953835 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856611 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.856611 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856611 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.856611 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35196.546925 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35196.546925 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45088.166415 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45088.166415 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39052.842060 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39052.842060 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39052.842060 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39052.842060 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1001,114 +1001,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98879 # number of read accesses completed -system.cpu3.num_writes 53514 # number of write accesses completed +system.cpu3.num_reads 98442 # number of read accesses completed +system.cpu3.num_writes 53057 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 22321 # number of replacements -system.cpu3.l1c.tagsinuse 395.059941 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13052 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22702 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.574927 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 21593 # number of replacements +system.cpu3.l1c.tagsinuse 392.026155 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13022 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 21995 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.592044 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 395.059941 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.771601 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.771601 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8562 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8562 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1034 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1034 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9596 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9596 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9596 # number of overall hits -system.cpu3.l1c.overall_hits::total 9596 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35946 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35946 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 22965 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 22965 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 58911 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 58911 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 58911 # number of overall misses -system.cpu3.l1c.overall_misses::total 58911 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1334193508 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1334193508 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1085703243 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1085703243 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 2419896751 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 2419896751 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 2419896751 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 2419896751 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44508 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44508 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 23999 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 23999 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68507 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68507 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68507 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68507 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807630 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.807630 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956915 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.956915 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.859927 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.859927 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.859927 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.859927 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 37116.605686 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 37116.605686 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 47276.431221 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 47276.431221 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 41077.163026 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 41077.163026 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 41077.163026 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 41077.163026 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1431288 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 392.026155 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.765676 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.765676 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8553 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8553 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1036 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1036 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9589 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9589 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9589 # number of overall hits +system.cpu3.l1c.overall_hits::total 9589 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35616 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35616 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 22828 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 22828 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 58444 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 58444 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 58444 # number of overall misses +system.cpu3.l1c.overall_misses::total 58444 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1343250290 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1343250290 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 1077342427 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 1077342427 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 2420592717 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 2420592717 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 2420592717 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 2420592717 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44169 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44169 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 23864 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 23864 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68033 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68033 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68033 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68033 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806357 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.806357 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956587 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.956587 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.859054 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.859054 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.859054 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.859054 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 37714.799248 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 37714.799248 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 47193.903408 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 47193.903408 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 41417.300613 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 41417.300613 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 41417.300613 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 41417.300613 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1437847 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 66945 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66560 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.380058 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.602269 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9751 # number of writebacks -system.cpu3.l1c.writebacks::total 9751 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35946 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35946 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22965 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 22965 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 58911 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 58911 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 58911 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 58911 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1262305508 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1262305508 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1039775243 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1039775243 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2302080751 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 2302080751 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2302080751 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 2302080751 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 712475632 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 712475632 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 424398019 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 424398019 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1136873651 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1136873651 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807630 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807630 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956915 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956915 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859927 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.859927 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859927 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.859927 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 35116.716964 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 35116.716964 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45276.518310 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45276.518310 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 39077.264874 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 39077.264874 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 39077.264874 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 39077.264874 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9543 # number of writebacks +system.cpu3.l1c.writebacks::total 9543 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35616 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35616 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22828 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 22828 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 58444 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 58444 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 58444 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 58444 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1272022290 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1272022290 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1031688427 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1031688427 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2303710717 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 2303710717 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2303710717 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 2303710717 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 723405993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 723405993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 425307050 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 425307050 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1148713043 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1148713043 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806357 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806357 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956587 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956587 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859054 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.859054 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859054 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.859054 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 35714.911557 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 35714.911557 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45193.991020 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45193.991020 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 39417.403275 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 39417.403275 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 39417.403275 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 39417.403275 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1116,114 +1116,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99302 # number of read accesses completed -system.cpu4.num_writes 53818 # number of write accesses completed +system.cpu4.num_reads 99668 # number of read accesses completed +system.cpu4.num_writes 53668 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22353 # number of replacements -system.cpu4.l1c.tagsinuse 396.021323 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13287 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22757 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.583864 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22398 # number of replacements +system.cpu4.l1c.tagsinuse 394.185618 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13312 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22817 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.583425 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 396.021323 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.773479 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.773479 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8768 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8768 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1075 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1075 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9843 # 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number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1085022253 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 2421453838 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 2421453838 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 2421453838 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 2421453838 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44893 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44893 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24056 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24056 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68949 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68949 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68949 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68949 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804691 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.804691 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955313 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.955313 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.857242 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.857242 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.857242 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.857242 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 36994.645952 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 36994.645952 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 47213.883338 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 47213.883338 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 40967.986973 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 40967.986973 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 40967.986973 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 40967.986973 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1430986 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 394.185618 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.769894 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.769894 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8742 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8742 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1059 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1059 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9801 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9801 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9801 # number of overall hits +system.cpu4.l1c.overall_hits::total 9801 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36283 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36283 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23024 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23024 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59307 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59307 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59307 # number of overall misses +system.cpu4.l1c.overall_misses::total 59307 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1350032249 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1350032249 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 1082307804 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 1082307804 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 2432340053 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 2432340053 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 2432340053 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 2432340053 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45025 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45025 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24083 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24083 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 69108 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 69108 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 69108 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 69108 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805841 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.805841 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956027 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.956027 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858179 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858179 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858179 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858179 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 37208.396467 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 37208.396467 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 47007.809416 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 47007.809416 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 41012.697540 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 41012.697540 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 41012.697540 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 41012.697540 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1437185 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 67143 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 67419 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.312512 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.317210 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9680 # number of writebacks -system.cpu4.l1c.writebacks::total 9680 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36125 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36125 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22981 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 22981 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 59106 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 59106 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 59106 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 59106 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1264183585 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1264183585 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1039060253 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1039060253 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2303243838 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 2303243838 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2303243838 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 2303243838 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 711442657 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 711442657 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 433569420 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 433569420 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1145012077 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1145012077 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804691 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804691 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955313 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955313 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857242 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.857242 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857242 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.857242 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 34994.701315 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 34994.701315 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 45213.883338 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 45213.883338 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 38968.020810 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 38968.020810 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 38968.020810 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 38968.020810 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9672 # number of writebacks +system.cpu4.l1c.writebacks::total 9672 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36283 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36283 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23024 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23024 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59307 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59307 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59307 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59307 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1277470249 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1277470249 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1036263804 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1036263804 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2313734053 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 2313734053 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2313734053 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 2313734053 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 713854071 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 713854071 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 422821531 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 422821531 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1136675602 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1136675602 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805841 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805841 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956027 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956027 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858179 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858179 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858179 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858179 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 35208.506711 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 35208.506711 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 45007.983148 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 45007.983148 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 39012.832431 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 39012.832431 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 39012.832431 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 39012.832431 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1231,114 +1231,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98038 # number of read accesses completed -system.cpu5.num_writes 52677 # number of write accesses completed +system.cpu5.num_reads 98297 # number of read accesses completed +system.cpu5.num_writes 53409 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 21614 # number of replacements -system.cpu5.l1c.tagsinuse 395.041478 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13218 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22030 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.600000 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 21793 # number of replacements +system.cpu5.l1c.tagsinuse 394.840854 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13019 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22214 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.586072 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 395.041478 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.771565 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.771565 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8654 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8654 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1143 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1143 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9797 # 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number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1075550971 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 2418904875 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 2418904875 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 2418904875 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 2418904875 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44261 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44261 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 23792 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 23792 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 68053 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 68053 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 68053 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 68053 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.804478 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.804478 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951959 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.951959 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.856039 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.856039 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.856039 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.856039 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37727.241947 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 37727.241947 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47487.790675 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 47487.790675 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 41521.987006 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 41521.987006 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 41521.987006 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 41521.987006 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1431933 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 394.840854 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.771174 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.771174 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8574 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8574 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1037 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1037 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9611 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9611 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9611 # number of overall hits +system.cpu5.l1c.overall_hits::total 9611 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 35608 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 35608 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 22949 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 22949 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 58557 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 58557 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 58557 # number of overall misses +system.cpu5.l1c.overall_misses::total 58557 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1333115373 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1333115373 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 1089027179 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 1089027179 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 2422142552 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 2422142552 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 2422142552 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 2422142552 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44182 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44182 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 23986 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 23986 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68168 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68168 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68168 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68168 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805939 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.805939 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.956766 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.956766 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.859010 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.859010 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.859010 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.859010 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37438.647860 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 37438.647860 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47454.232385 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 47454.232385 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 41363.842956 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 41363.842956 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 41363.842956 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 41363.842956 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1437965 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 66282 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66766 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.603648 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.537384 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9279 # number of writebacks -system.cpu5.l1c.writebacks::total 9279 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35607 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 35607 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22649 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 22649 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 58256 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 58256 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 58256 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 58256 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1272141904 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1272141904 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1030256971 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1030256971 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2302398875 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 2302398875 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2302398875 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 2302398875 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 712509152 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 712509152 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 420356599 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 420356599 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1132865751 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1132865751 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.804478 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.804478 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951959 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951959 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.856039 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.856039 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.856039 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.856039 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35727.298116 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35727.298116 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45487.967283 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45487.967283 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39522.089999 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39522.089999 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39522.089999 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39522.089999 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9530 # number of writebacks +system.cpu5.l1c.writebacks::total 9530 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35608 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 35608 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22949 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 22949 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 58557 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 58557 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 58557 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 58557 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1261899373 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1261899373 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1043133179 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1043133179 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2305032552 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 2305032552 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2305032552 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 2305032552 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 722637545 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 722637545 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 432075918 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 432075918 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1154713463 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1154713463 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805939 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805939 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.956766 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.956766 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859010 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.859010 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859010 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.859010 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35438.647860 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35438.647860 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45454.406684 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45454.406684 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39363.911266 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39363.911266 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39363.911266 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39363.911266 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1346,114 +1346,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 98486 # number of read accesses completed -system.cpu6.num_writes 53296 # number of write accesses completed +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 53851 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 22107 # number of replacements -system.cpu6.l1c.tagsinuse 394.242179 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13254 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22518 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.588596 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 22533 # number of replacements +system.cpu6.l1c.tagsinuse 396.232181 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13413 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22918 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.585260 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 394.242179 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.770004 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.770004 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8629 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8629 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1104 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1104 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9733 # 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number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1095786214 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 2430425459 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 2430425459 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 2430425459 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 2430425459 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44462 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44462 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24137 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24137 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 68599 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 68599 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 68599 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 68599 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805924 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805924 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954261 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954261 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858117 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858117 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858117 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858117 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37246.092847 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 37246.092847 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 47574.619633 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 47574.619633 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 41287.423283 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 41287.423283 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 41287.423283 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 41287.423283 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1431647 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 396.232181 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.773891 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.773891 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8765 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8765 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1112 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1112 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9877 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9877 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9877 # number of overall hits +system.cpu6.l1c.overall_hits::total 9877 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36287 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36287 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23071 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23071 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 59358 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 59358 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 59358 # number of overall misses +system.cpu6.l1c.overall_misses::total 59358 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1346746093 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1346746093 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 1082399151 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 1082399151 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 2429145244 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 2429145244 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 2429145244 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 2429145244 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45052 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45052 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24183 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24183 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 69235 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 69235 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 69235 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 69235 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805447 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805447 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954017 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954017 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.857341 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.857341 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.857341 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.857341 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37113.734753 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 37113.734753 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 46916.004985 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 46916.004985 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 40923.636982 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 40923.636982 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 40923.636982 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 40923.636982 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1436888 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66759 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 67354 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.445004 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.333373 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9651 # number of writebacks -system.cpu6.l1c.writebacks::total 9651 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35833 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 35833 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23033 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 58866 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 58866 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 58866 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 58866 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1262977245 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1262977245 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1049724214 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1049724214 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2312701459 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 2312701459 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2312701459 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 2312701459 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702275141 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702275141 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 427671023 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 427671023 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1129946164 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1129946164 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805924 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805924 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954261 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954261 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858117 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858117 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858117 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858117 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35246.204476 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35246.204476 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 45574.793297 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 45574.793297 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 39287.559185 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 39287.559185 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 39287.559185 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 39287.559185 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9760 # number of writebacks +system.cpu6.l1c.writebacks::total 9760 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36287 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36287 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23071 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23071 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 59358 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 59358 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 59358 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 59358 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1274178093 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1274178093 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1036259151 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1036259151 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2310437244 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 2310437244 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2310437244 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 2310437244 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 716759617 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 716759617 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 439137857 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 439137857 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1155897474 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1155897474 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805447 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805447 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954017 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954017 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857341 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.857341 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857341 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.857341 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35113.900102 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35113.900102 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 44916.091674 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 44916.091674 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 38923.771758 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 38923.771758 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 38923.771758 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 38923.771758 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1461,114 +1461,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 100000 # number of read accesses completed -system.cpu7.num_writes 53815 # number of write accesses completed +system.cpu7.num_reads 99311 # number of read accesses completed +system.cpu7.num_writes 53396 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22563 # number of replacements -system.cpu7.l1c.tagsinuse 397.316418 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13400 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22950 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.583878 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22280 # number of replacements +system.cpu7.l1c.tagsinuse 395.094392 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13351 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22696 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.588253 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 397.316418 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.776009 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.776009 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8738 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8738 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1123 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1123 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9861 # 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number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1076026419 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 2414343602 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 2414343602 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 2414343602 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 2414343602 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45299 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24006 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24006 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69305 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69305 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69305 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69305 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807104 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.807104 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953220 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953220 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.857716 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.857716 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.857716 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.857716 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 36605.048631 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 36605.048631 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47022.961106 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 47022.961106 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 40615.429682 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 40615.429682 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 40615.429682 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 40615.429682 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1430407 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 395.094392 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.771669 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.771669 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8656 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8656 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1129 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1129 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9785 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9785 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9785 # number of overall hits +system.cpu7.l1c.overall_hits::total 9785 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36252 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36252 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23067 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23067 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59319 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59319 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59319 # number of overall misses +system.cpu7.l1c.overall_misses::total 59319 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1344539775 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1344539775 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1092348717 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1092348717 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 2436888492 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 2436888492 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 2436888492 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 2436888492 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44908 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44908 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24196 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24196 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 69104 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 69104 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 69104 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 69104 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807250 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807250 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953339 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953339 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858402 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858402 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858402 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858402 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 37088.706140 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 37088.706140 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47355.473924 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 47355.473924 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 41081.078440 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 41081.078440 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 41081.078440 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 41081.078440 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1437300 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 67553 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 67375 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.174589 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.332839 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9844 # number of writebacks -system.cpu7.l1c.writebacks::total 9844 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36561 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36561 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22883 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 22883 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59444 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59444 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59444 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59444 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1265201183 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1265201183 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1030262419 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1030262419 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2295463602 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 2295463602 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2295463602 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 2295463602 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 718920000 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 718920000 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 432823408 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 432823408 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1151743408 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1151743408 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807104 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807104 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953220 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953220 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857716 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.857716 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857716 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.857716 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 34605.212740 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 34605.212740 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45023.048508 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45023.048508 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 38615.564262 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 38615.564262 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 38615.564262 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 38615.564262 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9656 # number of writebacks +system.cpu7.l1c.writebacks::total 9656 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36252 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36252 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23067 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23067 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59319 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59319 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59319 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59319 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1272035775 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1272035775 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1046218717 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1046218717 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2318254492 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 2318254492 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2318254492 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 2318254492 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 709343608 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 709343608 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 432591529 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 432591529 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1141935137 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1141935137 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807250 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807250 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953339 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953339 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858402 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858402 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858402 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858402 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 35088.706140 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 35088.706140 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45355.647332 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45355.647332 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 39081.145872 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 39081.145872 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 39081.145872 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 39081.145872 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |