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-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini4
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr146
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest/simout6
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt2850
4 files changed, 1504 insertions, 1502 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
index 120840f6d..1f567a1b9 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -16,7 +16,7 @@ kernel=
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
-memories=system.physmem system.funcmem
+memories=system.funcmem system.physmem
num_work_ids=16
readfile=
symbolfile=
@@ -415,6 +415,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=16
master=system.physmem.port
@@ -438,6 +439,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=16
master=system.l2c.cpu_side
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
index ac8f30c3e..014cde607 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
@@ -1,74 +1,74 @@
-system.cpu4: completed 10000 read, 5213 write accesses @76807500
-system.cpu7: completed 10000 read, 5302 write accesses @79251000
-system.cpu3: completed 10000 read, 5351 write accesses @81062000
-system.cpu5: completed 10000 read, 5541 write accesses @82066500
-system.cpu1: completed 10000 read, 5479 write accesses @82140500
-system.cpu2: completed 10000 read, 5270 write accesses @82209500
-system.cpu6: completed 10000 read, 5352 write accesses @82224000
-system.cpu0: completed 10000 read, 5437 write accesses @83502000
-system.cpu4: completed 20000 read, 10638 write accesses @152852500
-system.cpu7: completed 20000 read, 10671 write accesses @153245500
-system.cpu5: completed 20000 read, 10802 write accesses @155921500
-system.cpu1: completed 20000 read, 10780 write accesses @157898500
-system.cpu3: completed 20000 read, 10762 write accesses @158207000
-system.cpu2: completed 20000 read, 10562 write accesses @158441500
-system.cpu6: completed 20000 read, 10817 write accesses @160812000
-system.cpu0: completed 20000 read, 10942 write accesses @162138000
-system.cpu4: completed 30000 read, 15885 write accesses @226882500
-system.cpu7: completed 30000 read, 16162 write accesses @230488000
-system.cpu1: completed 30000 read, 15996 write accesses @231220000
-system.cpu5: completed 30000 read, 16227 write accesses @232272500
-system.cpu3: completed 30000 read, 16181 write accesses @234012000
-system.cpu6: completed 30000 read, 16285 write accesses @236458500
-system.cpu2: completed 30000 read, 16117 write accesses @236552000
-system.cpu0: completed 30000 read, 16426 write accesses @240306500
-system.cpu4: completed 40000 read, 21151 write accesses @301825500
-system.cpu7: completed 40000 read, 21649 write accesses @305825500
-system.cpu1: completed 40000 read, 21293 write accesses @308437500
-system.cpu3: completed 40000 read, 21436 write accesses @308497500
-system.cpu5: completed 40000 read, 21614 write accesses @310554000
-system.cpu2: completed 40000 read, 21323 write accesses @312243500
-system.cpu6: completed 40000 read, 21541 write accesses @312536000
-system.cpu0: completed 40000 read, 21919 write accesses @320331000
-system.cpu4: completed 50000 read, 26446 write accesses @376676500
-system.cpu7: completed 50000 read, 26971 write accesses @382643500
-system.cpu1: completed 50000 read, 26742 write accesses @382692500
-system.cpu3: completed 50000 read, 26868 write accesses @383729000
-system.cpu5: completed 50000 read, 26982 write accesses @388892000
-system.cpu2: completed 50000 read, 26690 write accesses @389746500
-system.cpu6: completed 50000 read, 26890 write accesses @390639500
-system.cpu0: completed 50000 read, 27239 write accesses @394395001
-system.cpu4: completed 60000 read, 31859 write accesses @454814000
-system.cpu3: completed 60000 read, 32157 write accesses @455574000
-system.cpu1: completed 60000 read, 32039 write accesses @458833000
-system.cpu7: completed 60000 read, 32494 write accesses @460248000
-system.cpu2: completed 60000 read, 32094 write accesses @465749500
-system.cpu5: completed 60000 read, 32378 write accesses @466634000
-system.cpu6: completed 60000 read, 32333 write accesses @468161500
-system.cpu0: completed 60000 read, 32569 write accesses @469644500
-system.cpu3: completed 70000 read, 37524 write accesses @531095000
-system.cpu4: completed 70000 read, 37387 write accesses @531724000
-system.cpu1: completed 70000 read, 37455 write accesses @534864500
-system.cpu2: completed 70000 read, 37386 write accesses @539742500
-system.cpu7: completed 70000 read, 38025 write accesses @540171500
-system.cpu5: completed 70000 read, 37779 write accesses @540661000
-system.cpu0: completed 70000 read, 37912 write accesses @543002000
-system.cpu6: completed 70000 read, 37876 write accesses @544926000
-system.cpu4: completed 80000 read, 42765 write accesses @607648000
-system.cpu3: completed 80000 read, 42947 write accesses @608627500
-system.cpu1: completed 80000 read, 42804 write accesses @612176500
-system.cpu5: completed 80000 read, 43215 write accesses @614679500
-system.cpu2: completed 80000 read, 42837 write accesses @616130500
-system.cpu7: completed 80000 read, 43372 write accesses @618251000
-system.cpu0: completed 80000 read, 43388 write accesses @620992000
-system.cpu6: completed 80000 read, 43420 write accesses @622851000
-system.cpu4: completed 90000 read, 48066 write accesses @681361000
-system.cpu3: completed 90000 read, 48251 write accesses @683201500
-system.cpu1: completed 90000 read, 48377 write accesses @690035500
-system.cpu5: completed 90000 read, 48546 write accesses @692142000
-system.cpu2: completed 90000 read, 48240 write accesses @693946000
-system.cpu7: completed 90000 read, 48816 write accesses @696757000
-system.cpu0: completed 90000 read, 48758 write accesses @697163500
-system.cpu6: completed 90000 read, 48649 write accesses @698059000
-system.cpu4: completed 100000 read, 53418 write accesses @758619000
+system.cpu6: completed 10000 read, 5435 write accesses @79021500
+system.cpu0: completed 10000 read, 5363 write accesses @79194500
+system.cpu7: completed 10000 read, 5392 write accesses @79770500
+system.cpu2: completed 10000 read, 5375 write accesses @80689500
+system.cpu1: completed 10000 read, 5373 write accesses @81623500
+system.cpu4: completed 10000 read, 5458 write accesses @81916000
+system.cpu5: completed 10000 read, 5507 write accesses @81975000
+system.cpu3: completed 10000 read, 5421 write accesses @82381000
+system.cpu2: completed 20000 read, 10678 write accesses @153864500
+system.cpu0: completed 20000 read, 10854 write accesses @154789000
+system.cpu7: completed 20000 read, 10817 write accesses @154953500
+system.cpu1: completed 20000 read, 10781 write accesses @155855500
+system.cpu3: completed 20000 read, 10799 write accesses @157033000
+system.cpu4: completed 20000 read, 10854 write accesses @157158000
+system.cpu6: completed 20000 read, 10878 write accesses @157795000
+system.cpu5: completed 20000 read, 10963 write accesses @159866500
+system.cpu0: completed 30000 read, 16180 write accesses @228385000
+system.cpu2: completed 30000 read, 15995 write accesses @229109500
+system.cpu7: completed 30000 read, 16232 write accesses @231170000
+system.cpu1: completed 30000 read, 16165 write accesses @231658500
+system.cpu4: completed 30000 read, 16252 write accesses @232783000
+system.cpu6: completed 30000 read, 16228 write accesses @233712000
+system.cpu3: completed 30000 read, 16226 write accesses @236523000
+system.cpu5: completed 30000 read, 16456 write accesses @239602000
+system.cpu0: completed 40000 read, 21598 write accesses @305262000
+system.cpu2: completed 40000 read, 21332 write accesses @306571000
+system.cpu1: completed 40000 read, 21599 write accesses @307778500
+system.cpu4: completed 40000 read, 21599 write accesses @307971000
+system.cpu7: completed 40000 read, 21551 write accesses @308441000
+system.cpu6: completed 40000 read, 21597 write accesses @310397000
+system.cpu3: completed 40000 read, 21704 write accesses @312891000
+system.cpu5: completed 40000 read, 21914 write accesses @315565000
+system.cpu4: completed 50000 read, 26891 write accesses @381925000
+system.cpu0: completed 50000 read, 26990 write accesses @382095500
+system.cpu2: completed 50000 read, 26686 write accesses @382917500
+system.cpu1: completed 50000 read, 26983 write accesses @384289000
+system.cpu6: completed 50000 read, 27066 write accesses @384539000
+system.cpu7: completed 50000 read, 26943 write accesses @385136500
+system.cpu3: completed 50000 read, 27037 write accesses @389922000
+system.cpu5: completed 50000 read, 27423 write accesses @393691500
+system.cpu6: completed 60000 read, 32353 write accesses @457634500
+system.cpu4: completed 60000 read, 32228 write accesses @457992000
+system.cpu1: completed 60000 read, 32457 write accesses @460714000
+system.cpu2: completed 60000 read, 32178 write accesses @461196500
+system.cpu0: completed 60000 read, 32542 write accesses @461690000
+system.cpu7: completed 60000 read, 32302 write accesses @462388500
+system.cpu3: completed 60000 read, 32488 write accesses @466103000
+system.cpu5: completed 60000 read, 32744 write accesses @469778000
+system.cpu6: completed 70000 read, 37747 write accesses @533745000
+system.cpu2: completed 70000 read, 37532 write accesses @535320500
+system.cpu4: completed 70000 read, 37773 write accesses @535591500
+system.cpu7: completed 70000 read, 37639 write accesses @538124500
+system.cpu0: completed 70000 read, 37909 write accesses @538334500
+system.cpu1: completed 70000 read, 37921 write accesses @541231500
+system.cpu3: completed 70000 read, 37871 write accesses @542226500
+system.cpu5: completed 70000 read, 38229 write accesses @548322500
+system.cpu4: completed 80000 read, 42983 write accesses @610769500
+system.cpu6: completed 80000 read, 43020 write accesses @610776000
+system.cpu2: completed 80000 read, 42982 write accesses @611661000
+system.cpu0: completed 80000 read, 43374 write accesses @615085500
+system.cpu1: completed 80000 read, 43250 write accesses @615627500
+system.cpu7: completed 80000 read, 43033 write accesses @615746000
+system.cpu3: completed 80000 read, 43154 write accesses @619760000
+system.cpu5: completed 80000 read, 43738 write accesses @625688001
+system.cpu6: completed 90000 read, 48339 write accesses @685422000
+system.cpu2: completed 90000 read, 48272 write accesses @687608500
+system.cpu4: completed 90000 read, 48507 write accesses @688615500
+system.cpu7: completed 90000 read, 48310 write accesses @688789000
+system.cpu0: completed 90000 read, 48650 write accesses @689991000
+system.cpu1: completed 90000 read, 48621 write accesses @693117500
+system.cpu3: completed 90000 read, 48493 write accesses @697608000
+system.cpu5: completed 90000 read, 49008 write accesses @701381500
+system.cpu6: completed 100000 read, 53851 write accesses @761435500
hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
index 86075abc3..077a1416b 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memt
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:46:00
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 14:39:12
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 758619000 because maximum number of loads reached
+Exiting @ tick 761435500 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
index 08d964bc4..5ed14465a 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -1,633 +1,633 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000758 # Number of seconds simulated
-sim_ticks 758227000 # Number of ticks simulated
-final_tick 758227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000761 # Number of seconds simulated
+sim_ticks 761435500 # Number of ticks simulated
+final_tick 761435500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 200763174 # Simulator tick rate (ticks/s)
-host_mem_usage 353776 # Number of bytes of host memory used
-host_seconds 3.78 # Real time elapsed on the host
-system.physmem.bytes_read::cpu0 94296 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 93084 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 90684 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 91125 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 90329 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 98961 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 91564 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 94442 # Number of bytes read from this memory
-system.physmem.bytes_read::total 744485 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 495744 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5338 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5288 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5371 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5302 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5445 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5231 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5370 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5430 # Number of bytes written to this memory
-system.physmem.bytes_written::total 538519 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 11262 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10932 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 11115 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 11115 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 11075 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 11202 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10987 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 11345 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 89033 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 7746 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5338 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5288 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5371 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5302 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5445 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5231 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5370 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5430 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 50521 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 124363812 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 122765346 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 119600067 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 120181687 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 119131869 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 130516323 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 120760669 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 124556366 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 981876140 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 653820030 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 7040108 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 6974165 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 7083631 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 6992629 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 7181227 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 6898989 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 7082312 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 7161444 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 710234534 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 653820030 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 131403920 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 129739511 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 126683698 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 127174316 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 126313096 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 137415312 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 127842981 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 131717810 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1692110674 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 15709 # number of replacements
-system.l2c.tagsinuse 802.621152 # Cycle average of tags in use
-system.l2c.total_refs 152986 # Total number of references to valid blocks.
-system.l2c.sampled_refs 16508 # Sample count of references to valid blocks.
-system.l2c.avg_refs 9.267386 # Average number of references to valid blocks.
+host_tick_rate 112752764 # Simulator tick rate (ticks/s)
+host_mem_usage 399024 # Number of bytes of host memory used
+host_seconds 6.75 # Real time elapsed on the host
+system.physmem.bytes_read::cpu0 92287 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 88521 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 93126 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 92216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 93858 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 91205 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 94911 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 89917 # Number of bytes read from this memory
+system.physmem.bytes_read::total 736041 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 486336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5427 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5222 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5377 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5288 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5289 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5451 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5508 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5340 # Number of bytes written to this memory
+system.physmem.bytes_written::total 529238 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 11206 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 11157 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 11163 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 11261 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 11265 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 11258 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 11247 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 11104 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 89661 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 7599 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5427 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5222 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5377 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5288 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5289 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5451 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5508 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5340 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 50501 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 121201336 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 116255415 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 122303202 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 121108091 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 123264544 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 119780336 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 124647459 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 118088794 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 966649178 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 638709385 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 7127327 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 6858099 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 7061662 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 6944777 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 6946091 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 7158847 # Write bandwidth from this memory (bytes/s)
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.837585 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.841486 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.845144 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.844255 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.826718 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.848394 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.841191 # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.670365 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.679739 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.680154 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.688666 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.678134 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.672005 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.668466 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.677572 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0 0.283666 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1 0.282439 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2 0.282255 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3 0.282975 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4 0.287589 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.286126 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.281040 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.276345 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.282801 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.283666 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.282439 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.282255 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.282975 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4 0.287589 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5 0.286126 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6 0.281040 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7 0.276345 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.282801 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48576.767107 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48188.661250 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 48098.382181 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 47668.238861 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48375.928489 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 47145.583829 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 47976.462243 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47751.479804 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 47974.747647 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41056.037594 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40960.677235 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41009.295431 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40978.911195 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40998.869048 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40963.232323 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41031.923077 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41060.743564 # average UpgradeReq mshr miss latency
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+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41775.122889 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41753.018575 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41609.860005 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41682.097753 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41595.595093 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41793.976722 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41701.918079 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 42808.889890 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu5 42572.906553 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu7 42762.204297 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 42725.145597 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 42808.889890 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 42729.909320 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu3 42697.396760 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 42725.103612 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu7 42762.204297 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
@@ -656,114 +656,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.num_reads 98877 # number of read accesses completed
-system.cpu0.num_writes 53303 # number of write accesses completed
+system.cpu0.num_reads 99397 # number of read accesses completed
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system.cpu0.num_copies 0 # number of copy accesses completed
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-system.cpu0.l1c.avg_refs 0.569187 # Average number of references to valid blocks.
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+system.cpu0.l1c.avg_refs 0.584664 # Average number of references to valid blocks.
system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
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system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
@@ -771,114 +771,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.num_copies 0 # number of copy accesses completed
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system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
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+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35248.022435 # average ReadReq mshr miss latency
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system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
@@ -886,114 +886,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu2.num_copies 0 # number of copy accesses completed
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system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39052.842060 # average overall mshr miss latency
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system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
@@ -1001,114 +1001,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu3.num_copies 0 # number of copy accesses completed
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system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
@@ -1116,114 +1116,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu4.num_copies 0 # number of copy accesses completed
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-system.cpu4.l1c.avg_refs 0.583864 # Average number of references to valid blocks.
+system.cpu4.l1c.replacements 22398 # number of replacements
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+system.cpu4.l1c.avg_refs 0.583425 # Average number of references to valid blocks.
system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.occ_blocks::cpu4 396.021323 # Average occupied blocks per requestor
-system.cpu4.l1c.occ_percent::cpu4 0.773479 # Average percentage of cache occupancy
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
@@ -1231,114 +1231,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu5.num_copies 0 # number of copy accesses completed
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system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
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system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
@@ -1346,114 +1346,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu6.num_copies 0 # number of copy accesses completed
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system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
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system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
@@ -1461,114 +1461,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu7.num_copies 0 # number of copy accesses completed
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-system.cpu7.l1c.avg_refs 0.583878 # Average number of references to valid blocks.
+system.cpu7.l1c.replacements 22280 # number of replacements
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+system.cpu7.l1c.avg_refs 0.588253 # Average number of references to valid blocks.
system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu7.l1c.overall_miss_rate::total 0.858402 # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 37088.706140 # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 37088.706140 # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47355.473924 # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 47355.473924 # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 41081.078440 # average overall miss latency
+system.cpu7.l1c.demand_avg_miss_latency::total 41081.078440 # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 41081.078440 # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 41081.078440 # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs 1437300 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs 67553 # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs 67375 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.174589 # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.332839 # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks 9844 # number of writebacks
-system.cpu7.l1c.writebacks::total 9844 # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36561 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total 36561 # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22883 # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total 22883 # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7 59444 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total 59444 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7 59444 # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total 59444 # number of overall MSHR misses
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-system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1265201183 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1030262419 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1030262419 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2295463602 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total 2295463602 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2295463602 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total 2295463602 # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 718920000 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 718920000 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 432823408 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 432823408 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1151743408 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1151743408 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807104 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807104 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953220 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953220 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857716 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total 0.857716 # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857716 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total 0.857716 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 34605.212740 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 34605.212740 # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45023.048508 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45023.048508 # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 38615.564262 # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 38615.564262 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 38615.564262 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 38615.564262 # average overall mshr miss latency
+system.cpu7.l1c.writebacks::writebacks 9656 # number of writebacks
+system.cpu7.l1c.writebacks::total 9656 # number of writebacks
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+system.cpu7.l1c.WriteReq_mshr_misses::total 23067 # number of WriteReq MSHR misses
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+system.cpu7.l1c.overall_mshr_misses::total 59319 # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1272035775 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1272035775 # number of ReadReq MSHR miss cycles
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+system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2318254492 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total 2318254492 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2318254492 # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total 2318254492 # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 709343608 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 709343608 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 432591529 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 432591529 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1141935137 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1141935137 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807250 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807250 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953339 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953339 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858402 # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total 0.858402 # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858402 # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total 0.858402 # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 35088.706140 # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 35088.706140 # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45355.647332 # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45355.647332 # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 39081.145872 # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 39081.145872 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 39081.145872 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 39081.145872 # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency