diff options
Diffstat (limited to 'tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt')
| -rw-r--r-- | tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt | 3352 |
1 files changed, 1713 insertions, 1639 deletions
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 1b6566181..c01cc2902 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1735 +1,1809 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000730 # Number of seconds simulated -sim_ticks 729906500 # Number of ticks simulated -final_tick 729906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000790 # Number of seconds simulated +sim_ticks 789792500 # Number of ticks simulated +final_tick 789792500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 158517498 # Simulator tick rate (ticks/s) -host_mem_usage 277860 # Number of bytes of host memory used -host_seconds 4.60 # Real time elapsed on the host +host_tick_rate 129975147 # Simulator tick rate (ticks/s) +host_mem_usage 221936 # Number of bytes of host memory used +host_seconds 6.08 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 76606 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 79713 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 76745 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 78087 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 75189 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 77277 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 77630 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 79795 # Number of bytes read from this memory -system.physmem.bytes_read::total 621042 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 386688 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5350 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5335 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5338 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5543 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5476 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5444 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5451 # Number of bytes written to this memory -system.physmem.bytes_written::total 430089 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11106 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10812 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10850 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10810 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87117 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6042 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5350 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5335 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5338 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5543 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5476 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5444 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5451 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49443 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 104953169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 109209878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 105143604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 106982196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 103011824 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 105872464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 106356088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 109322221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 850851445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 529777444 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7329706 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 7309155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 7313265 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 7594123 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 7485890 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 7502331 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 7458490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 7468080 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 589238485 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 529777444 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 112282875 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 116519034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 112456869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 114576319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 110497714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 113374795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 113814578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 116790301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1440089929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 78179 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 78681 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 79146 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 76465 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 76157 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 75918 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 79229 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 81414 # Number of bytes read from this memory +system.physmem.bytes_read::total 625189 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 393152 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5414 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5436 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5494 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5519 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5358 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5458 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5447 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5462 # Number of bytes written to this memory +system.physmem.bytes_written::total 436740 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11021 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11015 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10874 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10980 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87862 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6143 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5414 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5436 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5494 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5519 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5358 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5458 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5447 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5462 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49731 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 98986759 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 99622369 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 100211131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 96816569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 96426593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 96123982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 100316222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 103082772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 791586398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 497791509 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 6854965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6882820 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 6956257 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 6987911 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 6784060 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 6910676 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 6896748 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 6915741 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 552980688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 497791509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 105841724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 106505190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 107167389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 103804480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 103210653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 103034658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 107212970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 109998512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1344567086 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99153 # number of read accesses completed -system.cpu0.num_writes 54942 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22508 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.884164 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13343 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22908 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.582460 # Average number of references to valid blocks. +system.cpu0.num_reads 99211 # number of read accesses completed +system.cpu0.num_writes 54990 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22470 # number of replacements +system.cpu0.l1c.tags.tagsinuse 393.865816 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13332 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22858 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.583253 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.884164 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.769305 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.769305 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 366 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 337372 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 337372 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8651 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8651 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1083 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1083 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9734 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9734 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9734 # number of overall hits -system.cpu0.l1c.overall_hits::total 9734 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36335 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36335 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 24086 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 24086 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60421 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60421 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60421 # number of overall misses -system.cpu0.l1c.overall_misses::total 60421 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1008804376 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1008804376 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 935467464 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 935467464 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1944271840 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1944271840 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1944271840 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1944271840 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44986 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44986 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25169 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25169 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70155 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70155 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70155 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70155 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807696 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807696 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956971 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.956971 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.861250 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.861250 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.861250 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.861250 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27763.984478 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 27763.984478 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38838.639209 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 38838.639209 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 32178.743152 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 32178.743152 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 32178.743152 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 32178.743152 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1068204 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 393.865816 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.769269 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.769269 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 352 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337265 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337265 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8594 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8594 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1143 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1143 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9737 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9737 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9737 # number of overall hits +system.cpu0.l1c.overall_hits::total 9737 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36367 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36367 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 24030 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 24030 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60397 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60397 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60397 # number of overall misses +system.cpu0.l1c.overall_misses::total 60397 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1097985534 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1097985534 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1003527320 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1003527320 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 2101512854 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 2101512854 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 2101512854 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 2101512854 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44961 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44961 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25173 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25173 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70134 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70134 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70134 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70134 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808857 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.808857 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954594 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954594 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.861166 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.861166 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.861166 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.861166 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 30191.809443 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 30191.809443 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 41761.436538 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 41761.436538 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 34794.987400 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 34794.987400 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 34794.987400 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 34794.987400 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1144726 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 61717 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61078 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 17.308100 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 18.742035 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9915 # number of writebacks -system.cpu0.l1c.writebacks::total 9915 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36335 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36335 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24086 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 24086 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60421 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60421 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60421 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60421 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 953224016 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 953224016 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 898871386 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 898871386 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1852095402 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1852095402 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1852095402 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1852095402 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 743740324 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 743740324 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1921383275 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1921383275 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2665123599 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2665123599 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807696 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807696 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956971 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956971 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861250 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.861250 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861250 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.861250 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26234.319967 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26234.319967 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37319.247115 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37319.247115 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 30653.173599 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30653.173599 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30653.173599 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30653.173599 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9946 # number of writebacks +system.cpu0.l1c.writebacks::total 9946 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36367 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36367 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24030 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 24030 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60397 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60397 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60397 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60397 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9956 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9956 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5416 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5416 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15372 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15372 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1042449014 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1042449014 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 966947420 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 966947420 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2009396434 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 2009396434 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2009396434 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 2009396434 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 778948863 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 778948863 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 2127994240 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 2127994240 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2906943103 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2906943103 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808857 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808857 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954594 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954594 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861166 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.861166 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861166 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.861166 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 28664.696401 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 28664.696401 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 40239.176862 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 40239.176862 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 33269.805355 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 33269.805355 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 33269.805355 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 33269.805355 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78239.138509 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78239.138509 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 392908.833087 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392908.833087 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 189106.368918 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 189106.368918 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 54938 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22377 # number of replacements -system.cpu1.l1c.tags.tagsinuse 394.468790 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13456 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.590564 # Average number of references to valid blocks. +system.cpu1.num_writes 55318 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22177 # number of replacements +system.cpu1.l1c.tags.tagsinuse 393.980771 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13598 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22566 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.602588 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 394.468790 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.770447 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.770447 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338150 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338150 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8709 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8709 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1179 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1179 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9888 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9888 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9888 # number of overall hits -system.cpu1.l1c.overall_hits::total 9888 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36587 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36587 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23856 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23856 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60443 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60443 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60443 # number of overall misses -system.cpu1.l1c.overall_misses::total 60443 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1017715976 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1017715976 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 924313604 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 924313604 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1942029580 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1942029580 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1942029580 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1942029580 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45296 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45296 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25035 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25035 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70331 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70331 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70331 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70331 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807731 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.807731 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.952906 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.952906 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859408 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859408 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859408 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859408 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 27816.327548 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 27816.327548 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38745.540074 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 38745.540074 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 32129.933657 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 32129.933657 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 32129.933657 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 32129.933657 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1075887 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 393.980771 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.769494 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.769494 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 357 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338430 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338430 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8884 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8884 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1068 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1068 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9952 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9952 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9952 # number of overall hits +system.cpu1.l1c.overall_hits::total 9952 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36538 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36538 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23930 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23930 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60468 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60468 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60468 # number of overall misses +system.cpu1.l1c.overall_misses::total 60468 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1108002821 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1108002821 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 993849096 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 993849096 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 2101851917 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 2101851917 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 2101851917 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 2101851917 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45422 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45422 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24998 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24998 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70420 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70420 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70420 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70420 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804412 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.804412 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.957277 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.957277 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.858677 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.858677 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.858677 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.858677 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 30324.670781 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 30324.670781 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 41531.512578 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 41531.512578 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 34759.739317 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 34759.739317 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 34759.739317 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 34759.739317 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1147241 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62059 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61428 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 17.336518 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 18.676190 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9753 # number of writebacks -system.cpu1.l1c.writebacks::total 9753 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36587 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36587 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23856 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23856 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60443 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60443 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60443 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60443 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 961736168 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 961736168 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 888050076 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 888050076 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1849786244 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1849786244 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1849786244 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1849786244 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 753708733 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 753708733 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1923800282 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1923800282 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2677509015 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2677509015 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807731 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807731 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.952906 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.952906 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859408 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859408 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859408 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859408 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 26286.281138 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26286.281138 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37225.439135 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37225.439135 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 30603.812584 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 30603.812584 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 30603.812584 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 30603.812584 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9780 # number of writebacks +system.cpu1.l1c.writebacks::total 9780 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36538 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36538 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23930 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23930 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60468 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60468 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60468 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60468 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 10010 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 10010 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5438 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5438 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15448 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15448 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1052180887 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1052180887 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 957433148 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 957433148 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2009614035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 2009614035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2009614035 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 2009614035 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 780874824 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 780874824 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 2141613646 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 2141613646 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2922488470 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2922488470 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804412 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804412 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.957277 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.957277 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858677 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.858677 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858677 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.858677 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 28796.893289 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 28796.893289 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 40009.742917 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 40009.742917 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 33234.339403 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 33234.339403 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 33234.339403 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 33234.339403 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78009.472927 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78009.472927 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 393823.767194 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 393823.767194 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 189182.319394 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 189182.319394 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99515 # number of read accesses completed -system.cpu2.num_writes 55356 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22413 # number of replacements -system.cpu2.l1c.tags.tagsinuse 394.491739 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13448 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22815 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.589437 # Average number of references to valid blocks. +system.cpu2.num_reads 99906 # number of read accesses completed +system.cpu2.num_writes 55186 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22429 # number of replacements +system.cpu2.l1c.tags.tagsinuse 394.168243 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13360 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22814 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.585605 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 394.491739 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.770492 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.770492 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338294 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338294 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8726 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8726 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1175 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1175 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9901 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9901 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9901 # number of overall hits -system.cpu2.l1c.overall_hits::total 9901 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36442 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36442 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 24017 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 24017 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60459 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60459 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60459 # number of overall misses -system.cpu2.l1c.overall_misses::total 60459 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1013968188 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1013968188 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 926155084 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 926155084 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1940123272 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1940123272 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1940123272 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1940123272 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45168 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45168 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25192 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25192 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70360 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70360 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70360 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70360 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806810 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806810 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953358 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953358 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.859281 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.859281 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.859281 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.859281 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 27824.164096 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 27824.164096 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38562.480077 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 38562.480077 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 32089.900131 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 32089.900131 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 32089.900131 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 32089.900131 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1067763 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 394.168243 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.769860 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.769860 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 385 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.751953 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338029 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338029 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8660 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8660 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1124 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1124 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9784 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9784 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9784 # number of overall hits +system.cpu2.l1c.overall_hits::total 9784 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36507 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36507 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 24000 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 24000 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60507 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60507 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60507 # number of overall misses +system.cpu2.l1c.overall_misses::total 60507 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1106428919 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1106428919 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1000960978 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1000960978 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 2107389897 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 2107389897 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 2107389897 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 2107389897 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45167 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45167 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25124 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25124 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70291 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70291 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70291 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70291 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808267 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.808267 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955262 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955262 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.860807 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.860807 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.860807 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.860807 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 30307.308708 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 30307.308708 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 41706.707417 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 41706.707417 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 34828.861074 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 34828.861074 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 34828.861074 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 34828.861074 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1143492 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 61601 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 61259 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 17.333534 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 18.666514 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9861 # number of writebacks -system.cpu2.l1c.writebacks::total 9861 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36442 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36442 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24017 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 24017 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60459 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60459 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60459 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60459 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 958233322 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 958233322 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 889641050 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 889641050 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1847874372 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1847874372 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1847874372 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1847874372 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 744958366 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 744958366 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1919549279 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1919549279 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2664507645 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2664507645 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806810 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806810 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953358 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953358 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859281 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.859281 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859281 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.859281 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 26294.751166 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26294.751166 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37042.138902 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37042.138902 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 30564.090905 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 30564.090905 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30564.090905 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30564.090905 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9834 # number of writebacks +system.cpu2.l1c.writebacks::total 9834 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36507 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36507 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24000 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60507 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60507 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60507 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60507 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9899 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9899 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5496 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5496 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15395 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15395 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1050702877 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1050702877 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 964435030 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 964435030 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2015137907 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 2015137907 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2015137907 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 2015137907 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 774345338 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 774345338 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 2129438676 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 2129438676 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2903784014 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2903784014 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808267 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808267 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955262 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955262 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860807 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.860807 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860807 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.860807 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 28780.860575 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 28780.860575 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 40184.792917 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 40184.792917 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 33304.211199 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 33304.211199 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 33304.211199 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 33304.211199 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78224.602283 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78224.602283 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 387452.451965 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 387452.451965 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 188618.643326 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 188618.643326 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99509 # number of read accesses completed -system.cpu3.num_writes 55322 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22357 # number of replacements -system.cpu3.l1c.tags.tagsinuse 394.352238 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13564 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22743 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.596403 # Average number of references to valid blocks. +system.cpu3.num_reads 99687 # number of read accesses completed +system.cpu3.num_writes 54914 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22514 # number of replacements +system.cpu3.l1c.tags.tagsinuse 394.486423 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13398 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22905 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.584938 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 394.352238 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.770219 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.770219 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 354 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 338647 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 338647 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8763 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8763 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1221 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1221 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9984 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9984 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9984 # number of overall hits -system.cpu3.l1c.overall_hits::total 9984 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36641 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36641 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23832 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23832 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60473 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60473 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60473 # number of overall misses -system.cpu3.l1c.overall_misses::total 60473 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1024295614 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1024295614 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 922064777 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 922064777 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1946360391 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1946360391 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1946360391 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1946360391 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45404 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45404 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25053 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25053 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70457 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70457 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70457 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70457 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806999 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.806999 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.951263 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.951263 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.858297 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.858297 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.858297 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.858297 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 27954.903360 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 27954.903360 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38690.197088 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 38690.197088 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 32185.609958 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 32185.609958 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 32185.609958 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 32185.609958 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1061792 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 394.486423 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.770481 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.770481 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 351 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 337490 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 337490 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8775 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8775 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1091 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1091 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9866 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9866 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9866 # number of overall hits +system.cpu3.l1c.overall_hits::total 9866 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36393 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36393 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23929 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23929 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60322 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60322 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60322 # number of overall misses +system.cpu3.l1c.overall_misses::total 60322 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1101223942 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1101223942 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 999641040 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 999641040 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 2100864982 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 2100864982 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 2100864982 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 2100864982 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45168 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45168 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25020 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25020 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70188 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70188 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70188 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70188 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805725 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.805725 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956395 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.956395 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.859435 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.859435 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.859435 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.859435 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 30259.224082 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 30259.224082 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 41775.295248 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 41775.295248 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 34827.508736 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 34827.508736 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 34827.508736 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 34827.508736 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1140042 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 61430 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 60968 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 17.284584 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 18.699022 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9814 # number of writebacks -system.cpu3.l1c.writebacks::total 9814 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36641 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36641 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23832 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23832 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60473 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60473 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60473 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60473 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 968238306 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 968238306 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 885855695 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 885855695 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1854094001 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1854094001 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1854094001 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1854094001 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 733819505 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 733819505 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1976786114 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1976786114 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2710605619 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2710605619 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806999 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806999 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.951263 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.951263 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858297 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.858297 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858297 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.858297 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 26424.996752 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 26424.996752 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37170.849908 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37170.849908 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 30659.864750 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 30659.864750 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 30659.864750 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 30659.864750 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9981 # number of writebacks +system.cpu3.l1c.writebacks::total 9981 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36393 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36393 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23929 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23929 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60322 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60322 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60322 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60322 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9906 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9906 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5522 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5522 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15428 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15428 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1045674368 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1045674368 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 963227618 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 963227618 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2008901986 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 2008901986 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2008901986 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 2008901986 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 776644993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 776644993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 2134037166 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 2134037166 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2910682159 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2910682159 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805725 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805725 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956395 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956395 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859435 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.859435 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859435 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.859435 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 28732.843349 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 28732.843349 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 40253.567554 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 40253.567554 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 33302.973807 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 33302.973807 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 33302.973807 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 33302.973807 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78401.473148 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78401.473148 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 386460.913799 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 386460.913799 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 188662.312613 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 188662.312613 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99688 # number of read accesses completed -system.cpu4.num_writes 55538 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22215 # number of replacements -system.cpu4.l1c.tags.tagsinuse 391.788113 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13621 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22618 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.602219 # Average number of references to valid blocks. +system.cpu4.num_reads 99646 # number of read accesses completed +system.cpu4.num_writes 55076 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22475 # number of replacements +system.cpu4.l1c.tags.tagsinuse 394.666578 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13432 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.587243 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 391.788113 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.765211 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.765211 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 365 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 338206 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 338206 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8861 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8861 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1198 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1198 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 10059 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 10059 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 10059 # number of overall hits -system.cpu4.l1c.overall_hits::total 10059 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36318 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36318 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 24000 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 24000 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60318 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60318 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60318 # number of overall misses -system.cpu4.l1c.overall_misses::total 60318 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1007698293 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1007698293 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 930213172 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 930213172 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1937911465 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1937911465 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1937911465 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1937911465 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45179 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45179 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25198 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25198 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70377 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70377 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70377 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70377 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.803869 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.803869 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952457 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.952457 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.857070 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.857070 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.857070 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.857070 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 27746.524946 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 27746.524946 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38758.882167 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 38758.882167 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 32128.244720 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 32128.244720 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 32128.244720 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 32128.244720 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1066740 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 394.666578 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.770833 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.770833 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 352 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338590 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338590 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8683 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8683 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1163 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1163 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9846 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9846 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9846 # number of overall hits +system.cpu4.l1c.overall_hits::total 9846 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36657 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36657 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23918 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23918 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60575 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60575 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60575 # number of overall misses +system.cpu4.l1c.overall_misses::total 60575 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1108449638 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1108449638 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 999797609 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 999797609 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 2108247247 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 2108247247 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 2108247247 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 2108247247 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45340 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45340 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25081 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25081 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70421 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70421 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70421 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70421 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.808491 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.808491 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953630 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953630 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.860184 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.860184 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.860184 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.860184 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 30238.416619 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 30238.416619 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 41801.053976 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 41801.053976 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 34803.916583 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 34803.916583 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 34803.916583 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 34803.916583 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1151337 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 61639 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61602 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 17.306251 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 18.689929 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9826 # number of writebacks -system.cpu4.l1c.writebacks::total 9826 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36318 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36318 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24000 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60318 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60318 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60318 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60318 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 952156937 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 952156937 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 893690718 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 893690718 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1845847655 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1845847655 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1845847655 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1845847655 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 748268844 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 748268844 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1945456088 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1945456088 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2693724932 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2693724932 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.803869 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.803869 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952457 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952457 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857070 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.857070 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857070 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.857070 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 26217.218377 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 26217.218377 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37237.113250 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37237.113250 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 30601.937316 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 30601.937316 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 30601.937316 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 30601.937316 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9802 # number of writebacks +system.cpu4.l1c.writebacks::total 9802 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36657 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36657 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23918 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23918 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60575 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60575 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60575 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60575 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9982 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9982 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5360 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5360 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15342 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15342 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1052462662 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1052462662 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 963409159 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 963409159 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2015871821 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 2015871821 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2015871821 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 2015871821 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 780487806 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 780487806 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 2113182760 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 2113182760 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2893670566 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2893670566 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.808491 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.808491 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953630 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953630 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860184 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.860184 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860184 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.860184 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 28711.096435 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 28711.096435 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 40279.670499 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 40279.670499 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 33278.940504 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 33278.940504 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 33278.940504 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 33278.940504 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78189.521739 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78189.521739 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 394250.514925 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 394250.514925 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 188611.039369 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 188611.039369 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98777 # number of read accesses completed -system.cpu5.num_writes 55102 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22389 # number of replacements -system.cpu5.l1c.tags.tagsinuse 394.368473 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13612 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.597411 # Average number of references to valid blocks. +system.cpu5.num_reads 99659 # number of read accesses completed +system.cpu5.num_writes 54989 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22353 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.762821 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13360 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22726 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.587873 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 394.368473 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.770251 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.770251 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 338353 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 338353 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8788 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8788 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1200 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1200 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9988 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9988 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9988 # number of overall hits -system.cpu5.l1c.overall_hits::total 9988 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36608 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36608 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23815 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23815 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60423 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60423 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60423 # number of overall misses -system.cpu5.l1c.overall_misses::total 60423 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1017800983 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1017800983 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 926597102 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 926597102 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1944398085 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1944398085 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1944398085 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1944398085 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45396 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45396 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25015 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25015 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70411 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70411 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70411 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70411 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806415 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806415 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952029 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952029 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858147 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858147 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858147 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858147 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 27802.692936 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 27802.692936 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38908.129414 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 38908.129414 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 32179.767390 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 32179.767390 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 32179.767390 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 32179.767390 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1064852 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 392.762821 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.767115 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.767115 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 325 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.728516 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337942 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337942 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8666 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8666 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1136 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1136 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9802 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9802 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9802 # number of overall hits +system.cpu5.l1c.overall_hits::total 9802 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36641 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36641 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23834 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23834 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60475 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60475 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60475 # number of overall misses +system.cpu5.l1c.overall_misses::total 60475 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1106472248 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1106472248 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 994607245 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 994607245 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 2101079493 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 2101079493 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 2101079493 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 2101079493 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45307 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45307 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24970 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24970 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70277 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70277 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70277 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70277 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808727 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808727 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954505 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.954505 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860523 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860523 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860523 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860523 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 30197.654212 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 30197.654212 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 41730.605228 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 41730.605228 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 34742.943249 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 34742.943249 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 34742.943249 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 34742.943249 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1144155 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 61539 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61191 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 17.303694 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 18.698093 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9851 # number of writebacks -system.cpu5.l1c.writebacks::total 9851 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36608 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36608 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23815 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23815 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60423 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60423 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60423 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60423 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 961777191 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 961777191 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 890427492 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 890427492 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1852204683 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1852204683 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1852204683 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1852204683 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 736504009 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 736504009 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1948720715 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1948720715 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2685224724 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2685224724 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806415 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806415 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952029 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952029 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858147 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858147 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858147 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858147 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 26272.322744 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 26272.322744 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37389.355112 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37389.355112 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 30653.967579 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 30653.967579 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 30653.967579 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 30653.967579 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9829 # number of writebacks +system.cpu5.l1c.writebacks::total 9829 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36641 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36641 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23834 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23834 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60475 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60475 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60475 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9934 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9934 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5460 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5460 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15394 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15394 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1050521774 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1050521774 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 958365245 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 958365245 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2008887019 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 2008887019 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2008887019 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 2008887019 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 778256892 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 778256892 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 2141596587 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 2141596587 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2919853479 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2919853479 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808727 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808727 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954505 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954505 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860523 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860523 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860523 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860523 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 28670.663301 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 28670.663301 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 40210.004405 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 40210.004405 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 33218.470757 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 33218.470757 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 33218.470757 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 33218.470757 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78342.751359 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78342.751359 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 392233.807143 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392233.807143 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 189674.774523 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 189674.774523 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99339 # number of read accesses completed -system.cpu6.num_writes 55520 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22403 # number of replacements -system.cpu6.l1c.tags.tagsinuse 393.263413 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13582 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22789 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.595989 # Average number of references to valid blocks. +system.cpu6.num_reads 99691 # number of read accesses completed +system.cpu6.num_writes 55108 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22433 # number of replacements +system.cpu6.l1c.tags.tagsinuse 394.732703 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13465 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22813 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.590234 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 393.263413 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.768093 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.768093 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338803 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338803 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8815 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8815 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1164 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1164 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9979 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9979 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9979 # number of overall hits -system.cpu6.l1c.overall_hits::total 9979 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36385 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36385 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 24126 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 24126 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60511 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60511 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60511 # number of overall misses -system.cpu6.l1c.overall_misses::total 60511 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1008730718 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1008730718 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 936995994 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 936995994 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1945726712 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1945726712 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1945726712 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1945726712 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45200 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45200 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25290 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25290 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70490 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70490 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70490 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70490 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804978 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.804978 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953974 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953974 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858434 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858434 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858434 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858434 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 27723.807008 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 27723.807008 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38837.602338 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 38837.602338 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 32154.925749 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 32154.925749 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 32154.925749 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 32154.925749 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1063684 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 394.732703 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.770962 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.770962 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 337 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.742188 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 339043 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 339043 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8806 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8806 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1144 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1144 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9950 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9950 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9950 # number of overall hits +system.cpu6.l1c.overall_hits::total 9950 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36628 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36628 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23944 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23944 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60572 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60572 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60572 # number of overall misses +system.cpu6.l1c.overall_misses::total 60572 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1115774950 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1115774950 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 994580574 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 994580574 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 2110355524 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 2110355524 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 2110355524 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 2110355524 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45434 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45434 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25088 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25088 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70522 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70522 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70522 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70522 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806180 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806180 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954401 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954401 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858909 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858909 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858909 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858909 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 30462.349842 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 30462.349842 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 41537.778734 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 41537.778734 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 34840.446477 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 34840.446477 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 34840.446477 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 34840.446477 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1141787 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61545 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61213 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 17.283029 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 18.652688 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9842 # number of writebacks -system.cpu6.l1c.writebacks::total 9842 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36385 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36385 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24126 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 24126 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60511 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60511 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60511 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60511 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 953086366 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 953086366 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 900293024 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 900293024 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1853379390 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1853379390 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1853379390 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1853379390 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 738599910 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 738599910 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1965255677 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1965255677 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2703855587 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2703855587 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804978 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804978 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953974 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953974 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858434 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858434 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858434 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858434 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 26194.485805 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 26194.485805 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37316.298765 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37316.298765 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 30628.801210 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 30628.801210 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 30628.801210 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 30628.801210 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9839 # number of writebacks +system.cpu6.l1c.writebacks::total 9839 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36628 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36628 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23944 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23944 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60572 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60572 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60572 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60572 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9790 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9790 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5449 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5449 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15239 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15239 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1059827480 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1059827480 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 958175570 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 958175570 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2018003050 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 2018003050 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2018003050 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 2018003050 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 767222409 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 767222409 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 2138123651 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 2138123651 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2905346060 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2905346060 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806180 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806180 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954401 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954401 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858909 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858909 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858909 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858909 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 28934.898984 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 28934.898984 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 40017.355914 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 40017.355914 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 33315.773790 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 33315.773790 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 33315.773790 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 33315.773790 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78367.968233 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78367.968233 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 392388.264085 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392388.264085 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 190652.015224 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 190652.015224 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99565 # number of read accesses completed -system.cpu7.num_writes 55051 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22600 # number of replacements -system.cpu7.l1c.tags.tagsinuse 394.642544 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13380 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22986 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.582093 # Average number of references to valid blocks. +system.cpu7.num_reads 99881 # number of read accesses completed +system.cpu7.num_writes 55258 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22490 # number of replacements +system.cpu7.l1c.tags.tagsinuse 394.773487 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13394 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22887 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.585223 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 394.642544 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.770786 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.770786 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 349 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338392 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338392 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8664 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8664 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1142 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1142 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9806 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9806 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9806 # number of overall hits -system.cpu7.l1c.overall_hits::total 9806 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36635 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36635 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23923 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23923 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60558 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60558 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60558 # number of overall misses -system.cpu7.l1c.overall_misses::total 60558 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1023029462 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1023029462 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 929610099 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 929610099 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1952639561 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1952639561 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1952639561 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1952639561 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45299 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25065 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25065 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70364 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70364 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70364 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70364 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808737 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.808737 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954438 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954438 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.860639 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.860639 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.860639 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.860639 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 27924.920486 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 27924.920486 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 38858.424905 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 38858.424905 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 32244.122346 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 32244.122346 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 32244.122346 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 32244.122346 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1066072 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 394.773487 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.771042 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.771042 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 361 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338728 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338728 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8705 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8705 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1114 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1114 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9819 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9819 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9819 # number of overall hits +system.cpu7.l1c.overall_hits::total 9819 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36637 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36637 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23983 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23983 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60620 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60620 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60620 # number of overall misses +system.cpu7.l1c.overall_misses::total 60620 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1106293724 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1106293724 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1002572296 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1002572296 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 2108866020 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 2108866020 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 2108866020 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 2108866020 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45342 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45342 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25097 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25097 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70439 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70439 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70439 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70439 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808015 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.808015 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955612 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955612 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.860603 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.860603 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.860603 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.860603 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 30196.078391 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 30196.078391 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 41803.456448 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 41803.456448 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 34788.288024 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 34788.288024 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 34788.288024 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 34788.288024 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1141532 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 61535 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 61288 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 17.324645 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 18.625702 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9831 # number of writebacks -system.cpu7.l1c.writebacks::total 9831 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36635 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36635 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23923 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23923 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60558 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60558 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60558 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60558 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 966974672 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 966974672 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 893289987 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 893289987 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1860264659 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1860264659 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1860264659 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1860264659 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 731988929 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 731988929 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1960595657 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1960595657 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2692584586 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2692584586 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808737 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808737 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954438 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954438 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860639 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.860639 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860639 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.860639 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 26394.832046 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 26394.832046 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 37340.215985 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 37340.215985 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 30718.726824 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 30718.726824 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 30718.726824 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 30718.726824 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9784 # number of writebacks +system.cpu7.l1c.writebacks::total 9784 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36637 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36637 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23983 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60620 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60620 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60620 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60620 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9862 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9862 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5465 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5465 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15327 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15327 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1050368666 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1050368666 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 966121280 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 966121280 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2016489946 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 2016489946 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2016489946 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 2016489946 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 770060879 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 770060879 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 2135523645 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 2135523645 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2905584524 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2905584524 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808015 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808015 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955612 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955612 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860603 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.860603 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860603 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.860603 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 28669.614488 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 28669.614488 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 40283.587541 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 40283.587541 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 33264.433289 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 33264.433289 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 33264.433289 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 33264.433289 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 78083.642162 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78083.642162 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 390763.704483 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 390763.704483 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 189572.944738 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 189572.944738 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 12974 # number of replacements -system.l2c.tags.tagsinuse 782.339791 # Cycle average of tags in use -system.l2c.tags.total_refs 149980 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 13746 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.910810 # Average number of references to valid blocks. +system.l2c.tags.replacements 12865 # number of replacements +system.l2c.tags.tagsinuse 778.482244 # Cycle average of tags in use +system.l2c.tags.total_refs 150454 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 13664 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.010978 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 728.962494 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.892190 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.186949 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.375204 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.806314 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.399875 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.389081 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.432209 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.895475 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.711877 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007019 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006226 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006647 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006250 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006239 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006281 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006734 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.764004 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 772 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 551 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1963370 # Number of tag accesses -system.l2c.tags.data_accesses 1963370 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10704 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10790 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10626 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10750 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10729 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10684 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10653 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10669 # number of ReadReq hits -system.l2c.ReadReq_hits::total 85605 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 75955 # number of Writeback hits -system.l2c.Writeback_hits::total 75955 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 335 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 339 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 335 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 336 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 340 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 357 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 325 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 325 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2692 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1953 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1945 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1922 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1952 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1880 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1895 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15383 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12657 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12735 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12548 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12702 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12609 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12579 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12571 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12587 # number of demand (read+write) hits -system.l2c.demand_hits::total 100988 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12657 # number of overall hits -system.l2c.overall_hits::cpu1 12735 # number of overall hits -system.l2c.overall_hits::cpu2 12548 # number of overall hits -system.l2c.overall_hits::cpu3 12702 # number of overall hits -system.l2c.overall_hits::cpu4 12609 # number of overall hits -system.l2c.overall_hits::cpu5 12579 # number of overall hits -system.l2c.overall_hits::cpu6 12571 # number of overall hits -system.l2c.overall_hits::cpu7 12587 # number of overall hits -system.l2c.overall_hits::total 100988 # number of overall hits -system.l2c.ReadReq_misses::cpu0 670 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 709 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 686 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 695 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 670 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 684 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 670 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 712 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5496 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1986 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1941 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1876 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1923 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1955 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1959 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1992 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1968 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15600 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4451 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4405 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4381 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4368 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4432 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4389 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4443 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4389 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 35258 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5121 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5114 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5067 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5063 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5102 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5073 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5113 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5101 # number of demand (read+write) misses -system.l2c.demand_misses::total 40754 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5121 # number of overall misses -system.l2c.overall_misses::cpu1 5114 # number of overall misses -system.l2c.overall_misses::cpu2 5067 # number of overall misses -system.l2c.overall_misses::cpu3 5063 # number of overall misses -system.l2c.overall_misses::cpu4 5102 # number of overall misses -system.l2c.overall_misses::cpu5 5073 # number of overall misses -system.l2c.overall_misses::cpu6 5113 # number of overall misses -system.l2c.overall_misses::cpu7 5101 # number of overall misses -system.l2c.overall_misses::total 40754 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 40741945 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 44011935 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 41982431 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 42625443 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 40765941 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 42066438 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 41647921 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 44074423 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 337916477 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 57100999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 55902999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 53747499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 56068000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 57148499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 57843500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 58231500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 56606999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 452649995 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 243244959 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 240870461 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 239571460 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 239260458 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 242194954 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 240150463 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 242838464 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 239503467 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1927634686 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 283986904 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 284882396 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 281553891 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 281885901 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 282960895 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 282216901 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 284486385 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 283577890 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2265551163 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 283986904 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 284882396 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 281553891 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 281885901 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 282960895 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 282216901 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 284486385 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 283577890 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2265551163 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11374 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11499 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11312 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11445 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11399 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11368 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11323 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11381 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 91101 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 75955 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 75955 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2321 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2280 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2211 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2259 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2295 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2293 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18292 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6404 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6350 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6303 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6320 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6312 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6284 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6361 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6307 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50641 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17778 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17849 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17615 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17765 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17711 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17652 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17684 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17688 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 141742 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17778 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17849 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17615 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17765 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17711 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17652 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17684 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17688 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 141742 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.058906 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.061658 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.060644 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.060725 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.058777 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.060169 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.059172 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.062560 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.060329 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.855666 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.851316 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.848485 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.851262 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.851852 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.845855 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.859732 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.858264 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.852832 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.695034 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.693701 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.695066 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.691139 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.702155 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.698440 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.698475 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.695893 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.696234 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.288053 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.286515 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.287653 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.284999 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.288070 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.287390 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.289131 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.288388 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.287522 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.288053 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.286515 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.287653 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.284999 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.288070 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.287390 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.289131 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.288388 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.287522 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 60808.873134 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 62076.071932 # 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average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 29527.054620 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29232.680723 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28763.719004 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29016.025321 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 54649.507751 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 54681.148922 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 54684.195389 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 54775.745879 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 54646.875903 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54716.441786 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 54656.417736 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 54569.028708 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 54672.264054 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55455.361062 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 55706.373876 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 55566.191237 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55675.666798 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 55460.779106 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55631.165188 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 55639.817133 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55592.607332 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 55590.890784 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55455.361062 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 6.516565 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.767835 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.065793 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.555833 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.650782 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.161030 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.709195 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.005802 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006453 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006364 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006609 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.005924 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006402 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006495 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006993 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.760237 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 799 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 529 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.780273 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1961721 # Number of tag accesses +system.l2c.tags.data_accesses 1961721 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10688 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10718 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10681 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10576 # 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number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 59492999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 481588993 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 251503956 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 247640970 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 250450295 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 250803462 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 252427455 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 254173970 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 245128968 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 257532451 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2009661527 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 289670904 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 90816 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 75954 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 75954 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2275 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2310 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2295 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2305 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2298 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2265 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2248 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2278 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18274 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6311 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6279 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6272 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6327 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6411 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6407 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6262 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6466 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50735 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17631 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17684 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17644 # 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miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.887146 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.885033 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.874238 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.875055 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.875890 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.878841 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.880048 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.727460 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.722090 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.730548 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.724988 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.717829 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.726705 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.715905 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.726879 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.724056 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.296240 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.295239 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.298855 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.298473 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.294470 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.300525 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.291909 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.303873 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.297448 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.296240 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.295239 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.298855 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.298473 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.294470 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.300525 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.291909 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.303873 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.297448 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 60390.740506 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61394.381368 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 61453.606368 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61192.859112 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 60431.632777 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 61890.053812 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61174.914706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 60878.852436 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61108.128143 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 30275.160635 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 30610.754810 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 30825.884086 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 30288.479902 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28343.454455 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 30092.078708 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 29379.632301 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29716.782717 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29945.839634 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 54781.955130 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 54618.652404 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 54659.601702 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 54677.013734 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 54851.685137 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54590.629296 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 54679.671648 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54794.138511 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54706.996788 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55460.636416 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55510.229841 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 55549.921676 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55489.007443 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55550.636951 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55507.683756 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 55535.136549 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55580.935532 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55523.253539 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55460.636416 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55510.229841 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 55549.921676 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55489.007443 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55550.636951 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55507.683756 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 55535.136549 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55580.935532 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55523.253539 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 8422 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1439 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1138 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.295344 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.400703 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6042 # number of writebacks -system.l2c.writebacks::total 6042 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6144 # number of writebacks +system.l2c.writebacks::total 6144 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 4 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu2 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::total 23 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 662 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 705 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 678 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 691 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 663 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 677 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 662 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 707 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5445 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1985 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1941 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1876 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1922 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1955 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1959 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1992 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1967 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15597 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4445 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4400 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4378 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4367 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4430 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4387 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4441 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4387 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 35235 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5107 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5105 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5056 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5058 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5093 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5064 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5103 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5094 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40680 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5107 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5105 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5056 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5058 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5093 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5064 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5103 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5094 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40680 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 32455941 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 35292936 # 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number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 81980984 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 82268488 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 83402478 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 82404992 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 653716911 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 189131446 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 187405945 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 186408946 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 186284944 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 188429940 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 186911948 # 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number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 419015931 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 413234441 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 407408946 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 415648431 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 408376439 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 410035928 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 406831940 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3293198967 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 229215970 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 228786954 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 227259971 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 236423452 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 233573451 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 234334469 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 233635458 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 232899980 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1856129705 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 641862881 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 647802885 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 640494412 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 643832398 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 649221882 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 642710908 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 643671386 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 639731920 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5149328672 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.058203 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.061310 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.059936 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.060376 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.058163 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.059553 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.058465 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.062121 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.059769 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.855235 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.851316 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.848485 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.850819 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.851852 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.845855 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.859732 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.857828 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.852668 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.694097 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.692913 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.694590 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.690981 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.701838 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.698122 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.698161 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.695576 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.695780 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.287265 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.286010 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.287028 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.284717 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.287561 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.286880 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.288566 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.287992 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.287000 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.287265 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.286010 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.287028 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.284717 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.287561 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.286880 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.288566 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.287992 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.287000 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49027.101208 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50060.902128 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49440.893805 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49444.918958 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49079.093514 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49589.264402 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 50408.490937 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50010.496464 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49637.365473 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41847.602519 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41908.803709 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41926.437633 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41932.098335 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41934.007161 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41995.144461 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41868.713855 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41893.742755 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41912.990383 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42549.256693 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42592.260227 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42578.562357 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42657.417907 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42534.975169 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42605.869159 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42556.394055 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42455.650558 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 42566.171534 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 43388.953789 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 43623.678942 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 43498.787975 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 43584.694148 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 43386.879835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 43539.470774 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 43575.027827 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 43504.193168 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 43512.647714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 43388.953789 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 43623.678942 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 43498.787975 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 43584.694148 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 43386.879835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 43539.470774 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 43575.027827 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 43504.193168 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 43512.647714 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.demand_mshr_hits::cpu0 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 63 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 628 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 680 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 688 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 646 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 652 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 666 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 676 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 693 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5329 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 2017 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2027 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2034 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2040 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2008 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1982 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1968 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2002 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16078 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4588 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4530 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4579 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4586 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4599 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4651 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4482 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4697 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 36712 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5216 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5210 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5267 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5232 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5251 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5317 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5158 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5390 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 42041 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5216 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5210 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5267 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5232 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5251 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5317 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5158 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5390 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 42041 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0 9956 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1 10009 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2 9898 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3 9906 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu4 9982 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu5 9934 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu6 9790 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu7 9862 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 79337 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0 5414 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1 5436 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2 5494 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3 5519 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu4 5358 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu5 5458 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu6 5448 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu7 5462 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 43589 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15370 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15445 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15392 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 15425 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu4 15340 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu5 15392 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu6 15238 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu7 15324 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 122926 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 30458949 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 33700940 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 34051940 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 31884439 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 31746444 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 33289946 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 33296940 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 33931439 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 262361037 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 84760496 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 85183996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 85374489 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 85565499 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 84458998 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 83295996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 82516991 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 84106992 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 675263457 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 195759954 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 192669961 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 194828295 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 195239452 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 196619949 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 197755466 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 190831957 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 200614450 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1564319484 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 226218903 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 226370901 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 228880235 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 227123891 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 228366393 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 231045412 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 224128897 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 234545889 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1826680521 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 226218903 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 226370901 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 228880235 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 227123891 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 228366393 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 231045412 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 224128897 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 234545889 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1826680521 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 420391962 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 422439462 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 417792957 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 418505281 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 421118468 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 419294453 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 413123964 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 416090788 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3348757335 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 237106474 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 237782975 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 241705476 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 241076980 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 235943478 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 241042480 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 238750464 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 240064477 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1913472804 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 657498436 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 660222437 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 659498433 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 659582261 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 657061946 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 660336933 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 651874428 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 656155265 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5262230139 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.055477 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.059623 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.060499 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.057530 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.056918 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.058876 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059168 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061338 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.058679 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.886593 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.877489 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.886275 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.885033 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.873803 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.875055 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.875445 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.878841 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.879829 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726985 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.721452 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.730070 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.724830 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.717361 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.725925 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.715746 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.726415 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.723603 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.295843 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.294617 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.298515 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.298018 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.293910 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.300073 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.291627 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.303423 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.297002 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.295843 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.294617 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.298515 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.298018 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.293910 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.300073 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.291627 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.303423 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.297002 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48501.511146 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49560.205882 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49494.098837 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49356.716718 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48690.865031 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49984.903904 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49255.828402 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 48963.115440 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49232.696003 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42023.052058 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42024.665022 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41973.691740 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41943.872059 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42061.253984 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42026.234107 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41929.365346 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42011.484515 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41999.219866 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42667.819093 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42532.000221 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42548.219043 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42572.928914 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42752.761252 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42518.913352 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42577.411200 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42711.187992 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42610.576487 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 43370.188459 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 43449.309213 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 43455.522119 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43410.529625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43490.076747 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 43454.092910 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 43452.674874 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 43515.007236 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 43449.977903 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 43370.188459 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 43449.309213 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 43455.522119 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43410.529625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43490.076747 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 43454.092910 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 43452.674874 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 43515.007236 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 43449.977903 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 42224.986139 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 42205.960835 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 42209.836027 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 42247.656067 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 42187.784813 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 42208.018220 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 42198.566292 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 42191.319002 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 42209.276063 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 43795.063539 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 43742.269132 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 43994.444121 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 43681.279217 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 44035.736842 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 44163.151337 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 43823.506608 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 43951.753387 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 43898.066118 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 42778.037476 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 42746.677695 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 42846.831666 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 42760.600389 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 42833.242894 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 42901.308017 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 42779.526710 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 42818.798290 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 42808.113328 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 123330 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 121282 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 252480 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 249408 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 84079 # Transaction distribution -system.membus.trans_dist::ReadResp 84076 # Transaction distribution -system.membus.trans_dist::WriteReq 43401 # Transaction distribution -system.membus.trans_dist::WriteResp 43399 # Transaction distribution -system.membus.trans_dist::Writeback 6042 # Transaction distribution -system.membus.trans_dist::UpgradeReq 58662 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47800 # Transaction distribution -system.membus.trans_dist::ReadExReq 50251 # Transaction distribution -system.membus.trans_dist::ReadExResp 3038 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 420748 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1051128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1051128 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 58073 # Total snoops (count) -system.membus.snoop_fanout::samples 123330 # Request fanout histogram +system.membus.trans_dist::ReadReq 84654 # Transaction distribution +system.membus.trans_dist::ReadResp 84652 # Transaction distribution +system.membus.trans_dist::WriteReq 43588 # Transaction distribution +system.membus.trans_dist::WriteResp 43585 # Transaction distribution +system.membus.trans_dist::Writeback 6143 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60492 # Transaction distribution +system.membus.trans_dist::UpgradeResp 49595 # Transaction distribution +system.membus.trans_dist::ReadExReq 50638 # Transaction distribution +system.membus.trans_dist::ReadExResp 3207 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 426554 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 426554 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1061863 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1061863 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 58325 # Total snoops (count) +system.membus.snoop_fanout::samples 252480 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 123330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 252480 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 123330 # Request fanout histogram -system.membus.reqLayer0.occupancy 349185814 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 47.8 # Layer utilization (%) -system.membus.respLayer0.occupancy 311191349 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 42.6 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 561297 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 261699 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 297550 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 252480 # Request fanout histogram +system.membus.reqLayer0.occupancy 472884580 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 59.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 313892142 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 39.7 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 684630 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 383351 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 298207 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 370588 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370576 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43402 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43399 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 75955 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29152 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29150 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162499 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162497 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120510 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120652 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120226 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120519 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120569 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120393 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120447 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120346 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 963662 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1766434 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1757944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1752931 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1758190 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1756878 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1755329 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1752897 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1753790 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14054393 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 323559 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 561297 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.683086 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.176196 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 371695 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371689 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43589 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43585 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 75954 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29169 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29167 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162397 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162391 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120614 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120783 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120664 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120646 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120853 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120726 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120516 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120736 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 965538 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1750933 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1748576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754368 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1762730 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756512 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757509 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1755676 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14042920 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 324098 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 684630 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.384232 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.250303 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 53942 9.61% 9.61% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 251180 44.75% 54.36% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 141382 25.19% 79.55% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 68926 12.28% 91.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 30158 5.37% 97.20% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 11557 2.06% 99.26% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 3492 0.62% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 660 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 176832 25.83% 25.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 250927 36.65% 62.48% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 141295 20.64% 83.12% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 69195 10.11% 93.23% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 30377 4.44% 97.66% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 11672 1.70% 99.37% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 3607 0.53% 99.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 725 0.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 561297 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 720580520 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 100512947 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 100775889 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 100644932 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 100575951 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 100528413 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 100450921 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 100623449 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 100655480 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 13.8 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 684630 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 782327755 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 99.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 100591456 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 12.7 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 100721944 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 100768962 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 100555978 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 12.7 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 100847968 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 100723976 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 100740497 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 100846524 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 12.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- |