diff options
Diffstat (limited to 'tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt')
| -rw-r--r-- | tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt | 3448 |
1 files changed, 1728 insertions, 1720 deletions
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index c01cc2902..96f88f923 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1809 +1,1817 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000790 # Number of seconds simulated -sim_ticks 789792500 # Number of ticks simulated -final_tick 789792500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000889 # Number of seconds simulated +sim_ticks 888991000 # Number of ticks simulated +final_tick 888991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 129975147 # Simulator tick rate (ticks/s) -host_mem_usage 221936 # Number of bytes of host memory used -host_seconds 6.08 # Real time elapsed on the host +host_tick_rate 170326912 # Simulator tick rate (ticks/s) +host_mem_usage 278304 # Number of bytes of host memory used +host_seconds 5.22 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 78179 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 78681 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 79146 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 76465 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 76157 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 75918 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 79229 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 81414 # Number of bytes read from this memory -system.physmem.bytes_read::total 625189 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 393152 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5414 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5436 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5494 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5519 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5358 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5458 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5447 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5462 # Number of bytes written to this memory -system.physmem.bytes_written::total 436740 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11021 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10945 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11015 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10874 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10980 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87862 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6143 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5414 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5436 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5494 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5519 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5358 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5458 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5447 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5462 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49731 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 98986759 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 99622369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 100211131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 96816569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 96426593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 96123982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 100316222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 103082772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 791586398 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 497791509 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 6854965 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6882820 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 6956257 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 6987911 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 6784060 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 6910676 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 6896748 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 6915741 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 552980688 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 497791509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 105841724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 106505190 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 107167389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 103804480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 103210653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 103034658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 107212970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 109998512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1344567086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 77301 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 77008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 78427 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 77571 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 81605 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 77234 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 80454 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 78765 # Number of bytes read from this memory +system.physmem.bytes_read::total 628365 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 396032 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5354 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5486 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5463 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5457 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5585 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5519 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5444 # Number of bytes written to this memory +system.physmem.bytes_written::total 439804 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10773 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10795 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11043 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11171 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10895 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10839 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10977 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87447 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6188 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5354 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5486 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5463 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5457 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5585 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5519 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5444 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49960 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 86953636 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 86624049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 88220241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 87257351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 91795080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 86878270 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 90500354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 88600447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 706829428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 445484825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 6022558 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6171041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 6145169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 6138420 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 6146294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 6282403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 6208162 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 6123797 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 494722669 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 445484825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 92976194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 92795090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 94365410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 93395771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 97941374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 93160673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 96708516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 94724244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1201552097 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99211 # number of read accesses completed -system.cpu0.num_writes 54990 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22470 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.865816 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13332 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22858 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.583253 # Average number of references to valid blocks. +system.cpu0.num_reads 99131 # number of read accesses completed +system.cpu0.num_writes 55164 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22535 # number of replacements +system.cpu0.l1c.tags.tagsinuse 395.025918 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13450 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22939 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.586338 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.865816 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.769269 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.769269 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 352 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 337265 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 337265 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8594 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8594 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1143 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1143 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9737 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9737 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9737 # number of overall hits -system.cpu0.l1c.overall_hits::total 9737 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36367 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36367 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 24030 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 24030 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60397 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60397 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60397 # number of overall misses -system.cpu0.l1c.overall_misses::total 60397 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1097985534 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1097985534 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1003527320 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1003527320 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 2101512854 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 2101512854 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 2101512854 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 2101512854 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44961 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44961 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25173 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25173 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70134 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70134 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70134 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70134 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808857 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.808857 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954594 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954594 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.861166 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.861166 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.861166 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.861166 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 30191.809443 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 30191.809443 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 41761.436538 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 41761.436538 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 34794.987400 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 34794.987400 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 34794.987400 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 34794.987400 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1144726 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 395.025918 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.771535 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.771535 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 341 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338659 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338659 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8591 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8591 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1192 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1192 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9783 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9783 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9783 # number of overall hits +system.cpu0.l1c.overall_hits::total 9783 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36665 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36665 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23983 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23983 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60648 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60648 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60648 # number of overall misses +system.cpu0.l1c.overall_misses::total 60648 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1205183022 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1205183022 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1064148669 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1064148669 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 2269331691 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 2269331691 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 2269331691 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 2269331691 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45256 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45256 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25175 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25175 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70431 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70431 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70431 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70431 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.810169 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.810169 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952651 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.952651 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.861098 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.861098 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.861098 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.861098 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 32870.121969 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 32870.121969 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 44370.957303 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 44370.957303 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 37418.079590 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 37418.079590 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 37418.079590 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 37418.079590 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1129963 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 61078 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 56549 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 18.742035 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 19.982016 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9946 # number of writebacks -system.cpu0.l1c.writebacks::total 9946 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36367 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36367 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24030 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 24030 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60397 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60397 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60397 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60397 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9956 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9956 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5416 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5416 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15372 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15372 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1042449014 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1042449014 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 966947420 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 966947420 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2009396434 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 2009396434 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2009396434 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 2009396434 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 778948863 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 778948863 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 2127994240 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 2127994240 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2906943103 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2906943103 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808857 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808857 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954594 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954594 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861166 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.861166 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861166 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.861166 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 28664.696401 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 28664.696401 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 40239.176862 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 40239.176862 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 33269.805355 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 33269.805355 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 33269.805355 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 33269.805355 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78239.138509 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78239.138509 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 392908.833087 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392908.833087 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 189106.368918 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 189106.368918 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9979 # number of writebacks +system.cpu0.l1c.writebacks::total 9979 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36665 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36665 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23983 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60648 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60648 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9718 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9718 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5355 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5355 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15073 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15073 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1168518022 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1168518022 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1040166669 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1040166669 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2208684691 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 2208684691 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2208684691 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 2208684691 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 789521900 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 789521900 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1493953369 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1493953369 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2283475269 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2283475269 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.810169 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.810169 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952651 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952651 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.861098 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.861098 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 31870.121969 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 31870.121969 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 43370.998999 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 43370.998999 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 81243.249640 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81243.249640 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 278982.888702 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 278982.888702 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 151494.411796 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 151494.411796 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 55318 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22177 # number of replacements -system.cpu1.l1c.tags.tagsinuse 393.980771 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13598 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22566 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.602588 # Average number of references to valid blocks. +system.cpu1.num_reads 99860 # number of read accesses completed +system.cpu1.num_writes 55211 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22541 # number of replacements +system.cpu1.l1c.tags.tagsinuse 395.711444 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13500 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22934 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.588646 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 393.980771 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.769494 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.769494 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 357 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338430 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338430 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8884 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8884 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1068 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1068 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9952 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9952 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9952 # number of overall hits -system.cpu1.l1c.overall_hits::total 9952 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36538 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36538 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23930 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23930 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60468 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60468 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60468 # number of overall misses -system.cpu1.l1c.overall_misses::total 60468 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1108002821 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1108002821 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 993849096 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 993849096 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 2101851917 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 2101851917 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 2101851917 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 2101851917 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45422 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45422 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24998 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24998 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70420 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70420 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70420 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70420 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804412 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.804412 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.957277 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.957277 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.858677 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.858677 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.858677 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.858677 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 30324.670781 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 30324.670781 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 41531.512578 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 41531.512578 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 34759.739317 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 34759.739317 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 34759.739317 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 34759.739317 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1147241 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 395.711444 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.772874 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.772874 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338432 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338432 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8752 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8752 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1139 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1139 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9891 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9891 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9891 # number of overall hits +system.cpu1.l1c.overall_hits::total 9891 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36537 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36537 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23971 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23971 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60508 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60508 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60508 # number of overall misses +system.cpu1.l1c.overall_misses::total 60508 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1195916774 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1195916774 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 1059745891 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 1059745891 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 2255662665 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 2255662665 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 2255662665 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 2255662665 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45289 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45289 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25110 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25110 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70399 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70399 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70399 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70399 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806752 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.806752 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954640 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954640 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.859501 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.859501 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.859501 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.859501 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 32731.663081 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 32731.663081 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 44209.498602 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 44209.498602 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 37278.750992 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 37278.750992 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 37278.750992 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 37278.750992 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1120827 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 61428 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 56192 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 18.676190 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 19.946380 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9780 # number of writebacks -system.cpu1.l1c.writebacks::total 9780 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36538 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36538 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23930 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23930 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60468 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60468 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60468 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60468 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 10010 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 10010 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5438 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5438 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15448 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15448 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1052180887 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1052180887 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 957433148 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 957433148 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2009614035 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 2009614035 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2009614035 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 2009614035 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 780874824 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 780874824 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 2141613646 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 2141613646 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2922488470 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2922488470 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804412 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804412 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.957277 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.957277 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858677 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.858677 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858677 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.858677 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 28796.893289 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 28796.893289 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 40009.742917 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 40009.742917 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 33234.339403 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 33234.339403 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 33234.339403 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 33234.339403 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78009.472927 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78009.472927 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 393823.767194 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 393823.767194 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 189182.319394 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 189182.319394 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9897 # number of writebacks +system.cpu1.l1c.writebacks::total 9897 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36537 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36537 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23971 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60508 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60508 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60508 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60508 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9744 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9744 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5487 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5487 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15231 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15231 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1159382774 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1159382774 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1035775891 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1035775891 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2195158665 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 2195158665 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2195158665 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 2195158665 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 792485431 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 792485431 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1532713252 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1532713252 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2325198683 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2325198683 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806752 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806752 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954640 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954640 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.859501 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.859501 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 31731.745190 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 31731.745190 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 43209.540320 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 43209.540320 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 81330.606630 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81330.606630 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 279335.383999 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279335.383999 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 152662.246931 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 152662.246931 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99906 # number of read accesses completed -system.cpu2.num_writes 55186 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22429 # number of replacements -system.cpu2.l1c.tags.tagsinuse 394.168243 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13360 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22814 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.585605 # Average number of references to valid blocks. +system.cpu2.num_reads 99820 # number of read accesses completed +system.cpu2.num_writes 54950 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22307 # number of replacements +system.cpu2.l1c.tags.tagsinuse 395.344704 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13648 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22708 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.601022 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 394.168243 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.769860 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.769860 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 385 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.751953 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338029 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338029 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8660 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8660 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1124 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1124 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9784 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9784 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9784 # number of overall hits -system.cpu2.l1c.overall_hits::total 9784 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36507 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36507 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 24000 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 24000 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60507 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60507 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60507 # number of overall misses -system.cpu2.l1c.overall_misses::total 60507 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1106428919 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1106428919 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1000960978 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1000960978 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 2107389897 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 2107389897 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 2107389897 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 2107389897 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45167 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45167 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25124 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25124 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70291 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70291 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70291 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70291 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808267 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.808267 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955262 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955262 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.860807 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.860807 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.860807 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.860807 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 30307.308708 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 30307.308708 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 41706.707417 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 41706.707417 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 34828.861074 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 34828.861074 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 34828.861074 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 34828.861074 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1143492 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 395.344704 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.772158 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.772158 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 349 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 339436 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 339436 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8860 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8860 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1133 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1133 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9993 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9993 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9993 # number of overall hits +system.cpu2.l1c.overall_hits::total 9993 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36664 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36664 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23971 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23971 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60635 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60635 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60635 # number of overall misses +system.cpu2.l1c.overall_misses::total 60635 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1194013761 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1194013761 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1064419870 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1064419870 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 2258433631 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 2258433631 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 2258433631 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 2258433631 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45524 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45524 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25104 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25104 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70628 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70628 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70628 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70628 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805377 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805377 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954868 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954868 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858512 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858512 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858512 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858512 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 32566.380128 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 32566.380128 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 44404.483334 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 44404.483334 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 37246.369770 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 37246.369770 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 37246.369770 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 37246.369770 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1131174 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 61259 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 56579 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 18.666514 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 19.992824 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9834 # number of writebacks -system.cpu2.l1c.writebacks::total 9834 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36507 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36507 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24000 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60507 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60507 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60507 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60507 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9899 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9899 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5496 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5496 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15395 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15395 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1050702877 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1050702877 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 964435030 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 964435030 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2015137907 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 2015137907 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2015137907 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 2015137907 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 774345338 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 774345338 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 2129438676 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 2129438676 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2903784014 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2903784014 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808267 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808267 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955262 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955262 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860807 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.860807 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860807 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.860807 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 28780.860575 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 28780.860575 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 40184.792917 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 40184.792917 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 33304.211199 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 33304.211199 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 33304.211199 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 33304.211199 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78224.602283 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78224.602283 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 387452.451965 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 387452.451965 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 188618.643326 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 188618.643326 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9745 # number of writebacks +system.cpu2.l1c.writebacks::total 9745 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36664 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36664 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23971 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60635 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60635 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60635 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60635 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9885 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5464 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15349 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15349 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1157350761 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1157350761 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1040448870 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1040448870 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2197799631 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 2197799631 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2197799631 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 2197799631 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 800475880 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 800475880 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1507844825 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1507844825 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2308320705 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2308320705 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805377 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805377 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954868 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954868 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858512 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858512 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 31566.407402 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 31566.407402 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 43404.483334 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 43404.483334 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 80978.844714 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80978.844714 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 275959.887445 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 275959.887445 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 150388.996352 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 150388.996352 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99687 # number of read accesses completed -system.cpu3.num_writes 54914 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22514 # number of replacements -system.cpu3.l1c.tags.tagsinuse 394.486423 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13398 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22905 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.584938 # Average number of references to valid blocks. +system.cpu3.num_reads 99181 # number of read accesses completed +system.cpu3.num_writes 54913 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22385 # number of replacements +system.cpu3.l1c.tags.tagsinuse 394.599023 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13320 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22779 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.584749 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 394.486423 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.770481 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.770481 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 351 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337490 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337490 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8775 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8775 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1091 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1091 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9866 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9866 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9866 # number of overall hits -system.cpu3.l1c.overall_hits::total 9866 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36393 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36393 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23929 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23929 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60322 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60322 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60322 # number of overall misses -system.cpu3.l1c.overall_misses::total 60322 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1101223942 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1101223942 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 999641040 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 999641040 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 2100864982 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 2100864982 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 2100864982 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 2100864982 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45168 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45168 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25020 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25020 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70188 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70188 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70188 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70188 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805725 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.805725 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956395 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.956395 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.859435 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.859435 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.859435 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.859435 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 30259.224082 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 30259.224082 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 41775.295248 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 41775.295248 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 34827.508736 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 34827.508736 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 34827.508736 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 34827.508736 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1140042 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 394.599023 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.770701 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.770701 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 337671 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 337671 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8526 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8526 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1172 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1172 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9698 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9698 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9698 # number of overall hits +system.cpu3.l1c.overall_hits::total 9698 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36662 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36662 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23851 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23851 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60513 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60513 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60513 # number of overall misses +system.cpu3.l1c.overall_misses::total 60513 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1194465114 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1194465114 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 1056306776 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 1056306776 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 2250771890 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 2250771890 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 2250771890 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 2250771890 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45188 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45188 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25023 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25023 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70211 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70211 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70211 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70211 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.811322 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.811322 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953163 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.953163 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.861873 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.861873 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.861873 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.861873 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 32580.467896 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 32580.467896 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 44287.735357 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 44287.735357 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 37194.848875 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 37194.848875 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 37194.848875 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 37194.848875 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1130263 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 60968 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 56535 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 18.699022 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 19.992270 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9981 # number of writebacks -system.cpu3.l1c.writebacks::total 9981 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36393 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36393 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23929 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23929 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60322 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60322 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60322 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60322 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9906 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9906 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5522 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5522 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15428 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15428 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1045674368 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1045674368 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 963227618 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 963227618 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2008901986 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 2008901986 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2008901986 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 2008901986 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 776644993 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 776644993 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 2134037166 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 2134037166 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2910682159 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2910682159 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805725 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805725 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956395 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956395 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859435 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.859435 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859435 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.859435 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 28732.843349 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 28732.843349 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 40253.567554 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 40253.567554 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 33302.973807 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 33302.973807 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 33302.973807 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 33302.973807 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78401.473148 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78401.473148 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 386460.913799 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 386460.913799 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 188662.312613 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 188662.312613 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9719 # number of writebacks +system.cpu3.l1c.writebacks::total 9719 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36662 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36662 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23851 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23851 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60513 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60513 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60513 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60513 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9988 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9988 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5458 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5458 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15446 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15446 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1157803114 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1157803114 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1032457776 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1032457776 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2190260890 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 2190260890 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2190260890 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 2190260890 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 807637161 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 807637161 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1532365329 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1532365329 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2340002490 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2340002490 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.811322 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.811322 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953163 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953163 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.861873 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.861873 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 31580.467896 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 31580.467896 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 43287.819211 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 43287.819211 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 80860.748999 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80860.748999 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 280755.831623 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 280755.831623 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 151495.694031 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 151495.694031 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99646 # number of read accesses completed -system.cpu4.num_writes 55076 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22475 # number of replacements -system.cpu4.l1c.tags.tagsinuse 394.666578 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13432 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.587243 # Average number of references to valid blocks. +system.cpu4.num_reads 99531 # number of read accesses completed +system.cpu4.num_writes 55217 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22414 # number of replacements +system.cpu4.l1c.tags.tagsinuse 393.784167 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13493 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22803 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.591720 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 394.666578 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.770833 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.770833 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 352 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 338590 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 338590 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8683 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8683 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1163 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1163 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9846 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9846 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9846 # number of overall hits -system.cpu4.l1c.overall_hits::total 9846 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36657 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36657 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23918 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23918 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60575 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60575 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60575 # number of overall misses -system.cpu4.l1c.overall_misses::total 60575 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1108449638 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1108449638 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 999797609 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 999797609 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 2108247247 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 2108247247 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 2108247247 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 2108247247 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45340 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45340 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25081 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25081 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70421 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70421 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70421 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70421 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.808491 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.808491 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953630 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953630 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.860184 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.860184 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.860184 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.860184 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 30238.416619 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 30238.416619 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 41801.053976 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 41801.053976 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 34803.916583 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 34803.916583 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 34803.916583 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 34803.916583 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1151337 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 393.784167 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.769110 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.769110 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 47 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337660 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337660 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8661 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8661 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1197 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1197 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9858 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9858 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9858 # number of overall hits +system.cpu4.l1c.overall_hits::total 9858 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36381 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36381 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 24008 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 24008 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60389 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60389 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60389 # number of overall misses +system.cpu4.l1c.overall_misses::total 60389 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1185615268 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1185615268 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 1062060825 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 1062060825 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 2247676093 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 2247676093 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 2247676093 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 2247676093 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45042 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45042 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25205 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25205 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70247 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70247 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70247 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70247 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807713 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807713 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952509 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952509 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859667 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859667 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859667 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859667 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 32588.858690 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 32588.858690 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 44237.788446 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 44237.788446 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 37219.958817 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 37219.958817 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 37219.958817 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 37219.958817 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1133314 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 61602 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 56676 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 18.689929 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 19.996365 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9802 # number of writebacks -system.cpu4.l1c.writebacks::total 9802 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36657 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36657 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23918 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23918 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60575 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60575 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60575 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60575 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9982 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9982 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5360 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5360 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15342 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15342 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1052462662 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1052462662 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 963409159 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 963409159 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2015871821 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 2015871821 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2015871821 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 2015871821 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 780487806 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 780487806 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 2113182760 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 2113182760 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2893670566 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2893670566 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.808491 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.808491 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953630 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953630 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860184 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.860184 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860184 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.860184 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 28711.096435 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 28711.096435 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 40279.670499 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 40279.670499 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 33278.940504 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 33278.940504 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 33278.940504 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 33278.940504 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78189.521739 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78189.521739 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 394250.514925 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 394250.514925 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 188611.039369 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 188611.039369 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9784 # number of writebacks +system.cpu4.l1c.writebacks::total 9784 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36381 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36381 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24008 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 24008 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60389 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60389 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60389 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60389 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 10053 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 10053 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5464 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15517 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15517 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1149238268 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1149238268 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1038052825 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1038052825 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2187291093 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 2187291093 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2187291093 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 2187291093 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 813079130 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 813079130 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1517158795 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1517158795 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2330237925 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2330237925 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807713 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807713 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952509 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952509 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859667 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859667 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 31588.968637 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 31588.968637 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 43237.788446 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 43237.788446 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 80879.252959 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80879.252959 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 277664.493960 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 277664.493960 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 150173.224528 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 150173.224528 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99659 # number of read accesses completed -system.cpu5.num_writes 54989 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22353 # number of replacements -system.cpu5.l1c.tags.tagsinuse 392.762821 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13360 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22726 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.587873 # Average number of references to valid blocks. +system.cpu5.num_reads 100000 # number of read accesses completed +system.cpu5.num_writes 55296 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22532 # number of replacements +system.cpu5.l1c.tags.tagsinuse 395.145821 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13497 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22906 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.589234 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 392.762821 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.767115 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.767115 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 325 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.728516 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337942 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337942 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8666 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8666 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1136 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1136 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9802 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9802 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9802 # number of overall hits -system.cpu5.l1c.overall_hits::total 9802 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36641 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36641 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23834 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23834 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60475 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60475 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60475 # number of overall misses -system.cpu5.l1c.overall_misses::total 60475 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1106472248 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1106472248 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 994607245 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 994607245 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 2101079493 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 2101079493 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 2101079493 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 2101079493 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45307 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45307 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24970 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24970 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70277 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70277 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70277 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70277 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808727 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.808727 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954505 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954505 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.860523 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.860523 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.860523 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.860523 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 30197.654212 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 30197.654212 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 41730.605228 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 41730.605228 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 34742.943249 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 34742.943249 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 34742.943249 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 34742.943249 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1144155 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 395.145821 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.771769 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.771769 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 374 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.730469 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337979 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337979 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8739 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8739 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1202 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1202 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9941 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9941 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9941 # number of overall hits +system.cpu5.l1c.overall_hits::total 9941 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36450 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36450 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23918 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23918 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60368 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60368 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60368 # number of overall misses +system.cpu5.l1c.overall_misses::total 60368 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1193062548 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1193062548 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 1058341769 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 1058341769 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 2251404317 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 2251404317 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 2251404317 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 2251404317 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45189 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45189 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25120 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25120 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70309 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70309 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70309 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70309 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806612 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806612 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952150 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952150 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.858610 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.858610 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.858610 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.858610 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 32731.482798 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 32731.482798 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 44248.756961 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 44248.756961 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 37294.664673 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 37294.664673 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 37294.664673 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 37294.664673 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1121436 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 61191 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 56172 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 18.698093 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 19.964324 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9829 # number of writebacks -system.cpu5.l1c.writebacks::total 9829 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36641 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36641 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23834 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23834 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60475 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60475 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60475 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9934 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9934 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5460 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5460 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15394 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15394 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1050521774 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1050521774 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 958365245 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 958365245 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2008887019 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 2008887019 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2008887019 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 2008887019 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 778256892 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 778256892 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 2141596587 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 2141596587 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2919853479 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2919853479 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808727 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808727 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954505 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954505 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860523 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.860523 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860523 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.860523 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 28670.663301 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 28670.663301 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 40210.004405 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 40210.004405 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 33218.470757 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 33218.470757 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 33218.470757 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 33218.470757 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78342.751359 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78342.751359 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 392233.807143 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392233.807143 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 189674.774523 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 189674.774523 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9981 # number of writebacks +system.cpu5.l1c.writebacks::total 9981 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36450 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36450 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23918 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23918 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60368 # 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number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1034424769 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1034424769 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2191039317 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 2191039317 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2191039317 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 2191039317 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 798681353 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 798681353 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1559836698 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1559836698 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2358518051 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2358518051 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806612 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806612 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952150 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952150 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.858610 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.858610 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 31731.537668 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 31731.537668 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 43248.798771 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 43248.798771 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 81150.310201 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81150.310201 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 279190.388044 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279190.388044 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 152862.664528 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 152862.664528 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99691 # number of read accesses completed -system.cpu6.num_writes 55108 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22433 # number of replacements -system.cpu6.l1c.tags.tagsinuse 394.732703 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13465 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22813 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.590234 # Average number of references to valid blocks. +system.cpu6.num_reads 99879 # number of read accesses completed +system.cpu6.num_writes 55426 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22371 # number of replacements +system.cpu6.l1c.tags.tagsinuse 395.326557 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13543 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22792 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.594200 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 394.732703 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.770962 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.770962 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 337 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.742188 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 339043 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 339043 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8806 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8806 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1144 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1144 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9950 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9950 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9950 # number of overall hits -system.cpu6.l1c.overall_hits::total 9950 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36628 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36628 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23944 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23944 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60572 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60572 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60572 # number of overall misses -system.cpu6.l1c.overall_misses::total 60572 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1115774950 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1115774950 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 994580574 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 994580574 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 2110355524 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 2110355524 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 2110355524 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 2110355524 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45434 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45434 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25088 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25088 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70522 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70522 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70522 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70522 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806180 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.806180 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954401 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954401 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858909 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858909 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858909 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858909 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 30462.349842 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 30462.349842 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 41537.778734 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 41537.778734 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 34840.446477 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 34840.446477 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 34840.446477 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 34840.446477 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1141787 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 395.326557 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.772122 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.772122 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 339285 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 339285 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8751 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8751 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1170 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1170 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9921 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9921 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9921 # number of overall hits +system.cpu6.l1c.overall_hits::total 9921 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36633 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36633 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 24021 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 24021 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60654 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60654 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60654 # number of overall misses +system.cpu6.l1c.overall_misses::total 60654 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1194061806 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1194061806 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 1068136243 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 1068136243 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 2262198049 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 2262198049 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 2262198049 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 2262198049 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45384 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45384 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25191 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25191 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70575 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70575 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70575 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70575 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807179 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807179 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953555 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953555 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859426 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859426 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859426 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859426 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 32595.250348 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 32595.250348 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 44466.768369 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 44466.768369 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 37296.766067 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 37296.766067 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 37296.766067 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 37296.766067 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1121671 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61213 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 56232 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 18.652688 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 19.947201 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9839 # number of writebacks -system.cpu6.l1c.writebacks::total 9839 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36628 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36628 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23944 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23944 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60572 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60572 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60572 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60572 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9790 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9790 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5449 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5449 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15239 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15239 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1059827480 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1059827480 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 958175570 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 958175570 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2018003050 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 2018003050 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2018003050 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 2018003050 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 767222409 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 767222409 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 2138123651 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 2138123651 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2905346060 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2905346060 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806180 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806180 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954401 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954401 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858909 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858909 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858909 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858909 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 28934.898984 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 28934.898984 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 40017.355914 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 40017.355914 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 33315.773790 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 33315.773790 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 33315.773790 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 33315.773790 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78367.968233 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78367.968233 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 392388.264085 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392388.264085 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 190652.015224 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 190652.015224 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9808 # number of writebacks +system.cpu6.l1c.writebacks::total 9808 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36633 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36633 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24021 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 24021 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60654 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60654 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60654 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60654 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9734 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9734 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5519 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5519 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15253 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15253 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1157429806 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1157429806 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1044117243 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1044117243 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2201547049 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 2201547049 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2201547049 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 2201547049 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 789209928 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 789209928 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1545234814 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1545234814 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2334444742 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2334444742 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807179 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807179 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953555 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953555 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859426 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859426 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 31595.277646 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 31595.277646 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 43466.851630 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 43466.851630 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 81077.658517 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81077.658517 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 279984.564957 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279984.564957 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 153048.235888 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 153048.235888 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99881 # number of read accesses completed -system.cpu7.num_writes 55258 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22490 # number of replacements -system.cpu7.l1c.tags.tagsinuse 394.773487 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13394 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22887 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.585223 # Average number of references to valid blocks. +system.cpu7.num_reads 99237 # number of read accesses completed +system.cpu7.num_writes 54706 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22568 # number of replacements +system.cpu7.l1c.tags.tagsinuse 396.130968 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13545 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22967 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.589759 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 394.773487 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.771042 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.771042 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 361 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338728 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338728 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8705 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8705 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1114 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1114 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9819 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9819 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9819 # number of overall hits -system.cpu7.l1c.overall_hits::total 9819 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36637 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36637 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23983 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23983 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60620 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60620 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60620 # number of overall misses -system.cpu7.l1c.overall_misses::total 60620 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1106293724 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1106293724 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1002572296 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1002572296 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 2108866020 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 2108866020 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 2108866020 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 2108866020 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45342 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45342 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25097 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25097 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70439 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70439 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70439 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70439 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808015 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.808015 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955612 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955612 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.860603 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.860603 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.860603 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.860603 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 30196.078391 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 30196.078391 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 41803.456448 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 41803.456448 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 34788.288024 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 34788.288024 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 34788.288024 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 34788.288024 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1141532 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 396.130968 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.773693 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.773693 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 336 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337631 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337631 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8763 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8763 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1110 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1110 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9873 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9873 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9873 # number of overall hits +system.cpu7.l1c.overall_hits::total 9873 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36422 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36422 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23951 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23951 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60373 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60373 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60373 # number of overall misses +system.cpu7.l1c.overall_misses::total 60373 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1187262746 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1187262746 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1066556279 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1066556279 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 2253819025 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 2253819025 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 2253819025 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 2253819025 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45185 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45185 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25061 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70246 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70246 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70246 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70246 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806064 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.806064 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955708 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955708 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859451 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859451 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859451 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859451 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 32597.406677 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 32597.406677 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 44530.761931 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 44530.761931 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 37331.572474 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 37331.572474 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 37331.572474 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 37331.572474 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1126172 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 61288 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 56351 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 18.625702 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 19.984951 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9784 # number of writebacks -system.cpu7.l1c.writebacks::total 9784 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36637 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36637 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23983 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60620 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60620 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60620 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60620 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9862 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9862 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5465 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5465 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15327 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15327 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1050368666 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1050368666 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 966121280 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 966121280 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2016489946 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 2016489946 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2016489946 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 2016489946 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 770060879 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 770060879 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 2135523645 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 2135523645 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2905584524 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2905584524 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808015 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808015 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955612 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955612 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860603 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.860603 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860603 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.860603 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 28669.614488 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 28669.614488 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 40283.587541 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 40283.587541 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 33264.433289 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 33264.433289 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 33264.433289 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 33264.433289 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 78083.642162 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78083.642162 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 390763.704483 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 390763.704483 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 189572.944738 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 189572.944738 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9950 # number of writebacks +system.cpu7.l1c.writebacks::total 9950 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36422 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36422 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23951 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23951 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60373 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60373 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60373 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60373 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9901 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9901 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5444 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5444 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15345 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15345 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1150841746 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1150841746 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1042608279 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1042608279 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2193450025 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 2193450025 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2193450025 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 2193450025 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 802753372 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 802753372 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1502766880 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1502766880 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2305520252 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2305520252 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806064 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806064 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955708 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955708 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859451 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859451 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859451 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859451 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 31597.434133 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 31597.434133 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 43530.887186 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 43530.887186 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 36331.638729 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 36331.638729 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 36331.638729 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 36331.638729 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 81078.009494 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81078.009494 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 276040.940485 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 276040.940485 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 150245.699055 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 150245.699055 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 12865 # number of replacements -system.l2c.tags.tagsinuse 778.482244 # Cycle average of tags in use -system.l2c.tags.total_refs 150454 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 13664 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.010978 # Average number of references to valid blocks. +system.l2c.tags.replacements 13238 # number of replacements +system.l2c.tags.tagsinuse 783.486176 # Cycle average of tags in use +system.l2c.tags.total_refs 163749 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14027 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.673843 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 726.215945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 5.941011 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.607450 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.516565 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.767835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.065793 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.555833 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.650782 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.161030 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.709195 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.005802 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006453 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006364 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006609 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.005924 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006402 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006495 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006993 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.760237 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 799 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 529 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.780273 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1961721 # Number of tag accesses -system.l2c.tags.data_accesses 1961721 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10688 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10718 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10681 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10576 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10796 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10643 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10745 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10600 # number of ReadReq hits -system.l2c.ReadReq_hits::total 85447 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 75954 # number of Writeback hits -system.l2c.Writeback_hits::total 75954 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 258 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 259 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 265 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 289 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 279 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 276 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2192 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1720 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1745 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1690 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1740 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1809 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1751 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1779 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1766 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14000 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12408 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12463 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12371 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12316 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12605 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12394 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12524 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12366 # number of demand (read+write) hits -system.l2c.demand_hits::total 99447 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12408 # number of overall hits -system.l2c.overall_hits::cpu1 12463 # number of overall hits -system.l2c.overall_hits::cpu2 12371 # number of overall hits -system.l2c.overall_hits::cpu3 12316 # number of overall hits -system.l2c.overall_hits::cpu4 12605 # number of overall hits -system.l2c.overall_hits::cpu5 12394 # number of overall hits -system.l2c.overall_hits::cpu6 12524 # number of overall hits -system.l2c.overall_hits::cpu7 12366 # number of overall hits -system.l2c.overall_hits::total 99447 # number of overall hits -system.l2c.ReadReq_misses::cpu0 632 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 687 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 691 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 653 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 659 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 669 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 680 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 698 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5369 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 2017 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2027 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2036 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2040 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2009 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1982 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1969 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2002 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16082 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4591 # number of ReadExReq misses +system.l2c.tags.occ_blocks::writebacks 731.907933 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.423018 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 6.356158 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 6.459637 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.505664 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.498026 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.297131 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.613319 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 6.425290 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.714754 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006272 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006207 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006308 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006353 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006346 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006150 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006458 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006275 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.765123 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 503 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.770508 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2093442 # Number of tag accesses +system.l2c.tags.data_accesses 2093442 # Number of data accesses +system.l2c.Writeback_hits::writebacks 77141 # number of Writeback hits +system.l2c.Writeback_hits::total 77141 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 278 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 288 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 234 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 250 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 237 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 267 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 288 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 265 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2107 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1745 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1822 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1757 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1774 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1783 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1866 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1759 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1730 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14236 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 10764 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 10818 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 10858 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 10852 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 10715 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 10815 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 10778 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 10709 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 86309 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 12509 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12640 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12615 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12626 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12498 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12681 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12537 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12439 # number of demand (read+write) hits +system.l2c.demand_hits::total 100545 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12509 # number of overall hits +system.l2c.overall_hits::cpu1 12640 # number of overall hits +system.l2c.overall_hits::cpu2 12615 # number of overall hits +system.l2c.overall_hits::cpu3 12626 # number of overall hits +system.l2c.overall_hits::cpu4 12498 # number of overall hits +system.l2c.overall_hits::cpu5 12681 # number of overall hits +system.l2c.overall_hits::cpu6 12537 # number of overall hits +system.l2c.overall_hits::cpu7 12439 # number of overall hits +system.l2c.overall_hits::total 100545 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 2044 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2057 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2093 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2098 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 2109 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 2052 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 2068 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2060 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16581 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4635 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1 4534 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4582 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4587 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4602 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4656 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4483 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4700 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 36735 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5223 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5221 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5273 # 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number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 38166948 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 42177940 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 42464442 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 39958937 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 39824446 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 41404446 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 41598942 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 42493439 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 328089540 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 61064999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 62048000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 62761500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 61788499 # 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number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 254124963 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 254900472 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 257627958 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 256511954 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2030652683 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 41112446 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 40920945 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 42356442 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 41376937 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 44597922 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 42076925 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 42377442 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 41033442 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 335852501 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 293793905 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 288431908 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 297663399 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 293364894 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 298722885 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 296977397 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 300005400 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 297545396 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2366505184 # 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number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2327 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2348 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2346 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2319 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2356 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2325 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18688 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6380 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6356 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6433 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6391 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6443 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6547 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6463 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6421 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51434 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11446 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11495 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11559 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11535 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11447 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11497 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11486 # 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number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17851 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17992 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17926 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17890 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 18044 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17949 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17814 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143292 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.880276 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.877186 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.899441 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.893526 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.898977 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.884864 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.877759 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.886022 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.887254 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.726489 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.713342 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.726877 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.722422 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.723266 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.714984 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.727835 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.730572 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.723218 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.059584 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.058895 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.060645 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.059211 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.063947 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.059320 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.061640 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.060037 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.060408 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.298272 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.291916 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2 0.298855 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.298473 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.294470 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.300525 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.291909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.303873 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.297448 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.296240 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.295239 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu3 0.295660 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.301397 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.297218 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.301521 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.301729 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.298321 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.298272 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.291916 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2 0.298855 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.298473 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.294470 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.300525 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.291909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.303873 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.297448 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 60390.740506 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 61394.381368 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 61453.606368 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 61192.859112 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 60431.632777 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 61890.053812 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 61174.914706 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 60878.852436 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 61108.128143 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 30275.160635 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 30610.754810 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 30825.884086 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 30288.479902 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28343.454455 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 30092.078708 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29379.632301 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29716.782717 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29945.839634 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 54781.955130 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 54618.652404 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 54659.601702 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 54677.013734 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 54851.685137 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54590.629296 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 54679.671648 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 54794.138511 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 54706.996788 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55460.636416 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 55510.229841 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 55549.921676 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55489.007443 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 55550.636951 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55507.683756 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 55535.136549 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55580.935532 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 55523.253539 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55460.636416 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 55510.229841 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 55549.921676 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55489.007443 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 55550.636951 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55507.683756 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 55535.136549 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 55580.935532 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 55523.253539 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 8422 # number of cycles access was blocked +system.l2c.overall_miss_rate::cpu3 0.295660 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.301397 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.297218 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.301521 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.301729 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.298321 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 29972.358121 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 30263.732620 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 30704.012422 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29711.153003 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 29288.762447 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 29602.095029 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 29495.889265 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29497.087379 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29816.566733 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 54515.956634 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 54589.978606 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 54599.434773 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 54578.288282 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 54533.253863 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54454.277291 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 54767.848214 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54681.721168 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54590.372681 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 60282.178886 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 60444.527326 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 60422.884451 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 60581.166911 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 60926.122951 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 61696.370968 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 59855.144068 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 59990.412281 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 60524.869526 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55255.577393 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55350.586836 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 55358.638460 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55351.866792 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55401.128524 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55375.237181 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 55433.370288 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55357.282977 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55360.731373 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55255.577393 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55350.586836 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 55358.638460 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55351.866792 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55401.128524 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55375.237181 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 55433.370288 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55357.282977 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55360.731373 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 8992 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1138 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1204 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.400703 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.468439 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6144 # number of writebacks -system.l2c.writebacks::total 6144 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu2 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits +system.l2c.writebacks::writebacks 6188 # number of writebacks +system.l2c.writebacks::total 6188 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 8 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 23 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 63 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 628 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 680 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 688 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 646 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 652 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 666 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 676 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 693 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5329 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 2017 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2027 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2034 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2040 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2008 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1982 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1968 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2002 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16078 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4588 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4530 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4579 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4586 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4599 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4651 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4482 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4697 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 36712 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5216 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5210 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5267 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5232 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5251 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5317 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5158 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5390 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42041 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5216 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5210 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5267 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5232 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5251 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5317 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5158 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5390 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 42041 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9956 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 10009 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9898 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9906 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9982 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9934 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9790 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9862 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 79337 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5414 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5436 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5494 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3 5519 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu4 5358 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu5 5458 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu6 5448 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu7 5462 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 43589 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0 15370 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1 15445 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2 15392 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3 15425 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu4 15340 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu5 15392 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu6 15238 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu7 15324 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 122926 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 30458949 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 33700940 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 34051940 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 31884439 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 31746444 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 33289946 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 33296940 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 33931439 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 262361037 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 84760496 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 85183996 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 85374489 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 85565499 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 84458998 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 83295996 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 82516991 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 84106992 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 675263457 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 195759954 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 192669961 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 194828295 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 195239452 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 196619949 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 197755466 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 190831957 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 200614450 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1564319484 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 226218903 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 226370901 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 228880235 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 227123891 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 228366393 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 231045412 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 224128897 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 234545889 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1826680521 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 226218903 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 226370901 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 228880235 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 227123891 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 228366393 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 231045412 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 224128897 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 234545889 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1826680521 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 420391962 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 422439462 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 417792957 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 418505281 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 421118468 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 419294453 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 413123964 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 416090788 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3348757335 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 237106474 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 237782975 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 241705476 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 241076980 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 235943478 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 241042480 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 238750464 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 240064477 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1913472804 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 657498436 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 660222437 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 659498433 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 659582261 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 657061946 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 660336933 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 651874428 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 656155265 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5262230139 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.055477 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.059623 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.060499 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.057530 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.056918 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.058876 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059168 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061338 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.058679 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.886593 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.877489 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.886275 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.885033 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.873803 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.875055 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.875445 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.878841 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.879829 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726985 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.721452 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.730070 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.724830 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.717361 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.725925 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.715746 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.726415 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.723603 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.295843 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.294617 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.298515 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.298018 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.293910 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.300073 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.291627 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.303423 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.297002 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.295843 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.294617 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.298515 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.298018 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.293910 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.300073 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.291627 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.303423 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.297002 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48501.511146 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49560.205882 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49494.098837 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49356.716718 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48690.865031 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49984.903904 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49255.828402 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 48963.115440 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49232.696003 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42023.052058 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42024.665022 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41973.691740 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41943.872059 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42061.253984 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42026.234107 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41929.365346 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42011.484515 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41999.219866 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42667.819093 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42532.000221 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42548.219043 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42572.928914 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42752.761252 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42518.913352 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42577.411200 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42711.187992 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 42610.576487 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 43370.188459 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 43449.309213 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 43455.522119 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 43410.529625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 43490.076747 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 43454.092910 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 43452.674874 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 43515.007236 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 43449.977903 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 43370.188459 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 43449.309213 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 43455.522119 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 43410.529625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 43490.076747 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 43454.092910 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 43452.674874 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 43515.007236 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 43449.977903 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 42224.986139 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 42205.960835 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 42209.836027 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 42247.656067 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 42187.784813 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 42208.018220 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 42198.566292 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 42191.319002 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 42209.276063 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 43795.063539 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 43742.269132 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 43994.444121 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 43681.279217 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 44035.736842 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 44163.151337 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 43823.506608 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 43951.753387 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 43898.066118 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 42778.037476 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 42746.677695 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 42846.831666 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 42760.600389 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 42833.242894 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 42901.308017 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 42779.526710 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 42818.798290 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 42808.113328 # average overall mshr uncacheable latency +system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 26 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu4 12 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu5 9 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu6 6 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu7 6 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 46 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 1198 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1198 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 2044 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2057 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2093 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2098 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2109 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2051 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 2068 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2059 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16579 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4627 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4532 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4674 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4616 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4656 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4680 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4700 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4687 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 37172 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0 678 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1 673 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2 700 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3 679 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu4 720 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu5 673 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu6 702 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu7 678 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 5503 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5305 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5205 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5374 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5295 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5376 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5353 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5402 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5365 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 42675 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5305 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5205 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5374 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5295 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5376 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5353 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5402 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5365 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 42675 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0 9717 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1 9744 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2 9883 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3 9988 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu4 10053 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu5 9842 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu6 9734 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu7 9901 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 78862 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0 5354 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1 5486 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2 5463 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3 5457 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu4 5464 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu5 5585 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu6 5519 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu7 5444 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 43772 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15071 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15230 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15346 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 15445 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu4 15517 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu5 15427 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu6 15253 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu7 15345 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 122634 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 89873000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 90484998 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 92033997 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 92268499 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 92811998 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 90292999 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 90927999 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 90564000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 729257490 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 206241460 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 202149464 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 208464458 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 205784957 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 207399964 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 208084972 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 210466959 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 209572454 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1658164688 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 34242946 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 34066945 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 35309442 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 34442937 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 37046924 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 35143925 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 35167942 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 34075942 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 279497003 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 240484406 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 236216409 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 243773900 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 240227894 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 244446888 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 243228897 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 245634901 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 243648396 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1937661691 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 240484406 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 236216409 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 243773900 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 240227894 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 244446888 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 243228897 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 245634901 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 243648396 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1937661691 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 429696979 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 430709962 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 436642475 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 441286981 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 444007972 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 434245978 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 430003472 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 437630301 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3484224120 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 244327984 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 248490489 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 246535993 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 247729989 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 247792491 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 253848482 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 250349488 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 246216989 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1985291905 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 674024963 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 679200451 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 683178468 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 689016970 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 691800463 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 688094460 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 680352960 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 683847290 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5469516025 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.880276 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.877186 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.899441 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.893526 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.898977 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.884433 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.877759 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.885591 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.887147 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.725235 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.713027 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.726566 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.722266 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.722645 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.714831 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.727216 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.729949 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.722713 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.059235 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.058547 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.060559 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.058864 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.062899 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.058537 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.061118 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.059510 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.059908 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.297599 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.291580 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.298688 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.295381 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.300503 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.296664 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.300964 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.301168 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.297818 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.297599 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.291580 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.298688 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.295381 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.300503 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.296664 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.300964 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.301168 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.297818 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 43969.178082 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 43988.817696 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 43972.287148 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 43979.265491 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44007.585586 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44023.890297 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 43969.051741 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 43984.458475 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43986.820074 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44573.473093 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44604.912621 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44600.868207 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44580.796577 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44544.665808 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44462.600855 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44780.204043 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44713.559633 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 44607.895405 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 50505.820059 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 50619.531947 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 50442.060000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 50725.974963 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51454.061111 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52219.799406 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 50096.783476 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 50259.501475 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50789.933309 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 45331.650518 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 45382.595389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 45361.723111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 45368.818508 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 45470.031250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 45437.866056 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 45471.103480 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 45414.426095 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 45405.077704 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 45331.650518 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 45382.595389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 45361.723111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 45368.818508 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 45470.031250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 45437.866056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 45471.103480 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 45414.426095 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 45405.077704 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44221.156633 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44202.582307 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44181.167156 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44181.716159 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44166.713618 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44121.720992 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44175.413191 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44200.616200 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44181.280211 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45634.662682 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45295.386256 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45128.316493 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45396.736119 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45350.016654 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45451.832050 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45361.385758 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45227.220610 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45355.293452 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44723.307213 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44596.221339 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44518.341457 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44611.004856 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44583.390024 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44603.257924 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44604.534190 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44564.828283 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 44600.323116 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 252480 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 249408 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 253876 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 250804 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 84654 # Transaction distribution -system.membus.trans_dist::ReadResp 84652 # Transaction distribution -system.membus.trans_dist::WriteReq 43588 # Transaction distribution -system.membus.trans_dist::WriteResp 43585 # Transaction distribution -system.membus.trans_dist::Writeback 6143 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60492 # Transaction distribution -system.membus.trans_dist::UpgradeResp 49595 # Transaction distribution -system.membus.trans_dist::ReadExReq 50638 # Transaction distribution -system.membus.trans_dist::ReadExResp 3207 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 426554 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 426554 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1061863 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1061863 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 58325 # Total snoops (count) -system.membus.snoop_fanout::samples 252480 # Request fanout histogram +system.membus.trans_dist::ReadReq 78861 # Transaction distribution +system.membus.trans_dist::ReadResp 84355 # Transaction distribution +system.membus.trans_dist::WriteReq 43772 # Transaction distribution +system.membus.trans_dist::WriteResp 43770 # Transaction distribution +system.membus.trans_dist::Writeback 6188 # Transaction distribution +system.membus.trans_dist::CleanEvict 1234 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61487 # Transaction distribution +system.membus.trans_dist::UpgradeResp 50676 # Transaction distribution +system.membus.trans_dist::ReadExReq 49401 # Transaction distribution +system.membus.trans_dist::ReadExResp 3090 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5496 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 428330 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1068167 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1068167 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57121 # Total snoops (count) +system.membus.snoop_fanout::samples 253876 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 252480 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253876 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 252480 # Request fanout histogram -system.membus.reqLayer0.occupancy 472884580 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 59.9 # Layer utilization (%) -system.membus.respLayer0.occupancy 313892142 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 39.7 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 684630 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 383351 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 298207 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 371695 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371689 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43589 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43585 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 75954 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29169 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29167 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162397 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162391 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120614 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120783 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120664 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120646 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120853 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120726 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120516 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120736 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 965538 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756616 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1750933 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1748576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754368 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1762730 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757509 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1755676 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14042920 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 324098 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 684630 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.384232 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.250303 # Request fanout histogram +system.membus.snoop_fanout::total 253876 # Request fanout histogram +system.membus.reqLayer0.occupancy 481009549 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 54.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 317350499 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 35.7 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 783985 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 389410 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 391503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 13238 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 4575 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 8663 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78862 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371257 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43772 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43769 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 83329 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 20018 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29498 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29497 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162169 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162167 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292402 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122283 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122529 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122863 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122791 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122820 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122959 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122669 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122503 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 981417 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1781215 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778494 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776817 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1770963 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1771805 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1794946 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1778453 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1777585 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14230278 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 335326 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 797223 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.523507 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.320965 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 176832 25.83% 25.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 250927 36.65% 62.48% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 141295 20.64% 83.12% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 69195 10.11% 93.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 30377 4.44% 97.66% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 11672 1.70% 99.37% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 3607 0.53% 99.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 725 0.11% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 184121 23.10% 23.10% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 277567 34.82% 57.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 172653 21.66% 79.57% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 93165 11.69% 91.26% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 44731 5.61% 96.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 17914 2.25% 99.11% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 5826 0.73% 99.84% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 1211 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 35 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 684630 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 782327755 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 99.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 100591456 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 12.7 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 100721944 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 12.8 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 100768962 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 12.8 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 100555978 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 12.7 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 100847968 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 12.8 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 100723976 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 12.8 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 100740497 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 12.8 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 100846524 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 12.8 # Layer utilization (%) +system.toL2Bus.snoop_fanout::max_value 8 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 797223 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 882991225 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 99.3 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 100686388 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 11.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 100571959 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 11.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 100903359 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 11.4 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 100786975 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 11.3 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 100705827 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 11.3 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 100586898 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 11.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 100884775 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 11.3 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 100465612 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 11.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |