diff options
Diffstat (limited to 'tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt')
| -rw-r--r-- | tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt | 3095 |
1 files changed, 1548 insertions, 1547 deletions
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index b29e580fa..e072d02ad 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,195 +1,195 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000476 # Number of seconds simulated -sim_ticks 475552000 # Number of ticks simulated -final_tick 475552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000473 # Number of seconds simulated +sim_ticks 473250000 # Number of ticks simulated +final_tick 473250000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 102852654 # Simulator tick rate (ticks/s) -host_mem_usage 276856 # Number of bytes of host memory used -host_seconds 4.62 # Real time elapsed on the host +host_tick_rate 101630905 # Simulator tick rate (ticks/s) +host_mem_usage 277340 # Number of bytes of host memory used +host_seconds 4.66 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 82626 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 79372 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 82635 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 78892 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 79911 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 82560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 82806 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 80499 # Number of bytes read from this memory -system.physmem.bytes_read::total 649301 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 411072 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5529 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5498 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5527 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5416 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5415 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5350 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5500 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5539 # Number of bytes written to this memory -system.physmem.bytes_written::total 454846 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10995 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10941 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10978 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11115 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11118 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10947 # Number of read requests responded to by this memory -system.physmem.num_reads::total 88160 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6423 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5529 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5498 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5527 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5416 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5415 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5350 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5500 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5539 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50197 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 173747561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 166904986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 173766486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 165895633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 168038406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 173608775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 174126068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 169274864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1365362778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 864410201 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 11626489 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 11561301 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 11622283 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 11388870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 11386767 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 11250084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 11565507 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 11647517 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 956459020 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 864410201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 185374050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 178466288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 185388769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 177284503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 179425173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 184858859 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 185691575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 180922381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2321821799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 80424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 83171 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 80813 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 86214 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79490 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 82665 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 85333 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 80902 # Number of bytes read from this memory +system.physmem.bytes_read::total 659012 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 419392 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5460 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5448 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5355 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5405 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5451 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5481 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5462 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5450 # Number of bytes written to this memory +system.physmem.bytes_written::total 462904 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11061 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10973 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10946 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11055 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11056 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10909 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87791 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6553 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5460 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5448 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5355 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5405 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5451 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5481 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5462 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5450 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50065 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 169939778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 175744321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 170761754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 182174326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 167966191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 174675119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 180312731 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 170949815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1392524036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 886195457 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 11537242 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 11511886 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 11315372 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 11421025 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 11518225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 11581616 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 11541469 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 11516112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 978138405 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 886195457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 181477021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 187256207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 182077126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 193595351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 179484416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 186256735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 191854200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 182465927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2370662441 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 55373 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22370 # number of replacements -system.cpu0.l1c.tags.tagsinuse 390.859535 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13365 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22757 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.587292 # Average number of references to valid blocks. +system.cpu0.num_reads 98988 # number of read accesses completed +system.cpu0.num_writes 54550 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22171 # number of replacements +system.cpu0.l1c.tags.tagsinuse 391.248330 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13318 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22569 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.590101 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 390.859535 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.763398 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.763398 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338979 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338979 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8642 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8642 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1137 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1137 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9779 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9779 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9779 # number of overall hits -system.cpu0.l1c.overall_hits::total 9779 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36791 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36791 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23910 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23910 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60701 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60701 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60701 # number of overall misses -system.cpu0.l1c.overall_misses::total 60701 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 598271123 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 598271123 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 653921249 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 653921249 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1252192372 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1252192372 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1252192372 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1252192372 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45433 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45433 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25047 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25047 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70480 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70480 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70480 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70480 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809786 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.809786 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954605 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954605 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.861251 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.861251 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.861251 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.861251 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16261.344432 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16261.344432 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27349.278503 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 27349.278503 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 20628.859030 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 20628.859030 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 20628.859030 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 20628.859030 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 775639 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 391.248330 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.764157 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.764157 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 335805 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 335805 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8501 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8501 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1143 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1143 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9644 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9644 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9644 # number of overall hits +system.cpu0.l1c.overall_hits::total 9644 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36474 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36474 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23719 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23719 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60193 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60193 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60193 # number of overall misses +system.cpu0.l1c.overall_misses::total 60193 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 587864141 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 587864141 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 652231215 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 652231215 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1240095356 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1240095356 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1240095356 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1240095356 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44975 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44975 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24862 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24862 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 69837 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 69837 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 69837 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 69837 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.810984 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.810984 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954026 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954026 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.861907 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.861907 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.861907 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.861907 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16117.347727 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16117.347727 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27498.259412 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 27498.259412 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 20601.986211 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 20601.986211 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 20601.986211 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 20601.986211 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 773904 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 66482 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 66096 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.666902 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.708787 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9788 # number of writebacks -system.cpu0.l1c.writebacks::total 9788 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36791 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36791 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23910 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23910 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60701 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60701 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60701 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60701 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 540766367 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 540766367 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 617095733 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 617095733 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1157862100 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1157862100 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1157862100 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1157862100 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 641214054 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 641214054 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 990476120 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 990476120 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1631690174 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1631690174 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809786 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809786 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954605 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954605 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861251 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.861251 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861251 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.861251 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14698.332935 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14698.332935 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25809.106357 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25809.106357 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19074.843907 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19074.843907 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19074.843907 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19074.843907 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9687 # number of writebacks +system.cpu0.l1c.writebacks::total 9687 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36474 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36474 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23719 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23719 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60193 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60193 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60193 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60193 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 531003039 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 531003039 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 615653301 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 615653301 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1146656340 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1146656340 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1146656340 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1146656340 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 646054384 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 646054384 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 971060215 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 971060215 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1617114599 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1617114599 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.810984 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.810984 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954026 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954026 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861907 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.861907 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861907 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.861907 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14558.398832 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14558.398832 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25956.123825 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25956.123825 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19049.662585 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19049.662585 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19049.662585 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19049.662585 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -197,119 +197,119 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99552 # number of read accesses completed -system.cpu1.num_writes 55312 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22247 # number of replacements -system.cpu1.l1c.tags.tagsinuse 391.170580 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13534 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22643 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.597712 # Average number of references to valid blocks. +system.cpu1.num_reads 99262 # number of read accesses completed +system.cpu1.num_writes 54743 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22415 # number of replacements +system.cpu1.l1c.tags.tagsinuse 391.761420 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13414 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22814 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.587972 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 391.170580 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.764005 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.764005 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338702 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338702 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8670 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8670 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1145 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1145 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9815 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9815 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9815 # number of overall hits -system.cpu1.l1c.overall_hits::total 9815 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36464 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36464 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 24184 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 24184 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60648 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60648 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60648 # number of overall misses -system.cpu1.l1c.overall_misses::total 60648 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 591998971 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 591998971 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 660686123 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 660686123 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1252685094 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1252685094 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1252685094 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1252685094 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45134 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45134 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25329 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25329 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70463 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70463 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70463 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70463 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807905 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.807905 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954795 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954795 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.860707 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.860707 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.860707 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.860707 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16235.162654 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16235.162654 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27319.141705 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 27319.141705 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 20655.010784 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 20655.010784 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 20655.010784 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 20655.010784 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 776857 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 391.761420 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.765159 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.765159 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 336589 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 336589 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8598 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8598 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1162 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1162 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9760 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9760 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9760 # number of overall hits +system.cpu1.l1c.overall_hits::total 9760 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36477 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36477 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23776 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23776 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60253 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60253 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60253 # number of overall misses +system.cpu1.l1c.overall_misses::total 60253 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 595460828 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 595460828 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 649149772 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 649149772 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1244610600 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1244610600 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1244610600 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1244610600 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45075 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45075 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24938 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24938 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70013 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70013 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70013 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70013 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809251 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.809251 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953404 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953404 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.860597 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.860597 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.860597 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.860597 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16324.281821 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16324.281821 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27302.732672 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 27302.732672 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 20656.408810 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 20656.408810 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 20656.408810 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 20656.408810 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 769857 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 66458 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 65915 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.689443 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.679542 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9776 # number of writebacks -system.cpu1.l1c.writebacks::total 9776 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36464 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36464 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24184 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 24184 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60648 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60648 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 534984781 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 534984781 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 623377675 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 623377675 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1158362456 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1158362456 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1158362456 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1158362456 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 640712682 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 640712682 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 989782156 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 989782156 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1630494838 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1630494838 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807905 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807905 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954795 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954795 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860707 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.860707 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860707 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.860707 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14671.587895 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14671.587895 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25776.450339 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25776.450339 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19099.763488 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19099.763488 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9826 # number of writebacks +system.cpu1.l1c.writebacks::total 9826 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36477 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36477 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23776 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23776 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60253 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60253 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60253 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60253 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 538442174 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 538442174 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 612498892 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 612498892 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1150941066 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1150941066 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1150941066 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1150941066 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 637533564 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 637533564 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 980538192 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 980538192 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1618071756 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1618071756 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809251 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809251 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953404 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953404 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860597 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.860597 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860597 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.860597 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14761.141925 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14761.141925 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25761.225269 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25761.225269 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19101.805155 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19101.805155 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19101.805155 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19101.805155 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -317,119 +317,119 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99606 # number of read accesses completed -system.cpu2.num_writes 55482 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22450 # number of replacements -system.cpu2.l1c.tags.tagsinuse 391.646892 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13596 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22843 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.595193 # Average number of references to valid blocks. +system.cpu2.num_reads 99661 # number of read accesses completed +system.cpu2.num_writes 54617 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22463 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.489979 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13594 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22875 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.594273 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 391.646892 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.764935 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.764935 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338700 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338700 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8761 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8761 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1179 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1179 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9940 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9940 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9940 # number of overall hits -system.cpu2.l1c.overall_hits::total 9940 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36421 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36421 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 24109 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 24109 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60530 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60530 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60530 # number of overall misses -system.cpu2.l1c.overall_misses::total 60530 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 592390101 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 592390101 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 664239589 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 664239589 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1256629690 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1256629690 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1256629690 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1256629690 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45182 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45182 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25288 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25288 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70470 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70470 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70470 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70470 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806095 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806095 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953377 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953377 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858947 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858947 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858947 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858947 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16265.069630 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16265.069630 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27551.519723 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 27551.519723 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 20760.444243 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 20760.444243 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 20760.444243 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 20760.444243 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 773028 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.489979 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.766582 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.766582 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 412 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.804688 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338191 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338191 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8852 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8852 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1132 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1132 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9984 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9984 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9984 # number of overall hits +system.cpu2.l1c.overall_hits::total 9984 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36597 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36597 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23791 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23791 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60388 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60388 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60388 # number of overall misses +system.cpu2.l1c.overall_misses::total 60388 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 596108462 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 596108462 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 646461820 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 646461820 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1242570282 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1242570282 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1242570282 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1242570282 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45449 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45449 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24923 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24923 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70372 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70372 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805232 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805232 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954580 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954580 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858125 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858125 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858125 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858125 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16288.451567 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16288.451567 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27172.536674 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 27172.536674 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 20576.443697 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 20576.443697 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 20576.443697 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 20576.443697 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 768951 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 66120 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 65985 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.691289 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.653421 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9975 # number of writebacks -system.cpu2.l1c.writebacks::total 9975 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36421 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36421 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24109 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 24109 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60530 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60530 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60530 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60530 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 535479769 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 535479769 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 627082203 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 627082203 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1162561972 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1162561972 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1162561972 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1162561972 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 634925616 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 634925616 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 991782664 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 991782664 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1626708280 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1626708280 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806095 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806095 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953377 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953377 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858947 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858947 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858947 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858947 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14702.500453 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14702.500453 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26010.295035 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26010.295035 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19206.376541 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19206.376541 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9852 # number of writebacks +system.cpu2.l1c.writebacks::total 9852 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36597 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36597 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23791 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23791 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60388 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60388 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60388 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60388 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 538960044 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 538960044 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 609774472 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 609774472 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1148734516 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1148734516 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1148734516 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1148734516 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 638400628 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 638400628 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 959722740 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 959722740 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1598123368 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1598123368 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805232 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805232 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954580 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954580 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858125 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858125 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858125 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858125 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14726.891385 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14726.891385 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 25630.468328 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 25630.468328 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19022.562695 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19022.562695 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19022.562695 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19022.562695 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -437,119 +437,119 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99549 # number of read accesses completed -system.cpu3.num_writes 55104 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22310 # number of replacements -system.cpu3.l1c.tags.tagsinuse 391.032656 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13513 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22709 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.595050 # Average number of references to valid blocks. +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 55095 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22209 # number of replacements +system.cpu3.l1c.tags.tagsinuse 391.627346 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13529 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22601 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.598602 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 391.032656 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.763736 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.763736 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 338332 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 338332 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8654 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8654 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1182 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1182 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9836 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9836 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9836 # number of overall hits -system.cpu3.l1c.overall_hits::total 9836 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36530 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36530 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 24013 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 24013 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60543 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60543 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60543 # number of overall misses -system.cpu3.l1c.overall_misses::total 60543 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 590001438 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 590001438 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 660132360 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 660132360 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1250133798 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1250133798 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1250133798 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1250133798 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45184 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45184 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25195 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25195 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70379 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70379 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70379 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70379 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808472 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.808472 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953086 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953086 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.860242 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.860242 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.860242 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.860242 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16151.148043 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16151.148043 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27490.624245 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 27490.624245 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 20648.692632 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 20648.692632 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 20648.692632 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 20648.692632 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 774871 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 391.627346 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.764897 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.764897 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 338542 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 338542 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8783 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8783 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1149 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1149 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9932 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9932 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9932 # number of overall hits +system.cpu3.l1c.overall_hits::total 9932 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36678 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36678 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23815 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23815 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60493 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60493 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60493 # number of overall misses +system.cpu3.l1c.overall_misses::total 60493 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 595385248 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 595385248 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 651992109 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 651992109 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1247377357 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1247377357 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1247377357 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1247377357 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45461 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45461 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24964 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24964 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70425 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70425 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70425 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70425 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806801 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.806801 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953974 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.953974 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.858971 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.858971 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.858971 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.858971 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16232.762092 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16232.762092 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27377.371782 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 27377.371782 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 20620.193361 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 20620.193361 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 20620.193361 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 20620.193361 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 774947 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 66332 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66468 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.681707 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.658949 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9907 # number of writebacks -system.cpu3.l1c.writebacks::total 9907 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36530 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36530 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24013 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 24013 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60543 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60543 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60543 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60543 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 532881722 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 532881722 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 623079094 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 623079094 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1155960816 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1155960816 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1155960816 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1155960816 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 642783574 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 642783574 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 972713175 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 972713175 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1615496749 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1615496749 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808472 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808472 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953086 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953086 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860242 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.860242 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860242 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.860242 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14587.509499 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14587.509499 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25947.573981 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25947.573981 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19093.219959 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19093.219959 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19093.219959 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19093.219959 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9869 # number of writebacks +system.cpu3.l1c.writebacks::total 9869 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36678 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36678 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23815 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23815 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60493 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60493 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60493 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60493 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 538014612 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 538014612 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 615289695 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 615289695 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1153304307 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1153304307 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1153304307 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1153304307 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 640462998 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 640462998 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 962755753 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 962755753 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1603218751 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1603218751 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806801 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806801 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953974 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953974 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858971 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.858971 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858971 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.858971 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14668.591853 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14668.591853 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25836.224858 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25836.224858 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19065.086985 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19065.086985 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19065.086985 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19065.086985 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -557,119 +557,119 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99755 # number of read accesses completed -system.cpu4.num_writes 55257 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22302 # number of replacements -system.cpu4.l1c.tags.tagsinuse 391.084224 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13540 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22693 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.596660 # Average number of references to valid blocks. +system.cpu4.num_reads 99958 # number of read accesses completed +system.cpu4.num_writes 55186 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22162 # number of replacements +system.cpu4.l1c.tags.tagsinuse 390.917230 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13739 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22564 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.608890 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 391.084224 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.763836 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.763836 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 338305 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 338305 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8852 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8852 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1084 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1084 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9936 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9936 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9936 # number of overall hits -system.cpu4.l1c.overall_hits::total 9936 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36600 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36600 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23847 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23847 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60447 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60447 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60447 # number of overall misses -system.cpu4.l1c.overall_misses::total 60447 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 590829220 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 590829220 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 656323200 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 656323200 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1247152420 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1247152420 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1247152420 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1247152420 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45452 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45452 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24931 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24931 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70383 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70383 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70383 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70383 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805245 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.805245 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956520 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.956520 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.858830 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.858830 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.858830 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.858830 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16142.874863 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16142.874863 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27522.254372 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 27522.254372 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 20632.164045 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 20632.164045 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 20632.164045 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 20632.164045 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 780817 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 390.917230 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.763510 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.763510 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 392 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338274 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338274 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8951 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8951 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1108 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1108 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 10059 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 10059 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 10059 # number of overall hits +system.cpu4.l1c.overall_hits::total 10059 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36463 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36463 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23892 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23892 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60355 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60355 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60355 # number of overall misses +system.cpu4.l1c.overall_misses::total 60355 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 590532010 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 590532010 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 657391664 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 657391664 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1247923674 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1247923674 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1247923674 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1247923674 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45414 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45414 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25000 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25000 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70414 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70414 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70414 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70414 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.802902 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.802902 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955680 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.955680 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.857145 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.857145 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.857145 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.857145 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16195.376409 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16195.376409 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27515.137452 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 27515.137452 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 20676.392577 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 20676.392577 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 20676.392577 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 20676.392577 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 772044 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 66569 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 66046 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.729439 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.689489 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9856 # number of writebacks -system.cpu4.l1c.writebacks::total 9856 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36600 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36600 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23847 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23847 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60447 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60447 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60447 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 533635904 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 533635904 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 619552810 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 619552810 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1153188714 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1153188714 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1153188714 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1153188714 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 651255905 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 651255905 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 973411350 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 973411350 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1624667255 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1624667255 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805245 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805245 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956520 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956520 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858830 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.858830 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858830 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.858830 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14580.215956 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14580.215956 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25980.324988 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 25980.324988 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19077.683160 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19077.683160 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19077.683160 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19077.683160 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9680 # number of writebacks +system.cpu4.l1c.writebacks::total 9680 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36463 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36463 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23892 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23892 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60355 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60355 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60355 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60355 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 533535272 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 533535272 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 620520370 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 620520370 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1154055642 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1154055642 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1154055642 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1154055642 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 636776082 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 636776082 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 976656146 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 976656146 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1613432228 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1613432228 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.802902 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.802902 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955680 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955680 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857145 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.857145 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857145 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.857145 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14632.237391 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14632.237391 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25971.888917 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 25971.888917 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19121.127363 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19121.127363 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19121.127363 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19121.127363 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -677,119 +677,119 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99495 # number of read accesses completed -system.cpu5.num_writes 54912 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22132 # number of replacements -system.cpu5.l1c.tags.tagsinuse 389.508075 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13369 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22545 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.592992 # Average number of references to valid blocks. +system.cpu5.num_reads 98793 # number of read accesses completed +system.cpu5.num_writes 54966 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22337 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.447401 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13310 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22755 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.584926 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 389.508075 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.760758 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.760758 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 409 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.806641 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337023 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337023 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8615 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8615 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1193 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1193 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9808 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9808 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9808 # number of overall hits -system.cpu5.l1c.overall_hits::total 9808 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36426 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36426 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23853 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23853 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60279 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60279 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60279 # number of overall misses -system.cpu5.l1c.overall_misses::total 60279 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 593740716 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 593740716 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 656837719 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 656837719 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1250578435 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1250578435 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1250578435 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1250578435 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45041 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45041 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25046 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25046 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70087 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70087 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70087 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70087 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808730 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.808730 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952368 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952368 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.860060 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.860060 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.860060 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.860060 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16299.915335 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16299.915335 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27536.901815 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 27536.901815 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 20746.502679 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 20746.502679 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 20746.502679 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 20746.502679 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 781949 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 392.447401 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.766499 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.766499 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 408 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 335862 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 335862 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8554 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8554 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1127 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1127 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9681 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9681 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9681 # number of overall hits +system.cpu5.l1c.overall_hits::total 9681 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36144 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36144 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 24019 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 24019 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60163 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60163 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60163 # number of overall misses +system.cpu5.l1c.overall_misses::total 60163 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 586243376 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 586243376 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 664085386 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 664085386 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1250328762 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1250328762 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1250328762 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1250328762 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44698 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44698 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25146 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25146 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 69844 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 69844 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 69844 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 69844 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808627 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808627 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955182 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.955182 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.861391 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.861391 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.861391 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.861391 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16219.659584 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16219.659584 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27648.336151 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 27648.336151 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 20782.353972 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 20782.353972 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 20782.353972 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 20782.353972 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 771700 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 66475 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 65809 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.763054 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.726360 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9742 # number of writebacks -system.cpu5.l1c.writebacks::total 9742 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36426 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36426 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23853 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23853 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60279 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60279 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60279 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60279 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 536794980 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 536794980 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 620108209 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 620108209 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1156903189 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1156903189 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1156903189 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1156903189 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 648821919 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 648821919 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 955346733 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 955346733 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1604168652 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1604168652 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808730 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808730 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952368 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952368 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860060 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.860060 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860060 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.860060 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14736.588700 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14736.588700 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 25997.074121 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 25997.074121 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19192.474809 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19192.474809 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19192.474809 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19192.474809 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9916 # number of writebacks +system.cpu5.l1c.writebacks::total 9916 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36144 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36144 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24019 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 24019 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60163 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60163 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60163 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60163 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 529678552 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 529678552 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 626959212 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 626959212 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1156637764 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1156637764 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1156637764 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1156637764 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 632837521 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 632837521 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 970316626 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 970316626 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1603154147 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1603154147 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808627 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808627 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955182 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955182 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.861391 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.861391 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861391 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.861391 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14654.674413 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14654.674413 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26102.635913 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26102.635913 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19225.067965 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19225.067965 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19225.067965 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19225.067965 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -797,119 +797,119 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99492 # number of read accesses completed -system.cpu6.num_writes 55188 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22041 # number of replacements -system.cpu6.l1c.tags.tagsinuse 390.749630 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13460 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22445 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.599688 # Average number of references to valid blocks. +system.cpu6.num_reads 99383 # number of read accesses completed +system.cpu6.num_writes 54752 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22371 # number of replacements +system.cpu6.l1c.tags.tagsinuse 391.299314 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13429 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22762 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.589975 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 390.749630 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.763183 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.763183 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 337459 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 337459 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8703 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8703 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1158 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1158 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9861 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9861 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9861 # number of overall hits -system.cpu6.l1c.overall_hits::total 9861 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36430 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36430 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23907 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23907 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60337 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60337 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60337 # number of overall misses -system.cpu6.l1c.overall_misses::total 60337 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 592106528 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 592106528 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 650271582 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 650271582 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1242378110 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1242378110 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1242378110 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1242378110 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45133 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45133 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25065 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25065 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70198 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70198 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70198 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70198 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807170 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.807170 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953800 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953800 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859526 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859526 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859526 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859526 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16253.267307 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16253.267307 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 27200.049442 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 27200.049442 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 20590.651010 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 20590.651010 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 20590.651010 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 20590.651010 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 773385 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 391.299314 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.764256 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.764256 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 336995 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 336995 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8731 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8731 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1088 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1088 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9819 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9819 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9819 # number of overall hits +system.cpu6.l1c.overall_hits::total 9819 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36545 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36545 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23737 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23737 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60282 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60282 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60282 # number of overall misses +system.cpu6.l1c.overall_misses::total 60282 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 590611551 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 590611551 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 651380889 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 651380889 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1241992440 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1241992440 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1241992440 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1241992440 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45276 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45276 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24825 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24825 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70101 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70101 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70101 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70101 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807161 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807161 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956173 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.956173 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859931 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859931 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859931 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859931 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16161.213600 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16161.213600 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 27441.584404 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 27441.584404 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 20603.039713 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 20603.039713 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 20603.039713 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 20603.039713 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 771561 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66167 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66088 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.688379 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.674752 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9775 # number of writebacks -system.cpu6.l1c.writebacks::total 9775 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36430 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36430 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23907 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23907 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60337 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60337 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60337 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60337 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 535158836 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 535158836 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 613445646 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 613445646 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1148604482 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1148604482 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1148604482 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1148604482 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 648116847 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 648116847 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 997038722 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 997038722 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1645155569 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1645155569 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807170 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807170 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953800 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953800 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859526 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859526 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859526 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859526 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14690.058633 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14690.058633 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 25659.666458 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 25659.666458 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19036.486435 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19036.486435 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19036.486435 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19036.486435 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9782 # number of writebacks +system.cpu6.l1c.writebacks::total 9782 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36545 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36545 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23737 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23737 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60282 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60282 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60282 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60282 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 533644023 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 533644023 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 614831387 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 614831387 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1148475410 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1148475410 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1148475410 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1148475410 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 641180935 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 641180935 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 971245186 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 971245186 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1612426121 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1612426121 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807161 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807161 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956173 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956173 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859931 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859931 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859931 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859931 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14602.381256 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14602.381256 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 25901.815183 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 25901.815183 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19051.713779 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19051.713779 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19051.713779 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19051.713779 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -917,119 +917,119 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99953 # number of read accesses completed -system.cpu7.num_writes 55743 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22636 # number of replacements -system.cpu7.l1c.tags.tagsinuse 393.668569 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13591 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 23039 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.589913 # Average number of references to valid blocks. +system.cpu7.num_reads 99477 # number of read accesses completed +system.cpu7.num_writes 54915 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22352 # number of replacements +system.cpu7.l1c.tags.tagsinuse 391.525005 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13561 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22758 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.595878 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 393.668569 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.768884 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.768884 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 340053 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 340053 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8802 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8802 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1188 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1188 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9990 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9990 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9990 # number of overall hits -system.cpu7.l1c.overall_hits::total 9990 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36601 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36601 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 24152 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 24152 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60753 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60753 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60753 # number of overall misses -system.cpu7.l1c.overall_misses::total 60753 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 595212008 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 595212008 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 656742976 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 656742976 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1251954984 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1251954984 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1251954984 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1251954984 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45403 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45403 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25340 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25340 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70743 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70743 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70743 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70743 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806136 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806136 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953118 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953118 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.858785 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.858785 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.858785 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.858785 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16262.178848 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16262.178848 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27192.074197 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 27192.074197 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 20607.294850 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 20607.294850 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 20607.294850 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 20607.294850 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 772653 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 391.525005 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.764697 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.764697 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337629 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337629 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8790 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8790 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1137 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1137 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9927 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9927 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9927 # number of overall hits +system.cpu7.l1c.overall_hits::total 9927 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36477 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36477 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23844 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23844 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60321 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60321 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60321 # number of overall misses +system.cpu7.l1c.overall_misses::total 60321 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 593716610 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 593716610 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 651325348 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 651325348 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1245041958 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1245041958 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1245041958 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1245041958 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45267 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45267 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24981 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24981 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70248 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70248 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70248 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70248 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805819 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.805819 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954485 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.954485 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858686 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858686 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858686 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858686 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16276.464896 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16276.464896 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27316.110887 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 27316.110887 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 20640.273835 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 20640.273835 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 20640.273835 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 20640.273835 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 768557 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 66243 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 65923 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.663919 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.658405 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9979 # number of writebacks -system.cpu7.l1c.writebacks::total 9979 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36601 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36601 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24152 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 24152 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60753 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60753 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60753 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60753 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 538040158 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 538040158 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 619565494 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 619565494 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1157605652 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1157605652 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1157605652 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1157605652 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 639132078 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 639132078 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 986824111 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 986824111 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1625956189 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1625956189 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806136 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806136 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953118 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953118 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858785 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.858785 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858785 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.858785 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14700.149122 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14700.149122 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 25652.761428 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 25652.761428 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19054.296117 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19054.296117 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19054.296117 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19054.296117 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9939 # number of writebacks +system.cpu7.l1c.writebacks::total 9939 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36477 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36477 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23844 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23844 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60321 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60321 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60321 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60321 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 536729312 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 536729312 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 614614324 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 614614324 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1151343636 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1151343636 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1151343636 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1151343636 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 635643033 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 635643033 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 965131654 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 965131654 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1600774687 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1600774687 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805819 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805819 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954485 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954485 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858686 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858686 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858686 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858686 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14714.184609 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14714.184609 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 25776.477269 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 25776.477269 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19086.945442 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19086.945442 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19086.945442 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19086.945442 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency @@ -1037,566 +1037,567 @@ system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13510 # number of replacements -system.l2c.tags.tagsinuse 783.849989 # Cycle average of tags in use -system.l2c.tags.total_refs 151949 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14294 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.630264 # Average number of references to valid blocks. +system.l2c.tags.replacements 13851 # number of replacements +system.l2c.tags.tagsinuse 783.697862 # Cycle average of tags in use +system.l2c.tags.total_refs 151322 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14625 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.346803 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 725.717756 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.606207 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.042760 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.314362 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.280142 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.903512 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 7.337678 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.211948 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.435623 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.708709 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.007428 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006878 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007143 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007110 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006742 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.007166 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.007043 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.007261 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.765479 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 680 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1986932 # Number of tag accesses -system.l2c.tags.data_accesses 1986932 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10772 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10720 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10796 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10828 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10876 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10784 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10725 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10741 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86242 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 77037 # number of Writeback hits -system.l2c.Writeback_hits::total 77037 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 331 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 373 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 363 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 353 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 321 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 363 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 346 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 366 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2816 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2031 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1999 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1974 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2000 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1993 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1980 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1967 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1970 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15914 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12803 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12719 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12770 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12828 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12869 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12764 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12692 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12711 # number of demand (read+write) hits -system.l2c.demand_hits::total 102156 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12803 # number of overall hits -system.l2c.overall_hits::cpu1 12719 # number of overall hits -system.l2c.overall_hits::cpu2 12770 # number of overall hits -system.l2c.overall_hits::cpu3 12828 # number of overall hits -system.l2c.overall_hits::cpu4 12869 # number of overall hits -system.l2c.overall_hits::cpu5 12764 # number of overall hits -system.l2c.overall_hits::cpu6 12692 # number of overall hits -system.l2c.overall_hits::cpu7 12711 # number of overall hits -system.l2c.overall_hits::total 102156 # number of overall hits -system.l2c.ReadReq_misses::cpu0 731 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 674 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 746 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 694 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 702 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 746 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 722 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 727 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5742 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1949 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2075 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2001 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2024 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1976 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1982 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1991 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1901 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15899 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4373 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4324 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4508 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4412 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4451 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4429 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4229 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4405 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 35131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5104 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 4998 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5254 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5106 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5153 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5175 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 4951 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5132 # number of demand (read+write) misses -system.l2c.demand_misses::total 40873 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5104 # number of overall misses -system.l2c.overall_misses::cpu1 4998 # number of overall misses -system.l2c.overall_misses::cpu2 5254 # number of overall misses -system.l2c.overall_misses::cpu3 5106 # number of overall misses -system.l2c.overall_misses::cpu4 5153 # number of overall misses -system.l2c.overall_misses::cpu5 5175 # number of overall misses -system.l2c.overall_misses::cpu6 4951 # number of overall misses -system.l2c.overall_misses::cpu7 5132 # number of overall misses -system.l2c.overall_misses::total 40873 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 45095926 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 41549422 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 46449929 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 42922928 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 43252423 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 45919927 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 44260438 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 44979437 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 354430430 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 56379995 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 59258495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 58685995 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 56511495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 59771492 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 56753497 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 61514994 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 54850495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 463726458 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 240858936 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 238452262 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 247966448 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 242840437 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 244973443 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 243557270 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 233129438 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 242077945 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1933856179 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 285954862 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 280001684 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 294416377 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 285763365 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 288225866 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 289477197 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 277389876 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 287057382 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2288286609 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 285954862 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 280001684 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 294416377 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 285763365 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 288225866 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 289477197 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 277389876 # 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number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2280 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2448 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2364 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2377 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2297 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2345 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2337 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2267 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18715 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6404 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6323 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6482 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6412 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6444 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6409 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6196 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6375 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 51045 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17907 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17717 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18024 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17934 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18022 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17939 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17643 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17843 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143029 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17907 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17717 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18024 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17934 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18022 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17939 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17643 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17843 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143029 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.063549 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.059154 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.064634 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.060233 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.060632 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.064701 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.063073 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.063394 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.062424 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.854825 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.847631 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.846447 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.851493 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.860253 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.845203 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.851947 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.838553 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.849532 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.682854 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.683853 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.695464 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.688085 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.690720 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.691059 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.682537 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.690980 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.688236 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.285028 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.282102 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.291500 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.284711 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.285928 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.288478 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.280621 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.287620 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.285767 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.285028 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.282102 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.291500 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.284711 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.285928 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.288478 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.280621 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.287620 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.285767 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 61690.733242 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 61646.026706 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 62265.320375 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 61848.599424 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 61613.138177 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 61554.861930 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 61302.545706 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 61869.927098 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 61725.954371 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28927.652642 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28558.310843 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29328.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 27920.699111 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 30248.730769 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28634.458628 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 30896.531391 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28853.495529 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29167.020442 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 55078.649897 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 55146.221554 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 55005.866903 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 55040.896872 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 55037.843855 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54991.481147 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 55126.374557 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 54955.265607 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 55047.000626 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 56025.639107 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 56022.745898 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 56036.615341 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55966.189777 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 55933.604890 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55937.622609 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 56027.040194 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55934.797740 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 55985.286350 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 56025.639107 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 56022.745898 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 56036.615341 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55966.189777 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 55933.604890 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55937.622609 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 56027.040194 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 55934.797740 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 55985.286350 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 17581 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 724.401984 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.094586 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.546674 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.606935 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.397120 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 7.288170 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.917650 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.470007 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 6.974735 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.707424 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006928 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007370 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007429 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.007117 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007732 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007295 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006811 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.765330 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 774 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 649 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1983958 # Number of tag accesses +system.l2c.tags.data_accesses 1983958 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10711 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10778 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10851 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10748 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10782 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10733 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10660 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10974 # number of ReadReq hits +system.l2c.ReadReq_hits::total 86237 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 76857 # number of Writeback hits +system.l2c.Writeback_hits::total 76857 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 346 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 384 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 373 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 367 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 376 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 343 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 361 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 335 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2885 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1899 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1990 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1993 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1893 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 2001 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 2049 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1965 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1890 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15680 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12610 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12768 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12844 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12641 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12783 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12782 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12625 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12864 # number of demand (read+write) hits +system.l2c.demand_hits::total 101917 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12610 # number of overall hits +system.l2c.overall_hits::cpu1 12768 # number of overall hits +system.l2c.overall_hits::cpu2 12844 # number of overall hits +system.l2c.overall_hits::cpu3 12641 # number of overall hits +system.l2c.overall_hits::cpu4 12783 # number of overall hits +system.l2c.overall_hits::cpu5 12782 # number of overall hits +system.l2c.overall_hits::cpu6 12625 # number of overall hits +system.l2c.overall_hits::cpu7 12864 # number of overall hits +system.l2c.overall_hits::total 101917 # number of overall hits +system.l2c.ReadReq_misses::cpu0 698 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 756 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 731 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 765 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 706 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 759 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 730 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 718 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5863 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1969 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1976 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1906 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1935 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 2000 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 2012 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1921 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1987 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15706 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4442 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4288 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4325 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4406 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4415 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4506 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4417 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4371 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 35170 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5140 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5044 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5056 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5171 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5121 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5265 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5147 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5089 # number of demand (read+write) misses +system.l2c.demand_misses::total 41033 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5140 # number of overall misses +system.l2c.overall_misses::cpu1 5044 # number of overall misses +system.l2c.overall_misses::cpu2 5056 # number of overall misses +system.l2c.overall_misses::cpu3 5171 # number of overall misses +system.l2c.overall_misses::cpu4 5121 # number of overall misses +system.l2c.overall_misses::cpu5 5265 # number of overall misses +system.l2c.overall_misses::cpu6 5147 # number of overall misses +system.l2c.overall_misses::cpu7 5089 # number of overall misses +system.l2c.overall_misses::total 41033 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 43733919 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 46361427 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 45254929 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 46924929 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 44013419 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 46972420 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 45169428 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 45070420 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 363500891 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 59896998 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 56953495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 54104996 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 56752496 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 58374994 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 58176496 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 54809998 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 58271994 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 457341467 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 244729947 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 236328444 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 237901947 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 242524942 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 242982942 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 248203441 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 243651932 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 239891953 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1936215548 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 288463866 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 282689871 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 283156876 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 289449871 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 286996361 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 295175861 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 288821360 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 284962373 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2299716439 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 288463866 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 282689871 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 283156876 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 289449871 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 286996361 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 295175861 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 288821360 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 284962373 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2299716439 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11409 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11534 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11582 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11513 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11488 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11492 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11390 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11692 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 92100 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 76857 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 76857 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2315 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2360 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2279 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2302 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2376 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2355 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2282 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2322 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18591 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6341 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6278 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6318 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6299 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6416 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6555 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6382 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6261 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50850 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17750 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17812 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17900 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17812 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17904 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18047 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17772 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17953 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 142950 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17750 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17812 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17900 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17812 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17904 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 18047 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17772 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17953 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 142950 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.061180 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.065545 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.063115 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.066447 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.061455 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.066046 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.064091 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.061410 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.063659 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.850540 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.837288 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.836332 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.840573 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.841751 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.854352 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.841805 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.855728 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.844817 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.700520 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.683020 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.684552 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.699476 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.688123 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.687414 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.692103 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.698131 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.691642 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.289577 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.283180 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.282458 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.290310 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.286025 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.291738 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.289613 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.283462 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.287044 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.289577 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.283180 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.282458 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.290310 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.286025 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.291738 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.289613 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.283462 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.287044 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 62656.044413 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61324.638889 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 61908.247606 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61339.776471 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 62341.953258 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 61887.246377 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61875.928767 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 62772.172702 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61999.128603 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 30420.009142 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28822.618927 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 28386.671563 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29329.455297 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 29187.497000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28914.759443 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28532.013535 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29326.620030 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29118.901503 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 55094.540072 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 55113.909515 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 55006.230520 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 55044.244666 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 55035.773952 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 55082.876387 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 55162.311976 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54882.624800 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55053.043730 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 56121.374708 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 56044.780135 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 56004.128956 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55975.608393 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 56043.030853 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 56063.791263 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 56114.505537 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55995.750246 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 56045.535033 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 56121.374708 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 56044.780135 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 56004.128956 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55975.608393 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 56043.030853 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 56063.791263 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 56114.505537 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55995.750246 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 56045.535033 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 17878 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 3250 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3319 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5.409538 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.386562 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6423 # number of writebacks -system.l2c.writebacks::total 6423 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 13 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6553 # number of writebacks +system.l2c.writebacks::total 6553 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 9 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 39 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 20 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 19 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 20 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 19 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 100 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 725 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 661 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 738 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 690 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 692 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 741 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 711 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 723 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5681 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1949 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2074 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2001 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2023 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1976 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1982 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1991 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1901 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15897 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4368 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4317 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4505 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4406 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4442 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4423 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4229 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4402 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 35092 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5093 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 4978 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5243 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5096 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5134 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5164 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 4940 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5125 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40773 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5093 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 4978 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5243 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5096 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5134 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5164 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 4940 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5125 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40773 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 36140918 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 33131910 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 37333917 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 34463914 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 34507911 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 36862423 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 35293427 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 36098935 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 283833355 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 82188451 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 87682473 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 84603955 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 85652462 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 83560954 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 83969963 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 84367474 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80329284 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 672355016 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 188025870 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 186115345 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 193429372 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 189404867 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 191140359 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 189945201 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 182082372 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 188836863 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1508980249 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 224166788 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 219247255 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 230763289 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 223868781 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 225648270 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 226807624 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 217375799 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 224935798 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1792813604 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 224166788 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 219247255 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 230763289 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 223868781 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 225648270 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 226807624 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 217375799 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 224935798 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1792813604 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 419997297 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 420394389 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 416554764 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 421667758 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 426680271 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 424776767 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 425015068 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 419160275 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3374246589 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 245735705 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 245037892 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 243130891 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 240328902 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 241689545 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 236933897 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 244635896 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 245230718 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1942723446 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 665733002 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 665432281 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 659685655 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 661996660 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 668369816 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 661710664 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 669650964 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 664390993 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5316970035 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.063027 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.058013 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.063940 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.059885 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.059769 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.064267 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.062112 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.063045 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.061761 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.854825 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.847222 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.846447 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.851073 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.860253 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.845203 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.851947 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.838553 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.849426 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.682074 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.682746 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.695002 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.687149 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.689323 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.690123 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.682537 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.690510 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.687472 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.284414 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.280973 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.290890 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.284153 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.284874 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.287864 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.279998 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.287227 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.285068 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.284414 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.280973 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.290890 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.284153 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.284874 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.287864 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.279998 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.287227 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.285068 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49849.542069 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50123.918306 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50587.963415 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49947.701449 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49866.923410 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49746.859649 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49639.137834 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49929.370678 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49961.864989 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42169.548999 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42276.987946 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42280.837081 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42339.328720 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42287.932186 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42366.278002 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42374.421899 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42256.330352 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42294.459080 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43046.215659 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43112.194811 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42936.597558 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42987.940763 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 43030.247411 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42944.879267 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43055.656656 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42897.969786 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 43000.691012 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 44014.684469 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 44043.241262 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 44013.596986 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 43930.294545 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 43951.747176 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 43920.918668 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 44003.198178 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 43889.911805 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 43970.608098 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 44014.684469 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 44043.241262 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 44013.596986 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 43930.294545 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 43951.747176 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 43920.918668 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 44003.198178 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 43889.911805 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 43970.608098 # average overall mshr miss latency +system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 48 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 15 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 20 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 108 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 690 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 748 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 723 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 759 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 699 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 748 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 725 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 711 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5803 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1969 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1976 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1906 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1935 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1999 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2012 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1921 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1986 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15704 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4438 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4282 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4318 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4399 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4410 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4497 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4413 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4365 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 35122 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5128 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5030 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5041 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5158 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5109 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5245 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5138 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5076 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40925 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5128 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5030 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5041 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5158 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5109 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5245 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5138 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5076 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40925 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 35173417 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 37031918 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 36254417 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 37641417 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 35371412 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 37570056 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 36289420 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 36247403 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 291579460 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 83090959 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 83391451 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80567464 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 81939961 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 84801962 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 85113946 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 81126982 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 83903452 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 663936177 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 190977391 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 184459864 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 185520379 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 189280870 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 189565364 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 193586876 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 190188358 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 187005383 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1510584485 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 226150808 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 221491782 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 221774796 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 226922287 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 224936776 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 231156932 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 226477778 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 223252786 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1802163945 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 226150808 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 221491782 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 221774796 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 226922287 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 224936776 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 231156932 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 226477778 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 223252786 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1802163945 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 423951568 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 418494765 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 418742272 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 420173606 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 417698791 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 416045242 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 420505761 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 416931790 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3352543795 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 241936896 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 242321875 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 237941390 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 239219888 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 241365909 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 242888399 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 243671384 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 242767880 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1932113621 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 665888464 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 660816640 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 656683662 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 659393494 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 659064700 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 658933641 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 664177145 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 659699670 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5284657416 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.060479 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064852 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.062424 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.065925 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.060846 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.065089 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.063652 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.060811 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.063008 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.850540 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.837288 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.836332 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.840573 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.841330 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.854352 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.841805 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.855297 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.844710 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.699890 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.682064 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.683444 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.698365 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.687344 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.686041 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.691476 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.697173 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.690698 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.288901 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.282394 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.281620 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.289580 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.285355 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.290630 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.289106 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.282738 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.286289 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.288901 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.282394 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.281620 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.289580 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.285355 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.290630 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.289106 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.282738 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.286289 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50975.966667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49507.911765 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50144.421853 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49593.434783 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 50602.878398 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 50227.347594 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 50054.372414 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50980.876231 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 50246.331208 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42199.572880 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42202.151316 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42270.442812 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42346.233075 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42422.192096 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42303.154076 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42231.640812 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42247.458207 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42278.156966 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43032.309824 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43077.969173 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42964.423113 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 43028.158672 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42985.343311 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 43048.004447 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43097.293904 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42842.012142 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 43009.637407 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 44101.171607 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 44034.151491 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 43994.206705 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43994.239434 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 44027.554512 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 44071.865014 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 44078.975866 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 43982.030339 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 44035.771411 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 44101.171607 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 44034.151491 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 43994.206705 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43994.239434 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 44027.554512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 44071.865014 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 44078.975866 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 43982.030339 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 44035.771411 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -1625,64 +1626,64 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 84922 # Transaction distribution -system.membus.trans_dist::ReadResp 84916 # Transaction distribution -system.membus.trans_dist::WriteReq 43774 # Transaction distribution -system.membus.trans_dist::WriteResp 43771 # Transaction distribution -system.membus.trans_dist::Writeback 6423 # Transaction distribution -system.membus.trans_dist::UpgradeReq 58524 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47755 # Transaction distribution -system.membus.trans_dist::ReadExReq 50059 # Transaction distribution -system.membus.trans_dist::ReadExResp 3238 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 423382 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 423382 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1104141 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1104141 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57586 # Total snoops (count) -system.membus.snoop_fanout::samples 124108 # Request fanout histogram +system.membus.trans_dist::ReadReq 84510 # Transaction distribution +system.membus.trans_dist::ReadResp 84504 # Transaction distribution +system.membus.trans_dist::WriteReq 43512 # Transaction distribution +system.membus.trans_dist::WriteResp 43509 # Transaction distribution +system.membus.trans_dist::Writeback 6553 # Transaction distribution +system.membus.trans_dist::UpgradeReq 58529 # Transaction distribution +system.membus.trans_dist::UpgradeResp 47554 # Transaction distribution +system.membus.trans_dist::ReadExReq 49190 # Transaction distribution +system.membus.trans_dist::ReadExResp 3281 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 421142 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 421142 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1121847 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1121847 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 56880 # Total snoops (count) +system.membus.snoop_fanout::samples 123632 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 124108 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 123632 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 124108 # Request fanout histogram -system.membus.reqLayer0.occupancy 285888056 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 60.1 # Layer utilization (%) -system.membus.respLayer0.occupancy 306910429 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 64.5 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 371514 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371497 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43774 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43771 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 77037 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29480 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29478 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162492 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162484 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 121222 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121108 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 121316 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 121170 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 121269 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120825 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 121366 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 969045 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1773466 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1761542 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1792162 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1783057 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1785037 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1774053 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1756466 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1780883 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14206666 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 322486 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 565861 # Request fanout histogram +system.membus.snoop_fanout::total 123632 # Request fanout histogram +system.membus.reqLayer0.occupancy 285799779 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 60.4 # Layer utilization (%) +system.membus.respLayer0.occupancy 306149550 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 64.7 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 370575 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370557 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 7 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43514 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43509 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 76857 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29562 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29559 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161030 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161024 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120584 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120575 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120590 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120766 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120584 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120839 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 965293 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1758906 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1769834 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1777815 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1771618 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1766732 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1791122 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1765164 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1788112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14189303 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 320901 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 563826 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1693,29 +1694,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 565861 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 563826 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 565861 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 447470354 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 94.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 102002382 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 563826 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 445759226 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 94.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101149991 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101806870 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 101191512 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101634818 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 101359906 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101702738 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101696707 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 101648274 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 21.5 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101307289 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 101422885 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 21.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101516818 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 21.3 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101999422 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 101134998 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101213033 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101242964 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |