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-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest/config.ini173
-rwxr-xr-xtests/quick/se/50.memtest/ref/null/none/memtest/simerr146
-rwxr-xr-xtests/quick/se/50.memtest/ref/null/none/memtest/simout14
3 files changed, 212 insertions, 121 deletions
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
index 1f567a1b9..0b50bed4c 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
@@ -8,15 +8,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcbus funcmem l2c membus physmem toL2Bus
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem l2c membus physmem toL2Bus voltage_domain
boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
-memories=system.funcmem system.physmem
+memories=system.physmem system.funcmem
num_work_ids=16
readfile=
symbolfile=
@@ -29,11 +30,16 @@ work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[1]
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
[system.cpu0]
type=MemTest
children=l1c
atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -51,10 +57,10 @@ test=system.cpu0.l1c.cpu_side
[system.cpu0.l1c]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -65,17 +71,26 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu0.l1c.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.test
mem_side=system.toL2Bus.slave[0]
+[system.cpu0.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu1]
type=MemTest
children=l1c
atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -93,10 +108,10 @@ test=system.cpu1.l1c.cpu_side
[system.cpu1.l1c]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -107,17 +122,26 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu1.l1c.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.test
mem_side=system.toL2Bus.slave[1]
+[system.cpu1.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu2]
type=MemTest
children=l1c
atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -135,10 +159,10 @@ test=system.cpu2.l1c.cpu_side
[system.cpu2.l1c]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -149,17 +173,26 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu2.l1c.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu2.test
mem_side=system.toL2Bus.slave[2]
+[system.cpu2.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu3]
type=MemTest
children=l1c
atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -177,10 +210,10 @@ test=system.cpu3.l1c.cpu_side
[system.cpu3.l1c]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -191,17 +224,26 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu3.l1c.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu3.test
mem_side=system.toL2Bus.slave[3]
+[system.cpu3.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu4]
type=MemTest
children=l1c
atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -219,10 +261,10 @@ test=system.cpu4.l1c.cpu_side
[system.cpu4.l1c]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -233,17 +275,26 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu4.l1c.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu4.test
mem_side=system.toL2Bus.slave[4]
+[system.cpu4.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu5]
type=MemTest
children=l1c
atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -261,10 +312,10 @@ test=system.cpu5.l1c.cpu_side
[system.cpu5.l1c]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -275,17 +326,26 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu5.l1c.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu5.test
mem_side=system.toL2Bus.slave[5]
+[system.cpu5.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu6]
type=MemTest
children=l1c
atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -303,10 +363,10 @@ test=system.cpu6.l1c.cpu_side
[system.cpu6.l1c]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -317,17 +377,26 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu6.l1c.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu6.test
mem_side=system.toL2Bus.slave[6]
+[system.cpu6.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu7]
type=MemTest
children=l1c
atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -345,10 +414,10 @@ test=system.cpu7.l1c.cpu_side
[system.cpu7.l1c]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -359,16 +428,29 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu7.l1c.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu7.test
mem_side=system.toL2Bus.slave[7]
+[system.cpu7.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
[system.funcbus]
type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
header_cycles=1
use_default_range=false
width=8
@@ -378,22 +460,21 @@ slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional syste
[system.funcmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
in_addr_map=false
latency=30000
latency_var=0
null=false
range=0:134217727
-zero=false
port=system.funcbus.master[0]
[system.l2c]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -404,16 +485,24 @@ prefetcher=Null
response_latency=20
size=65536
system=system
+tags=system.l2c.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[0]
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=65536
+
[system.membus]
type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
header_cycles=1
system=system
use_default_range=false
@@ -424,20 +513,18 @@ slave=system.l2c.mem_side system.system_port
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
-zero=false
port=system.membus.master[0]
[system.toL2Bus]
type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
header_cycles=1
system=system
use_default_range=false
@@ -445,3 +532,7 @@ width=16
master=system.l2c.cpu_side
slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
index 014cde607..ad8539d90 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
@@ -1,74 +1,74 @@
-system.cpu6: completed 10000 read, 5435 write accesses @79021500
-system.cpu0: completed 10000 read, 5363 write accesses @79194500
-system.cpu7: completed 10000 read, 5392 write accesses @79770500
-system.cpu2: completed 10000 read, 5375 write accesses @80689500
-system.cpu1: completed 10000 read, 5373 write accesses @81623500
-system.cpu4: completed 10000 read, 5458 write accesses @81916000
-system.cpu5: completed 10000 read, 5507 write accesses @81975000
-system.cpu3: completed 10000 read, 5421 write accesses @82381000
-system.cpu2: completed 20000 read, 10678 write accesses @153864500
-system.cpu0: completed 20000 read, 10854 write accesses @154789000
-system.cpu7: completed 20000 read, 10817 write accesses @154953500
-system.cpu1: completed 20000 read, 10781 write accesses @155855500
-system.cpu3: completed 20000 read, 10799 write accesses @157033000
-system.cpu4: completed 20000 read, 10854 write accesses @157158000
-system.cpu6: completed 20000 read, 10878 write accesses @157795000
-system.cpu5: completed 20000 read, 10963 write accesses @159866500
-system.cpu0: completed 30000 read, 16180 write accesses @228385000
-system.cpu2: completed 30000 read, 15995 write accesses @229109500
-system.cpu7: completed 30000 read, 16232 write accesses @231170000
-system.cpu1: completed 30000 read, 16165 write accesses @231658500
-system.cpu4: completed 30000 read, 16252 write accesses @232783000
-system.cpu6: completed 30000 read, 16228 write accesses @233712000
-system.cpu3: completed 30000 read, 16226 write accesses @236523000
-system.cpu5: completed 30000 read, 16456 write accesses @239602000
-system.cpu0: completed 40000 read, 21598 write accesses @305262000
-system.cpu2: completed 40000 read, 21332 write accesses @306571000
-system.cpu1: completed 40000 read, 21599 write accesses @307778500
-system.cpu4: completed 40000 read, 21599 write accesses @307971000
-system.cpu7: completed 40000 read, 21551 write accesses @308441000
-system.cpu6: completed 40000 read, 21597 write accesses @310397000
-system.cpu3: completed 40000 read, 21704 write accesses @312891000
-system.cpu5: completed 40000 read, 21914 write accesses @315565000
-system.cpu4: completed 50000 read, 26891 write accesses @381925000
-system.cpu0: completed 50000 read, 26990 write accesses @382095500
-system.cpu2: completed 50000 read, 26686 write accesses @382917500
-system.cpu1: completed 50000 read, 26983 write accesses @384289000
-system.cpu6: completed 50000 read, 27066 write accesses @384539000
-system.cpu7: completed 50000 read, 26943 write accesses @385136500
-system.cpu3: completed 50000 read, 27037 write accesses @389922000
-system.cpu5: completed 50000 read, 27423 write accesses @393691500
-system.cpu6: completed 60000 read, 32353 write accesses @457634500
-system.cpu4: completed 60000 read, 32228 write accesses @457992000
-system.cpu1: completed 60000 read, 32457 write accesses @460714000
-system.cpu2: completed 60000 read, 32178 write accesses @461196500
-system.cpu0: completed 60000 read, 32542 write accesses @461690000
-system.cpu7: completed 60000 read, 32302 write accesses @462388500
-system.cpu3: completed 60000 read, 32488 write accesses @466103000
-system.cpu5: completed 60000 read, 32744 write accesses @469778000
-system.cpu6: completed 70000 read, 37747 write accesses @533745000
-system.cpu2: completed 70000 read, 37532 write accesses @535320500
-system.cpu4: completed 70000 read, 37773 write accesses @535591500
-system.cpu7: completed 70000 read, 37639 write accesses @538124500
-system.cpu0: completed 70000 read, 37909 write accesses @538334500
-system.cpu1: completed 70000 read, 37921 write accesses @541231500
-system.cpu3: completed 70000 read, 37871 write accesses @542226500
-system.cpu5: completed 70000 read, 38229 write accesses @548322500
-system.cpu4: completed 80000 read, 42983 write accesses @610769500
-system.cpu6: completed 80000 read, 43020 write accesses @610776000
-system.cpu2: completed 80000 read, 42982 write accesses @611661000
-system.cpu0: completed 80000 read, 43374 write accesses @615085500
-system.cpu1: completed 80000 read, 43250 write accesses @615627500
-system.cpu7: completed 80000 read, 43033 write accesses @615746000
-system.cpu3: completed 80000 read, 43154 write accesses @619760000
-system.cpu5: completed 80000 read, 43738 write accesses @625688001
-system.cpu6: completed 90000 read, 48339 write accesses @685422000
-system.cpu2: completed 90000 read, 48272 write accesses @687608500
-system.cpu4: completed 90000 read, 48507 write accesses @688615500
-system.cpu7: completed 90000 read, 48310 write accesses @688789000
-system.cpu0: completed 90000 read, 48650 write accesses @689991000
-system.cpu1: completed 90000 read, 48621 write accesses @693117500
-system.cpu3: completed 90000 read, 48493 write accesses @697608000
-system.cpu5: completed 90000 read, 49008 write accesses @701381500
-system.cpu6: completed 100000 read, 53851 write accesses @761435500
+system.cpu6: completed 10000 read, 5217 write accesses @68085999
+system.cpu4: completed 10000 read, 5435 write accesses @69661000
+system.cpu2: completed 10000 read, 5368 write accesses @70121500
+system.cpu3: completed 10000 read, 5457 write accesses @70317500
+system.cpu1: completed 10000 read, 5387 write accesses @70875500
+system.cpu7: completed 10000 read, 5470 write accesses @70949000
+system.cpu0: completed 10000 read, 5435 write accesses @71227500
+system.cpu5: completed 10000 read, 5514 write accesses @71894000
+system.cpu6: completed 20000 read, 10518 write accesses @132327500
+system.cpu4: completed 20000 read, 10839 write accesses @133525000
+system.cpu1: completed 20000 read, 10784 write accesses @134714500
+system.cpu7: completed 20000 read, 10701 write accesses @135318500
+system.cpu0: completed 20000 read, 10821 write accesses @135563500
+system.cpu2: completed 20000 read, 10843 write accesses @135684500
+system.cpu3: completed 20000 read, 10685 write accesses @135938500
+system.cpu5: completed 20000 read, 11031 write accesses @136425000
+system.cpu6: completed 30000 read, 16001 write accesses @197849500
+system.cpu4: completed 30000 read, 16254 write accesses @198725500
+system.cpu0: completed 30000 read, 16109 write accesses @199579499
+system.cpu1: completed 30000 read, 16209 write accesses @200016500
+system.cpu5: completed 30000 read, 16414 write accesses @200525000
+system.cpu3: completed 30000 read, 15978 write accesses @200724000
+system.cpu7: completed 30000 read, 16153 write accesses @201563500
+system.cpu2: completed 30000 read, 16316 write accesses @202401999
+system.cpu4: completed 40000 read, 21506 write accesses @263053500
+system.cpu6: completed 40000 read, 21338 write accesses @263431500
+system.cpu5: completed 40000 read, 21670 write accesses @263987000
+system.cpu3: completed 40000 read, 21219 write accesses @264608000
+system.cpu1: completed 40000 read, 21536 write accesses @265348500
+system.cpu0: completed 40000 read, 21604 write accesses @265426500
+system.cpu7: completed 40000 read, 21465 write accesses @265674000
+system.cpu2: completed 40000 read, 21690 write accesses @268754000
+system.cpu6: completed 50000 read, 26563 write accesses @327819000
+system.cpu4: completed 50000 read, 27066 write accesses @328101000
+system.cpu5: completed 50000 read, 26900 write accesses @328372000
+system.cpu3: completed 50000 read, 26596 write accesses @328811500
+system.cpu1: completed 50000 read, 26845 write accesses @328908500
+system.cpu7: completed 50000 read, 26873 write accesses @331316999
+system.cpu0: completed 50000 read, 26988 write accesses @331358000
+system.cpu2: completed 50000 read, 27102 write accesses @333876000
+system.cpu1: completed 60000 read, 32156 write accesses @392077000
+system.cpu6: completed 60000 read, 31998 write accesses @392784000
+system.cpu5: completed 60000 read, 32223 write accesses @393227500
+system.cpu4: completed 60000 read, 32446 write accesses @394175000
+system.cpu3: completed 60000 read, 32090 write accesses @394842000
+system.cpu0: completed 60000 read, 32282 write accesses @395716500
+system.cpu7: completed 60000 read, 32292 write accesses @397180000
+system.cpu2: completed 60000 read, 32266 write accesses @397288500
+system.cpu6: completed 70000 read, 37440 write accesses @457780500
+system.cpu1: completed 70000 read, 37577 write accesses @458242500
+system.cpu5: completed 70000 read, 37616 write accesses @458643500
+system.cpu4: completed 70000 read, 37952 write accesses @459569500
+system.cpu3: completed 70000 read, 37486 write accesses @460007500
+system.cpu0: completed 70000 read, 37804 write accesses @461418499
+system.cpu2: completed 70000 read, 37588 write accesses @461790000
+system.cpu7: completed 70000 read, 37743 write accesses @462130500
+system.cpu1: completed 80000 read, 42976 write accesses @523192500
+system.cpu5: completed 80000 read, 43028 write accesses @523895500
+system.cpu6: completed 80000 read, 42870 write accesses @524155000
+system.cpu4: completed 80000 read, 43341 write accesses @524226000
+system.cpu3: completed 80000 read, 42885 write accesses @524383000
+system.cpu2: completed 80000 read, 43005 write accesses @527239000
+system.cpu7: completed 80000 read, 43156 write accesses @528371000
+system.cpu0: completed 80000 read, 43239 write accesses @528519000
+system.cpu3: completed 90000 read, 48037 write accesses @586595000
+system.cpu1: completed 90000 read, 48299 write accesses @588010000
+system.cpu4: completed 90000 read, 48806 write accesses @589147500
+system.cpu6: completed 90000 read, 48454 write accesses @589844000
+system.cpu5: completed 90000 read, 48341 write accesses @590185000
+system.cpu2: completed 90000 read, 48395 write accesses @591584000
+system.cpu7: completed 90000 read, 48496 write accesses @592485000
+system.cpu0: completed 90000 read, 48680 write accesses @594831500
+system.cpu3: completed 100000 read, 53536 write accesses @652606500
hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simout b/tests/quick/se/50.memtest/ref/null/none/memtest/simout
index 077a1416b..de32ac2d8 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/simout
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simout
@@ -1,12 +1,12 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simerr
+Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simout
+Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 14:39:12
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest
+gem5 compiled Sep 22 2013 05:53:51
+gem5 started Sep 22 2013 05:53:54
+gem5 executing on zizzer
+command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 761435500 because maximum number of loads reached
+Exiting @ tick 652606500 because maximum number of loads reached