diff options
Diffstat (limited to 'tests/quick/se/50.memtest/ref/null/none')
| -rw-r--r-- | tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt | 3448 | ||||
| -rw-r--r-- | tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt | 3438 |
2 files changed, 3443 insertions, 3443 deletions
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 61ea5a710..00706da1e 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1819 +1,1819 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000518 # Number of seconds simulated -sim_ticks 518362500 # Number of ticks simulated -final_tick 518362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000541 # Number of seconds simulated +sim_ticks 540820000 # Number of ticks simulated +final_tick 540820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 97254136 # Simulator tick rate (ticks/s) -host_mem_usage 280792 # Number of bytes of host memory used -host_seconds 5.33 # Real time elapsed on the host +host_tick_rate 106172397 # Simulator tick rate (ticks/s) +host_mem_usage 280772 # Number of bytes of host memory used +host_seconds 5.09 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 83556 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 80496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 82210 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 83458 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 79724 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 80437 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 82031 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 84431 # Number of bytes read from this memory -system.physmem.bytes_read::total 656343 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 416960 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5350 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5428 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5478 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5268 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5521 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5505 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5477 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5442 # Number of bytes written to this memory -system.physmem.bytes_written::total 460429 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11020 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10676 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11074 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11030 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10910 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87516 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6515 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5350 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5428 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5478 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5268 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5521 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5505 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5477 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5442 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49984 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 161192216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 155289011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 158595577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 161003159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 153799706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 155175191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 158250259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 162880224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1266185343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 804379175 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10320963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10471436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10567894 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10162772 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10650848 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10619981 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10565965 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10498445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 888237479 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 804379175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 171513179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 165760448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 169163472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 171165931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 164450553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 165795172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 168816224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 173378668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2154422822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 88157 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 82701 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 84142 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 82645 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 83993 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 79749 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 78765 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 84222 # Number of bytes read from this memory +system.physmem.bytes_read::total 664374 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 426368 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5567 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5462 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5416 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5447 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5329 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5472 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5421 # Number of bytes written to this memory +system.physmem.bytes_written::total 470013 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11108 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10881 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10951 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11102 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10890 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10914 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11079 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87861 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6662 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5567 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5462 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5416 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5447 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5329 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5472 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5421 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50307 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 163006176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 152917792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 155582264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 152814245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 155306756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 147459413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 145639954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 155730187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1228456788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 788373211 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10293628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10099479 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10014423 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10071743 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 9853556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10117969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10227063 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10023668 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 869074738 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 788373211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 173299804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 163017270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 165596687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 162885988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 165160312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 157577382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 155867017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 165753855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2097531526 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99891 # number of read accesses completed -system.cpu0.num_writes 54838 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22327 # number of replacements -system.cpu0.l1c.tags.tagsinuse 391.597191 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13273 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22716 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.584302 # Average number of references to valid blocks. +system.cpu0.num_reads 99596 # number of read accesses completed +system.cpu0.num_writes 55268 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22066 # number of replacements +system.cpu0.l1c.tags.tagsinuse 391.486377 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13717 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22459 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.610757 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 391.597191 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.764838 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.764838 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 337776 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 337776 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8714 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8714 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1148 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1148 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9862 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9862 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9862 # number of overall hits -system.cpu0.l1c.overall_hits::total 9862 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36629 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36629 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23739 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23739 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60368 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60368 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60368 # number of overall misses -system.cpu0.l1c.overall_misses::total 60368 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 614304512 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 614304512 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 680799251 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 680799251 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1295103763 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1295103763 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1295103763 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1295103763 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45343 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45343 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24887 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24887 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70230 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70230 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70230 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807820 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807820 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953871 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.953871 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.859576 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.859576 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.859576 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.859576 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16770.987797 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16770.987797 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28678.514301 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 28678.514301 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 21453.481364 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 21453.481364 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 21453.481364 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 21453.481364 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 764972 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 391.486377 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.764622 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.764622 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338295 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338295 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8878 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8878 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1162 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1162 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 10040 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 10040 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 10040 # number of overall hits +system.cpu0.l1c.overall_hits::total 10040 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36478 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36478 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23899 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23899 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60377 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60377 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60377 # number of overall misses +system.cpu0.l1c.overall_misses::total 60377 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 603408975 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 603408975 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 722750184 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 722750184 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1326159159 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1326159159 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1326159159 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1326159159 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45356 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45356 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25061 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70417 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70417 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70417 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70417 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804260 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.804260 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953633 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.953633 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.857421 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.857421 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.857421 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.857421 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16541.723093 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16541.723093 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 30241.858823 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 30241.858823 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21964.641486 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21964.641486 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21964.641486 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21964.641486 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 828428 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 61598 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 62795 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.418780 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.192579 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9814 # number of writebacks -system.cpu0.l1c.writebacks::total 9814 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36629 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36629 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23739 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23739 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60368 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60368 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9828 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9828 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5350 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5350 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15178 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15178 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 577676512 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 577676512 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 657061251 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 657061251 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1234737763 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1234737763 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1234737763 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1234737763 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 645410094 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 645410094 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 821386793 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 821386793 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1466796887 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1466796887 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807820 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807820 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953871 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953871 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859576 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.859576 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859576 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.859576 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15771.015097 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15771.015097 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27678.556426 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27678.556426 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20453.514494 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20453.514494 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20453.514494 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20453.514494 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65670.542735 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65670.542735 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153530.241682 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153530.241682 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 96639.668402 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 96639.668402 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9669 # number of writebacks +system.cpu0.l1c.writebacks::total 9669 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36478 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36478 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23899 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23899 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60377 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60377 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60377 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60377 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9885 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5567 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5567 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15452 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15452 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 566933975 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 566933975 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 698852184 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 698852184 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1265786159 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1265786159 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1265786159 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1265786159 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 722511018 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 722511018 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 853790554 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 853790554 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1576301572 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1576301572 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.804260 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.804260 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953633 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953633 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.857421 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.857421 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15541.805335 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15541.805335 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 29241.900665 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 29241.900665 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 73091.655842 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73091.655842 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153366.365008 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153366.365008 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102012.786177 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102012.786177 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99259 # number of read accesses completed -system.cpu1.num_writes 55194 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22288 # number of replacements -system.cpu1.l1c.tags.tagsinuse 392.187813 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13481 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22683 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.594322 # Average number of references to valid blocks. +system.cpu1.num_reads 98929 # number of read accesses completed +system.cpu1.num_writes 55238 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22532 # number of replacements +system.cpu1.l1c.tags.tagsinuse 392.132482 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13440 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22931 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.586106 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 392.187813 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.765992 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.765992 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 337082 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 337082 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8742 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8742 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1127 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1127 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9869 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9869 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9869 # number of overall hits -system.cpu1.l1c.overall_hits::total 9869 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36456 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36456 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23797 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23797 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60253 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60253 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60253 # number of overall misses -system.cpu1.l1c.overall_misses::total 60253 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 609449513 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 609449513 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 681132433 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 681132433 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1290581946 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1290581946 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1290581946 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1290581946 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45198 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45198 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24924 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70122 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70122 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70122 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70122 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806584 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.806584 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954783 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954783 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859260 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859260 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859260 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859260 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16717.399413 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16717.399413 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28622.617683 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 28622.617683 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 21419.380711 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 21419.380711 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 21419.380711 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 21419.380711 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 761379 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 392.132482 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.765884 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.765884 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338385 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338385 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8754 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8754 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1152 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9906 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9906 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9906 # number of overall hits +system.cpu1.l1c.overall_hits::total 9906 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36277 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36277 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 24198 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 24198 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60475 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60475 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60475 # number of overall misses +system.cpu1.l1c.overall_misses::total 60475 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 602891984 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 602891984 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 733995398 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 733995398 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1336887382 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1336887382 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1336887382 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1336887382 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45031 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45031 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25350 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25350 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70381 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70381 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70381 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70381 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805601 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805601 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954556 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954556 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.859252 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.859252 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.859252 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.859252 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16619.124624 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16619.124624 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 30332.895198 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 30332.895198 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 22106.446995 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 22106.446995 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 22106.446995 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 22106.446995 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 828861 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 61322 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 62856 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.416082 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 13.186665 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9824 # number of writebacks -system.cpu1.l1c.writebacks::total 9824 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36456 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36456 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23797 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23797 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60253 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60253 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60253 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60253 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9840 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9840 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5428 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5428 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15268 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15268 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 572994513 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 572994513 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 657337433 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 657337433 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1230331946 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1230331946 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1230331946 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1230331946 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 646152701 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 646152701 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 842788738 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 842788738 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1488941439 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1488941439 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806584 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806584 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954783 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954783 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859260 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859260 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859260 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859260 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15717.426843 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15717.426843 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27622.701727 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27622.701727 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20419.430501 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20419.430501 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20419.430501 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20419.430501 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65665.924898 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65665.924898 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 155266.900884 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155266.900884 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 97520.398153 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 97520.398153 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9918 # number of writebacks +system.cpu1.l1c.writebacks::total 9918 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36277 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36277 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24198 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 24198 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60475 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60475 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60475 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9741 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9741 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5463 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5463 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15204 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15204 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 566614984 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 566614984 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 709800398 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 709800398 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1276415382 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1276415382 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1276415382 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1276415382 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 713705140 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 713705140 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 858653101 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 858653101 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1572358241 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1572358241 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805601 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805601 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954556 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954556 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.859252 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.859252 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15619.124624 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15619.124624 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 29333.019175 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 29333.019175 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 73268.159327 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73268.159327 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157176.112209 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157176.112209 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103417.406012 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103417.406012 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99508 # number of read accesses completed -system.cpu2.num_writes 54525 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22121 # number of replacements -system.cpu2.l1c.tags.tagsinuse 392.684502 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13597 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22507 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.604123 # Average number of references to valid blocks. +system.cpu2.num_reads 99726 # number of read accesses completed +system.cpu2.num_writes 55227 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22340 # number of replacements +system.cpu2.l1c.tags.tagsinuse 393.100704 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13463 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22750 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.591780 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 392.684502 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.766962 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.766962 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338301 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338301 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8815 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8815 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1121 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1121 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9936 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9936 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9936 # number of overall hits -system.cpu2.l1c.overall_hits::total 9936 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36608 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36608 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23851 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23851 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60459 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60459 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60459 # number of overall misses -system.cpu2.l1c.overall_misses::total 60459 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 611593894 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 611593894 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 682333894 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 682333894 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1293927788 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1293927788 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1293927788 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1293927788 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45423 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45423 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24972 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24972 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70395 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70395 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70395 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70395 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805935 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805935 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955110 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955110 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858854 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858854 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858854 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858854 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16706.563975 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16706.563975 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 28608.188084 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 28608.188084 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 21401.739824 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 21401.739824 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 21401.739824 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 21401.739824 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 766345 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 393.100704 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.767775 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.767775 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 400 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338035 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338035 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1109 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1109 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9766 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9766 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9766 # number of overall hits +system.cpu2.l1c.overall_hits::total 9766 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36622 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36622 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23922 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23922 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60544 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60544 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60544 # number of overall misses +system.cpu2.l1c.overall_misses::total 60544 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 606579368 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 606579368 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 739451035 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 739451035 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1346030403 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1346030403 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1346030403 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1346030403 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45279 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45279 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25031 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25031 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70310 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70310 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808808 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.808808 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955695 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955695 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.861101 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.861101 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.861101 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.861101 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16563.250724 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16563.250724 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30910.920283 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 30910.920283 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 22232.267491 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 22232.267491 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 22232.267491 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 22232.267491 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 834628 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 61950 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 63193 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.370379 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.207602 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9721 # number of writebacks -system.cpu2.l1c.writebacks::total 9721 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36608 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36608 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23851 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23851 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60459 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60459 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60459 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60459 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9890 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9890 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5479 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5479 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15369 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 574987894 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 574987894 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 658483894 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 658483894 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1233471788 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1233471788 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1233471788 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1233471788 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 648669577 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 648669577 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 848315711 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 848315711 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1496985288 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1496985288 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805935 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805935 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955110 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955110 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858854 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858854 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858854 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858854 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15706.618608 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15706.618608 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 27608.230011 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 27608.230011 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20401.789444 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20401.789444 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20401.789444 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20401.789444 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65588.430435 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65588.430435 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154830.390765 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154830.390765 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97402.907671 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97402.907671 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9768 # number of writebacks +system.cpu2.l1c.writebacks::total 9768 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36622 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36622 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23922 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23922 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60544 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60544 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9774 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9774 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5417 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5417 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15191 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15191 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 569957368 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 569957368 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 715531035 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 715531035 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1285488403 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1285488403 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1285488403 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1285488403 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 714145091 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 714145091 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 834952155 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 834952155 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1549097246 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1549097246 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808808 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808808 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955695 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955695 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.861101 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.861101 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15563.250724 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15563.250724 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29911.003888 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29911.003888 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73065.796092 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73065.796092 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154135.527968 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154135.527968 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 101974.672240 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 101974.672240 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 100000 # number of read accesses completed -system.cpu3.num_writes 55096 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22478 # number of replacements -system.cpu3.l1c.tags.tagsinuse 393.167313 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13728 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22864 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.600420 # Average number of references to valid blocks. +system.cpu3.num_reads 99494 # number of read accesses completed +system.cpu3.num_writes 54686 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22431 # number of replacements +system.cpu3.l1c.tags.tagsinuse 392.658378 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13393 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22832 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.586589 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 393.167313 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.767905 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.767905 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 380 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 339546 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 339546 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8879 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8879 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1139 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1139 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 10018 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 10018 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 10018 # number of overall hits -system.cpu3.l1c.overall_hits::total 10018 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36721 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36721 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23927 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23927 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60648 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60648 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60648 # number of overall misses -system.cpu3.l1c.overall_misses::total 60648 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 620124867 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 620124867 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 683533364 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 683533364 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1303658231 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1303658231 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1303658231 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1303658231 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45600 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45600 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25066 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25066 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70666 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70666 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70666 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70666 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805285 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.805285 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954560 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954560 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.858235 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.858235 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.858235 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.858235 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16887.472209 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16887.472209 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28567.449492 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 28567.449492 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 21495.485935 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 21495.485935 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 21495.485935 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 21495.485935 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 763846 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 392.658378 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.766911 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.766911 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 337999 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 337999 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8615 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8615 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1106 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1106 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9721 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9721 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9721 # number of overall hits +system.cpu3.l1c.overall_hits::total 9721 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36594 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36594 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23974 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23974 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60568 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60568 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60568 # number of overall misses +system.cpu3.l1c.overall_misses::total 60568 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 607642440 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 607642440 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 730577546 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 730577546 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1338219986 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1338219986 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1338219986 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1338219986 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45209 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45209 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25080 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25080 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70289 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70289 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70289 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70289 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809441 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.809441 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955901 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955901 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.861700 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.861700 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.861700 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.861700 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16604.974586 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16604.974586 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 30473.744306 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 30473.744306 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 22094.505118 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 22094.505118 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 22094.505118 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 22094.505118 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 833585 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 61681 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 63208 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.383813 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.187967 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 10011 # number of writebacks -system.cpu3.l1c.writebacks::total 10011 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36721 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36721 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23927 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23927 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60648 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60648 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9730 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9730 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5269 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5269 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 14999 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 14999 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 583406867 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 583406867 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 659607364 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 659607364 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1243014231 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1243014231 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1243014231 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1243014231 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 639132205 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 639132205 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 818596366 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 818596366 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1457728571 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1457728571 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805285 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805285 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954560 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954560 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858235 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.858235 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858235 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.858235 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15887.553906 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15887.553906 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27567.491286 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27567.491286 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20495.551890 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20495.551890 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20495.551890 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20495.551890 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65686.763104 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65686.763104 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 155360.858987 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155360.858987 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97188.383959 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97188.383959 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9871 # number of writebacks +system.cpu3.l1c.writebacks::total 9871 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36594 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36594 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23974 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23974 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60568 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60568 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60568 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60568 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9814 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9814 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5449 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5449 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15263 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15263 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 571049440 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 571049440 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 706605546 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 706605546 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1277654986 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1277654986 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1277654986 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1277654986 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 718813002 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 718813002 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 842609106 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 842609106 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1561422108 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1561422108 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809441 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809441 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955901 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955901 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.861700 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.861700 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15605.001913 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15605.001913 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 29473.827730 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 29473.827730 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 73243.631751 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73243.631751 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 154635.548908 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154635.548908 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102301.127432 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102301.127432 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 98810 # number of read accesses completed -system.cpu4.num_writes 55636 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22565 # number of replacements -system.cpu4.l1c.tags.tagsinuse 393.118080 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13493 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22961 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.587649 # Average number of references to valid blocks. +system.cpu4.num_reads 99490 # number of read accesses completed +system.cpu4.num_writes 54928 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22277 # number of replacements +system.cpu4.l1c.tags.tagsinuse 391.439470 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13388 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22671 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.590534 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 393.118080 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.767809 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.767809 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 338158 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 338158 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8694 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8694 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1170 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1170 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9864 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9864 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9864 # number of overall hits -system.cpu4.l1c.overall_hits::total 9864 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36355 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36355 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 24124 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 24124 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60479 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60479 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60479 # number of overall misses -system.cpu4.l1c.overall_misses::total 60479 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 612629802 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 612629802 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 686589261 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 686589261 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1299219063 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1299219063 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1299219063 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1299219063 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45049 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45049 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25294 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25294 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70343 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70343 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70343 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70343 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807010 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807010 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953744 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953744 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859773 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859773 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859773 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859773 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16851.321744 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16851.321744 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28460.838211 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 28460.838211 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 21482.151871 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 21482.151871 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 21482.151871 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 21482.151871 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 755009 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 391.439470 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.764530 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.764530 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337649 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337649 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8692 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8692 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1145 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1145 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9837 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9837 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9837 # number of overall hits +system.cpu4.l1c.overall_hits::total 9837 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36462 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36462 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23928 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23928 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60390 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60390 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60390 # number of overall misses +system.cpu4.l1c.overall_misses::total 60390 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 604688688 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 604688688 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 724847511 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 724847511 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1329536199 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1329536199 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1329536199 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1329536199 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45154 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45154 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25073 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25073 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70227 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70227 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70227 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70227 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807503 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807503 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954333 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.954333 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859926 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859926 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859926 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859926 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16584.078986 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16584.078986 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30292.858200 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 30292.858200 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 22015.833731 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 22015.833731 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 22015.833731 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 22015.833731 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 834109 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 61034 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 63123 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.370302 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.214027 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 10039 # number of writebacks -system.cpu4.l1c.writebacks::total 10039 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36355 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36355 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24124 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 24124 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60479 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60479 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60479 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60479 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9580 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9580 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5521 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5521 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15101 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15101 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 576274802 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 576274802 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 662467261 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 662467261 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1238742063 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1238742063 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1238742063 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1238742063 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 630980804 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 630980804 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 867176198 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 867176198 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1498157002 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1498157002 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807010 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807010 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953744 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953744 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859773 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859773 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859773 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859773 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15851.321744 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15851.321744 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27460.921116 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27460.921116 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20482.184940 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20482.184940 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20482.184940 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20482.184940 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65864.384551 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65864.384551 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157068.682847 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157068.682847 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 99209.125356 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 99209.125356 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9949 # number of writebacks +system.cpu4.l1c.writebacks::total 9949 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36462 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36462 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23928 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23928 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60390 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60390 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60390 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60390 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9946 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9946 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5329 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15275 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15275 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 568228688 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 568228688 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 700919511 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 700919511 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1269148199 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1269148199 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1269148199 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1269148199 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 727166434 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 727166434 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 837934166 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 837934166 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1565100600 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1565100600 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807503 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807503 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954333 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954333 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859926 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859926 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15584.133838 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15584.133838 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29292.858200 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29292.858200 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 73111.445204 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73111.445204 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157240.413961 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157240.413961 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102461.577741 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102461.577741 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98552 # number of read accesses completed -system.cpu5.num_writes 54926 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22151 # number of replacements -system.cpu5.l1c.tags.tagsinuse 392.121942 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13428 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22535 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.595873 # Average number of references to valid blocks. +system.cpu5.num_reads 99495 # number of read accesses completed +system.cpu5.num_writes 55318 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22409 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.682039 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13393 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22790 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.587670 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 392.121942 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.765863 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.765863 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 336693 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 336693 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8529 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8529 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1201 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1201 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9730 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9730 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9730 # number of overall hits -system.cpu5.l1c.overall_hits::total 9730 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36363 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36363 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23944 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23944 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60307 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60307 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60307 # number of overall misses -system.cpu5.l1c.overall_misses::total 60307 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 609487073 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 609487073 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 677626855 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 677626855 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1287113928 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1287113928 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1287113928 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1287113928 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44892 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44892 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25145 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25145 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70037 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70037 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70037 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70037 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.810011 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.810011 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952237 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952237 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.861073 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.861073 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.861073 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.861073 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16761.187828 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16761.187828 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 28300.486761 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 28300.486761 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 21342.695342 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 21342.695342 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 21342.695342 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 21342.695342 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 765746 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 392.682039 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.766957 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.766957 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337688 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337688 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8637 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8637 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1146 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1146 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9783 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9783 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9783 # number of overall hits +system.cpu5.l1c.overall_hits::total 9783 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36329 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36329 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 24118 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 24118 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60447 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60447 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60447 # number of overall misses +system.cpu5.l1c.overall_misses::total 60447 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 601479868 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 601479868 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 729882091 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 729882091 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1331361959 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1331361959 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1331361959 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1331361959 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44966 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44966 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25264 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25264 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70230 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70230 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70230 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807922 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.807922 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954639 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.954639 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860701 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860701 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860701 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860701 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16556.466404 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16556.466404 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 30262.960901 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 30262.960901 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 22025.277665 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 22025.277665 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 22025.277665 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 22025.277665 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 826632 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 61759 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 62727 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.398938 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.178249 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9825 # number of writebacks -system.cpu5.l1c.writebacks::total 9825 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36363 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36363 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23944 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23944 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60307 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60307 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60307 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60307 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9974 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9974 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5505 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5505 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15479 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15479 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 573124073 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 573124073 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 653684855 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 653684855 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1226808928 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1226808928 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1226808928 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1226808928 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 653819057 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 653819057 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 856353181 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 856353181 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1510172238 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1510172238 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.810011 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.810011 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952237 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952237 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.861073 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.861073 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861073 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.861073 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15761.187828 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15761.187828 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 27300.570289 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27300.570289 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20342.728506 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20342.728506 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20342.728506 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20342.728506 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65552.341789 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65552.341789 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 155559.160945 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155559.160945 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 97562.648621 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 97562.648621 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9995 # number of writebacks +system.cpu5.l1c.writebacks::total 9995 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36329 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36329 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24118 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 24118 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60447 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60447 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60447 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9798 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9798 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5473 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5473 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15271 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15271 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 565152868 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 565152868 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 705764091 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 705764091 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1270916959 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1270916959 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1270916959 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1270916959 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 717311081 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 717311081 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 861132955 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 861132955 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1578444036 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1578444036 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807922 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807922 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954639 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954639 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860701 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860701 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15556.521457 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15556.521457 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 29262.960901 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 29262.960901 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 73209.949071 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73209.949071 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 157342.034533 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157342.034533 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 103362.192129 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 103362.192129 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 98949 # number of read accesses completed -system.cpu6.num_writes 55414 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22111 # number of replacements -system.cpu6.l1c.tags.tagsinuse 389.931977 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13393 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22506 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.595086 # Average number of references to valid blocks. +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 55059 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22318 # number of replacements +system.cpu6.l1c.tags.tagsinuse 390.741535 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22720 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.592033 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 389.931977 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.761586 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.761586 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 337246 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 337246 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8611 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8611 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1144 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1144 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9755 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9755 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9755 # number of overall hits -system.cpu6.l1c.overall_hits::total 9755 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36346 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36346 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 24035 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 24035 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60381 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60381 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60381 # number of overall misses -system.cpu6.l1c.overall_misses::total 60381 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 607533641 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 607533641 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 684112648 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 684112648 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1291646289 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1291646289 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1291646289 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1291646289 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44957 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44957 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25179 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25179 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70136 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70136 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70136 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70136 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808461 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.808461 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954565 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954565 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.860913 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.860913 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.860913 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.860913 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16715.282039 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16715.282039 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28463.184855 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 28463.184855 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 21391.601481 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 21391.601481 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 21391.601481 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 21391.601481 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 766078 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 390.741535 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.763167 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.763167 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338536 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338536 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8731 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8731 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1150 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1150 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9881 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9881 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9881 # number of overall hits +system.cpu6.l1c.overall_hits::total 9881 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36733 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36733 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23795 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23795 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60528 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60528 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60528 # number of overall misses +system.cpu6.l1c.overall_misses::total 60528 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 609896687 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 609896687 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 716784676 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 716784676 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1326681363 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1326681363 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1326681363 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1326681363 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45464 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45464 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24945 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24945 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70409 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70409 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70409 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70409 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807958 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807958 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953899 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953899 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859663 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859663 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859663 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859663 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16603.508752 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16603.508752 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 30123.331624 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 30123.331624 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21918.473483 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21918.473483 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21918.473483 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21918.473483 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 822803 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61691 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 62827 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.417986 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.096328 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9648 # number of writebacks -system.cpu6.l1c.writebacks::total 9648 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36346 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36346 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24035 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 24035 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60381 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60381 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60381 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60381 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5478 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5478 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15382 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15382 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 571188641 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 571188641 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 660079648 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 660079648 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1231268289 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1231268289 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1231268289 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1231268289 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 650717068 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 650717068 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 843701696 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 843701696 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1494418764 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1494418764 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808461 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808461 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954565 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954565 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860913 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.860913 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860913 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.860913 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15715.309553 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15715.309553 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27463.268067 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27463.268067 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20391.651165 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20391.651165 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20391.651165 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20391.651165 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65702.450323 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65702.450323 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 154016.373859 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154016.373859 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 97153.735795 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 97153.735795 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9777 # number of writebacks +system.cpu6.l1c.writebacks::total 9777 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36733 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36733 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23795 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23795 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60528 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60528 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60528 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60528 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9837 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9837 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5532 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5532 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15369 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 573164687 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 573164687 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 692991676 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 692991676 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1266156363 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1266156363 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1266156363 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1266156363 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 718909036 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 718909036 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 867837123 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 867837123 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1586746159 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1586746159 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807958 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807958 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953899 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953899 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859663 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859663 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15603.535976 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15603.535976 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 29123.415676 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 29123.415676 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 73082.142523 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73082.142523 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156875.835683 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156875.835683 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103243.292277 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103243.292277 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99388 # number of read accesses completed -system.cpu7.num_writes 55153 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22255 # number of replacements -system.cpu7.l1c.tags.tagsinuse 390.416736 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13442 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22659 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.593230 # Average number of references to valid blocks. +system.cpu7.num_reads 99734 # number of read accesses completed +system.cpu7.num_writes 54921 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22329 # number of replacements +system.cpu7.l1c.tags.tagsinuse 392.290074 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13499 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22713 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.594329 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 390.416736 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.762533 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.762533 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338136 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338136 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8702 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8702 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1125 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1125 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9827 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9827 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9827 # number of overall hits -system.cpu7.l1c.overall_hits::total 9827 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36623 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36623 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23879 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23879 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60502 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60502 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60502 # number of overall misses -system.cpu7.l1c.overall_misses::total 60502 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 619428018 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 619428018 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 681256931 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 681256931 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1300684949 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1300684949 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1300684949 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1300684949 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45325 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45325 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25004 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25004 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70329 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70329 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70329 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70329 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808009 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.808009 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955007 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955007 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.860271 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.860271 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.860271 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.860271 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16913.634000 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16913.634000 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28529.541899 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 28529.541899 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 21498.214092 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 21498.214092 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 21498.214092 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 21498.214092 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 764751 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 392.290074 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.766192 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.766192 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338596 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338596 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8795 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8795 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1165 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1165 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9960 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9960 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9960 # number of overall hits +system.cpu7.l1c.overall_hits::total 9960 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36684 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36684 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23790 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23790 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60474 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60474 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60474 # number of overall misses +system.cpu7.l1c.overall_misses::total 60474 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 611011013 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 611011013 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 715403706 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 715403706 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1326414719 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1326414719 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1326414719 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1326414719 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45479 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45479 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24955 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24955 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70434 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70434 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70434 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70434 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806614 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.806614 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953316 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953316 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858591 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858591 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858591 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858591 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16656.062943 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16656.062943 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 30071.614376 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 30071.614376 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21933.636257 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21933.636257 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21933.636257 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21933.636257 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 829723 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 61551 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 63058 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.424672 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.158093 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9698 # number of writebacks -system.cpu7.l1c.writebacks::total 9698 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36623 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36623 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23879 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23879 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60502 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60502 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60502 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60502 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9744 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9744 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5445 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5445 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15189 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15189 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 582807018 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 582807018 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 657378931 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 657378931 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1240185949 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1240185949 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1240185949 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1240185949 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 639625650 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 639625650 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 835380703 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 835380703 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1475006353 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1475006353 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808009 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808009 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955007 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955007 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860271 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.860271 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860271 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.860271 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15913.688611 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15913.688611 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27529.583777 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27529.583777 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20498.263677 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20498.263677 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20498.263677 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20498.263677 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65643.026478 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65643.026478 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 153421.616713 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153421.616713 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 97110.168741 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 97110.168741 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9746 # number of writebacks +system.cpu7.l1c.writebacks::total 9746 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36684 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36684 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23790 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23790 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60474 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60474 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60474 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60474 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9918 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9918 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5421 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5421 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15339 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15339 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 574327013 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 574327013 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 691615706 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 691615706 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1265942719 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1265942719 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1265942719 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1265942719 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 726668427 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 726668427 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 847371643 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 847371643 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1574040070 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1574040070 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806614 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806614 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953316 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953316 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858591 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858591 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858591 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858591 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15656.062943 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15656.062943 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 29071.698445 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 29071.698445 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 73267.637326 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73267.637326 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 156312.791551 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156312.791551 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102616.863550 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102616.863550 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 14059 # number of replacements -system.l2c.tags.tagsinuse 786.833616 # Cycle average of tags in use -system.l2c.tags.total_refs 163279 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14835 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.006336 # Average number of references to valid blocks. +system.l2c.tags.replacements 14328 # number of replacements +system.l2c.tags.tagsinuse 791.177993 # Cycle average of tags in use +system.l2c.tags.total_refs 163940 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 15120 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.842593 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 728.191655 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.576246 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.765492 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.413353 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.547486 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 7.173407 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 7.531253 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.038544 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.596181 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.711125 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.007399 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006607 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007240 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007371 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.007005 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.007355 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006874 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.007418 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768392 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 637 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2098126 # Number of tag accesses -system.l2c.tags.data_accesses 2098126 # Number of data accesses -system.l2c.Writeback_hits::writebacks 77297 # number of Writeback hits -system.l2c.Writeback_hits::total 77297 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 246 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 268 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 270 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 289 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 282 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 269 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 297 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2204 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1720 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1708 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1780 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1750 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1833 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1787 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1793 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1756 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14127 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10721 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10733 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10896 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 11023 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10756 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10769 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 10556 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10900 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 86354 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12441 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12441 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12676 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12773 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12589 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12556 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12349 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12656 # number of demand (read+write) hits -system.l2c.demand_hits::total 100481 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12441 # number of overall hits -system.l2c.overall_hits::cpu1 12441 # number of overall hits -system.l2c.overall_hits::cpu2 12676 # number of overall hits -system.l2c.overall_hits::cpu3 12773 # number of overall hits -system.l2c.overall_hits::cpu4 12589 # number of overall hits -system.l2c.overall_hits::cpu5 12556 # number of overall hits -system.l2c.overall_hits::cpu6 12349 # number of overall hits -system.l2c.overall_hits::cpu7 12656 # number of overall hits -system.l2c.overall_hits::total 100481 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 1978 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2026 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2150 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2091 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2034 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2071 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2011 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2018 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16379 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4713 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4655 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4607 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4594 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4660 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4574 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4699 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4645 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37147 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 745 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 703 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 745 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 740 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 719 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 741 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 735 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 779 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5907 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5458 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5358 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5352 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5334 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5379 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5315 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5434 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5424 # number of demand (read+write) misses -system.l2c.demand_misses::total 43054 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5458 # number of overall misses -system.l2c.overall_misses::cpu1 5358 # number of overall misses -system.l2c.overall_misses::cpu2 5352 # number of overall misses -system.l2c.overall_misses::cpu3 5334 # number of overall misses -system.l2c.overall_misses::cpu4 5379 # number of overall misses -system.l2c.overall_misses::cpu5 5315 # number of overall misses -system.l2c.overall_misses::cpu6 5434 # number of overall misses -system.l2c.overall_misses::cpu7 5424 # number of overall misses -system.l2c.overall_misses::total 43054 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 60264491 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 62631489 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 64255988 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 63421482 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 62636494 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 62720987 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 60083486 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 62493486 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 498507903 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 264922404 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 260661407 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 257895914 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 258059392 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 261142926 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 256126416 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 263147923 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 259849424 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2081805806 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 46156062 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 44483916 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 46780409 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 45792918 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 45003906 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 46499399 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 45597417 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 48662406 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 368976433 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 311078466 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 305145323 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 304676323 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 303852310 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 306146832 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 302625815 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 308745340 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 308511830 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2450782239 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 311078466 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 305145323 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 304676323 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 303852310 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 306146832 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 302625815 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 308745340 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 308511830 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2450782239 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 77297 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 77297 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2224 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2294 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2420 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2374 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2323 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2353 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2280 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2315 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18583 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6433 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6363 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6387 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6344 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6493 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6361 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6492 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6401 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 51274 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11466 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11436 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11641 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11763 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11475 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11510 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11291 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11679 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 92261 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17899 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17799 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18028 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18107 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17968 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17871 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17783 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18080 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143535 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17899 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17799 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18028 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18107 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17968 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17871 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17783 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18080 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143535 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.889388 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.883173 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.888430 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.880792 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.875592 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.880153 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.882018 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.871706 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.881397 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.732629 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.731573 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.721309 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.724149 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.717696 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.719069 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.723814 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.725668 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.724480 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.064975 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.061473 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.063998 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.062909 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.062658 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.064379 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.065096 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.066701 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.064025 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.304933 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.301028 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.296872 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.294582 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.299366 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.297409 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.305573 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.300000 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.299955 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.304933 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.301028 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.296872 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.294582 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.299366 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.297409 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.305573 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.300000 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.299955 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 30467.386754 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 30913.864265 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29886.506047 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 30330.694405 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 30794.736480 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 30285.363110 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29877.417205 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 30968.030723 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 30435.796019 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 56210.991725 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 55996.005800 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 55979.143477 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 56173.137135 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 56039.254506 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 55996.155662 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 56000.834858 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 55941.748977 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 56042.366974 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 61954.445638 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 63277.263158 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 62792.495302 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 61882.321622 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 62592.358832 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 62752.225371 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 62037.302041 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62467.786906 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 62464.268326 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 56994.955295 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 56951.348078 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 56927.564088 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 56965.187477 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 56915.194646 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 56938.064911 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 56817.324255 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 56879.024705 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 56923.450527 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 56994.955295 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 56951.348078 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 56927.564088 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 56965.187477 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 56915.194646 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 56938.064911 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 56817.324255 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 56879.024705 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 56923.450527 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 19361 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 732.189847 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.660754 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.418431 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.928491 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.181835 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 7.391664 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.508374 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.134486 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.764111 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.715029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007481 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007245 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007743 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.007218 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006356 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006967 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007582 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.772635 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 792 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 650 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2105170 # Number of tag accesses +system.l2c.tags.data_accesses 2105170 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 77576 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 77576 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0 276 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 259 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 279 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 261 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 303 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 269 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 291 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 289 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2227 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1751 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1771 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1804 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1773 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1863 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1769 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1750 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1757 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14238 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 10760 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 10778 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 10893 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 11049 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 10672 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 10913 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 11141 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 10949 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 87155 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 12511 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12549 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12697 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12822 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12535 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12682 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12891 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12706 # number of demand (read+write) hits +system.l2c.demand_hits::total 101393 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12511 # number of overall hits +system.l2c.overall_hits::cpu1 12549 # number of overall hits +system.l2c.overall_hits::cpu2 12697 # number of overall hits +system.l2c.overall_hits::cpu3 12822 # number of overall hits +system.l2c.overall_hits::cpu4 12535 # number of overall hits +system.l2c.overall_hits::cpu5 12682 # number of overall hits +system.l2c.overall_hits::cpu6 12891 # number of overall hits +system.l2c.overall_hits::cpu7 12706 # number of overall hits +system.l2c.overall_hits::total 101393 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 2046 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2029 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2111 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2056 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 2033 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 2090 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 2030 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1987 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16382 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4599 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4725 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4817 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4668 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4596 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4594 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4511 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4557 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 37067 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 771 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 761 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 769 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 709 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 779 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 699 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 722 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 759 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 5969 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 5370 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5486 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5586 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5377 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5375 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5293 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5233 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5316 # number of demand (read+write) misses +system.l2c.demand_misses::total 43036 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5370 # number of overall misses +system.l2c.overall_misses::cpu1 5486 # number of overall misses +system.l2c.overall_misses::cpu2 5586 # number of overall misses +system.l2c.overall_misses::cpu3 5377 # number of overall misses +system.l2c.overall_misses::cpu4 5375 # number of overall misses +system.l2c.overall_misses::cpu5 5293 # number of overall misses +system.l2c.overall_misses::cpu6 5233 # number of overall misses +system.l2c.overall_misses::cpu7 5316 # number of overall misses +system.l2c.overall_misses::total 43036 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0 72840477 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 70862981 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 74683475 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 72897976 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 72564980 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 68905302 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 71238981 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 72107979 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 576102151 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 293596847 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 301266861 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 306960376 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 297631356 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 293263365 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 292806382 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 287321715 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 290617373 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2363464275 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 53018410 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 52427412 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 53340392 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 48936413 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 53163418 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 48227901 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 50021405 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 52163904 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 411299255 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 346615257 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 353694273 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 360300768 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 346567769 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 346426783 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 341034283 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 337343120 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 342781277 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2774763530 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 346615257 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 353694273 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 360300768 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 346567769 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 346426783 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 341034283 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 337343120 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 342781277 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2774763530 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 77576 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 77576 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2322 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2288 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2390 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2317 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2336 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2359 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2321 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2276 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18609 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6350 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6496 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6621 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6441 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6459 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6363 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6261 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6314 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51305 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11531 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11539 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11662 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11758 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11451 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11612 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11863 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11708 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 93124 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17881 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18035 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18283 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18199 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17910 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17975 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18124 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18022 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 144429 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17881 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18035 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18283 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18199 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17910 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17975 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18124 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18022 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 144429 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.881137 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.886801 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.883264 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.887354 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.870291 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.885969 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.874623 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.873023 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.880327 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.724252 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.727371 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.727534 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.724732 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.711565 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.721986 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.720492 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.721729 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.722483 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.066863 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.065950 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.065941 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.060299 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.068029 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.060196 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.060862 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.064827 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.064097 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.300319 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.304186 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.305530 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.295456 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.300112 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.294465 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.288733 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.294973 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.297973 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.300319 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.304186 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.305530 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.295456 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.300112 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.294465 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.288733 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.294973 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.297973 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 35601.406158 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 34925.076885 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 35378.244908 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 35456.214008 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 35693.546483 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 32969.044019 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 35093.094089 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 36289.873679 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 35166.777622 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 63839.279626 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 63760.182222 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 63724.387793 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 63759.930591 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 63808.390992 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 63736.696125 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 63693.574595 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 63773.836515 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 63761.952006 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68765.771725 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68892.788436 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69363.318596 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69021.739069 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68245.722721 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68995.566524 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69281.724377 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68727.146245 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 68905.889596 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 64546.602793 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 64472.160591 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 64500.674544 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 64453.741678 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 64451.494512 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 64431.188929 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 64464.574814 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 64481.052859 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 64475.405010 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 64546.602793 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 64472.160591 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 64500.674544 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 64453.741678 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 64451.494512 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 64431.188929 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 64464.574814 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 64481.052859 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 64475.405010 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 37689 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 3488 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 7229 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5.550745 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.213584 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6515 # number of writebacks -system.l2c.writebacks::total 6515 # number of writebacks +system.l2c.writebacks::writebacks 6662 # number of writebacks +system.l2c.writebacks::total 6662 # number of writebacks system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 5 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 5 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 8 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 7 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 6 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu7 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 34 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 69 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 103 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1301 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1301 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1977 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2026 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2150 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2090 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2034 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2069 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2011 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2017 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_hits::total 45 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0 9 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 9 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 12 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3 7 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu4 14 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu5 5 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu6 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu7 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 72 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 17 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 17 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 117 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 1261 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1261 # 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number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15452 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15203 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15190 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 15260 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu4 15274 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu5 15270 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu6 15369 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu7 15339 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 122357 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 109082461 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 108150960 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 112626780 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 109540787 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 108317960 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 111427287 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 108309961 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 105900964 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 873357160 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 247432848 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 253923362 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 258718876 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 250876356 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 247138365 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 246828882 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 242219215 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 244887373 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1992025277 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 45035910 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 44634913 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 45307393 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 41572414 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 44985419 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 41094402 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 42561407 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 44302905 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 349494763 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 292468758 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 298558275 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 304026269 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 292448770 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 292123784 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 287923284 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 284780622 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 289190278 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2341520040 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 292468758 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 298558275 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 304026269 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 292448770 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 292123784 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 287923284 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 284780622 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 289190278 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2341520040 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 521573114 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 514181757 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 515732776 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 517979251 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 524791253 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 517494740 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 519233265 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 524055269 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 4155041425 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 302263386 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 299275381 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 295496378 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 297456387 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 290732905 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 298997210 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 303692889 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 296080198 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2383994734 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 823836500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 813457138 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 811229154 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 815435638 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 815524158 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 816491950 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 822926154 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 820135467 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6539036159 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.888939 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.883173 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.888430 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.880371 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.875592 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.879303 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.882018 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.871274 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.881128 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.732007 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.730787 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.720839 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.723676 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.716926 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.718440 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.723198 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.724731 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.723817 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.064364 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060598 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.063139 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062229 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.061786 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.063510 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.064653 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.065930 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063277 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.304319 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.300185 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.296150 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.293975 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.298531 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.296626 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.305067 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.299170 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.299237 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.304319 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.300185 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.296150 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.293975 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.298531 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.296626 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.305067 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.299170 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.299237 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 45450.420840 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 45460.256170 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 45384.873953 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 45421.041148 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 45371.430678 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 45448.514258 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 45378.159125 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 45405.790778 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45414.855258 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 46229.221491 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 46032.345591 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 46000.198523 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 46190.566761 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 46073.560902 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 46021.316411 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 46020.856869 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45971.206079 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 46067.626088 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52281.249322 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 53772.607504 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 53044.776871 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52136.500000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 52982.239774 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 53144.868673 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52161.531507 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52767.411688 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52778.681055 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 47049.195153 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 47036.276249 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 46969.999063 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 47008.230321 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 46986.732662 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 47003.643652 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 46847.159631 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 46938.682196 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 46979.808316 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 47049.195153 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 47036.276249 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 46969.999063 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 47008.230321 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 46986.732662 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 47003.643652 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 46847.159631 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 46938.682196 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 46979.808316 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44927.218559 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 45002.272561 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 45006.490495 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 45019.805550 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 45047.220146 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44972.916082 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 45028.391963 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44938.341544 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44992.694522 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 46260.365421 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46369.461496 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 46373.118474 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 46391.945900 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 46368.309183 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46372.920254 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46332.743655 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46551.714627 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 46377.702156 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 45397.131308 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45488.328465 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 45493.631832 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 45501.765502 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 45530.216807 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45470.817947 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45492.856836 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45516.504083 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 45486.343181 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.880706 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.884615 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.883264 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.886923 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.869863 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.885969 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.874623 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.873023 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.879897 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.723150 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726601 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.726476 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.723645 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.711101 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.721358 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.719534 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.720779 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.721606 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.066083 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.065170 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.064912 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.059704 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.066806 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.059766 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.060187 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.064144 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063324 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.297163 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.297163 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 53341.056724 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 53434.268775 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 53352.335386 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 53304.519221 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 53306.082677 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 53314.491388 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 53354.660591 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 53296.911928 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 53338.045682 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 53883.459930 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 53797.322458 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 53787.708108 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 53824.577558 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 53807.612671 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 53775.355556 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 53766.751387 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 53809.574379 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 53806.527929 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59102.244094 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59354.937500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59851.245707 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59219.962963 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58804.469281 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59213.835735 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59609.813725 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58991.884154 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59266.536035 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 52764.098533 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 52785.315368 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 52765.784326 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 52785.004688 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 52769.356762 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 52816.364564 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 52783.700823 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 52838.805102 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 52788.573706 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 54295.560625 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 54792.270414 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54559.892541 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 54609.213696 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 54556.747044 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 54641.302997 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 54897.485358 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 54617.265818 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 54621.150483 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 53315.849081 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 53506.356509 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 53405.474259 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 53436.149279 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 53392.965693 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 53470.330714 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 53544.547726 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 53467.336006 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 53442.272686 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 127987 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 121935 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 127545 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 121489 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 78487 # Transaction distribution -system.membus.trans_dist::ReadResp 84311 # Transaction distribution -system.membus.trans_dist::WriteReq 43469 # Transaction distribution -system.membus.trans_dist::WriteResp 43465 # Transaction distribution -system.membus.trans_dist::Writeback 6515 # Transaction distribution -system.membus.trans_dist::CleanEvict 1324 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61199 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50308 # Transaction distribution -system.membus.trans_dist::ReadExReq 49356 # Transaction distribution -system.membus.trans_dist::ReadExResp 3201 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5828 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427463 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 427463 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1116768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1116768 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57043 # Total snoops (count) -system.membus.snoop_fanout::samples 255514 # Request fanout histogram +system.membus.trans_dist::ReadReq 78710 # Transaction distribution +system.membus.trans_dist::ReadResp 84594 # Transaction distribution +system.membus.trans_dist::WriteReq 43645 # Transaction distribution +system.membus.trans_dist::WriteResp 43644 # Transaction distribution +system.membus.trans_dist::WritebackDirty 6662 # Transaction distribution +system.membus.trans_dist::CleanEvict 1288 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60944 # Transaction distribution +system.membus.trans_dist::UpgradeResp 50160 # Transaction distribution +system.membus.trans_dist::ReadExReq 49324 # Transaction distribution +system.membus.trans_dist::ReadExResp 3261 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5890 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 428122 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1134381 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1134381 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 56843 # Total snoops (count) +system.membus.snoop_fanout::samples 246442 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 255514 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 246442 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 255514 # Request fanout histogram -system.membus.reqLayer0.occupancy 292277246 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 56.4 # Layer utilization (%) -system.membus.respLayer0.occupancy 310111858 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 59.8 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 663155 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 282754 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 334620 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12643 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 6068 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6575 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 78490 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370569 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43469 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43464 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 83812 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20730 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29471 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29469 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161822 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161815 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292094 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122083 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122289 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122819 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122567 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122495 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122827 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122357 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122446 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 979883 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1778056 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1772835 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1781127 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1803862 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1797691 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1778038 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1761236 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1781905 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14254750 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 335326 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 800967 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.187618 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.006332 # Request fanout histogram +system.membus.snoop_fanout::total 246442 # Request fanout histogram +system.membus.reqLayer0.occupancy 292771939 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 54.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 296967000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 54.9 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 667370 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 284034 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 336982 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12889 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 5997 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6892 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78711 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370868 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 5 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43646 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43643 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 84238 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 20479 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29389 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29387 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162232 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162225 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292173 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122572 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122851 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122953 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122545 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122770 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122967 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122678 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 981914 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1769628 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1794530 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1801428 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1802844 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1789097 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1796324 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1791880 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1784489 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14330220 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 335082 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 628739 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.148986 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.990092 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 216572 27.04% 27.04% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 322054 40.21% 67.25% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 178446 22.28% 89.53% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 65924 8.23% 97.76% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 15526 1.94% 99.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 2251 0.28% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 192 0.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 2 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 176143 28.02% 28.02% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 257926 41.02% 69.04% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 134453 21.38% 90.42% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 47224 7.51% 97.93% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 11211 1.78% 99.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1632 0.26% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 146 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 800967 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 495267856 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 95.5 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 101287347 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 19.5 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101004376 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 19.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101361922 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101351771 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101153250 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 19.5 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 101246693 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 19.5 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101297808 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 19.5 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101337760 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 19.5 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 628739 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 500695190 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 92.6 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101141048 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 101214213 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101195728 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101296930 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101179412 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 101203668 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101388789 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101354632 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 18.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index 76540bca6..366a5b776 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,1811 +1,1811 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000518 # Number of seconds simulated -sim_ticks 517786000 # Number of ticks simulated -final_tick 517786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000534 # Number of seconds simulated +sim_ticks 534039500 # Number of ticks simulated +final_tick 534039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 99723528 # Simulator tick rate (ticks/s) -host_mem_usage 280036 # Number of bytes of host memory used -host_seconds 5.19 # Real time elapsed on the host +host_tick_rate 107991246 # Simulator tick rate (ticks/s) +host_mem_usage 280540 # Number of bytes of host memory used +host_seconds 4.95 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 82733 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 82298 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 83808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 81707 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 79210 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 80419 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 83957 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 82578 # Number of bytes read from this memory -system.physmem.bytes_read::total 656710 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 415488 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5449 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5329 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5533 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5454 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5382 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5483 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5508 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5404 # Number of bytes written to this memory -system.physmem.bytes_written::total 459030 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10913 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10856 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10917 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10895 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10981 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10993 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11003 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10884 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87442 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6492 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5449 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5329 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5533 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5454 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5382 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5483 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5508 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5404 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50034 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 159782227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 158942111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 161858374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 157800713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 152978257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 155313199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 162146138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 159482875 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1268303894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 802431893 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10523653 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10291897 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10685882 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10533309 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10394256 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10589317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10637599 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10436744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 886524549 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 802431893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 170305879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 169234008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 172544256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 168334022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 163372513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 165902516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 172783737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 169919619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2154828443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 80135 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 83816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 79566 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 82290 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 82935 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 84320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 79631 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 84304 # Number of bytes read from this memory +system.physmem.bytes_read::total 656997 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 418368 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5512 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5388 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5320 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5503 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5449 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5363 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5499 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5488 # Number of bytes written to this memory +system.physmem.bytes_written::total 461890 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10833 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10911 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10989 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10835 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10972 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87288 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6537 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5512 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5388 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5320 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5503 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5449 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5363 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5499 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5488 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50059 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 150054444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 156947192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 148988979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 154089726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 155297501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 157890943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 149110693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 157860982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1230240460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 783402726 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10321334 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10089141 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 9961810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10304481 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10203365 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10042328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10296991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10276393 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 864898570 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 783402726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 160375777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 167036333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 158950789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 164394207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 165500867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 167933271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 159407684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 168137376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2095139030 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99592 # number of read accesses completed -system.cpu0.num_writes 55369 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22465 # number of replacements -system.cpu0.l1c.tags.tagsinuse 392.038302 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13410 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22854 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.586768 # Average number of references to valid blocks. +system.cpu0.num_reads 98970 # number of read accesses completed +system.cpu0.num_writes 54697 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22262 # number of replacements +system.cpu0.l1c.tags.tagsinuse 392.444163 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13142 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22657 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.580041 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 392.038302 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.765700 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.765700 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338870 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338870 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8751 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8751 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1148 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1148 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9899 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9899 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9899 # number of overall hits -system.cpu0.l1c.overall_hits::total 9899 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36676 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36676 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23894 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23894 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60570 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60570 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60570 # number of overall misses -system.cpu0.l1c.overall_misses::total 60570 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 605837577 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 605837577 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 675142476 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 675142476 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1280980053 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1280980053 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1280980053 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1280980053 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45427 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45427 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25042 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25042 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70469 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70469 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70469 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70469 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807361 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807361 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954157 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954157 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.859527 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.859527 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.859527 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.859527 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16518.638265 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16518.638265 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28255.732653 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 28255.732653 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 21148.754383 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 21148.754383 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 21148.754383 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 21148.754383 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 743435 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 392.444163 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.766493 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.766493 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 335259 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 335259 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8424 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8424 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1108 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1108 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9532 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9532 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9532 # number of overall hits +system.cpu0.l1c.overall_hits::total 9532 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36392 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36392 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23768 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23768 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60160 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60160 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60160 # number of overall misses +system.cpu0.l1c.overall_misses::total 60160 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 598420373 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 598420373 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 705577272 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 705577272 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1303997645 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1303997645 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1303997645 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1303997645 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44816 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44816 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24876 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24876 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 69692 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 69692 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 69692 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 69692 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.812031 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.812031 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955459 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.955459 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.863227 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.863227 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.863227 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.863227 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16443.734145 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16443.734145 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 29686.017839 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 29686.017839 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21675.492769 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21675.492769 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21675.492769 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21675.492769 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 798798 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 61083 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61887 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.170899 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.907363 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9922 # number of writebacks -system.cpu0.l1c.writebacks::total 9922 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36676 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36676 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23894 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23894 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60570 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60570 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60570 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60570 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9773 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5450 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5450 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15223 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15223 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 569161577 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 569161577 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 651248476 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 651248476 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1220410053 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1220410053 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1220410053 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1220410053 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 638102868 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 638102868 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 843396249 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 843396249 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1481499117 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1481499117 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807361 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807361 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954157 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954157 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859527 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.859527 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859527 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.859527 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15518.638265 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15518.638265 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27255.732653 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27255.732653 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20148.754383 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20148.754383 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20148.754383 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20148.754383 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65292.424844 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65292.424844 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 154751.605321 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154751.605321 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 97319.786967 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 97319.786967 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9766 # number of writebacks +system.cpu0.l1c.writebacks::total 9766 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36392 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36392 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23768 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23768 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60160 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60160 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60160 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60160 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9799 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9799 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5512 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5512 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15311 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15311 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 562029373 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 562029373 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 681810272 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 681810272 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1243839645 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1243839645 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1243839645 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1243839645 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 706647630 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 706647630 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 855364129 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 855364129 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1562011759 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1562011759 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.812031 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.812031 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955459 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955459 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.863227 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.863227 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.863227 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.863227 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15443.761623 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15443.761623 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 28686.059912 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 28686.059912 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20675.526014 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20675.526014 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20675.526014 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20675.526014 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 72114.259618 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72114.259618 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 155182.171444 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155182.171444 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102018.924891 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102018.924891 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99505 # number of read accesses completed -system.cpu1.num_writes 55135 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22526 # number of replacements -system.cpu1.l1c.tags.tagsinuse 393.510444 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13408 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22912 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.585196 # Average number of references to valid blocks. +system.cpu1.num_reads 98379 # number of read accesses completed +system.cpu1.num_writes 54883 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22236 # number of replacements +system.cpu1.l1c.tags.tagsinuse 391.015365 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13378 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22622 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.591371 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 393.510444 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.768575 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.768575 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_blocks::cpu1 391.015365 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.763702 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.763702 # Average percentage of cache occupancy system.cpu1.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id system.cpu1.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 339206 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 339206 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8687 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8687 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1167 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1167 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9854 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9854 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9854 # number of overall hits -system.cpu1.l1c.overall_hits::total 9854 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36759 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36759 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23925 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23925 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60684 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60684 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60684 # number of overall misses -system.cpu1.l1c.overall_misses::total 60684 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 611192958 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 611192958 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 677073428 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 677073428 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1288266386 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1288266386 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1288266386 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1288266386 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45446 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45446 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25092 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25092 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70538 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70538 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70538 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70538 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808850 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.808850 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953491 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.953491 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.860302 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.860302 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.860302 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.860302 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16627.028972 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16627.028972 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28299.829801 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 28299.829801 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 21229.094753 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 21229.094753 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 21229.094753 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 21229.094753 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 746931 # number of cycles access was blocked +system.cpu1.l1c.tags.tag_accesses 335372 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 335372 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8546 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8546 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1143 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1143 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9689 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9689 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9689 # number of overall hits +system.cpu1.l1c.overall_hits::total 9689 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36240 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36240 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23835 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23835 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60075 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60075 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60075 # number of overall misses +system.cpu1.l1c.overall_misses::total 60075 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 593535449 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 593535449 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 712426271 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 712426271 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1305961720 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1305961720 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1305961720 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1305961720 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44786 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44786 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24978 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24978 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 69764 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 69764 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 69764 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 69764 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809181 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.809181 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954240 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954240 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.861117 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.861117 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.861117 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.861117 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16377.909741 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16377.909741 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 29889.921166 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 29889.921166 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 21738.855098 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 21738.855098 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 21738.855098 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 21738.855098 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 803378 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 61259 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 62137 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.193000 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.929140 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9855 # number of writebacks -system.cpu1.l1c.writebacks::total 9855 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36759 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36759 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23925 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23925 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60684 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60684 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60684 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60684 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9724 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9724 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5329 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15053 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15053 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 574433958 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 574433958 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 653148428 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 653148428 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1227582386 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1227582386 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1227582386 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1227582386 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 636306689 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 636306689 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 841464320 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 841464320 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1477771009 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1477771009 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808850 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808850 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953491 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953491 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860302 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.860302 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860302 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.860302 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15627.028972 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15627.028972 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27299.829801 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27299.829801 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20229.094753 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20229.094753 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20229.094753 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20229.094753 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65436.722439 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65436.722439 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157902.856071 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157902.856071 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 98171.195708 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 98171.195708 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9779 # number of writebacks +system.cpu1.l1c.writebacks::total 9779 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36240 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36240 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23835 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23835 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60075 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60075 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60075 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60075 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9833 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9833 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5388 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5388 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15221 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15221 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 557295449 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 557295449 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 688592271 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 688592271 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1245887720 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1245887720 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1245887720 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1245887720 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 707451122 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 707451122 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 858171680 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 858171680 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1565622802 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1565622802 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809181 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809181 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954240 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954240 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861117 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.861117 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861117 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.861117 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15377.909741 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15377.909741 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 28889.963121 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 28889.963121 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20738.871744 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20738.871744 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20738.871744 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20738.871744 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 71946.620767 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71946.620767 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 159274.625093 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159274.625093 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 102859.391761 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 102859.391761 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99747 # number of read accesses completed -system.cpu2.num_writes 54917 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22440 # number of replacements -system.cpu2.l1c.tags.tagsinuse 392.958774 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13419 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22848 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.587316 # Average number of references to valid blocks. +system.cpu2.num_reads 99126 # number of read accesses completed +system.cpu2.num_writes 55057 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22416 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.045662 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13448 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22823 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.589230 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 392.958774 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.767498 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.767498 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 337058 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 337058 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8566 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8566 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1197 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1197 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9763 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9763 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9763 # number of overall hits -system.cpu2.l1c.overall_hits::total 9763 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36656 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36656 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23689 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23689 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60345 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60345 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60345 # number of overall misses -system.cpu2.l1c.overall_misses::total 60345 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 609273651 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 609273651 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 671190571 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 671190571 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1280464222 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1280464222 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1280464222 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1280464222 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45222 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45222 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24886 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24886 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70108 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70108 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70108 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70108 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.810579 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.810579 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.951901 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.951901 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.860743 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.860743 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.860743 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.860743 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16621.389431 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16621.389431 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 28333.427793 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 28333.427793 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 21219.060767 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 21219.060767 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 21219.060767 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 21219.060767 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 742867 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.045662 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.765714 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.765714 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337969 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337969 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8656 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8656 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1187 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1187 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9843 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9843 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9843 # number of overall hits +system.cpu2.l1c.overall_hits::total 9843 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36613 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36613 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23839 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23839 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60452 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60452 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60452 # number of overall misses +system.cpu2.l1c.overall_misses::total 60452 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 594021809 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 594021809 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 716005587 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 716005587 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1310027396 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1310027396 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1310027396 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1310027396 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45269 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45269 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25026 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25026 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70295 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70295 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70295 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70295 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808787 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.808787 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952569 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.952569 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.859976 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.859976 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.859976 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.859976 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16224.341327 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16224.341327 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30035.051261 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 30035.051261 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 21670.538543 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 21670.538543 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 21670.538543 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 21670.538543 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 801429 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 60931 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 62324 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.191938 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.859075 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9836 # number of writebacks -system.cpu2.l1c.writebacks::total 9836 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36656 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36656 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23689 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23689 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60345 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60345 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60345 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60345 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9760 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9760 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5535 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5535 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15295 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15295 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 572617651 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 572617651 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 647503571 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 647503571 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1220121222 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1220121222 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1220121222 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1220121222 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 638440786 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 638440786 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 853548639 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 853548639 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1491989425 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1491989425 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.810579 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.810579 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.951901 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.951901 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860743 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.860743 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860743 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.860743 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15621.389431 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15621.389431 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 27333.512221 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 27333.512221 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20219.093910 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20219.093910 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65414.014959 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65414.014959 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154209.329539 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154209.329539 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97547.526970 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97547.526970 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9798 # number of writebacks +system.cpu2.l1c.writebacks::total 9798 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36613 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36613 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23839 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23839 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60452 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60452 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60452 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60452 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9743 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5322 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5322 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15065 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15065 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 557410809 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 557410809 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 692167587 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 692167587 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1249578396 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1249578396 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1249578396 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1249578396 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 702012144 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 702012144 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 835893746 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 835893746 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1537905890 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1537905890 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808787 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808787 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952569 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952569 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859976 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.859976 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859976 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.859976 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15224.395952 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15224.395952 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29035.093209 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29035.093209 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20670.588169 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20670.588169 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20670.588169 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20670.588169 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 72052.975880 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72052.975880 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 157063.838031 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157063.838031 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 102084.692333 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 102084.692333 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98987 # number of read accesses completed -system.cpu3.num_writes 55311 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22430 # number of replacements -system.cpu3.l1c.tags.tagsinuse 392.656254 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13364 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22840 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.585114 # Average number of references to valid blocks. +system.cpu3.num_reads 99267 # number of read accesses completed +system.cpu3.num_writes 54937 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22308 # number of replacements +system.cpu3.l1c.tags.tagsinuse 393.396608 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13642 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22699 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.600996 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 392.656254 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.766907 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.766907 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337200 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337200 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8601 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8601 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1133 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1133 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9734 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9734 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9734 # number of overall hits -system.cpu3.l1c.overall_hits::total 9734 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36299 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36299 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 24092 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 24092 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60391 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60391 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60391 # number of overall misses -system.cpu3.l1c.overall_misses::total 60391 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 601442350 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 601442350 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 682370713 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 682370713 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1283813063 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1283813063 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1283813063 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1283813063 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44900 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44900 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25225 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25225 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70125 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70125 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70125 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70125 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808441 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.808441 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955084 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.955084 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.861191 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.861191 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.861191 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.861191 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16569.116229 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16569.116229 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28323.539474 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 28323.539474 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 21258.350797 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 21258.350797 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 21258.350797 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 21258.350797 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 746578 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 393.396608 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.768353 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.768353 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 377 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 336965 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 336965 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8834 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8834 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1126 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1126 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9960 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9960 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9960 # number of overall hits +system.cpu3.l1c.overall_hits::total 9960 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36404 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36404 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23769 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23769 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60173 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60173 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60173 # number of overall misses +system.cpu3.l1c.overall_misses::total 60173 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 595557078 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 595557078 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 707954928 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 707954928 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1303512006 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1303512006 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1303512006 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1303512006 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45238 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45238 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24895 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24895 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70133 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70133 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70133 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70133 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.804722 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.804722 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954770 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954770 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.857984 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.857984 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.857984 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.857984 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16359.660422 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16359.660422 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 29784.800707 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 29784.800707 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 21662.739202 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 21662.739202 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 21662.739202 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 21662.739202 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 796210 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 60969 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 61792 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.245207 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.885325 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9891 # number of writebacks -system.cpu3.l1c.writebacks::total 9891 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36299 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36299 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24092 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 24092 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60391 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60391 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60391 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60391 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9771 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9771 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5455 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5455 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15226 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15226 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 565143350 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 565143350 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 658281713 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 658281713 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1223425063 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1223425063 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1223425063 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1223425063 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 638944774 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 638944774 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 852450723 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 852450723 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1491395497 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1491395497 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808441 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808441 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955084 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955084 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861191 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.861191 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861191 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.861191 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15569.116229 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15569.116229 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27323.663996 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27323.663996 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20258.400474 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20258.400474 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20258.400474 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20258.400474 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65391.953127 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65391.953127 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 156269.610082 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156269.610082 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97950.577762 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97950.577762 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9835 # number of writebacks +system.cpu3.l1c.writebacks::total 9835 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36404 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36404 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23769 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23769 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60173 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60173 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60173 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60173 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9778 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9778 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5503 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5503 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15281 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15281 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 559153078 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 559153078 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 684188928 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 684188928 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1243342006 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1243342006 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1243342006 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1243342006 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 702217176 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 702217176 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 867552200 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 867552200 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1569769376 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1569769376 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.804722 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.804722 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954770 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954770 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857984 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.857984 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857984 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.857984 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15359.660422 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15359.660422 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 28784.926922 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 28784.926922 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20662.789058 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20662.789058 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20662.789058 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20662.789058 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 71816.033545 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71816.033545 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 157650.772306 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157650.772306 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102726.874943 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102726.874943 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 54901 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22108 # number of replacements -system.cpu4.l1c.tags.tagsinuse 392.325245 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13548 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22499 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.602160 # Average number of references to valid blocks. +system.cpu4.num_reads 98613 # number of read accesses completed +system.cpu4.num_writes 54610 # number of write accesses completed +system.cpu4.l1c.tags.replacements 21998 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.447255 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13326 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22393 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.595097 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 392.325245 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.766260 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.766260 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 338175 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 338175 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8785 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8785 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1156 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1156 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9941 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9941 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9941 # number of overall hits -system.cpu4.l1c.overall_hits::total 9941 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36616 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36616 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23803 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23803 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60419 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60419 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60419 # number of overall misses -system.cpu4.l1c.overall_misses::total 60419 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 606172682 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 606172682 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 676089465 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 676089465 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1282262147 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1282262147 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1282262147 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1282262147 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45401 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45401 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24959 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70360 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70360 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70360 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70360 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806502 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.806502 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953684 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953684 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.858712 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.858712 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.858712 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.858712 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16554.858040 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16554.858040 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28403.540100 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 28403.540100 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 21222.829689 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 21222.829689 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 21222.829689 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 21222.829689 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 752786 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.447255 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.766499 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.766499 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 385 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 335144 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 335144 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8557 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8557 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1170 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1170 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9727 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9727 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9727 # number of overall hits +system.cpu4.l1c.overall_hits::total 9727 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36223 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36223 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23758 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23758 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59981 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59981 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59981 # number of overall misses +system.cpu4.l1c.overall_misses::total 59981 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 587952444 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 587952444 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 716203349 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 716203349 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1304155793 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1304155793 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1304155793 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1304155793 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44780 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44780 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24928 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24928 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 69708 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 69708 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 69708 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 69708 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.808910 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.808910 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953065 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953065 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.860461 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.860461 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.860461 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.860461 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16231.467410 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16231.467410 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30145.776118 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 30145.776118 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 21742.815108 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 21742.815108 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 21742.815108 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 21742.815108 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 805297 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 61311 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61957 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.278156 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.997676 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9736 # number of writebacks -system.cpu4.l1c.writebacks::total 9736 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36616 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36616 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23803 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23803 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60419 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60419 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60419 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60419 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9898 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9898 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5382 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5382 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15280 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15280 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 569559682 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 569559682 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 652287465 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 652287465 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1221847147 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1221847147 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1221847147 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1221847147 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 646717625 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 646717625 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 846861232 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 846861232 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1493578857 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1493578857 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806502 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806502 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953684 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953684 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858712 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.858712 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858712 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.858712 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15554.939972 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15554.939972 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27403.582111 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27403.582111 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20222.895894 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20222.895894 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20222.895894 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20222.895894 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65338.212265 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65338.212265 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157350.656262 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157350.656262 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 97747.307395 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 97747.307395 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9749 # number of writebacks +system.cpu4.l1c.writebacks::total 9749 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36223 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36223 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23758 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23758 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59981 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59981 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59981 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59981 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9847 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9847 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5452 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5452 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15299 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15299 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 551729444 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 551729444 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 692447349 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 692447349 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1244176793 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1244176793 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1244176793 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1244176793 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 708336585 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 708336585 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 860694197 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 860694197 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1569030782 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1569030782 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.808910 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.808910 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953065 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953065 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860461 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.860461 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860461 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.860461 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15231.467410 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15231.467410 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29145.860300 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29145.860300 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20742.848452 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20742.848452 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20742.848452 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20742.848452 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 71934.252564 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71934.252564 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157867.607667 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157867.607667 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102557.734623 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102557.734623 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99420 # number of read accesses completed -system.cpu5.num_writes 55050 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22127 # number of replacements -system.cpu5.l1c.tags.tagsinuse 390.223258 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13616 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22515 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.604752 # Average number of references to valid blocks. +system.cpu5.num_reads 99530 # number of read accesses completed +system.cpu5.num_writes 55068 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22260 # number of replacements +system.cpu5.l1c.tags.tagsinuse 393.692529 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13670 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22641 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.603772 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 390.223258 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.762155 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.762155 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 338569 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 338569 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8830 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8830 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1218 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1218 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 10048 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 10048 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 10048 # number of overall hits -system.cpu5.l1c.overall_hits::total 10048 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36409 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36409 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23995 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23995 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60404 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60404 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60404 # number of overall misses -system.cpu5.l1c.overall_misses::total 60404 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 603629256 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 603629256 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 675904407 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 675904407 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1279533663 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1279533663 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1279533663 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1279533663 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45239 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45239 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25213 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25213 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70452 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70452 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70452 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70452 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.804814 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.804814 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951692 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.951692 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.857378 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.857378 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.857378 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.857378 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16579.122085 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16579.122085 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 28168.552073 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 28168.552073 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 21182.929326 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 21182.929326 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 21182.929326 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 21182.929326 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 750665 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 393.692529 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.768931 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.768931 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337364 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337364 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8908 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8908 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1154 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1154 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 10062 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 10062 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 10062 # number of overall hits +system.cpu5.l1c.overall_hits::total 10062 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36264 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36264 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23895 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23895 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60159 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60159 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60159 # number of overall misses +system.cpu5.l1c.overall_misses::total 60159 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 595565994 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 595565994 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 715910266 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 715910266 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1311476260 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1311476260 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1311476260 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1311476260 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45172 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45172 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25049 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70221 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70221 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70221 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70221 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.802798 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.802798 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953930 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.953930 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.856710 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.856710 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.856710 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.856710 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16423.064030 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16423.064030 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 29960.672358 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 29960.672358 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 21800.167224 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 21800.167224 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 21800.167224 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 21800.167224 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 800309 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 61291 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61932 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.247557 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.922383 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9761 # number of writebacks -system.cpu5.l1c.writebacks::total 9761 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36409 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36409 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23995 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23995 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60404 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60404 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60404 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60404 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9891 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9891 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5483 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5483 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15374 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15374 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 567222256 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 567222256 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 651909407 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 651909407 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1219131663 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1219131663 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1219131663 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1219131663 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 648234678 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 648234678 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 860459231 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 860459231 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1508693909 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1508693909 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.804814 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.804814 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951692 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951692 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.857378 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.857378 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.857378 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.857378 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15579.177017 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15579.177017 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 27168.552073 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27168.552073 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20182.962436 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20182.962436 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20182.962436 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20182.962436 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65537.830149 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65537.830149 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 156932.196061 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156932.196061 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 98132.815728 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 98132.815728 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9774 # number of writebacks +system.cpu5.l1c.writebacks::total 9774 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36264 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36264 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23895 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23895 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60159 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60159 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60159 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60159 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9698 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9698 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5363 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5363 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15061 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15061 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 559302994 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 559302994 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 692016266 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 692016266 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1251319260 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1251319260 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1251319260 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1251319260 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 697234186 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 697234186 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 847695253 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 847695253 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1544929439 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1544929439 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.802798 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.802798 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953930 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953930 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.856710 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.856710 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.856710 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.856710 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15423.091606 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15423.091606 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 28960.714208 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 28960.714208 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20800.200469 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20800.200469 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20800.200469 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20800.200469 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 71894.636626 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71894.636626 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 158063.630990 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158063.630990 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 102578.144811 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 102578.144811 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99130 # number of read accesses completed -system.cpu6.num_writes 55082 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22211 # number of replacements -system.cpu6.l1c.tags.tagsinuse 391.729996 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22620 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.594651 # Average number of references to valid blocks. +system.cpu6.num_reads 100001 # number of read accesses completed +system.cpu6.num_writes 54955 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22371 # number of replacements +system.cpu6.l1c.tags.tagsinuse 392.789220 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13659 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22773 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.599789 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 391.729996 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.765098 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.765098 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338357 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338357 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8673 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8673 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1155 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1155 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9828 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9828 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9828 # number of overall hits -system.cpu6.l1c.overall_hits::total 9828 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36524 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36524 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 24020 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 24020 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60544 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60544 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60544 # number of overall misses -system.cpu6.l1c.overall_misses::total 60544 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 604615121 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 604615121 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 676363327 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 676363327 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1280978448 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1280978448 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1280978448 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1280978448 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45197 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45197 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25175 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25175 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70372 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70372 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808107 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.808107 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954121 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954121 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.860342 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.860342 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.860342 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.860342 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16553.913071 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16553.913071 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28158.340008 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 28158.340008 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 21157.809989 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 21157.809989 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 21157.809989 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 21157.809989 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 747919 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 392.789220 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.767166 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.767166 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338676 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338676 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8791 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8791 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1193 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1193 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9984 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9984 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9984 # number of overall hits +system.cpu6.l1c.overall_hits::total 9984 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36779 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36779 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23715 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23715 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60494 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60494 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60494 # number of overall misses +system.cpu6.l1c.overall_misses::total 60494 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 595549144 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 595549144 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 708070907 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 708070907 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1303620051 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1303620051 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1303620051 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1303620051 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45570 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45570 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24908 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70478 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70478 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70478 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70478 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807088 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807088 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.952104 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.952104 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858339 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858339 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858339 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858339 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16192.641018 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16192.641018 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 29857.512418 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 29857.512418 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21549.576008 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21549.576008 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21549.576008 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21549.576008 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 794028 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61299 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 62044 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.201162 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.797821 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9790 # number of writebacks -system.cpu6.l1c.writebacks::total 9790 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36524 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36524 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24020 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 24020 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60544 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60544 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9846 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9846 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5510 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5510 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15356 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15356 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 568091121 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 568091121 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 652345327 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 652345327 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1220436448 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1220436448 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1220436448 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1220436448 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 644948195 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 644948195 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 860679200 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 860679200 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1505627395 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1505627395 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808107 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808107 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954121 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954121 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860342 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.860342 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860342 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.860342 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15553.913071 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15553.913071 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27158.423272 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27158.423272 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20157.843023 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20157.843023 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20157.843023 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20157.843023 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65503.574548 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65503.574548 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156203.121597 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156203.121597 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 98048.150234 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 98048.150234 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9773 # number of writebacks +system.cpu6.l1c.writebacks::total 9773 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36779 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36779 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23715 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23715 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60494 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60494 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60494 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60494 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9743 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5502 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5502 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15245 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15245 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 558770144 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 558770144 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 684356907 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 684356907 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1243127051 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1243127051 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1243127051 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1243127051 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702205139 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702205139 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 875087157 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 875087157 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1577292296 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1577292296 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807088 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807088 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.952104 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952104 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858339 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858339 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858339 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858339 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15192.641018 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15192.641018 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 28857.554586 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 28857.554586 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20549.592538 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20549.592538 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20549.592538 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20549.592538 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 72072.784461 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72072.784461 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 159048.919847 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159048.919847 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103462.925287 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103462.925287 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99282 # number of read accesses completed -system.cpu7.num_writes 55000 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22412 # number of replacements -system.cpu7.l1c.tags.tagsinuse 392.240178 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13369 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22828 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.585640 # Average number of references to valid blocks. +system.cpu7.num_reads 99732 # number of read accesses completed +system.cpu7.num_writes 55186 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22105 # number of replacements +system.cpu7.l1c.tags.tagsinuse 391.370136 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13595 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22490 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.604491 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 392.240178 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.766094 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.766094 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 337994 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 337994 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8608 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8608 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1119 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1119 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9727 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9727 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9727 # number of overall hits -system.cpu7.l1c.overall_hits::total 9727 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36557 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36557 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 24000 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 24000 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60557 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60557 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60557 # number of overall misses -system.cpu7.l1c.overall_misses::total 60557 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 604992547 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 604992547 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 682517760 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 682517760 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1287510307 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1287510307 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1287510307 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1287510307 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45165 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45165 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25119 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25119 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70284 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70284 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70284 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70284 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.809410 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.809410 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955452 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955452 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.861604 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.861604 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.861604 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.861604 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16549.294171 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16549.294171 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28438.240000 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 28438.240000 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 21261.130951 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 21261.130951 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 21261.130951 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 21261.130951 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 748003 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 391.370136 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.764395 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.764395 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 385 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.751953 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337196 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337196 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8779 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8779 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1155 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1155 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9934 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9934 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9934 # number of overall hits +system.cpu7.l1c.overall_hits::total 9934 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36327 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36327 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23913 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23913 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60240 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60240 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60240 # number of overall misses +system.cpu7.l1c.overall_misses::total 60240 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 591115609 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 591115609 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 714870765 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 714870765 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1305986374 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1305986374 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1305986374 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1305986374 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45106 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45106 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25068 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25068 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70174 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70174 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70174 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70174 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805370 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.805370 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953925 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953925 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858438 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858438 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858438 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858438 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16272.073361 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16272.073361 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 29894.649981 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 29894.649981 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21679.720684 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21679.720684 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21679.720684 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21679.720684 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 800916 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 61301 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 62109 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.202134 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.895329 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9927 # number of writebacks -system.cpu7.l1c.writebacks::total 9927 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36557 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36557 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24000 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60557 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60557 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60557 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60557 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9747 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9747 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5404 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5404 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15151 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15151 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 568436547 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 568436547 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 658518760 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 658518760 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1226955307 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1226955307 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1226955307 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1226955307 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 638135236 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 638135236 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 851560751 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 851560751 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1489695987 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1489695987 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.809410 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.809410 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955452 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955452 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.861604 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.861604 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.861604 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.861604 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15549.321525 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15549.321525 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27438.281667 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27438.281667 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20261.163978 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20261.163978 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20261.163978 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20261.163978 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65469.912383 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65469.912383 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 157579.709660 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157579.709660 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 98323.278133 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 98323.278133 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9688 # number of writebacks +system.cpu7.l1c.writebacks::total 9688 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36327 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36327 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23913 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23913 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60240 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60240 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60240 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60240 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9808 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9808 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5490 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5490 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15298 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15298 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 554789609 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 554789609 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 690958765 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 690958765 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1245748374 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1245748374 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1245748374 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1245748374 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 704741576 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 704741576 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 868948151 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 868948151 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1573689727 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1573689727 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805370 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805370 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953925 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953925 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858438 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858438 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858438 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858438 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15272.100889 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15272.100889 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 28894.691799 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 28894.691799 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20679.753884 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20679.753884 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20679.753884 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20679.753884 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 71853.749592 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71853.749592 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 158278.351730 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158278.351730 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102868.984639 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102868.984639 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 14184 # number of replacements -system.l2c.tags.tagsinuse 788.596931 # Cycle average of tags in use -system.l2c.tags.total_refs 165124 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14990 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.015610 # Average number of references to valid blocks. +system.l2c.tags.replacements 13995 # number of replacements +system.l2c.tags.tagsinuse 787.283340 # Cycle average of tags in use +system.l2c.tags.total_refs 163090 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14802 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.018106 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 730.575268 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.784178 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.707727 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.687216 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.484376 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.524449 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 7.360121 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.299960 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.173635 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.713452 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006625 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007527 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007507 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007309 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006372 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.007188 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.007129 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.007006 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.770114 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 806 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 681 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2105340 # Number of tag accesses -system.l2c.tags.data_accesses 2105340 # Number of data accesses -system.l2c.Writeback_hits::writebacks 77391 # number of Writeback hits -system.l2c.Writeback_hits::total 77391 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 263 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 239 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 258 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 273 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 248 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 266 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 263 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2093 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1731 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1747 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1743 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1722 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1763 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1786 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1787 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1783 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14062 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10988 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10938 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10927 # number of ReadSharedReq hits +system.l2c.tags.occ_blocks::writebacks 729.204744 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.276243 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.685702 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.303189 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.305571 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.947966 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.333904 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.314281 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 6.911739 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.712114 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007106 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007506 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007132 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007134 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006785 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007143 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006750 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768831 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 807 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 673 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.788086 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2092027 # Number of tag accesses +system.l2c.tags.data_accesses 2092027 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 76994 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 76994 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0 283 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 283 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 290 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 275 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 271 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 268 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 273 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 273 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2216 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1696 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1826 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1766 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1793 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1691 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1701 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1693 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1794 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 13960 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 10787 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 10737 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 10799 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu3 10853 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 11009 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10877 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 10827 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10964 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 87383 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12719 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12685 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12670 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12575 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12772 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12663 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12614 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12747 # number of demand (read+write) hits -system.l2c.demand_hits::total 101445 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12719 # number of overall hits -system.l2c.overall_hits::cpu1 12685 # number of overall hits -system.l2c.overall_hits::cpu2 12670 # number of overall hits -system.l2c.overall_hits::cpu3 12575 # number of overall hits -system.l2c.overall_hits::cpu4 12772 # number of overall hits -system.l2c.overall_hits::cpu5 12663 # number of overall hits -system.l2c.overall_hits::cpu6 12614 # number of overall hits -system.l2c.overall_hits::cpu7 12747 # number of overall hits -system.l2c.overall_hits::total 101445 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 1986 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2040 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2071 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2052 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2099 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2039 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2050 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2087 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16424 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4684 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4646 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4587 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4709 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4574 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4603 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4641 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4708 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37152 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 746 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 738 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 778 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 755 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 710 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 726 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 763 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 735 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5951 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5430 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5384 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5365 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5464 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5284 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5329 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5404 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5443 # number of demand (read+write) misses -system.l2c.demand_misses::total 43103 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5430 # number of overall misses -system.l2c.overall_misses::cpu1 5384 # number of overall misses -system.l2c.overall_misses::cpu2 5365 # number of overall misses -system.l2c.overall_misses::cpu3 5464 # number of overall misses -system.l2c.overall_misses::cpu4 5284 # number of overall misses -system.l2c.overall_misses::cpu5 5329 # number of overall misses -system.l2c.overall_misses::cpu6 5404 # number of overall misses -system.l2c.overall_misses::cpu7 5443 # number of overall misses -system.l2c.overall_misses::total 43103 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 59643812 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 60697485 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 64325987 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 61406491 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 65507992 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 63321487 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 63031988 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 64081491 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 502016733 # 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number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 46986917 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 43700923 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 45387411 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 47108917 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 45792412 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 368245824 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 306640319 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 303351339 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 302797833 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 307866334 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 297676352 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 300924320 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 304570833 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 307193843 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2431021173 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 306640319 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 303351339 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 302797833 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 307866334 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 297676352 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 300924320 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 304570833 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 307193843 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2431021173 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 77391 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 77391 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2249 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2279 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2329 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2325 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2347 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2305 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2313 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2370 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18517 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6415 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6393 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6330 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6431 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6337 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6389 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6428 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6491 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 51214 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11734 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11676 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11705 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11608 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11719 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11603 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11590 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11699 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 93334 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 18149 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18069 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18035 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18039 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18056 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17992 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 18018 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18190 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 144548 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 18149 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18069 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18035 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18039 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18056 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17992 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 18018 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18190 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 144548 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.883059 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.895129 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.889223 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.882581 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.894333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.884599 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.886295 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.880591 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.886969 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.730164 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.726732 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.724645 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.732234 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.721793 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.720457 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.721998 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.725312 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.725427 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.063576 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.063207 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.066467 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.065041 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.060585 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.062570 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.065833 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.062826 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.063760 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.299190 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.297969 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.297477 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.302899 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.292645 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.296187 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.299922 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.299230 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.298192 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.299190 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.297969 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.297477 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.302899 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.292645 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.296187 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.299922 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.299230 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.298192 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 30032.130916 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 29753.669118 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 31060.351038 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 29925.190546 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 31209.143402 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 31055.167729 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 30747.311220 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 30705.074748 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 30566.045604 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 55648.145816 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 55578.758502 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 55514.589056 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 55400.173498 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 55525.891780 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 55515.296328 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 55475.525964 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 55522.818819 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 55522.592297 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 61641.292225 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 61155.050136 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 61892.561697 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 62234.327152 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 61550.595775 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 62517.095041 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 61741.699869 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62302.601361 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 61879.654512 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 56471.513628 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 56343.116456 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 56439.484250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 56344.497438 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 56335.418622 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 56469.191218 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 56360.257772 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 56438.332353 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 56400.277776 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 56471.513628 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 56343.116456 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 56439.484250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 56344.497438 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 56335.418622 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 56469.191218 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 56360.257772 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 56438.332353 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 56400.277776 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 17704 # number of cycles access was blocked +system.l2c.ReadSharedReq_hits::cpu4 10789 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 10747 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 10936 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 10812 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 86460 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 12483 # 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number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 50638402 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 48277416 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 51495417 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 49403402 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 50638912 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 403370758 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 332201277 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 338148266 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 340044284 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 336285098 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 340734294 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 339429288 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 335167781 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 341384275 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2703394563 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 332201277 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 338148266 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 340044284 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 336285098 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 340734294 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 339429288 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 335167781 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 341384275 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2703394563 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 76994 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 76994 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2287 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2378 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2328 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2336 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2349 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2368 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2347 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2342 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18735 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6220 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6394 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6430 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6373 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6375 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6310 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6280 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6461 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50843 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11521 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11527 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11528 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11595 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11505 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11516 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11661 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11556 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 92409 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17741 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17921 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17958 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17968 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17880 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17826 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17941 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18017 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143252 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17741 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17921 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17958 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17968 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17880 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17826 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17941 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18017 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143252 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.876257 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.880992 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.875430 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.882277 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.884632 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.886824 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.883681 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.883433 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.881719 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.727331 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.714420 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.725350 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.718657 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.734745 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.730428 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.730414 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.722334 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.725429 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.063710 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.068535 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.063237 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.063993 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.062234 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.066777 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.062173 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.064382 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.064377 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.296376 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.298979 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.300312 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.296193 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.302013 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.301694 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.296082 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.300327 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.298998 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.296376 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.298979 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.300312 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.296193 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.302013 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.301694 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.296082 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.300327 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.298998 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 34087.565868 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 34057.982816 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 35130.263003 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 34039.291121 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 34562.309432 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 34068.563810 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 34543.625362 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 36143.692122 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 34578.524850 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 62346.677498 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 62366.215193 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 62292.319468 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 62368.274236 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 62437.420581 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 62472.091777 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 62298.752780 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 62298.127919 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 62359.997967 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68317.313351 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 67416.955696 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 67918.938272 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68245.824798 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 67426.558659 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 66964.131339 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68142.623448 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68063.053763 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 67804.800471 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 63180.159186 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 63110.911907 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 63052.898943 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 63187.729801 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 63098.943333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 63114.408330 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 63096.344315 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 63090.791905 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 63116.234661 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 63180.159186 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 63110.911907 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 63052.898943 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 63187.729801 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 63098.943333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 63114.408330 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 63096.344315 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 63090.791905 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 63116.234661 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 33757 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 3172 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 6432 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5.581337 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.248290 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6492 # number of writebacks -system.l2c.writebacks::total 6492 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 8 # number of ReadExReq MSHR hits +system.l2c.writebacks::writebacks 6537 # number of writebacks +system.l2c.writebacks::total 6537 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 10 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu6 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 40 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 11 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 15 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 11 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 70 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 110 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1197 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1197 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1986 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2039 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2071 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2052 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2099 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2037 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2050 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2087 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16421 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4678 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4641 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4584 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4701 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4570 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 39 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 13 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 7 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3 6 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu4 14 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu5 11 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu6 9 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu7 11 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 75 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 17 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 18 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 21 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 17 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 18 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 21 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 15 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 114 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 1240 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1240 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 2003 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2095 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2038 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2061 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2078 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2099 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 2074 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2069 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16517 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4519 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4564 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4662 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4577 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4680 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu5 4599 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4634 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4705 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 37112 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 738 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 727 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 763 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 747 # number of ReadSharedReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4580 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4663 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 36844 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0 730 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1 777 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2 722 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3 736 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu4 702 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 721 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 752 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 731 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5881 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5416 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5368 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5347 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5448 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5272 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5320 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5386 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5436 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42993 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5416 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5368 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5347 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5448 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5272 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5320 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5386 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5436 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 42993 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9773 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9723 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9760 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9771 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9898 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9891 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9845 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9747 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 78408 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5449 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5329 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5533 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3 5455 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu4 5382 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu5 5483 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu6 5508 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu7 5404 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 43543 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0 15222 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1 15052 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2 15293 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3 15226 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu4 15280 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu5 15374 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu6 15353 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu7 15151 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 121951 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 89216305 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 91661476 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 93067979 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 92238981 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 94104480 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 91562476 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 91964478 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 93840981 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 737657156 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 213700915 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 211685412 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 208764420 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 213671917 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 208164429 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 209421909 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 210919416 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 214243431 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1690571849 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 38320904 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 37446428 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 40065914 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 39278917 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 36377424 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 38015411 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 39226917 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 38343914 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 307075829 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 252021819 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 249131840 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 248830334 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 252950834 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 244541853 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 247437320 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 250146333 # 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number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 105681456 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 106934463 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 107650463 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 108806472 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 107556959 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 107077279 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 856095511 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 236726369 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 239139871 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 243801378 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 239818196 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 245529878 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 241617872 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 239761379 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 244006864 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1930401807 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 42764408 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 44950896 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 42066908 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 43073402 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 40746918 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 43606418 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 41895903 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 42768413 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 341873266 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 279490777 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 284090767 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 285868286 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 282891598 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 286276796 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 285224290 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 281657282 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 286775277 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2272275073 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 279490777 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 284090767 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 285868286 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 282891598 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 286276796 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 285224290 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 281657282 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 286775277 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2272275073 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 503232104 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 504891308 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 500756647 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 501380612 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 505534787 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 497694775 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 500159589 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 503166776 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 4016816598 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 292229228 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 286836409 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 283709721 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 292753904 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 289394212 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 284248382 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 293152393 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 291492896 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2313817145 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 795461332 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 791727717 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 784466368 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 794134516 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 794928999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 781943157 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 793311982 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 794659672 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6330633743 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.883059 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.894691 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.889223 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882581 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.894333 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.883731 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.886295 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.880591 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.886807 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.729228 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.725950 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.724171 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.730991 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.721161 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.719831 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.720909 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.724850 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.724646 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.062894 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062264 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.065186 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.064352 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.059903 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.062139 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.064884 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.062484 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063010 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.297431 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.297431 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 44922.610775 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 44954.132418 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 44938.666828 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 44950.770468 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44833.006193 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44949.669121 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44860.720976 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44964.533301 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44921.573351 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45682.110945 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45612.025856 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 45541.976440 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 45452.439268 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45550.203282 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 45536.401174 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 45515.627104 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45535.266950 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 45553.240165 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 51925.344173 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51508.154058 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52511.027523 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52582.218206 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51819.692308 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52725.951456 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52163.453457 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52454.054720 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52214.900357 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 46410.551416 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 46536.438003 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 46385.025228 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 46443.804864 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 46465.663171 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 46464.486730 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 46410.551416 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 46536.438003 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 46385.025228 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 46443.804864 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 46465.663171 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 46464.486730 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44420.329070 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44451.631081 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44461.256660 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44495.280217 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44517.718428 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44486.777070 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44473.425597 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44477.416538 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44473.085348 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45722.229950 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46311.681366 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45905.193385 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45877.502108 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45846.631364 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46046.768557 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46061.443718 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46016.177831 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45972.703971 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44886.368874 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45110.162038 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44983.672268 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44990.487127 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44985.794961 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45043.134123 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45043.138605 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45026.255957 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 45008.529040 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.875820 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.880992 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.875430 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882277 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.884632 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.886402 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.883681 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.883433 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.881612 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726527 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.713794 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.725039 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.718186 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.734118 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.728843 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.729299 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721715 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.724662 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.063363 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.067407 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.062630 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.063476 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.061017 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.065821 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.061401 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.063430 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063565 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.295868 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.298030 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.299811 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.295692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.301007 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.300516 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.295190 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.299495 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.298202 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.295868 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.298030 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.299811 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.295692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.301007 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.300516 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.295190 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.299495 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.298202 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 51820.502247 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 51833.867780 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 51855.473994 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 51884.746725 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 51804.842637 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 51837.290138 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 51859.671649 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 51753.155631 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 51831.174608 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 52384.680018 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 52396.991893 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 52295.447876 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 52396.372296 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 52463.649145 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 52537.045445 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 52349.646070 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 52328.300236 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 52393.925931 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 58581.380822 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 57851.861004 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 58264.415512 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58523.644022 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58044.042735 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 57528.255937 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58513.831006 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58347.084584 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58201.100783 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 53246.480663 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 53190.557386 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 53095.892645 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 53245.171843 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 53191.526570 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 53243.287288 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 53183.021526 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 53145.900111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 53192.449857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 53246.480663 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 53190.557386 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 53095.892645 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 53245.171843 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 53191.526570 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 53243.287288 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 53183.021526 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 53145.900111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 53192.449857 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51355.455046 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51346.619343 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51401.831965 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51276.397218 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51338.964862 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51319.320994 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51335.275480 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51301.669657 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51334.431525 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53016.913643 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 53236.156088 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 53328.894925 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53198.964928 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53109.600294 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53001.749394 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 53310.127841 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53104.918200 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53163.089516 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 51953.584482 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 52015.486302 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 52082.483601 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 51968.753092 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 51969.730583 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 51918.408937 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52047.761580 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 51948.726678 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 51988.024595 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 78406 # Transaction distribution -system.membus.trans_dist::ReadResp 84270 # Transaction distribution -system.membus.trans_dist::WriteReq 43542 # Transaction distribution -system.membus.trans_dist::WriteResp 43539 # Transaction distribution -system.membus.trans_dist::Writeback 6492 # Transaction distribution -system.membus.trans_dist::CleanEvict 1226 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61182 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50391 # Transaction distribution -system.membus.trans_dist::ReadExReq 49587 # Transaction distribution -system.membus.trans_dist::ReadExResp 3167 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5869 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427671 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 427671 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1115735 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1115735 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57207 # Total snoops (count) -system.membus.snoop_fanout::samples 255615 # Request fanout histogram +system.membus.trans_dist::ReadReq 78245 # Transaction distribution +system.membus.trans_dist::ReadResp 84100 # Transaction distribution +system.membus.trans_dist::WriteReq 43522 # Transaction distribution +system.membus.trans_dist::WriteResp 43520 # Transaction distribution +system.membus.trans_dist::WritebackDirty 6537 # Transaction distribution +system.membus.trans_dist::CleanEvict 1268 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61107 # Transaction distribution +system.membus.trans_dist::UpgradeResp 50201 # Transaction distribution +system.membus.trans_dist::ReadExReq 48942 # Transaction distribution +system.membus.trans_dist::ReadExResp 3181 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5862 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 426485 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 426485 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1118817 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1118817 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 56662 # Total snoops (count) +system.membus.snoop_fanout::samples 253744 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 255615 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253744 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 255615 # Request fanout histogram -system.membus.reqLayer0.occupancy 293172648 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 56.6 # Layer utilization (%) -system.membus.respLayer0.occupancy 310812284 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 60.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 663719 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 283046 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 335146 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12757 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 5920 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6837 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 78408 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370885 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43543 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43537 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 83883 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20723 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29304 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29302 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162111 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162107 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292494 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122467 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122636 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122530 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122681 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122805 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 981273 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1801396 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1791690 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1789116 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1791289 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1784816 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1780428 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1784184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1802670 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14325589 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 335027 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 801595 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.188537 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.005333 # Request fanout histogram +system.membus.snoop_fanout::total 253744 # Request fanout histogram +system.membus.reqLayer0.occupancy 292620525 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 54.8 # Layer utilization (%) +system.membus.respLayer0.occupancy 295409000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 55.3 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 663684 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 282033 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 335738 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12570 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 5835 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6735 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78248 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 369469 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43523 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43520 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 83531 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 20342 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29636 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29633 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 160854 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 160848 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 291239 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 121995 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122071 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122139 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122334 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122013 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 121723 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122513 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122322 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 977110 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1766349 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778610 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1781270 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1785072 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1775296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1771667 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1779976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1778751 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14216991 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 333737 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 624990 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.150519 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.991140 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 216155 26.97% 26.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 322197 40.19% 67.16% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 179904 22.44% 89.60% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 65286 8.14% 97.75% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 15605 1.95% 99.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 2259 0.28% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 176 0.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 13 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 174852 27.98% 27.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 256379 41.02% 69.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 133497 21.36% 90.36% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 47307 7.57% 97.93% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 11157 1.79% 99.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1650 0.26% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 145 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 801595 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 495500281 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 95.7 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 101557213 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101587169 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101172758 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 19.5 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101251086 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101367103 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 101469413 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101588792 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101399821 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 624990 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 497290718 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 93.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 100872915 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 18.9 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 100601006 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 18.8 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101141480 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 18.9 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 100780789 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 18.9 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 100568051 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 18.8 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 100691951 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 18.9 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101210192 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.0 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 100872512 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 18.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- |