diff options
Diffstat (limited to 'tests/quick/se/50.memtest/ref')
| -rw-r--r-- | tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt | 3452 | ||||
| -rw-r--r-- | tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt | 3417 |
2 files changed, 3438 insertions, 3431 deletions
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 96f88f923..61ea5a710 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1817 +1,1819 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000889 # Number of seconds simulated -sim_ticks 888991000 # Number of ticks simulated -final_tick 888991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000518 # Number of seconds simulated +sim_ticks 518362500 # Number of ticks simulated +final_tick 518362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 170326912 # Simulator tick rate (ticks/s) -host_mem_usage 278304 # Number of bytes of host memory used -host_seconds 5.22 # Real time elapsed on the host +host_tick_rate 97254136 # Simulator tick rate (ticks/s) +host_mem_usage 280792 # Number of bytes of host memory used +host_seconds 5.33 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 77301 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 77008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 78427 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 77571 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 81605 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 77234 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 80454 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78765 # Number of bytes read from this memory -system.physmem.bytes_read::total 628365 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 396032 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5354 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5486 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5463 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5457 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5585 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5519 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5444 # Number of bytes written to this memory -system.physmem.bytes_written::total 439804 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10773 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10795 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11043 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10895 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10839 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10977 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87447 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6188 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5354 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5486 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5463 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5457 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5585 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5519 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5444 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49960 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 86953636 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 86624049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 88220241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 87257351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 91795080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 86878270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 90500354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 88600447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 706829428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 445484825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 6022558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6171041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 6145169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 6138420 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 6146294 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 6282403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 6208162 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 6123797 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 494722669 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 445484825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 92976194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 92795090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 94365410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 93395771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 97941374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 93160673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 96708516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 94724244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1201552097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 83556 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 80496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 82210 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 83458 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79724 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 80437 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 82031 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 84431 # Number of bytes read from this memory +system.physmem.bytes_read::total 656343 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 416960 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5350 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5428 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5478 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5268 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5521 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5505 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5477 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5442 # Number of bytes written to this memory +system.physmem.bytes_written::total 460429 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10944 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10676 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11074 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11030 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10910 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87516 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6515 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5350 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5428 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5478 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5268 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5521 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5505 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5477 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5442 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49984 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 161192216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 155289011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 158595577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 161003159 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 153799706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 155175191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 158250259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 162880224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1266185343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 804379175 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10320963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10471436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10567894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10162772 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10650848 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10619981 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10565965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10498445 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 888237479 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 804379175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 171513179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 165760448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 169163472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 171165931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 164450553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 165795172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 168816224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 173378668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2154422822 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99131 # number of read accesses completed -system.cpu0.num_writes 55164 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22535 # number of replacements -system.cpu0.l1c.tags.tagsinuse 395.025918 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13450 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22939 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.586338 # Average number of references to valid blocks. +system.cpu0.num_reads 99891 # number of read accesses completed +system.cpu0.num_writes 54838 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22327 # number of replacements +system.cpu0.l1c.tags.tagsinuse 391.597191 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13273 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22716 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.584302 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 395.025918 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.771535 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.771535 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 341 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338659 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338659 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8591 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8591 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1192 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1192 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9783 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9783 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9783 # number of overall hits -system.cpu0.l1c.overall_hits::total 9783 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36665 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36665 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23983 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23983 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60648 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60648 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60648 # number of overall misses -system.cpu0.l1c.overall_misses::total 60648 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1205183022 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1205183022 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1064148669 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1064148669 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 2269331691 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 2269331691 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 2269331691 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 2269331691 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45256 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45256 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25175 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25175 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70431 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70431 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70431 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70431 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.810169 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.810169 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952651 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.952651 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.861098 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.861098 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.861098 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.861098 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 32870.121969 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 32870.121969 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 44370.957303 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 44370.957303 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 37418.079590 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 37418.079590 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 37418.079590 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 37418.079590 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1129963 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 391.597191 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.764838 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.764838 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337776 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337776 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8714 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8714 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1148 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1148 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9862 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9862 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9862 # number of overall hits +system.cpu0.l1c.overall_hits::total 9862 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36629 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36629 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23739 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23739 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60368 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60368 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60368 # number of overall misses +system.cpu0.l1c.overall_misses::total 60368 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 614304512 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 614304512 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 680799251 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 680799251 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1295103763 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1295103763 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1295103763 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1295103763 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45343 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45343 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24887 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24887 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70230 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70230 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70230 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807820 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807820 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953871 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.953871 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.859576 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.859576 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.859576 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.859576 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16770.987797 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16770.987797 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28678.514301 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 28678.514301 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21453.481364 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21453.481364 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21453.481364 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21453.481364 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 764972 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 56549 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61598 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 19.982016 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.418780 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9979 # number of writebacks -system.cpu0.l1c.writebacks::total 9979 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36665 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36665 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23983 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60648 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60648 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9718 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9718 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5355 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5355 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15073 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15073 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1168518022 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1168518022 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1040166669 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1040166669 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2208684691 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 2208684691 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2208684691 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 2208684691 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 789521900 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 789521900 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1493953369 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1493953369 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2283475269 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2283475269 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.810169 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.810169 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952651 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952651 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.861098 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.861098 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 31870.121969 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 31870.121969 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 43370.998999 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 43370.998999 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 81243.249640 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81243.249640 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 278982.888702 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 278982.888702 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 151494.411796 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 151494.411796 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9814 # number of writebacks +system.cpu0.l1c.writebacks::total 9814 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36629 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36629 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23739 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23739 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60368 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60368 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9828 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9828 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5350 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5350 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15178 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15178 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 577676512 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 577676512 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 657061251 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 657061251 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1234737763 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1234737763 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1234737763 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1234737763 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 645410094 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 645410094 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 821386793 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 821386793 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1466796887 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1466796887 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807820 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807820 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953871 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953871 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859576 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.859576 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859576 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.859576 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15771.015097 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15771.015097 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27678.556426 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27678.556426 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20453.514494 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20453.514494 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20453.514494 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20453.514494 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65670.542735 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65670.542735 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153530.241682 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153530.241682 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 96639.668402 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 96639.668402 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99860 # number of read accesses completed -system.cpu1.num_writes 55211 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22541 # number of replacements -system.cpu1.l1c.tags.tagsinuse 395.711444 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13500 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22934 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.588646 # Average number of references to valid blocks. +system.cpu1.num_reads 99259 # number of read accesses completed +system.cpu1.num_writes 55194 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22288 # number of replacements +system.cpu1.l1c.tags.tagsinuse 392.187813 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13481 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22683 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.594322 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 395.711444 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.772874 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.772874 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338432 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338432 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8752 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8752 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1139 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1139 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9891 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9891 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9891 # number of overall hits -system.cpu1.l1c.overall_hits::total 9891 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36537 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36537 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23971 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23971 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60508 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60508 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60508 # number of overall misses -system.cpu1.l1c.overall_misses::total 60508 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1195916774 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1195916774 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1059745891 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1059745891 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 2255662665 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 2255662665 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 2255662665 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 2255662665 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45289 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45289 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25110 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25110 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70399 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70399 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70399 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70399 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806752 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.806752 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954640 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954640 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859501 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859501 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859501 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859501 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 32731.663081 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 32731.663081 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 44209.498602 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 44209.498602 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 37278.750992 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 37278.750992 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 37278.750992 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 37278.750992 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1120827 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 392.187813 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.765992 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.765992 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 337082 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 337082 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8742 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8742 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1127 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1127 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9869 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9869 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9869 # number of overall hits +system.cpu1.l1c.overall_hits::total 9869 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36456 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36456 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23797 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23797 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60253 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60253 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60253 # number of overall misses +system.cpu1.l1c.overall_misses::total 60253 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 609449513 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 609449513 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 681132433 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 681132433 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1290581946 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1290581946 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1290581946 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1290581946 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45198 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45198 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24924 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70122 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70122 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70122 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70122 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806584 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.806584 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954783 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954783 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.859260 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.859260 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.859260 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.859260 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16717.399413 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16717.399413 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28622.617683 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 28622.617683 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 21419.380711 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 21419.380711 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 21419.380711 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 21419.380711 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 761379 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 56192 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61322 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 19.946380 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.416082 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9897 # number of writebacks -system.cpu1.l1c.writebacks::total 9897 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36537 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36537 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23971 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60508 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60508 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60508 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60508 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9744 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9744 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5487 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5487 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15231 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15231 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1159382774 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1159382774 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1035775891 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1035775891 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2195158665 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 2195158665 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2195158665 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 2195158665 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 792485431 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 792485431 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1532713252 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1532713252 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2325198683 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2325198683 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806752 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806752 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954640 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954640 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859501 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859501 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 31731.745190 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 31731.745190 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 43209.540320 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 43209.540320 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 81330.606630 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81330.606630 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 279335.383999 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279335.383999 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 152662.246931 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 152662.246931 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9824 # number of writebacks +system.cpu1.l1c.writebacks::total 9824 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36456 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36456 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23797 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23797 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60253 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60253 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60253 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60253 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9840 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9840 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5428 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5428 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15268 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15268 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 572994513 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 572994513 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 657337433 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 657337433 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1230331946 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1230331946 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1230331946 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1230331946 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 646152701 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 646152701 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 842788738 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 842788738 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1488941439 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1488941439 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806584 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806584 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954783 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954783 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859260 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.859260 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859260 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.859260 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15717.426843 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15717.426843 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27622.701727 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27622.701727 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20419.430501 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20419.430501 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20419.430501 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20419.430501 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65665.924898 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65665.924898 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 155266.900884 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155266.900884 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 97520.398153 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 97520.398153 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99820 # number of read accesses completed -system.cpu2.num_writes 54950 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22307 # number of replacements -system.cpu2.l1c.tags.tagsinuse 395.344704 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13648 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22708 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.601022 # Average number of references to valid blocks. +system.cpu2.num_reads 99508 # number of read accesses completed +system.cpu2.num_writes 54525 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22121 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.684502 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13597 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22507 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.604123 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 395.344704 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.772158 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.772158 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 349 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 339436 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 339436 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8860 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8860 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1133 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1133 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9993 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9993 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9993 # number of overall hits -system.cpu2.l1c.overall_hits::total 9993 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36664 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36664 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23971 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23971 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60635 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60635 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60635 # number of overall misses -system.cpu2.l1c.overall_misses::total 60635 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1194013761 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1194013761 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1064419870 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1064419870 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 2258433631 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 2258433631 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 2258433631 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 2258433631 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45524 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45524 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25104 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25104 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70628 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70628 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70628 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70628 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805377 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805377 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954868 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954868 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858512 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858512 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858512 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858512 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 32566.380128 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 32566.380128 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 44404.483334 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 44404.483334 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 37246.369770 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 37246.369770 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 37246.369770 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 37246.369770 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1131174 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.684502 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.766962 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.766962 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338301 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338301 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8815 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8815 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1121 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1121 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9936 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9936 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9936 # number of overall hits +system.cpu2.l1c.overall_hits::total 9936 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36608 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36608 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23851 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23851 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60459 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60459 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60459 # number of overall misses +system.cpu2.l1c.overall_misses::total 60459 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 611593894 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 611593894 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 682333894 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 682333894 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1293927788 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1293927788 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1293927788 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1293927788 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45423 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45423 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24972 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24972 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70395 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70395 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70395 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70395 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805935 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805935 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955110 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955110 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858854 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858854 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858854 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858854 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16706.563975 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16706.563975 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 28608.188084 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 28608.188084 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 21401.739824 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 21401.739824 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 21401.739824 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 21401.739824 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 766345 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 56579 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 61950 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 19.992824 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.370379 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9745 # number of writebacks -system.cpu2.l1c.writebacks::total 9745 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36664 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36664 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23971 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60635 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60635 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60635 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60635 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9885 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5464 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15349 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15349 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1157350761 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1157350761 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1040448870 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1040448870 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2197799631 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 2197799631 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2197799631 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 2197799631 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 800475880 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 800475880 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1507844825 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1507844825 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2308320705 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2308320705 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805377 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805377 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954868 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954868 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858512 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858512 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 31566.407402 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 31566.407402 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 43404.483334 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 43404.483334 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 80978.844714 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80978.844714 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 275959.887445 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 275959.887445 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 150388.996352 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 150388.996352 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9721 # number of writebacks +system.cpu2.l1c.writebacks::total 9721 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36608 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36608 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23851 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23851 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60459 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60459 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60459 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60459 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9890 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9890 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5479 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5479 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15369 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 574987894 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 574987894 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 658483894 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 658483894 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1233471788 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1233471788 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1233471788 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1233471788 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 648669577 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 648669577 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 848315711 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 848315711 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1496985288 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1496985288 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805935 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805935 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955110 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955110 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858854 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858854 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858854 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858854 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15706.618608 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15706.618608 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 27608.230011 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 27608.230011 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20401.789444 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20401.789444 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20401.789444 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20401.789444 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65588.430435 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65588.430435 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154830.390765 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154830.390765 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97402.907671 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97402.907671 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99181 # number of read accesses completed -system.cpu3.num_writes 54913 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22385 # number of replacements -system.cpu3.l1c.tags.tagsinuse 394.599023 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13320 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22779 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.584749 # Average number of references to valid blocks. +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 55096 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22478 # number of replacements +system.cpu3.l1c.tags.tagsinuse 393.167313 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13728 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22864 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.600420 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 394.599023 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.770701 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.770701 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337671 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337671 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8526 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8526 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1172 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1172 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9698 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9698 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9698 # number of overall hits -system.cpu3.l1c.overall_hits::total 9698 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36662 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36662 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23851 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23851 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60513 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60513 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60513 # number of overall misses -system.cpu3.l1c.overall_misses::total 60513 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1194465114 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1194465114 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1056306776 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1056306776 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 2250771890 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 2250771890 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 2250771890 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 2250771890 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45188 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45188 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25023 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25023 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70211 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70211 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70211 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70211 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.811322 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.811322 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953163 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953163 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.861873 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.861873 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.861873 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.861873 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 32580.467896 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 32580.467896 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 44287.735357 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 44287.735357 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 37194.848875 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 37194.848875 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 37194.848875 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 37194.848875 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1130263 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 393.167313 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.767905 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.767905 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 380 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 339546 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 339546 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8879 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8879 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1139 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1139 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 10018 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 10018 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 10018 # number of overall hits +system.cpu3.l1c.overall_hits::total 10018 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36721 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36721 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23927 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23927 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60648 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60648 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60648 # number of overall misses +system.cpu3.l1c.overall_misses::total 60648 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 620124867 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 620124867 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 683533364 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 683533364 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1303658231 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1303658231 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1303658231 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1303658231 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45600 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45600 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25066 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25066 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70666 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70666 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70666 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70666 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805285 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.805285 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954560 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954560 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.858235 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.858235 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.858235 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.858235 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16887.472209 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16887.472209 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28567.449492 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 28567.449492 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 21495.485935 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 21495.485935 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 21495.485935 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 21495.485935 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 763846 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 56535 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 61681 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 19.992270 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.383813 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9719 # number of writebacks -system.cpu3.l1c.writebacks::total 9719 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36662 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36662 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23851 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23851 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60513 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60513 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60513 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60513 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9988 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9988 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5458 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5458 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15446 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15446 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1157803114 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1157803114 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1032457776 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1032457776 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2190260890 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 2190260890 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2190260890 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 2190260890 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 807637161 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 807637161 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1532365329 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1532365329 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2340002490 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2340002490 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.811322 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.811322 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953163 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953163 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.861873 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.861873 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 31580.467896 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 31580.467896 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 43287.819211 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 43287.819211 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 80860.748999 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80860.748999 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 280755.831623 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 280755.831623 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 151495.694031 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 151495.694031 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 10011 # number of writebacks +system.cpu3.l1c.writebacks::total 10011 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36721 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36721 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23927 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23927 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60648 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60648 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9730 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9730 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5269 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5269 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 14999 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 14999 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 583406867 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 583406867 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 659607364 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 659607364 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1243014231 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1243014231 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1243014231 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1243014231 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 639132205 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 639132205 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 818596366 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 818596366 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1457728571 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1457728571 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805285 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805285 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954560 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954560 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858235 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.858235 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858235 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.858235 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15887.553906 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15887.553906 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27567.491286 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27567.491286 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20495.551890 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20495.551890 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20495.551890 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20495.551890 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65686.763104 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65686.763104 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 155360.858987 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155360.858987 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97188.383959 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97188.383959 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99531 # number of read accesses completed -system.cpu4.num_writes 55217 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22414 # number of replacements -system.cpu4.l1c.tags.tagsinuse 393.784167 # Cycle average of tags in use +system.cpu4.num_reads 98810 # number of read accesses completed +system.cpu4.num_writes 55636 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22565 # number of replacements +system.cpu4.l1c.tags.tagsinuse 393.118080 # Cycle average of tags in use system.cpu4.l1c.tags.total_refs 13493 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22803 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.591720 # Average number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22961 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.587649 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 393.784167 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.769110 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.769110 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 47 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 337660 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 337660 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8661 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8661 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1197 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1197 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9858 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9858 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9858 # number of overall hits -system.cpu4.l1c.overall_hits::total 9858 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36381 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36381 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 24008 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 24008 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60389 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60389 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60389 # number of overall misses -system.cpu4.l1c.overall_misses::total 60389 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1185615268 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1185615268 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 1062060825 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1062060825 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 2247676093 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 2247676093 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 2247676093 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 2247676093 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45042 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45042 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25205 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25205 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70247 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70247 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70247 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70247 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807713 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807713 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952509 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.952509 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859667 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859667 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859667 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859667 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 32588.858690 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 32588.858690 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 44237.788446 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 44237.788446 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 37219.958817 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 37219.958817 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 37219.958817 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 37219.958817 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1133314 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 393.118080 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.767809 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.767809 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338158 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338158 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8694 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8694 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1170 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1170 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9864 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9864 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9864 # number of overall hits +system.cpu4.l1c.overall_hits::total 9864 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36355 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36355 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 24124 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 24124 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60479 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60479 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60479 # number of overall misses +system.cpu4.l1c.overall_misses::total 60479 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 612629802 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 612629802 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 686589261 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 686589261 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1299219063 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1299219063 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1299219063 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1299219063 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25294 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25294 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70343 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70343 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70343 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70343 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807010 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807010 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953744 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953744 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859773 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859773 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859773 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859773 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16851.321744 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16851.321744 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28460.838211 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 28460.838211 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 21482.151871 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 21482.151871 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 21482.151871 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 21482.151871 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 755009 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 56676 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61034 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 19.996365 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.370302 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9784 # number of writebacks -system.cpu4.l1c.writebacks::total 9784 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36381 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36381 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24008 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 24008 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60389 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60389 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60389 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60389 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 10053 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 10053 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5464 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15517 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15517 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1149238268 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1149238268 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1038052825 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1038052825 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2187291093 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 2187291093 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2187291093 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 2187291093 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 813079130 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 813079130 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1517158795 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1517158795 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2330237925 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2330237925 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807713 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807713 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952509 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952509 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859667 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859667 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 31588.968637 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 31588.968637 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 43237.788446 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 43237.788446 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 80879.252959 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80879.252959 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 277664.493960 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 277664.493960 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 150173.224528 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 150173.224528 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 10039 # number of writebacks +system.cpu4.l1c.writebacks::total 10039 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36355 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36355 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24124 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 24124 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60479 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60479 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60479 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60479 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9580 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9580 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5521 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5521 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15101 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15101 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 576274802 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 576274802 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 662467261 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 662467261 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1238742063 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1238742063 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1238742063 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1238742063 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 630980804 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 630980804 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 867176198 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 867176198 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1498157002 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1498157002 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807010 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807010 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953744 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953744 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859773 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859773 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859773 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859773 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15851.321744 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15851.321744 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27460.921116 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27460.921116 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20482.184940 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20482.184940 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20482.184940 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20482.184940 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65864.384551 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65864.384551 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157068.682847 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157068.682847 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 99209.125356 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 99209.125356 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 100000 # number of read accesses completed -system.cpu5.num_writes 55296 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22532 # number of replacements -system.cpu5.l1c.tags.tagsinuse 395.145821 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13497 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22906 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.589234 # Average number of references to valid blocks. +system.cpu5.num_reads 98552 # number of read accesses completed +system.cpu5.num_writes 54926 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22151 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.121942 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13428 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22535 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.595873 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 395.145821 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.771769 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.771769 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 374 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.730469 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337979 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337979 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8739 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8739 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1202 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1202 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9941 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9941 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9941 # number of overall hits -system.cpu5.l1c.overall_hits::total 9941 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36450 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36450 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23918 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23918 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60368 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60368 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60368 # number of overall misses -system.cpu5.l1c.overall_misses::total 60368 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1193062548 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1193062548 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 1058341769 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1058341769 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 2251404317 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 2251404317 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 2251404317 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 2251404317 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45189 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45189 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25120 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25120 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70309 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70309 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70309 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70309 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806612 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806612 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952150 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952150 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858610 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858610 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858610 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858610 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 32731.482798 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 32731.482798 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 44248.756961 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 44248.756961 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 37294.664673 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 37294.664673 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 37294.664673 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 37294.664673 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1121436 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 392.121942 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.765863 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.765863 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 336693 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 336693 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8529 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8529 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1201 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1201 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9730 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9730 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9730 # number of overall hits +system.cpu5.l1c.overall_hits::total 9730 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36363 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36363 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23944 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23944 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60307 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60307 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60307 # number of overall misses +system.cpu5.l1c.overall_misses::total 60307 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 609487073 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 609487073 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 677626855 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 677626855 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1287113928 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1287113928 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1287113928 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1287113928 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44892 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44892 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25145 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25145 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70037 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70037 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70037 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70037 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.810011 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.810011 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952237 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952237 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.861073 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.861073 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.861073 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.861073 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16761.187828 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16761.187828 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 28300.486761 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 28300.486761 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 21342.695342 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 21342.695342 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 21342.695342 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 21342.695342 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 765746 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 56172 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61759 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 19.964324 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.398938 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9981 # number of writebacks -system.cpu5.l1c.writebacks::total 9981 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36450 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36450 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23918 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23918 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60368 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60368 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9842 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9842 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5587 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5587 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15429 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15429 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1156614548 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1156614548 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1034424769 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1034424769 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2191039317 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 2191039317 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2191039317 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 2191039317 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 798681353 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 798681353 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1559836698 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1559836698 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2358518051 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2358518051 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806612 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806612 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952150 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952150 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858610 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858610 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 31731.537668 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 31731.537668 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 43248.798771 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 43248.798771 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 81150.310201 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81150.310201 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 279190.388044 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279190.388044 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 152862.664528 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 152862.664528 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9825 # number of writebacks +system.cpu5.l1c.writebacks::total 9825 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36363 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36363 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23944 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23944 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60307 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60307 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60307 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60307 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9974 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9974 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5505 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5505 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15479 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15479 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 573124073 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 573124073 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 653684855 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 653684855 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1226808928 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1226808928 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1226808928 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1226808928 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 653819057 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 653819057 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 856353181 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 856353181 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1510172238 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1510172238 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.810011 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.810011 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952237 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952237 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.861073 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.861073 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861073 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.861073 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15761.187828 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15761.187828 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 27300.570289 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27300.570289 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20342.728506 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20342.728506 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20342.728506 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20342.728506 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65552.341789 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65552.341789 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 155559.160945 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155559.160945 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 97562.648621 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 97562.648621 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99879 # number of read accesses completed -system.cpu6.num_writes 55426 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22371 # number of replacements -system.cpu6.l1c.tags.tagsinuse 395.326557 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13543 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22792 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.594200 # Average number of references to valid blocks. +system.cpu6.num_reads 98949 # number of read accesses completed +system.cpu6.num_writes 55414 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22111 # number of replacements +system.cpu6.l1c.tags.tagsinuse 389.931977 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13393 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22506 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.595086 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 395.326557 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.772122 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.772122 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 339285 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 339285 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8751 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8751 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1170 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1170 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9921 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9921 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9921 # number of overall hits -system.cpu6.l1c.overall_hits::total 9921 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36633 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36633 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 24021 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 24021 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60654 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60654 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60654 # number of overall misses -system.cpu6.l1c.overall_misses::total 60654 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1194061806 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1194061806 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1068136243 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1068136243 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 2262198049 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 2262198049 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 2262198049 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 2262198049 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45384 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45384 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25191 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25191 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70575 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70575 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70575 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70575 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807179 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.807179 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953555 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953555 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859426 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859426 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859426 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859426 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 32595.250348 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 32595.250348 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 44466.768369 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 44466.768369 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 37296.766067 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 37296.766067 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 37296.766067 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 37296.766067 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1121671 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 389.931977 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.761586 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.761586 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337246 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337246 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8611 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8611 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1144 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1144 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9755 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9755 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9755 # number of overall hits +system.cpu6.l1c.overall_hits::total 9755 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36346 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36346 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 24035 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 24035 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60381 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60381 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60381 # number of overall misses +system.cpu6.l1c.overall_misses::total 60381 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 607533641 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 607533641 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 684112648 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 684112648 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1291646289 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1291646289 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1291646289 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1291646289 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44957 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44957 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25179 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25179 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70136 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70136 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70136 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70136 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808461 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.808461 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954565 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954565 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.860913 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.860913 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.860913 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.860913 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16715.282039 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16715.282039 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28463.184855 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 28463.184855 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21391.601481 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21391.601481 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21391.601481 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21391.601481 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 766078 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 56232 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61691 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 19.947201 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.417986 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9808 # number of writebacks -system.cpu6.l1c.writebacks::total 9808 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36633 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36633 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24021 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 24021 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60654 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60654 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60654 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60654 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9734 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9734 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5519 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5519 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15253 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15253 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1157429806 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1157429806 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1044117243 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1044117243 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2201547049 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 2201547049 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2201547049 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 2201547049 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 789209928 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 789209928 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1545234814 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1545234814 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2334444742 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2334444742 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807179 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807179 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953555 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953555 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859426 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859426 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 31595.277646 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 31595.277646 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 43466.851630 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 43466.851630 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 81077.658517 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81077.658517 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 279984.564957 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279984.564957 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 153048.235888 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 153048.235888 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9648 # number of writebacks +system.cpu6.l1c.writebacks::total 9648 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36346 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36346 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24035 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 24035 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60381 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60381 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60381 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60381 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5478 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5478 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15382 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15382 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 571188641 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 571188641 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 660079648 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 660079648 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1231268289 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1231268289 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1231268289 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1231268289 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 650717068 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 650717068 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 843701696 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 843701696 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1494418764 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1494418764 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808461 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808461 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954565 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954565 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860913 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.860913 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860913 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.860913 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15715.309553 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15715.309553 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27463.268067 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27463.268067 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20391.651165 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20391.651165 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20391.651165 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20391.651165 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65702.450323 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65702.450323 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 154016.373859 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154016.373859 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 97153.735795 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 97153.735795 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99237 # number of read accesses completed -system.cpu7.num_writes 54706 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22568 # number of replacements -system.cpu7.l1c.tags.tagsinuse 396.130968 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13545 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22967 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.589759 # Average number of references to valid blocks. +system.cpu7.num_reads 99388 # number of read accesses completed +system.cpu7.num_writes 55153 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22255 # number of replacements +system.cpu7.l1c.tags.tagsinuse 390.416736 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13442 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22659 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.593230 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 396.130968 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.773693 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.773693 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 336 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 337631 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 337631 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8763 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8763 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1110 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1110 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9873 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9873 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9873 # number of overall hits -system.cpu7.l1c.overall_hits::total 9873 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36422 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36422 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23951 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23951 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60373 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60373 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60373 # number of overall misses -system.cpu7.l1c.overall_misses::total 60373 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1187262746 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1187262746 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1066556279 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1066556279 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 2253819025 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 2253819025 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 2253819025 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 2253819025 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45185 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45185 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25061 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70246 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70246 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70246 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70246 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806064 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806064 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955708 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955708 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859451 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859451 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859451 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859451 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 32597.406677 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 32597.406677 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 44530.761931 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 44530.761931 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 37331.572474 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 37331.572474 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 37331.572474 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 37331.572474 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1126172 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 390.416736 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.762533 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.762533 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338136 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338136 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8702 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8702 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1125 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1125 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9827 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9827 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9827 # number of overall hits +system.cpu7.l1c.overall_hits::total 9827 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36623 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36623 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23879 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23879 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60502 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60502 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60502 # number of overall misses +system.cpu7.l1c.overall_misses::total 60502 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 619428018 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 619428018 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 681256931 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 681256931 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1300684949 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1300684949 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1300684949 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1300684949 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45325 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45325 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25004 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25004 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70329 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70329 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70329 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70329 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808009 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.808009 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955007 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955007 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.860271 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.860271 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.860271 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.860271 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16913.634000 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16913.634000 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28529.541899 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 28529.541899 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21498.214092 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21498.214092 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21498.214092 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21498.214092 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 764751 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 56351 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 61551 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 19.984951 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.424672 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9950 # number of writebacks -system.cpu7.l1c.writebacks::total 9950 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36422 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36422 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23951 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23951 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60373 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60373 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60373 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60373 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9901 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9901 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5444 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5444 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15345 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15345 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1150841746 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1150841746 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1042608279 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1042608279 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2193450025 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 2193450025 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2193450025 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 2193450025 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 802753372 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 802753372 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1502766880 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1502766880 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2305520252 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2305520252 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806064 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806064 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955708 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955708 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859451 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859451 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859451 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859451 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 31597.434133 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 31597.434133 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 43530.887186 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 43530.887186 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 36331.638729 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 36331.638729 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 36331.638729 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 36331.638729 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 81078.009494 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81078.009494 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 276040.940485 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 276040.940485 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 150245.699055 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 150245.699055 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9698 # number of writebacks +system.cpu7.l1c.writebacks::total 9698 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36623 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36623 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23879 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23879 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60502 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60502 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60502 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60502 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9744 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9744 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5445 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5445 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15189 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15189 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 582807018 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 582807018 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 657378931 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 657378931 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1240185949 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1240185949 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1240185949 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1240185949 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 639625650 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 639625650 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 835380703 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 835380703 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1475006353 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1475006353 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808009 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808009 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955007 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955007 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860271 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.860271 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860271 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.860271 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15913.688611 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15913.688611 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27529.583777 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27529.583777 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20498.263677 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20498.263677 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20498.263677 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20498.263677 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65643.026478 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65643.026478 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 153421.616713 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153421.616713 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 97110.168741 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 97110.168741 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13238 # number of replacements -system.l2c.tags.tagsinuse 783.486176 # Cycle average of tags in use -system.l2c.tags.total_refs 163749 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14027 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.673843 # Average number of references to valid blocks. +system.l2c.tags.replacements 14059 # number of replacements +system.l2c.tags.tagsinuse 786.833616 # Cycle average of tags in use +system.l2c.tags.total_refs 163279 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14835 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.006336 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 731.907933 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.423018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.356158 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.459637 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.505664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.498026 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.297131 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.613319 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.425290 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.714754 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006272 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006308 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006353 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006346 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006150 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006458 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006275 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.765123 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 503 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.770508 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2093442 # Number of tag accesses -system.l2c.tags.data_accesses 2093442 # Number of data accesses -system.l2c.Writeback_hits::writebacks 77141 # number of Writeback hits -system.l2c.Writeback_hits::total 77141 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 278 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 288 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 234 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 250 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 237 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 267 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 288 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 265 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2107 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1745 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1822 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1757 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1774 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1783 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1866 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1759 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1730 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14236 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10764 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10818 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10858 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 10852 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10715 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10815 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 10778 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10709 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 86309 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12509 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12640 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12615 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12626 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12498 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12681 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12537 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12439 # number of demand (read+write) hits -system.l2c.demand_hits::total 100545 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12509 # number of overall hits -system.l2c.overall_hits::cpu1 12640 # number of overall hits -system.l2c.overall_hits::cpu2 12615 # number of overall hits -system.l2c.overall_hits::cpu3 12626 # number of overall hits -system.l2c.overall_hits::cpu4 12498 # number of overall hits -system.l2c.overall_hits::cpu5 12681 # number of overall hits -system.l2c.overall_hits::cpu6 12537 # number of overall hits -system.l2c.overall_hits::cpu7 12439 # number of overall hits -system.l2c.overall_hits::total 100545 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 2044 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2057 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2093 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2098 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2109 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2052 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2068 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2060 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16581 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4635 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4534 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4676 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4617 # number of ReadExReq misses +system.l2c.tags.occ_blocks::writebacks 728.191655 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.576246 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 6.765492 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.413353 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.547486 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 7.173407 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.531253 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.038544 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.596181 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.711125 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007399 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006607 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007240 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007371 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.007005 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007355 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006874 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007418 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768392 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 637 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2098126 # Number of tag accesses +system.l2c.tags.data_accesses 2098126 # Number of data accesses +system.l2c.Writeback_hits::writebacks 77297 # number of Writeback hits +system.l2c.Writeback_hits::total 77297 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 246 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 268 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 270 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 283 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 289 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 282 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 269 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 297 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2204 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1720 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1708 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1780 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1750 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1833 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1787 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1793 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1756 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14127 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 10721 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 10733 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 10896 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 11023 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 10756 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 10769 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 10556 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 10900 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 86354 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 12441 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12441 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12676 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12773 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12589 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12556 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12349 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12656 # number of demand (read+write) hits +system.l2c.demand_hits::total 100481 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12441 # number of overall hits +system.l2c.overall_hits::cpu1 12441 # number of overall hits +system.l2c.overall_hits::cpu2 12676 # number of overall hits +system.l2c.overall_hits::cpu3 12773 # number of overall hits +system.l2c.overall_hits::cpu4 12589 # number of overall hits +system.l2c.overall_hits::cpu5 12556 # number of overall hits +system.l2c.overall_hits::cpu6 12349 # number of overall hits +system.l2c.overall_hits::cpu7 12656 # number of overall hits +system.l2c.overall_hits::total 100481 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 1978 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2026 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2150 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2091 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 2034 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 2071 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 2011 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2018 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16379 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4713 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4655 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4607 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4594 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu4 4660 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4681 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4704 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4691 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37198 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 682 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 677 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 701 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 683 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 732 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 682 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 708 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 684 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5549 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5317 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5211 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5377 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5300 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5392 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5363 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5412 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5375 # 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number of overall miss cycles +system.l2c.overall_miss_latency::total 2450782239 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 77297 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77297 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2224 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2294 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2420 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2374 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2323 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2353 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2280 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2315 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18583 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6433 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6363 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6387 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6344 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6493 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6361 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6492 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6401 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51274 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11466 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11436 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11641 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11763 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11475 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11510 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11291 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11679 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 92261 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17899 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17799 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18028 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18107 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17968 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17871 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17783 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18080 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143535 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17899 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17799 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18028 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18107 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17968 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17871 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17783 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18080 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143535 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.889388 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.883173 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.888430 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.880792 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.875592 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.880153 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.882018 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.871706 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.881397 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.732629 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.731573 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.721309 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.724149 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.717696 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.719069 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.723814 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.725668 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.724480 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.064975 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.061473 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.063998 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.062909 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.062658 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.064379 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.065096 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.066701 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.064025 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.304933 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.301028 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.296872 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.294582 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.299366 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.297409 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.305573 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.300000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.299955 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.304933 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.301028 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.296872 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.294582 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.299366 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.297409 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.305573 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.300000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.299955 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 30467.386754 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 30913.864265 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29886.506047 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 30330.694405 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 30794.736480 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 30285.363110 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 29877.417205 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 30968.030723 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 30435.796019 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 56210.991725 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 55996.005800 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 55979.143477 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 56173.137135 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 56039.254506 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 55996.155662 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 56000.834858 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 55941.748977 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 56042.366974 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 61954.445638 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 63277.263158 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 62792.495302 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 61882.321622 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 62592.358832 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 62752.225371 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 62037.302041 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62467.786906 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 62464.268326 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 56994.955295 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 56951.348078 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 56927.564088 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 56965.187477 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 56915.194646 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 56938.064911 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 56817.324255 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 56879.024705 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 56923.450527 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 56994.955295 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 56951.348078 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 56927.564088 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 56965.187477 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 56915.194646 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 56938.064911 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 56817.324255 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 56879.024705 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 56923.450527 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 19361 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1204 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3488 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.468439 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.550745 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6188 # number of writebacks -system.l2c.writebacks::total 6188 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 6515 # number of writebacks +system.l2c.writebacks::total 6515 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 8 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 1 # number of ReadExReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 5 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 26 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 1 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 12 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 6 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 6 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 46 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1198 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1198 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 2044 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2057 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2093 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2098 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2109 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2051 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2068 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2059 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16579 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4627 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4532 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4674 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4616 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4656 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4680 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4700 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4687 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 37172 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 678 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 673 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 700 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 679 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 720 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 673 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 702 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 678 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5503 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5305 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5205 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5374 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5295 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5376 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5353 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5402 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5365 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42675 # 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number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 34 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0 7 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu4 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu5 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu6 5 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu7 9 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 69 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 13 # 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number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu6 5477 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu7 5442 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 43469 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15178 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15268 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15368 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 14998 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu4 15101 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu5 15479 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu6 15381 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu7 15186 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 121959 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 89855482 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 92102479 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 97577479 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 94929976 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 92285490 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 94032976 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 91255478 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 91583480 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 743622840 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 217693404 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 214050407 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 211784914 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 212060892 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 214472426 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 210317416 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 216067923 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 213260425 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1709707807 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 38583562 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 37264417 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 38987911 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 38163918 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 37564408 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 38848899 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 38077918 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 40630907 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 308121940 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 256276966 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 251314824 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 250772825 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 250224810 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 252036834 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 249166315 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 254145841 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 253891332 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2017829747 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 256276966 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 251314824 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 250772825 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 250224810 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 252036834 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 249166315 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 254145841 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 253891332 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2017829747 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 441544704 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 442822362 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 445114191 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 438042708 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 431552369 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 448559865 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 445961194 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 437879200 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3531476593 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 247492955 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 251693437 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 254031943 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 244392771 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 255999435 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 255282926 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 253764437 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 253334431 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2015992335 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 689037659 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 694515799 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 699146134 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 682435479 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 687551804 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 703842791 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 699725631 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 691213631 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5547468928 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.880276 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.877186 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.899441 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.893526 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.898977 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.884433 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.877759 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.885591 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.887147 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.725235 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.713027 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.726566 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.722266 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.722645 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.714831 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.727216 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.729949 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.722713 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.059235 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.058547 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.060559 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.058864 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.062899 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.058537 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.061118 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.059510 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.059908 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.297599 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.291580 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.298688 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.295381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.300503 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.296664 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.300964 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.301168 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.297818 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.297599 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.291580 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.298688 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.295381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.300503 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.296664 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.300964 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.301168 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.297818 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 43969.178082 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 43988.817696 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 43972.287148 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 43979.265491 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44007.585586 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44023.890297 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 43969.051741 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 43984.458475 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43986.820074 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44573.473093 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44604.912621 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44600.868207 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44580.796577 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44544.665808 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44462.600855 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44780.204043 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44713.559633 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 44607.895405 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 50505.820059 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 50619.531947 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 50442.060000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 50725.974963 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51454.061111 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52219.799406 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 50096.783476 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 50259.501475 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50789.933309 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 45331.650518 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 45382.595389 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 45361.723111 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 45368.818508 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 45470.031250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 45437.866056 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 45471.103480 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 45414.426095 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 45405.077704 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 45331.650518 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 45382.595389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 45361.723111 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 45368.818508 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 45470.031250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 45437.866056 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 45471.103480 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 45414.426095 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 45405.077704 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44221.156633 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44202.582307 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44181.167156 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44181.716159 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44166.713618 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44121.720992 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44175.413191 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44200.616200 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44181.280211 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45634.662682 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45295.386256 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45128.316493 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45396.736119 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45350.016654 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45451.832050 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45361.385758 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45227.220610 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45355.293452 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44723.307213 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44596.221339 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44518.341457 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44611.004856 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44583.390024 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44603.257924 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44604.534190 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44564.828283 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 44600.323116 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.888939 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.883173 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.888430 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.880371 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.875592 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.879303 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.882018 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.871274 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.881128 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.732007 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.730787 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.720839 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.723676 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.716926 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.718440 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.723198 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.724731 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.723817 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.064364 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060598 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.063139 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062229 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.061786 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.063510 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.064653 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.065930 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063277 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.304319 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.300185 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.296150 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.293975 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.298531 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.296626 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.305067 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.299170 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.299237 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.304319 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.300185 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.296150 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.293975 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.298531 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.296626 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.305067 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.299170 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.299237 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 45450.420840 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 45460.256170 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 45384.873953 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 45421.041148 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 45371.430678 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 45448.514258 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 45378.159125 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 45405.790778 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45414.855258 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 46229.221491 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 46032.345591 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 46000.198523 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 46190.566761 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 46073.560902 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 46021.316411 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 46020.856869 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45971.206079 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 46067.626088 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52281.249322 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 53772.607504 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 53044.776871 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52136.500000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 52982.239774 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 53144.868673 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52161.531507 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52767.411688 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52778.681055 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 47049.195153 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 47036.276249 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 46969.999063 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 47008.230321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 46986.732662 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 47003.643652 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 46847.159631 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 46938.682196 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 46979.808316 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 47049.195153 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 47036.276249 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 46969.999063 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 47008.230321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 46986.732662 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 47003.643652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 46847.159631 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 46938.682196 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 46979.808316 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44927.218559 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 45002.272561 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 45006.490495 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 45019.805550 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 45047.220146 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44972.916082 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 45028.391963 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44938.341544 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44992.694522 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 46260.365421 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46369.461496 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 46373.118474 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 46391.945900 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 46368.309183 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46372.920254 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46332.743655 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46551.714627 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 46377.702156 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 45397.131308 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45488.328465 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 45493.631832 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 45501.765502 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 45530.216807 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45470.817947 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45492.856836 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45516.504083 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 45486.343181 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 253876 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 250804 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 127987 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 121935 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 78861 # Transaction distribution -system.membus.trans_dist::ReadResp 84355 # Transaction distribution -system.membus.trans_dist::WriteReq 43772 # Transaction distribution -system.membus.trans_dist::WriteResp 43770 # Transaction distribution -system.membus.trans_dist::Writeback 6188 # Transaction distribution -system.membus.trans_dist::CleanEvict 1234 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61487 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50676 # Transaction distribution -system.membus.trans_dist::ReadExReq 49401 # Transaction distribution -system.membus.trans_dist::ReadExResp 3090 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5496 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 428330 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1068167 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1068167 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57121 # Total snoops (count) -system.membus.snoop_fanout::samples 253876 # Request fanout histogram +system.membus.trans_dist::ReadReq 78487 # Transaction distribution +system.membus.trans_dist::ReadResp 84311 # Transaction distribution +system.membus.trans_dist::WriteReq 43469 # Transaction distribution +system.membus.trans_dist::WriteResp 43465 # Transaction distribution +system.membus.trans_dist::Writeback 6515 # Transaction distribution +system.membus.trans_dist::CleanEvict 1324 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61199 # Transaction distribution +system.membus.trans_dist::UpgradeResp 50308 # Transaction distribution +system.membus.trans_dist::ReadExReq 49356 # Transaction distribution +system.membus.trans_dist::ReadExResp 3201 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5828 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427463 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 427463 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1116768 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1116768 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57043 # Total snoops (count) +system.membus.snoop_fanout::samples 255514 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253876 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 255514 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253876 # Request fanout histogram -system.membus.reqLayer0.occupancy 481009549 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 54.1 # Layer utilization (%) -system.membus.respLayer0.occupancy 317350499 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 35.7 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 783985 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 389410 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 391503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 13238 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 4575 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 8663 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 78862 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371257 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43772 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43769 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 83329 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20018 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29498 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29497 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162169 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162167 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292402 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122283 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122529 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122863 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122791 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122820 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122959 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122669 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122503 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 981417 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1781215 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778494 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776817 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1770963 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1771805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1794946 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1778453 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1777585 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14230278 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_fanout::total 255514 # Request fanout histogram +system.membus.reqLayer0.occupancy 292277246 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 56.4 # Layer utilization (%) +system.membus.respLayer0.occupancy 310111858 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 59.8 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 663155 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 282754 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 334620 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12643 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 6068 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6575 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78490 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370569 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43469 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43464 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 83812 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 20730 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29471 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29469 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161822 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161815 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292094 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122083 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122289 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122819 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122567 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122495 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122827 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122357 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122446 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 979883 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1778056 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1772835 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1781127 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1803862 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1797691 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1778038 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1761236 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1781905 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14254750 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 335326 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 797223 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.523507 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.320965 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 800967 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.187618 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.006332 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 184121 23.10% 23.10% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 277567 34.82% 57.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 172653 21.66% 79.57% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 93165 11.69% 91.26% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 44731 5.61% 96.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 17914 2.25% 99.11% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 5826 0.73% 99.84% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 1211 0.15% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 35 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 216572 27.04% 27.04% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 322054 40.21% 67.25% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 178446 22.28% 89.53% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 65924 8.23% 97.76% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 15526 1.94% 99.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2251 0.28% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 192 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 2 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 8 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 797223 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 882991225 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 99.3 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 100686388 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 100571959 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 100903359 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 11.4 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 100786975 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 100705827 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 100586898 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 100884775 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 100465612 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 11.3 # Layer utilization (%) +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 800967 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 495267856 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 95.5 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101287347 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 101004376 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101361922 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101351771 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101153250 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 101246693 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101297808 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101337760 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 19.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index d439f20bd..76540bca6 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,1806 +1,1811 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000517 # Number of seconds simulated -sim_ticks 516502000 # Number of ticks simulated -final_tick 516502000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000518 # Number of seconds simulated +sim_ticks 517786000 # Number of ticks simulated +final_tick 517786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 87177041 # Simulator tick rate (ticks/s) -host_mem_usage 277532 # Number of bytes of host memory used -host_seconds 5.92 # Real time elapsed on the host +host_tick_rate 99723528 # Simulator tick rate (ticks/s) +host_mem_usage 280036 # Number of bytes of host memory used +host_seconds 5.19 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 77818 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 80958 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 77616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 81564 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 77320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 77018 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 77760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78103 # Number of bytes read from this memory -system.physmem.bytes_read::total 628157 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 397760 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5585 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5520 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5375 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5451 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5416 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5446 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5475 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5563 # Number of bytes written to this memory -system.physmem.bytes_written::total 441591 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10975 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10902 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11130 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10918 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10679 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10819 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87365 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6215 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5585 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5520 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5375 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5451 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5416 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5446 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5475 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5563 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50046 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 150663502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 156742859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 150272409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 157916136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 149699324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 149114621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 150551208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 151215291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1216175349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 770103504 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10813124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10687277 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10406542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10553686 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10485923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10544006 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10600153 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10770529 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 854964744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 770103504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 161476625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 167430136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 160678952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 168469822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 160185246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 159658627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 161151360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 161985820 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2071140092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 82733 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 82298 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 83808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 81707 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79210 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 80419 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 83957 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 82578 # Number of bytes read from this memory +system.physmem.bytes_read::total 656710 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 415488 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5449 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5329 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5533 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5454 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5382 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5483 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5508 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5404 # Number of bytes written to this memory +system.physmem.bytes_written::total 459030 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10913 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10856 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10917 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10895 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10993 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11003 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10884 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87442 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6492 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5449 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5329 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5533 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5454 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5382 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5483 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5508 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5404 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50034 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 159782227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 158942111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 161858374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 157800713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 152978257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 155313199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 162146138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 159482875 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1268303894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 802431893 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10523653 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10291897 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10685882 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10533309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10394256 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10589317 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10637599 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10436744 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 886524549 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 802431893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 170305879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 169234008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 172544256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 168334022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 163372513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 165902516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 172783737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 169919619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2154828443 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99458 # number of read accesses completed -system.cpu0.num_writes 55230 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22190 # number of replacements -system.cpu0.l1c.tags.tagsinuse 391.694293 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13468 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22585 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.596325 # Average number of references to valid blocks. +system.cpu0.num_reads 99592 # number of read accesses completed +system.cpu0.num_writes 55369 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22465 # number of replacements +system.cpu0.l1c.tags.tagsinuse 392.038302 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13410 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22854 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.586768 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 391.694293 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.765028 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.765028 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 337088 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 337088 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1212 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1212 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9897 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9897 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9897 # number of overall hits -system.cpu0.l1c.overall_hits::total 9897 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36327 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36327 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23903 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23903 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60230 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60230 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60230 # number of overall misses -system.cpu0.l1c.overall_misses::total 60230 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 590238894 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 590238894 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 671544552 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 671544552 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1261783446 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1261783446 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1261783446 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1261783446 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45012 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45012 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25115 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25115 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70127 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70127 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70127 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70127 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807051 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807051 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.951742 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.951742 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858870 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858870 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858870 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858870 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16247.939384 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16247.939384 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28094.571895 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 28094.571895 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 20949.417998 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 20949.417998 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 20949.417998 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 20949.417998 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 738586 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 392.038302 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.765700 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.765700 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338870 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338870 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8751 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8751 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1148 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1148 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9899 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9899 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9899 # number of overall hits +system.cpu0.l1c.overall_hits::total 9899 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36676 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36676 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23894 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23894 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60570 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60570 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60570 # number of overall misses +system.cpu0.l1c.overall_misses::total 60570 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 605837577 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 605837577 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 675142476 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 675142476 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1280980053 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1280980053 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1280980053 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1280980053 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45427 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45427 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25042 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25042 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70469 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70469 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70469 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70469 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807361 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807361 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954157 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954157 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.859527 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.859527 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.859527 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.859527 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16518.638265 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16518.638265 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28255.732653 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 28255.732653 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21148.754383 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21148.754383 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21148.754383 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21148.754383 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 743435 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 60679 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61083 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.172020 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.170899 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9780 # number of writebacks -system.cpu0.l1c.writebacks::total 9780 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36327 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36327 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23903 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23903 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60230 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60230 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60230 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60230 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9914 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9914 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5586 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5586 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15500 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15500 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 553912894 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 553912894 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 647643552 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 647643552 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1201556446 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1201556446 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1201556446 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1201556446 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 648458134 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 648458134 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 875575663 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 875575663 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1524033797 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1524033797 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807051 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807051 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.951742 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.951742 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858870 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858870 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858870 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858870 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15247.966912 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15247.966912 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27094.655566 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27094.655566 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19949.467807 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19949.467807 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19949.467807 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19949.467807 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65408.324995 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65408.324995 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 156744.658611 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156744.658611 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 98324.761097 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 98324.761097 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9922 # number of writebacks +system.cpu0.l1c.writebacks::total 9922 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36676 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36676 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23894 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23894 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60570 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60570 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60570 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60570 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9773 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5450 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5450 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15223 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15223 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 569161577 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 569161577 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 651248476 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 651248476 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1220410053 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1220410053 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1220410053 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1220410053 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 638102868 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 638102868 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 843396249 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 843396249 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1481499117 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1481499117 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807361 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807361 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954157 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954157 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859527 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.859527 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859527 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.859527 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15518.638265 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15518.638265 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27255.732653 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27255.732653 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20148.754383 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20148.754383 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20148.754383 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20148.754383 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65292.424844 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65292.424844 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 154751.605321 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154751.605321 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 97319.786967 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 97319.786967 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99343 # number of read accesses completed -system.cpu1.num_writes 54840 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22376 # number of replacements -system.cpu1.l1c.tags.tagsinuse 393.102021 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13319 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22762 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.585142 # Average number of references to valid blocks. +system.cpu1.num_reads 99505 # number of read accesses completed +system.cpu1.num_writes 55135 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22526 # number of replacements +system.cpu1.l1c.tags.tagsinuse 393.510444 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13408 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22912 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.585196 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 393.102021 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.767777 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.767777 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_blocks::cpu1 393.510444 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.768575 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.768575 # Average percentage of cache occupancy system.cpu1.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id system.cpu1.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 337670 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 337670 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8618 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8618 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1175 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1175 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9793 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9793 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9793 # number of overall hits -system.cpu1.l1c.overall_hits::total 9793 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36716 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36716 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23707 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23707 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60423 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60423 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60423 # number of overall misses -system.cpu1.l1c.overall_misses::total 60423 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 601446212 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 601446212 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 664813201 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 664813201 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1266259413 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1266259413 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1266259413 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1266259413 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45334 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45334 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24882 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24882 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70216 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70216 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70216 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70216 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809900 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.809900 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.952777 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.952777 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.860530 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.860530 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.860530 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.860530 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16381.038566 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16381.038566 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28042.907200 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 28042.907200 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 20956.579663 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 20956.579663 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 20956.579663 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 20956.579663 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 733404 # number of cycles access was blocked +system.cpu1.l1c.tags.tag_accesses 339206 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 339206 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8687 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8687 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1167 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1167 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9854 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9854 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9854 # number of overall hits +system.cpu1.l1c.overall_hits::total 9854 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36759 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36759 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23925 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23925 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60684 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60684 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60684 # number of overall misses +system.cpu1.l1c.overall_misses::total 60684 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 611192958 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 611192958 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 677073428 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 677073428 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1288266386 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1288266386 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1288266386 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1288266386 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45446 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45446 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25092 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25092 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70538 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70538 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70538 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70538 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808850 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.808850 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953491 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953491 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.860302 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.860302 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.860302 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.860302 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16627.028972 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16627.028972 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28299.829801 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 28299.829801 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 21229.094753 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 21229.094753 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 21229.094753 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 21229.094753 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 746931 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 60457 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61259 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.131002 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.193000 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9757 # number of writebacks -system.cpu1.l1c.writebacks::total 9757 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36716 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36716 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23707 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23707 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60423 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60423 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60423 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60423 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9790 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9790 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5520 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5520 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15310 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15310 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 564731212 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 564731212 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 641108201 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 641108201 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1205839413 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1205839413 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1205839413 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1205839413 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 639869720 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 639869720 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 879270140 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 879270140 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1519139860 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1519139860 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809900 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809900 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.952777 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.952777 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860530 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.860530 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860530 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.860530 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15381.065802 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15381.065802 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27042.991564 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27042.991564 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19956.629313 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19956.629313 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19956.629313 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19956.629313 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65359.521961 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65359.521961 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 159288.068841 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159288.068841 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 99225.333769 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 99225.333769 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9855 # number of writebacks +system.cpu1.l1c.writebacks::total 9855 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36759 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36759 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23925 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23925 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60684 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60684 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60684 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60684 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9724 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9724 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5329 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15053 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15053 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 574433958 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 574433958 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 653148428 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 653148428 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1227582386 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1227582386 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1227582386 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1227582386 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 636306689 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 636306689 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 841464320 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 841464320 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1477771009 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1477771009 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808850 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808850 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953491 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953491 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860302 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.860302 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860302 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.860302 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15627.028972 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15627.028972 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27299.829801 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27299.829801 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20229.094753 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20229.094753 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20229.094753 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20229.094753 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65436.722439 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65436.722439 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157902.856071 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157902.856071 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 98171.195708 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 98171.195708 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99555 # number of read accesses completed -system.cpu2.num_writes 54722 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22333 # number of replacements -system.cpu2.l1c.tags.tagsinuse 393.011664 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13583 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22742 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.597265 # Average number of references to valid blocks. +system.cpu2.num_reads 99747 # number of read accesses completed +system.cpu2.num_writes 54917 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22440 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.958774 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13419 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22848 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.587316 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 393.011664 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.767601 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.767601 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 337922 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 337922 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8790 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8790 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1177 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1177 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9967 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9967 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9967 # number of overall hits -system.cpu2.l1c.overall_hits::total 9967 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36445 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36445 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23901 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23901 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60346 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60346 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60346 # number of overall misses -system.cpu2.l1c.overall_misses::total 60346 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 601110816 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 601110816 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 668105531 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 668105531 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1269216347 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1269216347 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1269216347 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1269216347 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45235 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45235 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25078 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25078 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70313 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70313 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70313 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70313 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805681 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805681 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953066 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953066 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858248 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858248 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858248 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858248 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16493.642914 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16493.642914 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27953.036735 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 27953.036735 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 21032.319408 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 21032.319408 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 21032.319408 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 21032.319408 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 742378 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.958774 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.767498 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.767498 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337058 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337058 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8566 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8566 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1197 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1197 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9763 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9763 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9763 # number of overall hits +system.cpu2.l1c.overall_hits::total 9763 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36656 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36656 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23689 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23689 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60345 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60345 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60345 # number of overall misses +system.cpu2.l1c.overall_misses::total 60345 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 609273651 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 609273651 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 671190571 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 671190571 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1280464222 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1280464222 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1280464222 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1280464222 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45222 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45222 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24886 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24886 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70108 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70108 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70108 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70108 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.810579 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.810579 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.951901 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.951901 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.860743 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.860743 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.860743 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.860743 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16621.389431 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16621.389431 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 28333.427793 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 28333.427793 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 21219.060767 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 21219.060767 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 21219.060767 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 21219.060767 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 742867 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 60996 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 60931 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.170929 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.191938 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9726 # number of writebacks -system.cpu2.l1c.writebacks::total 9726 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36445 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36445 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23901 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23901 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60346 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60346 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60346 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60346 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9904 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5377 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5377 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15281 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15281 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 564666816 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 564666816 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 644204531 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 644204531 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1208871347 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1208871347 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1208871347 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1208871347 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 647672238 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 647672238 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 840893759 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 840893759 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1488565997 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1488565997 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805681 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805681 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953066 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953066 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858248 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858248 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858248 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858248 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15493.670353 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15493.670353 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26953.036735 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26953.036735 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20032.335979 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20032.335979 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20032.335979 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20032.335979 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65395.015953 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65395.015953 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 156387.159940 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156387.159940 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97412.865454 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97412.865454 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9836 # number of writebacks +system.cpu2.l1c.writebacks::total 9836 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36656 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36656 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23689 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23689 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60345 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60345 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60345 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60345 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9760 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9760 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5535 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5535 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15295 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15295 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 572617651 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 572617651 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 647503571 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 647503571 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1220121222 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1220121222 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1220121222 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1220121222 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 638440786 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 638440786 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 853548639 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 853548639 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1491989425 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1491989425 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.810579 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.810579 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.951901 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.951901 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860743 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.860743 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860743 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.860743 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15621.389431 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15621.389431 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 27333.512221 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 27333.512221 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20219.093910 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20219.093910 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65414.014959 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65414.014959 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154209.329539 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154209.329539 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97547.526970 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97547.526970 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99759 # number of read accesses completed -system.cpu3.num_writes 54933 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22211 # number of replacements -system.cpu3.l1c.tags.tagsinuse 391.604025 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13361 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22604 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.591090 # Average number of references to valid blocks. +system.cpu3.num_reads 98987 # number of read accesses completed +system.cpu3.num_writes 55311 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22430 # number of replacements +system.cpu3.l1c.tags.tagsinuse 392.656254 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13364 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22840 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.585114 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 391.604025 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.764852 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.764852 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 336889 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 336889 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8685 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8685 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1067 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1067 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9752 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9752 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9752 # number of overall hits -system.cpu3.l1c.overall_hits::total 9752 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36549 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36549 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23764 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23764 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60313 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60313 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60313 # number of overall misses -system.cpu3.l1c.overall_misses::total 60313 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 596458593 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 596458593 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 667670467 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 667670467 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1264129060 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1264129060 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1264129060 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1264129060 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45234 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45234 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24831 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24831 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70065 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70065 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70065 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70065 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807998 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.807998 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.957030 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.957030 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.860815 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.860815 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.860815 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.860815 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16319.423049 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16319.423049 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28095.878935 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 28095.878935 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 20959.479051 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 20959.479051 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 20959.479051 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 20959.479051 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 744732 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 392.656254 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.766907 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.766907 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 337200 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 337200 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8601 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8601 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1133 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1133 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9734 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9734 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9734 # number of overall hits +system.cpu3.l1c.overall_hits::total 9734 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36299 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36299 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 24092 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 24092 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60391 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60391 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60391 # number of overall misses +system.cpu3.l1c.overall_misses::total 60391 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 601442350 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 601442350 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 682370713 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 682370713 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1283813063 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1283813063 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1283813063 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1283813063 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44900 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44900 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25225 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25225 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70125 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70125 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70125 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70125 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808441 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808441 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955084 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955084 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.861191 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.861191 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.861191 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.861191 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16569.116229 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16569.116229 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28323.539474 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 28323.539474 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 21258.350797 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 21258.350797 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 21258.350797 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 21258.350797 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 746578 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 61238 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 60969 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.161272 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.245207 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9780 # number of writebacks -system.cpu3.l1c.writebacks::total 9780 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36549 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36549 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23764 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23764 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60313 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60313 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60313 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60313 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 10012 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 10012 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.writebacks::writebacks 9891 # number of writebacks +system.cpu3.l1c.writebacks::total 9891 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36299 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36299 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24092 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 24092 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60391 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60391 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60391 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60391 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9771 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9771 # number of ReadReq MSHR uncacheable system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5455 # number of WriteReq MSHR uncacheable system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5455 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15467 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15467 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 559909593 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 559909593 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 643907467 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 643907467 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1203817060 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1203817060 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1203817060 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1203817060 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 654349566 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 654349566 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 848349724 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 848349724 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1502699290 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1502699290 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807998 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807998 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.957030 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.957030 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860815 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.860815 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860815 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.860815 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15319.423049 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15319.423049 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27095.921015 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27095.921015 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19959.495631 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19959.495631 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19959.495631 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19959.495631 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65356.528765 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65356.528765 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 155517.822915 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155517.822915 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97155.187819 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97155.187819 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15226 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15226 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 565143350 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 565143350 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 658281713 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 658281713 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1223425063 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1223425063 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1223425063 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1223425063 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 638944774 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 638944774 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 852450723 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 852450723 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1491395497 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1491395497 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808441 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808441 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955084 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955084 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861191 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.861191 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861191 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.861191 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15569.116229 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15569.116229 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27323.663996 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27323.663996 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20258.400474 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20258.400474 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20258.400474 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20258.400474 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65391.953127 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65391.953127 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 156269.610082 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156269.610082 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97950.577762 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97950.577762 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 55127 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22421 # number of replacements -system.cpu4.l1c.tags.tagsinuse 392.948683 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13931 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22818 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.610527 # Average number of references to valid blocks. +system.cpu4.num_writes 54901 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22108 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.325245 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13548 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22499 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.602160 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 392.948683 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.767478 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.767478 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 339409 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 339409 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 9015 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 9015 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1217 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1217 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 10232 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 10232 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 10232 # number of overall hits -system.cpu4.l1c.overall_hits::total 10232 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36534 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36534 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23911 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23911 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60445 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60445 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60445 # number of overall misses -system.cpu4.l1c.overall_misses::total 60445 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 594216920 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 594216920 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 670376038 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 670376038 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1264592958 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1264592958 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1264592958 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1264592958 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45549 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45549 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25128 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25128 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70677 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70677 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70677 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70677 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.802081 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.802081 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.951568 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.951568 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.855229 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.855229 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.855229 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.855229 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16264.764877 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16264.764877 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28036.302873 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 28036.302873 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 20921.382381 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 20921.382381 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 20921.382381 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 20921.382381 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 737141 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.325245 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.766260 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.766260 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338175 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338175 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8785 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8785 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1156 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1156 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9941 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9941 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9941 # number of overall hits +system.cpu4.l1c.overall_hits::total 9941 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36616 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36616 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23803 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23803 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60419 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60419 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60419 # number of overall misses +system.cpu4.l1c.overall_misses::total 60419 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 606172682 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 606172682 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 676089465 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 676089465 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1282262147 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1282262147 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1282262147 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1282262147 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45401 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45401 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24959 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70360 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70360 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70360 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70360 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806502 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.806502 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953684 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953684 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858712 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858712 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858712 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858712 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16554.858040 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16554.858040 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28403.540100 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 28403.540100 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 21222.829689 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 21222.829689 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 21222.829689 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 21222.829689 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 752786 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 60832 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61311 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.117652 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.278156 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9985 # number of writebacks -system.cpu4.l1c.writebacks::total 9985 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36534 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36534 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23911 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23911 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60445 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60445 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60445 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60445 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9865 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9865 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5418 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5418 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15283 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15283 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 557683920 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 557683920 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 646466038 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 646466038 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1204149958 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1204149958 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1204149958 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1204149958 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 645821695 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 645821695 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 857369844 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 857369844 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1503191539 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1503191539 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.802081 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.802081 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.951568 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.951568 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.855229 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.855229 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.855229 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.855229 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15264.792248 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15264.792248 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27036.344695 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27036.344695 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19921.415469 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19921.415469 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19921.415469 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19921.415469 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65465.959959 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65465.959959 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 158244.710963 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158244.710963 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 98357.098672 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 98357.098672 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9736 # number of writebacks +system.cpu4.l1c.writebacks::total 9736 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36616 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36616 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23803 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23803 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60419 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60419 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60419 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60419 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9898 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9898 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5382 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5382 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15280 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15280 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 569559682 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 569559682 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 652287465 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 652287465 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1221847147 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1221847147 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1221847147 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1221847147 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 646717625 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 646717625 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 846861232 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 846861232 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1493578857 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1493578857 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806502 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806502 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953684 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953684 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858712 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858712 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858712 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858712 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15554.939972 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15554.939972 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27403.582111 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27403.582111 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20222.895894 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20222.895894 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20222.895894 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20222.895894 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65338.212265 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65338.212265 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157350.656262 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157350.656262 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 97747.307395 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 97747.307395 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99788 # number of read accesses completed -system.cpu5.num_writes 55138 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22475 # number of replacements -system.cpu5.l1c.tags.tagsinuse 392.735284 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13651 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.596817 # Average number of references to valid blocks. +system.cpu5.num_reads 99420 # number of read accesses completed +system.cpu5.num_writes 55050 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22127 # number of replacements +system.cpu5.l1c.tags.tagsinuse 390.223258 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13616 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22515 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.604752 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 392.735284 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.767061 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.767061 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_blocks::cpu5 390.223258 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.762155 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.762155 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 340255 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 340255 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8878 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8878 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1131 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1131 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 10009 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 10009 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 10009 # number of overall hits -system.cpu5.l1c.overall_hits::total 10009 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36858 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36858 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23929 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23929 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60787 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60787 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60787 # number of overall misses -system.cpu5.l1c.overall_misses::total 60787 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 604018831 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 604018831 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 667551562 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 667551562 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1271570393 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1271570393 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1271570393 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1271570393 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45736 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45736 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25060 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25060 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70796 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70796 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70796 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70796 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805886 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.805886 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954868 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954868 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858622 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858622 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858622 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858622 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16387.726708 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16387.726708 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27897.177567 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 27897.177567 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 20918.459424 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 20918.459424 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 20918.459424 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 20918.459424 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 731203 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 338569 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 338569 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8830 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8830 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1218 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1218 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 10048 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 10048 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 10048 # number of overall hits +system.cpu5.l1c.overall_hits::total 10048 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36409 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36409 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23995 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23995 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60404 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60404 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60404 # number of overall misses +system.cpu5.l1c.overall_misses::total 60404 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 603629256 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 603629256 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 675904407 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 675904407 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1279533663 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1279533663 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1279533663 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1279533663 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45239 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45239 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25213 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25213 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70452 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70452 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70452 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70452 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.804814 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.804814 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951692 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.951692 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.857378 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.857378 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.857378 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.857378 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16579.122085 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16579.122085 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 28168.552073 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 28168.552073 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 21182.929326 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 21182.929326 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 21182.929326 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 21182.929326 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 750665 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 60676 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61291 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.050943 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.247557 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9872 # number of writebacks -system.cpu5.l1c.writebacks::total 9872 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36858 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36858 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23929 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23929 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60787 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60787 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60787 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60787 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9627 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9627 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5446 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5446 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15073 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15073 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 567160831 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 567160831 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 643622562 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 643622562 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1210783393 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1210783393 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1210783393 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1210783393 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 632098852 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 632098852 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 869172204 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 869172204 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1501271056 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1501271056 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805886 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805886 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954868 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954868 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858622 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858622 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858622 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858622 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15387.726708 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15387.726708 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26897.177567 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26897.177567 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19918.459424 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19918.459424 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19918.459424 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19918.459424 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65658.964579 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65658.964579 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 159598.274697 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159598.274697 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 99600.016984 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 99600.016984 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9761 # number of writebacks +system.cpu5.l1c.writebacks::total 9761 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36409 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36409 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23995 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23995 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60404 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60404 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60404 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60404 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9891 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9891 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5483 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5483 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15374 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15374 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 567222256 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 567222256 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 651909407 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 651909407 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1219131663 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1219131663 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1219131663 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1219131663 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 648234678 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 648234678 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 860459231 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 860459231 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1508693909 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1508693909 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.804814 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.804814 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951692 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951692 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.857378 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.857378 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.857378 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.857378 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15579.177017 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15579.177017 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 27168.552073 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27168.552073 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20182.962436 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20182.962436 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20182.962436 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20182.962436 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65537.830149 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65537.830149 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 156932.196061 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156932.196061 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 98132.815728 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 98132.815728 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99577 # number of read accesses completed -system.cpu6.num_writes 55267 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22184 # number of replacements -system.cpu6.l1c.tags.tagsinuse 392.209079 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13575 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22573 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.601382 # Average number of references to valid blocks. +system.cpu6.num_reads 99130 # number of read accesses completed +system.cpu6.num_writes 55082 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22211 # number of replacements +system.cpu6.l1c.tags.tagsinuse 391.729996 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22620 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.594651 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 392.209079 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.766033 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.766033 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 337224 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 337224 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8787 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8787 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1092 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1092 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9879 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9879 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9879 # number of overall hits -system.cpu6.l1c.overall_hits::total 9879 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36436 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36436 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23858 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23858 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60294 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60294 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60294 # number of overall misses -system.cpu6.l1c.overall_misses::total 60294 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 592887114 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 592887114 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 676055850 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 676055850 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1268942964 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1268942964 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1268942964 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1268942964 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45223 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45223 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24950 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24950 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70173 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70173 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70173 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70173 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805696 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805696 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956232 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.956232 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859219 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859219 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859219 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859219 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16272.014326 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16272.014326 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28336.652276 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 28336.652276 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 21045.924371 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 21045.924371 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 21045.924371 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 21045.924371 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 742965 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 391.729996 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.765098 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.765098 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338357 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338357 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8673 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8673 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1155 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1155 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9828 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9828 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9828 # number of overall hits +system.cpu6.l1c.overall_hits::total 9828 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36524 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36524 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 24020 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 24020 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60544 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60544 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60544 # number of overall misses +system.cpu6.l1c.overall_misses::total 60544 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 604615121 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 604615121 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 676363327 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 676363327 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1280978448 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1280978448 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1280978448 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1280978448 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45197 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45197 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25175 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25175 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70372 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70372 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808107 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.808107 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954121 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954121 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.860342 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.860342 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.860342 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.860342 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16553.913071 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16553.913071 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28158.340008 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 28158.340008 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21157.809989 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21157.809989 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21157.809989 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21157.809989 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 747919 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61020 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61299 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.175762 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.201162 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9883 # number of writebacks -system.cpu6.l1c.writebacks::total 9883 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36436 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36436 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23858 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23858 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60294 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60294 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60294 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60294 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9920 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9920 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5475 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5475 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15395 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15395 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 556451114 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 556451114 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 652198850 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 652198850 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1208649964 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1208649964 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1208649964 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1208649964 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 646733639 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 646733639 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 847369233 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 847369233 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1494102872 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1494102872 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805696 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805696 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956232 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956232 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859219 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859219 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859219 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859219 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15272.014326 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15272.014326 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27336.694191 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27336.694191 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20045.940956 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20045.940956 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20045.940956 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20045.940956 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65194.923286 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65194.923286 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 154770.636164 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154770.636164 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 97051.177135 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 97051.177135 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9790 # number of writebacks +system.cpu6.l1c.writebacks::total 9790 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36524 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36524 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24020 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 24020 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60544 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60544 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9846 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9846 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5510 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5510 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15356 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15356 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 568091121 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 568091121 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 652345327 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 652345327 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1220436448 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1220436448 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1220436448 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1220436448 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 644948195 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 644948195 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 860679200 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 860679200 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1505627395 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1505627395 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808107 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808107 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954121 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954121 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860342 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.860342 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860342 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.860342 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15553.913071 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15553.913071 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27158.423272 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27158.423272 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20157.843023 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20157.843023 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20157.843023 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20157.843023 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65503.574548 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65503.574548 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156203.121597 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156203.121597 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 98048.150234 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 98048.150234 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99427 # number of read accesses completed -system.cpu7.num_writes 55134 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22242 # number of replacements -system.cpu7.l1c.tags.tagsinuse 391.816785 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13453 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22633 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.594398 # Average number of references to valid blocks. +system.cpu7.num_reads 99282 # number of read accesses completed +system.cpu7.num_writes 55000 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22412 # number of replacements +system.cpu7.l1c.tags.tagsinuse 392.240178 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13369 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22828 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.585640 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 391.816785 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.765267 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.765267 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_blocks::cpu7 392.240178 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.766094 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.766094 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338054 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338054 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8636 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8636 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1148 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1148 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9784 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9784 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9784 # number of overall hits -system.cpu7.l1c.overall_hits::total 9784 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36700 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36700 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23832 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23832 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60532 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60532 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60532 # number of overall misses -system.cpu7.l1c.overall_misses::total 60532 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 601580634 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 601580634 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 672036114 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 672036114 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1273616748 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1273616748 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1273616748 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1273616748 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45336 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45336 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24980 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24980 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70316 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70316 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70316 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70316 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.809511 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.809511 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954043 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954043 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.860857 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.860857 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.860857 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.860857 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16391.842888 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16391.842888 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28198.897029 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 28198.897029 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 21040.387696 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 21040.387696 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 21040.387696 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 21040.387696 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 739183 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337994 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337994 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8608 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8608 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1119 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1119 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9727 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9727 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9727 # number of overall hits +system.cpu7.l1c.overall_hits::total 9727 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36557 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36557 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 24000 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 24000 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60557 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60557 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60557 # number of overall misses +system.cpu7.l1c.overall_misses::total 60557 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 604992547 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 604992547 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 682517760 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 682517760 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1287510307 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1287510307 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1287510307 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1287510307 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45165 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45165 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25119 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25119 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70284 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70284 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70284 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70284 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.809410 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.809410 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955452 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955452 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.861604 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.861604 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.861604 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.861604 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16549.294171 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16549.294171 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28438.240000 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 28438.240000 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21261.130951 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21261.130951 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21261.130951 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21261.130951 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 748003 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 60836 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 61301 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.150421 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.202134 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9689 # number of writebacks -system.cpu7.l1c.writebacks::total 9689 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36700 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36700 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23832 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23832 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60532 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60532 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60532 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60532 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9751 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9751 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5566 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5566 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15317 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15317 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 564880634 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 564880634 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 648206114 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 648206114 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1213086748 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1213086748 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1213086748 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1213086748 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 637373819 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 637373819 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 878019147 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 878019147 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1515392966 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1515392966 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.809511 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.809511 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954043 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954043 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860857 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.860857 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860857 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.860857 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15391.842888 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15391.842888 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27198.980950 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27198.980950 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20040.420736 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20040.420736 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20040.420736 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20040.420736 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65364.969644 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65364.969644 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 157746.882321 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157746.882321 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 98935.363714 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 98935.363714 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9927 # number of writebacks +system.cpu7.l1c.writebacks::total 9927 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36557 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36557 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24000 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60557 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60557 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60557 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60557 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9747 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9747 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5404 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5404 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15151 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15151 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 568436547 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 568436547 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 658518760 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 658518760 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1226955307 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1226955307 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1226955307 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1226955307 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 638135236 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 638135236 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 851560751 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 851560751 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1489695987 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1489695987 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.809410 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.809410 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955452 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955452 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.861604 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.861604 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.861604 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.861604 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15549.321525 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15549.321525 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27438.281667 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27438.281667 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20261.163978 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20261.163978 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20261.163978 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20261.163978 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65469.912383 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65469.912383 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 157579.709660 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157579.709660 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 98323.278133 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 98323.278133 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13635 # number of replacements -system.l2c.tags.tagsinuse 787.795797 # Cycle average of tags in use -system.l2c.tags.total_refs 163881 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14421 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.364052 # Average number of references to valid blocks. +system.l2c.tags.replacements 14184 # number of replacements +system.l2c.tags.tagsinuse 788.596931 # Cycle average of tags in use +system.l2c.tags.total_refs 165124 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14990 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.015610 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 732.377461 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.931961 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.975655 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.944636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.398268 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.695089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.188919 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.047720 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.236089 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.715212 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006769 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006812 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006782 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007225 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006538 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006883 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.007066 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.769332 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 786 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 654 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2092959 # Number of tag accesses -system.l2c.tags.data_accesses 2092959 # Number of data accesses -system.l2c.Writeback_hits::writebacks 77190 # number of Writeback hits -system.l2c.Writeback_hits::total 77190 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 242 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 278 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 290 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 299 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 286 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 279 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 254 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 287 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2215 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1757 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1745 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1812 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1725 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1792 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1760 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1718 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1773 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14082 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10725 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10956 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10775 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 10922 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10805 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10917 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 10735 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10921 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 86756 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12482 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12701 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12587 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12597 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12677 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12453 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12694 # number of demand (read+write) hits -system.l2c.demand_hits::total 100838 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12482 # number of overall hits -system.l2c.overall_hits::cpu1 12701 # number of overall hits -system.l2c.overall_hits::cpu2 12587 # number of overall hits -system.l2c.overall_hits::cpu3 12647 # number of overall hits -system.l2c.overall_hits::cpu4 12597 # number of overall hits -system.l2c.overall_hits::cpu5 12677 # number of overall hits -system.l2c.overall_hits::cpu6 12453 # number of overall hits -system.l2c.overall_hits::cpu7 12694 # number of overall hits -system.l2c.overall_hits::total 100838 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 2065 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2004 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2022 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2044 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2054 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2029 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2097 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2076 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16391 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4632 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4551 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4580 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4616 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4586 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4561 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4720 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4602 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 36848 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 688 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 704 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 710 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 732 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 671 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 651 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 677 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 715 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5548 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5320 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5255 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5290 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5348 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5257 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5212 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5397 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5317 # 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number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2308 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2351 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2363 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18606 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6389 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6296 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6392 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6341 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6378 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6321 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6438 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6375 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50930 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11413 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11660 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11485 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11654 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11476 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11568 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11412 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11636 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 92304 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17802 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17956 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17877 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17995 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17854 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17889 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17850 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18011 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143234 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17802 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17956 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17877 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17995 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17854 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17889 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17850 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18011 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143234 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.895102 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.878177 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.874567 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.872386 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.877778 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.879116 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.891961 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.878544 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.880952 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.724996 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.722840 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.716521 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.727961 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.719034 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.721563 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.733147 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.721882 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.723503 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.060282 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.060377 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.061820 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.062811 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.058470 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.056276 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.059324 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.061447 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.060106 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.298843 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.292660 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.295911 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.297194 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.294444 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.291352 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.302353 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.295208 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.295991 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.298843 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.292660 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.295911 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.297194 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.294444 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.291352 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.302353 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.295208 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.295991 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 29710.886683 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 30527.442615 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29045.246785 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 31304.548434 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28750.481500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28813.697388 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 30681.205532 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29830.199422 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29835.179367 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 54827.162133 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 54831.226324 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 54690.158734 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 54804.467938 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 54779.859137 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54720.439597 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 54660.045339 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 54769.755758 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 54760.119030 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 62180.104651 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 61435.257102 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 62247.756338 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 61079.815574 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 61436.543964 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 61931.513057 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 62516.121123 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62234.833566 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 61878.031903 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55778.068985 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 55715.952807 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 55704.505482 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55663.397345 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 55629.513981 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55621.132003 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 55645.511951 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55773.617077 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 55691.579088 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55778.068985 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 55715.952807 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 55704.505482 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55663.397345 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 55629.513981 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55621.132003 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 55645.511951 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 55773.617077 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 55691.579088 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 18273 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 730.575268 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.784178 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.707727 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.687216 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.484376 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.524449 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.360121 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.299960 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.173635 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.713452 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006625 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007527 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007507 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007309 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006372 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007188 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007129 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007006 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.770114 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 806 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 681 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2105340 # Number of tag accesses +system.l2c.tags.data_accesses 2105340 # Number of data accesses +system.l2c.Writeback_hits::writebacks 77391 # number of Writeback hits +system.l2c.Writeback_hits::total 77391 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 263 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 239 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 258 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 273 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 248 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 266 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 263 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 283 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2093 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1731 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1747 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1743 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1722 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1763 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1786 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1787 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1783 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14062 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 10988 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 10938 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 10927 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 10853 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 11009 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 10877 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 10827 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 10964 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 87383 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 12719 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12685 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12670 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12575 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12772 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12663 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12614 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12747 # number of demand (read+write) hits +system.l2c.demand_hits::total 101445 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12719 # number of overall hits +system.l2c.overall_hits::cpu1 12685 # number of overall hits +system.l2c.overall_hits::cpu2 12670 # number of overall hits +system.l2c.overall_hits::cpu3 12575 # number of overall hits +system.l2c.overall_hits::cpu4 12772 # number of overall hits +system.l2c.overall_hits::cpu5 12663 # number of overall hits +system.l2c.overall_hits::cpu6 12614 # number of overall hits +system.l2c.overall_hits::cpu7 12747 # number of overall hits +system.l2c.overall_hits::total 101445 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 1986 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2040 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2071 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2052 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 2099 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 2039 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 2050 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2087 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16424 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4684 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4646 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4587 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4709 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4574 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4603 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4641 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4708 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 37152 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 746 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 738 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 778 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 755 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 710 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 726 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 763 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 735 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 5951 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 5430 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5384 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5365 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5464 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5284 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5329 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5404 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5443 # number of demand (read+write) misses +system.l2c.demand_misses::total 43103 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5430 # number of overall misses +system.l2c.overall_misses::cpu1 5384 # number of overall misses +system.l2c.overall_misses::cpu2 5365 # number of overall misses +system.l2c.overall_misses::cpu3 5464 # number of overall misses +system.l2c.overall_misses::cpu4 5284 # number of overall misses +system.l2c.overall_misses::cpu5 5329 # number of overall misses +system.l2c.overall_misses::cpu6 5404 # number of overall misses +system.l2c.overall_misses::cpu7 5443 # number of overall misses +system.l2c.overall_misses::total 43103 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0 59643812 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 60697485 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 64325987 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 61406491 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 65507992 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 63321487 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 63031988 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 64081491 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 502016733 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 260655915 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 258218912 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 254645420 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 260879417 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 253975429 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 255536909 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 257461916 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 261401431 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2062775349 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 45984404 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 45132427 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 48152413 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 46986917 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 43700923 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 45387411 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 47108917 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 45792412 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 368245824 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 306640319 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 303351339 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 302797833 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 307866334 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 297676352 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 300924320 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 304570833 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 307193843 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2431021173 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 306640319 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 303351339 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 302797833 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 307866334 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 297676352 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 300924320 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 304570833 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 307193843 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2431021173 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 77391 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77391 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2249 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2279 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2329 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2325 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2347 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2305 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2313 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2370 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18517 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6415 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6393 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6330 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6431 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6337 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6389 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6428 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6491 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51214 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11734 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11676 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11705 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11608 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11719 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11603 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11590 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11699 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 93334 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18149 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18069 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18035 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18039 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18056 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17992 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18018 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18190 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 144548 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 18149 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18069 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18035 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18039 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18056 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17992 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18018 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18190 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 144548 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.883059 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.895129 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.889223 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.882581 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.894333 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.884599 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.886295 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.880591 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.886969 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.730164 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.726732 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.724645 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.732234 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.721793 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.720457 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.721998 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.725312 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.725427 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.063576 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.063207 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.066467 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.065041 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.060585 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.062570 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.065833 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.062826 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.063760 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.299190 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.297969 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.297477 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.302899 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.292645 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.296187 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.299922 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.299230 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.298192 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.299190 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.297969 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.297477 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.302899 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.292645 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.296187 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.299922 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.299230 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.298192 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 30032.130916 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 29753.669118 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 31060.351038 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29925.190546 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 31209.143402 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 31055.167729 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 30747.311220 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 30705.074748 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 30566.045604 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 55648.145816 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 55578.758502 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 55514.589056 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 55400.173498 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 55525.891780 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 55515.296328 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 55475.525964 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 55522.818819 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55522.592297 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 61641.292225 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 61155.050136 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 61892.561697 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 62234.327152 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 61550.595775 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 62517.095041 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 61741.699869 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62302.601361 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 61879.654512 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 56471.513628 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 56343.116456 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 56439.484250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 56344.497438 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 56335.418622 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 56469.191218 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 56360.257772 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 56438.332353 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 56400.277776 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 56471.513628 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 56343.116456 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 56439.484250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 56344.497438 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 56335.418622 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 56469.191218 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 56360.257772 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 56438.332353 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 56400.277776 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 17704 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 3257 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3172 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5.610378 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.581337 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6215 # number of writebacks -system.l2c.writebacks::total 6215 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 6492 # number of writebacks +system.l2c.writebacks::total 6492 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 8 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 7 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 32 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 55 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 17 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 87 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1195 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1195 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 2064 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2004 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2022 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2044 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2053 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2028 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2097 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2076 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16388 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4627 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4548 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4577 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4615 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4579 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4556 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4715 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4599 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 36816 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 683 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 697 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 705 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 723 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 661 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 644 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 672 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 708 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5493 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5310 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5245 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5282 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5338 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5240 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5200 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5387 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5307 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42309 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5310 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5245 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5282 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5338 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5240 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5200 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5387 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5307 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 42309 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9914 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9790 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9904 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 10012 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9864 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9627 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9920 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9751 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 78782 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5585 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5520 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5375 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3 5452 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu4 5416 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu5 5446 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu6 5475 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu7 5563 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 43832 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0 15499 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1 15310 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2 15279 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3 15464 # number of overall MSHR uncacheable misses +system.l2c.ReadExReq_mshr_hits::total 40 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 11 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 15 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu4 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu5 5 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu6 11 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu7 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 70 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 18 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 18 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 18 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 18 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 110 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 1197 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1197 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1986 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2039 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2071 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2052 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2099 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2037 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 2050 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2087 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16421 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4678 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4641 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4584 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4701 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4570 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4599 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4634 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4705 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 37112 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0 738 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1 727 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2 763 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3 747 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu4 702 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu5 721 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu6 752 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu7 731 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 5881 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5416 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5368 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5347 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5448 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5272 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5320 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5386 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5436 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 42993 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5416 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5368 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5347 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5448 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5272 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5320 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5386 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5436 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 42993 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0 9773 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1 9723 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2 9760 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3 9771 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu4 9898 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu5 9891 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu6 9845 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu7 9747 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 78408 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0 5449 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1 5329 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2 5533 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3 5455 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu4 5382 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu5 5483 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu6 5508 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu7 5404 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 43543 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15222 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15052 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15293 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 15226 # 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number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 93067979 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 92238981 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 94104480 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 91562476 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 91964478 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 93840981 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 737657156 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 213700915 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 211685412 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 208764420 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 213671917 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 208164429 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 209421909 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 210919416 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 214243431 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1690571849 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 38320904 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 37446428 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 40065914 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 39278917 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 36377424 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 38015411 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 39226917 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 38343914 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 307075829 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 252021819 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 249131840 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 248830334 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 252950834 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 244541853 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 247437320 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 250146333 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 252587345 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1997647678 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 252021819 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 249131840 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 248830334 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 252950834 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 244541853 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 247437320 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 250146333 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 252587345 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1997647678 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 434119876 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 432203209 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 433941865 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 434763383 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 440636377 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 440018712 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 437840875 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 433521379 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3487045676 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 249140431 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 246794950 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 253993435 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 250261774 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 246746570 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 252474432 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 253706432 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 248671425 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2001789449 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 683260307 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 678998159 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 687935300 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 685025157 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 687382947 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 692493144 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 691547307 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 682192804 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5488835125 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.894668 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.878177 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.874567 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.872386 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.877350 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.878683 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.891961 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.878544 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.880791 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.724213 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.722363 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.716051 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.727803 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.717937 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.720772 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.732370 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721412 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.722875 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.059844 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.059777 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.061384 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062039 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.057598 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.055671 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.058885 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.060846 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.059510 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.298281 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.292103 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.295463 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.296638 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.293492 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.290681 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.301793 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.294653 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.295384 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.298281 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.292103 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.295463 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.296638 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.293492 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.290681 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.301793 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.294653 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.295384 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 44153.813953 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 44143.207086 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 44154.787339 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 44162.909002 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44126.387725 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44141.018245 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44148.535527 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44114.156069 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44143.052905 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44845.994381 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44851.673483 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44703.501857 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44814.176381 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44823.200262 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44734.180202 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44683.120679 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44790.805827 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 44780.567362 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52327.836018 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51742.355811 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52404.123404 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 51409.993084 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51785.054463 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52146.608696 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52778.891369 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52485.744350 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52131.499181 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 45808.348023 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 45767.365682 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 45731.320523 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 45707.540090 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 45701.403626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 45652.180962 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 45693.025617 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 45817.377614 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 45734.942754 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 45808.348023 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 45767.365682 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 45731.320523 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 45707.540090 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 45701.403626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 45652.180962 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 45693.025617 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 45817.377614 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 45734.942754 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44434.574642 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44385.022778 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44375.893074 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44381.776768 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44449.804846 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44425.871923 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44369.744556 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44358.191365 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44397.556218 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45566.328559 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45522.452536 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45629.941953 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45783.280264 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45522.884970 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45504.485678 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45710.947032 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45702.306849 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45617.859258 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44842.397445 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44795.121555 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44817.054977 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44875.891943 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44830.158377 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44815.584024 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44846.723027 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44846.457947 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 44833.789624 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.883059 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.894691 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.889223 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882581 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.894333 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.883731 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.886295 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.880591 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.886807 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.729228 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.725950 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.724171 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.730991 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.721161 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.719831 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.720909 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.724850 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.724646 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.062894 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062264 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.065186 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.064352 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.059903 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.062139 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.064884 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.062484 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063010 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.297431 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.297431 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 44922.610775 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 44954.132418 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 44938.666828 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 44950.770468 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44833.006193 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44949.669121 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44860.720976 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44964.533301 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44921.573351 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45682.110945 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45612.025856 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 45541.976440 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 45452.439268 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45550.203282 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 45536.401174 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 45515.627104 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45535.266950 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 45553.240165 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 51925.344173 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51508.154058 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52511.027523 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52582.218206 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51819.692308 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52725.951456 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52163.453457 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52454.054720 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52214.900357 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 46410.551416 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 46536.438003 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 46385.025228 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 46443.804864 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 46465.663171 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 46464.486730 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 46410.551416 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 46536.438003 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 46385.025228 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 46443.804864 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 46465.663171 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 46464.486730 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44420.329070 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44451.631081 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44461.256660 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44495.280217 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44517.718428 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44486.777070 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44473.425597 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44477.416538 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44473.085348 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45722.229950 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46311.681366 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45905.193385 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45877.502108 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45846.631364 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46046.768557 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46061.443718 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46016.177831 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45972.703971 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44886.368874 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45110.162038 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44983.672268 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44990.487127 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44985.794961 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45043.134123 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45043.138605 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45026.255957 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 45008.529040 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 78781 # Transaction distribution -system.membus.trans_dist::ReadResp 84254 # Transaction distribution -system.membus.trans_dist::WriteReq 43831 # Transaction distribution -system.membus.trans_dist::WriteResp 43828 # Transaction distribution -system.membus.trans_dist::Writeback 6215 # Transaction distribution -system.membus.trans_dist::CleanEvict 1216 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61094 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50117 # Transaction distribution -system.membus.trans_dist::ReadExReq 49522 # Transaction distribution -system.membus.trans_dist::ReadExResp 3101 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5483 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427442 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 427442 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1069738 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1069738 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57394 # Total snoops (count) -system.membus.snoop_fanout::samples 254906 # Request fanout histogram +system.membus.trans_dist::ReadReq 78406 # Transaction distribution +system.membus.trans_dist::ReadResp 84270 # Transaction distribution +system.membus.trans_dist::WriteReq 43542 # Transaction distribution +system.membus.trans_dist::WriteResp 43539 # Transaction distribution +system.membus.trans_dist::Writeback 6492 # Transaction distribution +system.membus.trans_dist::CleanEvict 1226 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61182 # Transaction distribution +system.membus.trans_dist::UpgradeResp 50391 # Transaction distribution +system.membus.trans_dist::ReadExReq 49587 # Transaction distribution +system.membus.trans_dist::ReadExResp 3167 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5869 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427671 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 427671 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1115735 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1115735 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57207 # Total snoops (count) +system.membus.snoop_fanout::samples 255615 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 254906 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 255615 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 254906 # Request fanout histogram -system.membus.reqLayer0.occupancy 291050214 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 56.4 # Layer utilization (%) -system.membus.respLayer0.occupancy 309370624 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 59.9 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 78782 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371328 # Transaction distribution +system.membus.snoop_fanout::total 255615 # Request fanout histogram +system.membus.reqLayer0.occupancy 293172648 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 56.6 # Layer utilization (%) +system.membus.respLayer0.occupancy 310812284 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 60.0 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 663719 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 283046 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 335146 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12757 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 5920 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6837 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78408 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370885 # Transaction distribution system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43832 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43827 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 83405 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20435 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29579 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29579 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161223 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161218 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292561 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122545 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122537 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122267 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122810 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122614 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122506 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122579 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 980614 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1769994 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778957 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1770860 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1783783 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1787183 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1781792 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1778656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1778193 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14229418 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 335158 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 800908 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7.017024 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.129362 # Request fanout histogram +system.toL2Bus.trans_dist::WriteReq 43543 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43537 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 83883 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 20723 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29304 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29302 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162111 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162107 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292494 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122467 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122636 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122530 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122681 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122805 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 981273 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1801396 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1791690 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1789116 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1791289 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1784816 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1780428 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1784184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1802670 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14325589 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 335027 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 801595 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.188537 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.005333 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 787273 98.30% 98.30% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 13635 1.70% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 216155 26.97% 26.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 322197 40.19% 67.16% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 179904 22.44% 89.60% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 65286 8.14% 97.75% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 15605 1.95% 99.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2259 0.28% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 176 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 13 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 8 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 800908 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 495395322 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 101110391 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 801595 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 495500281 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 95.7 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101557213 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101309873 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 101587169 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101121441 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101199500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 101172758 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101251086 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101216377 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 101367103 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 101535375 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 19.7 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101020631 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 101469413 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101588792 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101318353 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 101399821 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- |