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-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt6
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt6
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt6
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt3433
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt3436
5 files changed, 3442 insertions, 3445 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
index 1566487a2..7c2d41959 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
@@ -4,9 +4,9 @@ sim_seconds 0.010022 # Nu
sim_ticks 10021833 # Number of ticks simulated
final_tick 10021833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 66575 # Simulator tick rate (ticks/s)
-host_mem_usage 401248 # Number of bytes of host memory used
-host_seconds 150.54 # Real time elapsed on the host
+host_tick_rate 141404 # Simulator tick rate (ticks/s)
+host_mem_usage 425972 # Number of bytes of host memory used
+host_seconds 70.87 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39622272 # Number of bytes read from this memory
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
index 760ab889a..02b6c9c1b 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
@@ -4,9 +4,9 @@ sim_seconds 0.004723 # Nu
sim_ticks 4722948 # Number of ticks simulated
final_tick 4722948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 22839 # Simulator tick rate (ticks/s)
-host_mem_usage 403984 # Number of bytes of host memory used
-host_seconds 206.79 # Real time elapsed on the host
+host_tick_rate 43612 # Simulator tick rate (ticks/s)
+host_mem_usage 429416 # Number of bytes of host memory used
+host_seconds 108.30 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38973248 # Number of bytes read from this memory
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index edf017693..ac17b1f35 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -4,9 +4,9 @@ sim_seconds 0.007679 # Nu
sim_ticks 7678882 # Number of ticks simulated
final_tick 7678882 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 60394 # Simulator tick rate (ticks/s)
-host_mem_usage 401808 # Number of bytes of host memory used
-host_seconds 127.15 # Real time elapsed on the host
+host_tick_rate 131227 # Simulator tick rate (ticks/s)
+host_mem_usage 425824 # Number of bytes of host memory used
+host_seconds 58.52 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39687936 # Number of bytes read from this memory
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
index 6281c21fd..64e77dffe 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
@@ -1,1819 +1,1816 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000541 # Number of seconds simulated
-sim_ticks 540820000 # Number of ticks simulated
-final_tick 540820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000535 # Number of seconds simulated
+sim_ticks 535115500 # Number of ticks simulated
+final_tick 535115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 46544616 # Simulator tick rate (ticks/s)
-host_mem_usage 216108 # Number of bytes of host memory used
-host_seconds 11.62 # Real time elapsed on the host
+host_tick_rate 114251239 # Simulator tick rate (ticks/s)
+host_mem_usage 237088 # Number of bytes of host memory used
+host_seconds 4.68 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 88157 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 82701 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 84142 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 82645 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 83993 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 79749 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 78765 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 84222 # Number of bytes read from this memory
-system.physmem.bytes_read::total 664374 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 426368 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5567 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5462 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5416 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5447 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5329 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5472 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5421 # Number of bytes written to this memory
-system.physmem.bytes_written::total 470013 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 11108 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10881 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10936 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 10951 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 11102 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10890 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10914 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 11079 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 87861 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6662 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5567 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5462 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5416 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5447 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5329 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5472 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5421 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 50307 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 163006176 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 152917792 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 155582264 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 152814245 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 155306756 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 147459413 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 145639954 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 155730187 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1228456788 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 788373211 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 10293628 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 10099479 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 10014423 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 10071743 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 9853556 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 10117969 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 10227063 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 10023668 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 869074738 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 788373211 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 173299804 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 163017270 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 165596687 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 162885988 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 165160312 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 157577382 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 155867017 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 165753855 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2097531526 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0 81574 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 80110 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 79121 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 81238 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 80899 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 79820 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 79202 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 79066 # Number of bytes read from this memory
+system.physmem.bytes_read::total 641030 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 406208 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5473 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5509 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5540 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5388 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5404 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5375 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5435 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5475 # Number of bytes written to this memory
+system.physmem.bytes_written::total 449807 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 11077 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 10999 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10829 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 10993 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 11032 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 10961 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 10910 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 11026 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87827 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6347 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5473 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5509 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5540 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5388 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5404 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5375 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5435 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5475 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 49946 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 152441856 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 149705998 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 147857799 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 151813954 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 151180446 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 149164059 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 148009168 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 147755017 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1197928298 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 759103409 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 10227699 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 10294974 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 10352905 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 10068854 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 10098754 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 10044560 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 10156686 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 10231436 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 840579277 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 759103409 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 162669555 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 160000972 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 158210704 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 161882808 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 161279200 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 159208619 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 158165854 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 157986453 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2038507575 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.num_reads 99596 # number of read accesses completed
-system.cpu0.num_writes 55268 # number of write accesses completed
-system.cpu0.l1c.tags.replacements 22066 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 391.486377 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13717 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22459 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.610757 # Average number of references to valid blocks.
+system.cpu0.num_reads 100000 # number of read accesses completed
+system.cpu0.num_writes 55271 # number of write accesses completed
+system.cpu0.l1c.tags.replacements 22387 # number of replacements
+system.cpu0.l1c.tags.tagsinuse 391.751313 # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs 13331 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.584873 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 391.486377 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.764622 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.764622 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses 338295 # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses 338295 # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0 8878 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8878 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1162 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1162 # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0 10040 # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total 10040 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 10040 # number of overall hits
-system.cpu0.l1c.overall_hits::total 10040 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 36478 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 36478 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 23899 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 23899 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 60377 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 60377 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 60377 # number of overall misses
-system.cpu0.l1c.overall_misses::total 60377 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 603408975 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 603408975 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 722750184 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 722750184 # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0 1326159159 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total 1326159159 # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0 1326159159 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total 1326159159 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 45356 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 45356 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 25061 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0 70417 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total 70417 # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0 70417 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total 70417 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804260 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.804260 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953633 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.953633 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.857421 # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total 0.857421 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0 0.857421 # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total 0.857421 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16541.723093 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 16541.723093 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 30241.858823 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 30241.858823 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 21964.641486 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 21964.641486 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 21964.641486 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 21964.641486 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 828428 # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0 391.751313 # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0 0.765139 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total 0.765139 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses 338274 # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses 338274 # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0 8660 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total 8660 # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0 1174 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total 1174 # number of WriteReq hits
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+system.cpu0.l1c.overall_misses::total 60496 # number of overall misses
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+system.cpu0.l1c.ReadReq_miss_latency::total 647463503 # number of ReadReq miss cycles
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+system.cpu0.l1c.WriteReq_miss_latency::total 554640697 # number of WriteReq miss cycles
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+system.cpu0.l1c.demand_miss_latency::total 1202104200 # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0 1202104200 # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total 1202104200 # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0 45177 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total 45177 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0 25153 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total 25153 # number of WriteReq accesses(hits+misses)
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+system.cpu0.l1c.demand_accesses::total 70330 # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0 70330 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total 70330 # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808310 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total 0.808310 # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953326 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total 0.953326 # miss rate for WriteReq accesses
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+system.cpu0.l1c.overall_miss_rate::cpu0 0.860173 # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total 0.860173 # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 17730.468083 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 17730.468083 # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23130.268026 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 23130.268026 # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 19870.804681 # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 19870.804681 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 19870.804681 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 19870.804681 # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs 749854 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 62795 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs 59820 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.192579 # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.535172 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9669 # number of writebacks
-system.cpu0.l1c.writebacks::total 9669 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36478 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 36478 # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23899 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total 23899 # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0 60377 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total 60377 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0 60377 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total 60377 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9885 # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5567 # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5567 # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15452 # number of overall MSHR uncacheable misses
-system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15452 # number of overall MSHR uncacheable misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 566933975 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 566933975 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 698852184 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 698852184 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1265786159 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total 1265786159 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1265786159 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 1265786159 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 722511018 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 722511018 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 853790554 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 853790554 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1576301572 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1576301572 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.804260 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.804260 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953633 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953633 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total 0.857421 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.857421 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15541.805335 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15541.805335 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 29241.900665 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 29241.900665 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 73091.655842 # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73091.655842 # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153366.365008 # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153366.365008 # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102012.786177 # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102012.786177 # average overall mshr uncacheable latency
+system.cpu0.l1c.writebacks::writebacks 9840 # number of writebacks
+system.cpu0.l1c.writebacks::total 9840 # number of writebacks
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+system.cpu0.l1c.ReadReq_mshr_misses::total 36517 # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23979 # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::total 23979 # number of WriteReq MSHR misses
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+system.cpu0.l1c.demand_mshr_misses::total 60496 # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses::cpu0 60496 # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_misses::total 60496 # number of overall MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9959 # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9959 # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5475 # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5475 # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15434 # number of overall MSHR uncacheable misses
+system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15434 # number of overall MSHR uncacheable misses
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+system.cpu0.l1c.ReadReq_mshr_miss_latency::total 610946503 # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 530662697 # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::total 530662697 # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1141609200 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::total 1141609200 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1141609200 # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::total 1141609200 # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 751203683 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 751203683 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 933372844 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1684576527 # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1684576527 # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808310 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808310 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953326 # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953326 # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860173 # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_miss_rate::total 0.860173 # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860173 # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_miss_rate::total 0.860173 # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 16730.468083 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 16730.468083 # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22130.309729 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22130.309729 # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 18870.821211 # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 18870.821211 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18870.821211 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 18870.821211 # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 75429.629782 # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75429.629782 # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 170479.058265 # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170479.058265 # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 109147.112025 # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109147.112025 # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.num_reads 98929 # number of read accesses completed
-system.cpu1.num_writes 55238 # number of write accesses completed
-system.cpu1.l1c.tags.replacements 22532 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 392.132482 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13440 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22931 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.586106 # Average number of references to valid blocks.
+system.cpu1.num_reads 99085 # number of read accesses completed
+system.cpu1.num_writes 54836 # number of write accesses completed
+system.cpu1.l1c.tags.replacements 22258 # number of replacements
+system.cpu1.l1c.tags.tagsinuse 391.296117 # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs 13378 # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs 22654 # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs 0.590536 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 392.132482 # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1 0.765884 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total 0.765884 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses 338385 # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses 338385 # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1 8754 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total 8754 # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total 1152 # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1 9906 # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total 9906 # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1 9906 # number of overall hits
-system.cpu1.l1c.overall_hits::total 9906 # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1 36277 # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total 36277 # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1 24198 # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total 24198 # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1 60475 # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total 60475 # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1 60475 # number of overall misses
-system.cpu1.l1c.overall_misses::total 60475 # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1 602891984 # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total 602891984 # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1 733995398 # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total 733995398 # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1 1336887382 # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total 1336887382 # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1 1336887382 # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total 1336887382 # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1 45031 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total 45031 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1 25350 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total 25350 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1 70381 # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total 70381 # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1 70381 # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total 70381 # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805601 # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total 0.805601 # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954556 # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total 0.954556 # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1 0.859252 # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total 0.859252 # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1 0.859252 # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total 0.859252 # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16619.124624 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 16619.124624 # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 30332.895198 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 30332.895198 # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 22106.446995 # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 22106.446995 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 22106.446995 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 22106.446995 # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs 828861 # number of cycles access was blocked
+system.cpu1.l1c.tags.occ_blocks::cpu1 391.296117 # Average occupied blocks per requestor
+system.cpu1.l1c.tags.occ_percent::cpu1 0.764250 # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total 0.764250 # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses 336817 # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses 336817 # Number of data accesses
+system.cpu1.l1c.ReadReq_hits::cpu1 8647 # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total 8647 # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1 1131 # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total 1131 # number of WriteReq hits
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+system.cpu1.l1c.overall_hits::cpu1 9778 # number of overall hits
+system.cpu1.l1c.overall_hits::total 9778 # number of overall hits
+system.cpu1.l1c.ReadReq_misses::cpu1 36589 # number of ReadReq misses
+system.cpu1.l1c.ReadReq_misses::total 36589 # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses::cpu1 23685 # number of WriteReq misses
+system.cpu1.l1c.WriteReq_misses::total 23685 # number of WriteReq misses
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+system.cpu1.l1c.demand_misses::total 60274 # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1 60274 # number of overall misses
+system.cpu1.l1c.overall_misses::total 60274 # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1 652011208 # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total 652011208 # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1 548619495 # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total 548619495 # number of WriteReq miss cycles
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+system.cpu1.l1c.demand_miss_latency::total 1200630703 # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1 1200630703 # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total 1200630703 # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1 45236 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total 45236 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1 24816 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total 24816 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1 70052 # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total 70052 # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1 70052 # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total 70052 # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808847 # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total 0.808847 # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954425 # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total 0.954425 # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1 0.860418 # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total 0.860418 # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1 0.860418 # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total 0.860418 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 17819.869578 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 17819.869578 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23163.162128 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 23163.162128 # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 19919.545791 # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 19919.545791 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 19919.545791 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 19919.545791 # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs 748495 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 62856 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 59422 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 13.186665 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.596261 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9918 # number of writebacks
-system.cpu1.l1c.writebacks::total 9918 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36277 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36277 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24198 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 24198 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 60475 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 60475 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 60475 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9741 # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9741 # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5463 # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5463 # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15204 # number of overall MSHR uncacheable misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15204 # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 566614984 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 566614984 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 709800398 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 709800398 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1276415382 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 1276415382 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1276415382 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 1276415382 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 713705140 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 713705140 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 858653101 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 858653101 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1572358241 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1572358241 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805601 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805601 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954556 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954556 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total 0.859252 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.859252 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15619.124624 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15619.124624 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 29333.019175 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 29333.019175 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 73268.159327 # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73268.159327 # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157176.112209 # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157176.112209 # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103417.406012 # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103417.406012 # average overall mshr uncacheable latency
+system.cpu1.l1c.writebacks::writebacks 9809 # number of writebacks
+system.cpu1.l1c.writebacks::total 9809 # number of writebacks
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+system.cpu1.l1c.ReadReq_mshr_misses::total 36589 # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23685 # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total 23685 # number of WriteReq MSHR misses
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+system.cpu1.l1c.demand_mshr_misses::total 60274 # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1 60274 # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total 60274 # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9902 # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9902 # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5511 # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5511 # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15413 # number of overall MSHR uncacheable misses
+system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15413 # number of overall MSHR uncacheable misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 615423208 # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_latency::total 615423208 # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 524934495 # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::total 524934495 # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1140357703 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::total 1140357703 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1140357703 # number of overall MSHR miss cycles
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+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 747152224 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 747152224 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 944376752 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1691528976 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1691528976 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808847 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808847 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954425 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954425 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860418 # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_miss_rate::total 0.860418 # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860418 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total 0.860418 # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 16819.896909 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 16819.896909 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22163.162128 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22163.162128 # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 18919.562382 # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 18919.562382 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 18919.562382 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 18919.562382 # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 75454.678247 # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75454.678247 # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 171362.139721 # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 171362.139721 # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 109746.900409 # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 109746.900409 # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.num_reads 99726 # number of read accesses completed
-system.cpu2.num_writes 55227 # number of write accesses completed
-system.cpu2.l1c.tags.replacements 22340 # number of replacements
-system.cpu2.l1c.tags.tagsinuse 393.100704 # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs 13463 # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs 22750 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.591780 # Average number of references to valid blocks.
+system.cpu2.num_reads 99705 # number of read accesses completed
+system.cpu2.num_writes 55132 # number of write accesses completed
+system.cpu2.l1c.tags.replacements 22489 # number of replacements
+system.cpu2.l1c.tags.tagsinuse 393.363987 # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs 13472 # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs 22889 # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs 0.588580 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2 393.100704 # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2 0.767775 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total 0.767775 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0 400 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses 338035 # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses 338035 # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1109 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total 1109 # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2 9766 # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total 9766 # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2 9766 # number of overall hits
-system.cpu2.l1c.overall_hits::total 9766 # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2 36622 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total 36622 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2 23922 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total 23922 # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2 60544 # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total 60544 # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2 60544 # number of overall misses
-system.cpu2.l1c.overall_misses::total 60544 # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2 606579368 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total 606579368 # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2 739451035 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total 739451035 # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2 1346030403 # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total 1346030403 # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2 1346030403 # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total 1346030403 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 45279 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total 45279 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2 25031 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total 25031 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2 70310 # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2 70310 # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808808 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total 0.808808 # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955695 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total 0.955695 # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2 0.861101 # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total 0.861101 # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2 0.861101 # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total 0.861101 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16563.250724 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 16563.250724 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30910.920283 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 30910.920283 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 22232.267491 # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 22232.267491 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 22232.267491 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 22232.267491 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 834628 # number of cycles access was blocked
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system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 63193 # number of cycles access was blocked
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system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.207602 # average number of cycles each access was blocked
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system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9768 # number of writebacks
-system.cpu2.l1c.writebacks::total 9768 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36622 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 36622 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23922 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 23922 # number of WriteReq MSHR misses
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-system.cpu2.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 60544 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9774 # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9774 # number of ReadReq MSHR uncacheable
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-system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5417 # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15191 # number of overall MSHR uncacheable misses
-system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15191 # number of overall MSHR uncacheable misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 569957368 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 569957368 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 715531035 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 715531035 # number of WriteReq MSHR miss cycles
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-system.cpu2.l1c.demand_mshr_miss_latency::total 1285488403 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1285488403 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 1285488403 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 714145091 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 714145091 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 834952155 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 834952155 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1549097246 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1549097246 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808808 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808808 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955695 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955695 # mshr miss rate for WriteReq accesses
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-system.cpu2.l1c.demand_mshr_miss_rate::total 0.861101 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.861101 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15563.250724 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15563.250724 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29911.003888 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29911.003888 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73065.796092 # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73065.796092 # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154135.527968 # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154135.527968 # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 101974.672240 # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 101974.672240 # average overall mshr uncacheable latency
+system.cpu2.l1c.writebacks::writebacks 9941 # number of writebacks
+system.cpu2.l1c.writebacks::total 9941 # number of writebacks
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+system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15286 # number of overall MSHR uncacheable misses
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+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 16868.563111 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 16868.563111 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22154.912685 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22154.912685 # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 18957.597591 # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 18957.597591 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18957.597591 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 18957.597591 # average overall mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 75536.520369 # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75536.520369 # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 173009.153221 # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173009.153221 # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 110869.233874 # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 110869.233874 # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.num_reads 99494 # number of read accesses completed
-system.cpu3.num_writes 54686 # number of write accesses completed
-system.cpu3.l1c.tags.replacements 22431 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 392.658378 # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs 13393 # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs 22832 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.586589 # Average number of references to valid blocks.
+system.cpu3.num_reads 99493 # number of read accesses completed
+system.cpu3.num_writes 55186 # number of write accesses completed
+system.cpu3.l1c.tags.replacements 22493 # number of replacements
+system.cpu3.l1c.tags.tagsinuse 393.330553 # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs 13483 # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs 22894 # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs 0.588932 # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3 392.658378 # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3 0.766911 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total 0.766911 # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_blocks::cpu3 393.330553 # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3 0.768224 # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total 0.768224 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses 337999 # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses 337999 # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3 8615 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total 8615 # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3 1106 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total 1106 # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3 9721 # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total 9721 # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3 9721 # number of overall hits
-system.cpu3.l1c.overall_hits::total 9721 # number of overall hits
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-system.cpu3.l1c.ReadReq_misses::total 36594 # number of ReadReq misses
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-system.cpu3.l1c.WriteReq_misses::total 23974 # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3 60568 # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total 60568 # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3 60568 # number of overall misses
-system.cpu3.l1c.overall_misses::total 60568 # number of overall misses
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-system.cpu3.l1c.ReadReq_miss_latency::total 607642440 # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3 730577546 # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total 730577546 # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3 1338219986 # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total 1338219986 # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3 1338219986 # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total 1338219986 # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3 45209 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total 45209 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3 25080 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total 25080 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3 70289 # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total 70289 # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3 70289 # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total 70289 # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809441 # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total 0.809441 # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955901 # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total 0.955901 # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3 0.861700 # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total 0.861700 # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3 0.861700 # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total 0.861700 # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16604.974586 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 16604.974586 # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 30473.744306 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 30473.744306 # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 22094.505118 # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 22094.505118 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 22094.505118 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 22094.505118 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 833585 # number of cycles access was blocked
+system.cpu3.l1c.tags.tag_accesses 338296 # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses 338296 # Number of data accesses
+system.cpu3.l1c.ReadReq_hits::cpu3 8738 # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total 8738 # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3 1110 # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total 1110 # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3 9848 # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total 9848 # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3 9848 # number of overall hits
+system.cpu3.l1c.overall_hits::total 9848 # number of overall hits
+system.cpu3.l1c.ReadReq_misses::cpu3 36582 # number of ReadReq misses
+system.cpu3.l1c.ReadReq_misses::total 36582 # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses::cpu3 23939 # number of WriteReq misses
+system.cpu3.l1c.WriteReq_misses::total 23939 # number of WriteReq misses
+system.cpu3.l1c.demand_misses::cpu3 60521 # number of demand (read+write) misses
+system.cpu3.l1c.demand_misses::total 60521 # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3 60521 # number of overall misses
+system.cpu3.l1c.overall_misses::total 60521 # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3 654319900 # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total 654319900 # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3 552232159 # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total 552232159 # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3 1206552059 # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total 1206552059 # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3 1206552059 # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total 1206552059 # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3 45320 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total 45320 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3 25049 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3 70369 # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total 70369 # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3 70369 # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total 70369 # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807193 # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total 0.807193 # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955687 # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total 0.955687 # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3 0.860052 # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total 0.860052 # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3 0.860052 # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total 0.860052 # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 17886.389481 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 17886.389481 # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23068.305234 # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 23068.305234 # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 19936.089275 # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 19936.089275 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 19936.089275 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 19936.089275 # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs 748969 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 63208 # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs 59958 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.187967 # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.491561 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks 9871 # number of writebacks
-system.cpu3.l1c.writebacks::total 9871 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36594 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total 36594 # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23974 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total 23974 # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3 60568 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total 60568 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3 60568 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total 60568 # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9814 # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9814 # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5449 # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5449 # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15263 # number of overall MSHR uncacheable misses
-system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15263 # number of overall MSHR uncacheable misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 571049440 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 571049440 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 706605546 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 706605546 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1277654986 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total 1277654986 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1277654986 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 1277654986 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 718813002 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 718813002 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 842609106 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 842609106 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1561422108 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1561422108 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809441 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809441 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955901 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955901 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total 0.861700 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.861700 # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15605.001913 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15605.001913 # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 29473.827730 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 29473.827730 # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 73243.631751 # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73243.631751 # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 154635.548908 # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154635.548908 # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102301.127432 # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102301.127432 # average overall mshr uncacheable latency
+system.cpu3.l1c.writebacks::writebacks 9953 # number of writebacks
+system.cpu3.l1c.writebacks::total 9953 # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36582 # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total 36582 # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23939 # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total 23939 # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses::cpu3 60521 # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_misses::total 60521 # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3 60521 # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total 60521 # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9878 # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9878 # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5388 # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5388 # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15266 # number of overall MSHR uncacheable misses
+system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15266 # number of overall MSHR uncacheable misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 617737900 # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_latency::total 617737900 # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 528295159 # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total 528295159 # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1146033059 # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::total 1146033059 # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1146033059 # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total 1146033059 # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 746486832 # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 746486832 # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 927844496 # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 927844496 # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1674331328 # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1674331328 # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807193 # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807193 # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955687 # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955687 # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860052 # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_miss_rate::total 0.860052 # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860052 # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total 0.860052 # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 16886.389481 # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 16886.389481 # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22068.388780 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22068.388780 # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 18936.122321 # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 18936.122321 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 18936.122321 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 18936.122321 # average overall mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 75570.645070 # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75570.645070 # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 172205.734224 # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172205.734224 # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 109677.147124 # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109677.147124 # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.num_reads 99490 # number of read accesses completed
-system.cpu4.num_writes 54928 # number of write accesses completed
-system.cpu4.l1c.tags.replacements 22277 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 391.439470 # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs 13388 # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs 22671 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.590534 # Average number of references to valid blocks.
+system.cpu4.num_reads 99921 # number of read accesses completed
+system.cpu4.num_writes 55196 # number of write accesses completed
+system.cpu4.l1c.tags.replacements 22380 # number of replacements
+system.cpu4.l1c.tags.tagsinuse 392.777413 # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs 13581 # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs 22786 # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs 0.596024 # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4 391.439470 # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4 0.764530 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total 0.764530 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses 337649 # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses 337649 # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4 8692 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total 8692 # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4 1145 # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total 1145 # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4 9837 # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total 9837 # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4 9837 # number of overall hits
-system.cpu4.l1c.overall_hits::total 9837 # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4 36462 # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total 36462 # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4 23928 # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total 23928 # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4 60390 # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total 60390 # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4 60390 # number of overall misses
-system.cpu4.l1c.overall_misses::total 60390 # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4 604688688 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total 604688688 # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4 724847511 # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total 724847511 # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4 1329536199 # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total 1329536199 # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4 1329536199 # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total 1329536199 # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4 45154 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total 45154 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4 25073 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total 25073 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4 70227 # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total 70227 # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4 70227 # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total 70227 # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807503 # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total 0.807503 # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954333 # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total 0.954333 # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4 0.859926 # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total 0.859926 # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4 0.859926 # miss rate for overall accesses
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-system.cpu4.l1c.WriteReq_avg_miss_latency::total 30292.858200 # average WriteReq miss latency
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-system.cpu4.l1c.overall_avg_miss_latency::cpu4 22015.833731 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 22015.833731 # average overall miss latency
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+system.cpu4.l1c.overall_avg_miss_latency::cpu4 19876.960349 # average overall miss latency
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system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 63123 # number of cycles access was blocked
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system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks 9949 # number of writebacks
-system.cpu4.l1c.writebacks::total 9949 # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36462 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total 36462 # number of ReadReq MSHR misses
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-system.cpu4.l1c.WriteReq_mshr_misses::total 23928 # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4 60390 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total 60390 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4 60390 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total 60390 # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9946 # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9946 # number of ReadReq MSHR uncacheable
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-system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable
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-system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15275 # number of overall MSHR uncacheable misses
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-system.cpu4.l1c.ReadReq_mshr_miss_latency::total 568228688 # number of ReadReq MSHR miss cycles
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-system.cpu4.l1c.demand_mshr_miss_latency::total 1269148199 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1269148199 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 1269148199 # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 727166434 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 727166434 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 837934166 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 837934166 # number of WriteReq MSHR uncacheable cycles
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-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1565100600 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807503 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807503 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954333 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954333 # mshr miss rate for WriteReq accesses
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-system.cpu4.l1c.demand_mshr_miss_rate::total 0.859926 # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total 0.859926 # mshr miss rate for overall accesses
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-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15584.133838 # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29292.858200 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29292.858200 # average WriteReq mshr miss latency
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-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 73111.445204 # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73111.445204 # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157240.413961 # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157240.413961 # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102461.577741 # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102461.577741 # average overall mshr uncacheable latency
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+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18876.993364 # average overall mshr miss latency
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+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 75596.395466 # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75596.395466 # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174725.827784 # average WriteReq mshr uncacheable latency
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+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 110551.304546 # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.num_reads 99495 # number of read accesses completed
-system.cpu5.num_writes 55318 # number of write accesses completed
-system.cpu5.l1c.tags.replacements 22409 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 392.682039 # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs 13393 # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs 22790 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.587670 # Average number of references to valid blocks.
+system.cpu5.num_reads 99482 # number of read accesses completed
+system.cpu5.num_writes 55607 # number of write accesses completed
+system.cpu5.l1c.tags.replacements 22456 # number of replacements
+system.cpu5.l1c.tags.tagsinuse 392.242325 # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs 13457 # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs 22866 # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs 0.588516 # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5 392.682039 # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5 0.766957 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total 0.766957 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses 337688 # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses 337688 # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5 8637 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total 8637 # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5 1146 # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total 1146 # number of WriteReq hits
+system.cpu5.l1c.tags.occ_blocks::cpu5 392.242325 # Average occupied blocks per requestor
+system.cpu5.l1c.tags.occ_percent::cpu5 0.766098 # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_percent::total 0.766098 # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses 338143 # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses 338143 # Number of data accesses
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+system.cpu5.l1c.ReadReq_hits::total 8578 # number of ReadReq hits
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system.cpu5.l1c.demand_hits::cpu5 9783 # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total 9783 # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5 9783 # number of overall hits
system.cpu5.l1c.overall_hits::total 9783 # number of overall hits
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-system.cpu5.l1c.ReadReq_misses::total 36329 # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5 24118 # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total 24118 # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5 60447 # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total 60447 # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5 60447 # number of overall misses
-system.cpu5.l1c.overall_misses::total 60447 # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5 601479868 # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total 601479868 # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5 729882091 # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total 729882091 # number of WriteReq miss cycles
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-system.cpu5.l1c.overall_miss_latency::total 1331361959 # number of overall miss cycles
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-system.cpu5.l1c.WriteReq_accesses::total 25264 # number of WriteReq accesses(hits+misses)
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-system.cpu5.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses
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-system.cpu5.l1c.ReadReq_miss_rate::total 0.807922 # miss rate for ReadReq accesses
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-system.cpu5.l1c.WriteReq_avg_miss_latency::total 30262.960901 # average WriteReq miss latency
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-system.cpu5.l1c.demand_avg_miss_latency::total 22025.277665 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 22025.277665 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 22025.277665 # average overall miss latency
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+system.cpu5.l1c.demand_miss_latency::total 1206223609 # number of demand (read+write) miss cycles
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+system.cpu5.l1c.overall_miss_latency::total 1206223609 # number of overall miss cycles
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+system.cpu5.l1c.ReadReq_avg_miss_latency::total 17854.884820 # average ReadReq miss latency
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+system.cpu5.l1c.overall_avg_miss_latency::cpu5 19922.103638 # average overall miss latency
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system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 62727 # number of cycles access was blocked
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system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.178249 # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.499983 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks 9995 # number of writebacks
-system.cpu5.l1c.writebacks::total 9995 # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36329 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total 36329 # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24118 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total 24118 # number of WriteReq MSHR misses
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-system.cpu5.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5 60447 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total 60447 # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9798 # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9798 # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5473 # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5473 # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15271 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15271 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 565152868 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total 565152868 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 705764091 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total 705764091 # number of WriteReq MSHR miss cycles
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-system.cpu5.l1c.demand_mshr_miss_latency::total 1270916959 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1270916959 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 1270916959 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 717311081 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 717311081 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 861132955 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 861132955 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1578444036 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1578444036 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807922 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807922 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954639 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954639 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total 0.860701 # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total 0.860701 # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15556.521457 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15556.521457 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 29262.960901 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 29262.960901 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 73209.949071 # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73209.949071 # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 157342.034533 # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157342.034533 # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 103362.192129 # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 103362.192129 # average overall mshr uncacheable latency
+system.cpu5.l1c.writebacks::writebacks 10051 # number of writebacks
+system.cpu5.l1c.writebacks::total 10051 # number of writebacks
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+system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15244 # number of overall MSHR uncacheable misses
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+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22003.967336 # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22003.967336 # average WriteReq mshr miss latency
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+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 18922.103638 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 18922.103638 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 18922.103638 # average overall mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 75500.474111 # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75500.474111 # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 174623.790698 # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174623.790698 # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 110451.131855 # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 110451.131855 # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu6.num_reads 100000 # number of read accesses completed
-system.cpu6.num_writes 55059 # number of write accesses completed
-system.cpu6.l1c.tags.replacements 22318 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 390.741535 # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs 22720 # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs 0.592033 # Average number of references to valid blocks.
+system.cpu6.num_reads 99231 # number of read accesses completed
+system.cpu6.num_writes 55266 # number of write accesses completed
+system.cpu6.l1c.tags.replacements 22476 # number of replacements
+system.cpu6.l1c.tags.tagsinuse 393.210816 # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs 13488 # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs 22863 # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs 0.589949 # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6 390.741535 # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6 0.763167 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total 0.763167 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses 338536 # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses 338536 # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6 8731 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total 8731 # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6 1150 # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total 1150 # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6 9881 # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total 9881 # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6 9881 # number of overall hits
-system.cpu6.l1c.overall_hits::total 9881 # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6 36733 # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total 36733 # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6 23795 # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total 23795 # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6 60528 # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total 60528 # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6 60528 # number of overall misses
-system.cpu6.l1c.overall_misses::total 60528 # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6 609896687 # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total 609896687 # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6 716784676 # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total 716784676 # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6 1326681363 # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total 1326681363 # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6 1326681363 # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total 1326681363 # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6 45464 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total 45464 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6 24945 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total 24945 # number of WriteReq accesses(hits+misses)
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-system.cpu6.l1c.overall_accesses::total 70409 # number of overall (read+write) accesses
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-system.cpu6.l1c.ReadReq_avg_miss_latency::total 16603.508752 # average ReadReq miss latency
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-system.cpu6.l1c.WriteReq_avg_miss_latency::total 30123.331624 # average WriteReq miss latency
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-system.cpu6.l1c.demand_avg_miss_latency::total 21918.473483 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 21918.473483 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 21918.473483 # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs 822803 # number of cycles access was blocked
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+system.cpu6.l1c.overall_miss_latency::total 1208468246 # number of overall miss cycles
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system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs 62827 # number of cycles access was blocked
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system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks 9777 # number of writebacks
-system.cpu6.l1c.writebacks::total 9777 # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36733 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total 36733 # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23795 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total 23795 # number of WriteReq MSHR misses
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-system.cpu6.l1c.demand_mshr_misses::total 60528 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6 60528 # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total 60528 # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9837 # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9837 # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5532 # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5532 # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15369 # number of overall MSHR uncacheable misses
-system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 573164687 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total 573164687 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 692991676 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total 692991676 # number of WriteReq MSHR miss cycles
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-system.cpu6.l1c.demand_mshr_miss_latency::total 1266156363 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1266156363 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total 1266156363 # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 718909036 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 718909036 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 867837123 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 867837123 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1586746159 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1586746159 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807958 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807958 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953899 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953899 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total 0.859663 # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total 0.859663 # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15603.535976 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15603.535976 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 29123.415676 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 29123.415676 # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 73082.142523 # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73082.142523 # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156875.835683 # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156875.835683 # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103243.292277 # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103243.292277 # average overall mshr uncacheable latency
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+system.cpu6.l1c.writebacks::total 9811 # number of writebacks
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+system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9828 # number of ReadReq MSHR uncacheable
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+system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5436 # number of WriteReq MSHR uncacheable
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+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 16857.947712 # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22105.163050 # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22105.163050 # average WriteReq mshr miss latency
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+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 18936.456480 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18936.456480 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 18936.456480 # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 75690.869556 # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75690.869556 # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 172632.217807 # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172632.217807 # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 110214.793108 # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 110214.793108 # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.num_reads 99734 # number of read accesses completed
-system.cpu7.num_writes 54921 # number of write accesses completed
-system.cpu7.l1c.tags.replacements 22329 # number of replacements
-system.cpu7.l1c.tags.tagsinuse 392.290074 # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs 13499 # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs 22713 # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs 0.594329 # Average number of references to valid blocks.
+system.cpu7.num_reads 99956 # number of read accesses completed
+system.cpu7.num_writes 55531 # number of write accesses completed
+system.cpu7.l1c.tags.replacements 22312 # number of replacements
+system.cpu7.l1c.tags.tagsinuse 393.161929 # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs 13691 # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs 22714 # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs 0.602756 # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7 392.290074 # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7 0.766192 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total 0.766192 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses 338596 # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses 338596 # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7 8795 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total 8795 # number of ReadReq hits
+system.cpu7.l1c.tags.occ_blocks::cpu7 393.161929 # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7 0.767894 # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total 0.767894 # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses 338939 # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses 338939 # Number of data accesses
+system.cpu7.l1c.ReadReq_hits::cpu7 8916 # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total 8916 # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7 1165 # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total 1165 # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7 9960 # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total 9960 # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7 9960 # number of overall hits
-system.cpu7.l1c.overall_hits::total 9960 # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7 36684 # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total 36684 # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7 23790 # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total 23790 # number of WriteReq misses
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system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs 63058 # number of cycles access was blocked
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system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks 9746 # number of writebacks
-system.cpu7.l1c.writebacks::total 9746 # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36684 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total 36684 # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23790 # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total 23790 # number of WriteReq MSHR misses
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-system.cpu7.l1c.overall_mshr_misses::cpu7 60474 # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total 60474 # number of overall MSHR misses
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-system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9918 # number of ReadReq MSHR uncacheable
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-system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5421 # number of WriteReq MSHR uncacheable
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-system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15339 # number of overall MSHR uncacheable misses
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-system.cpu7.l1c.ReadReq_mshr_miss_latency::total 574327013 # number of ReadReq MSHR miss cycles
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-system.cpu7.l1c.WriteReq_mshr_miss_latency::total 691615706 # number of WriteReq MSHR miss cycles
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-system.cpu7.l1c.demand_mshr_miss_latency::total 1265942719 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1265942719 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total 1265942719 # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 726668427 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 726668427 # number of ReadReq MSHR uncacheable cycles
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-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 847371643 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1574040070 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1574040070 # number of overall MSHR uncacheable cycles
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-system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806614 # mshr miss rate for ReadReq accesses
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-system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953316 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858591 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total 0.858591 # mshr miss rate for demand accesses
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-system.cpu7.l1c.overall_mshr_miss_rate::total 0.858591 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15656.062943 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15656.062943 # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 29071.698445 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 29071.698445 # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 73267.637326 # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73267.637326 # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 156312.791551 # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156312.791551 # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102616.863550 # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102616.863550 # average overall mshr uncacheable latency
+system.cpu7.l1c.writebacks::writebacks 9825 # number of writebacks
+system.cpu7.l1c.writebacks::total 9825 # number of writebacks
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+system.cpu7.l1c.WriteReq_mshr_misses::total 23963 # number of WriteReq MSHR misses
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+system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9946 # number of ReadReq MSHR uncacheable
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+system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5477 # number of WriteReq MSHR uncacheable
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+system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15423 # number of overall MSHR uncacheable misses
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+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 18924.629003 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 18924.629003 # average overall mshr miss latency
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+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75408.023829 # average ReadReq mshr uncacheable latency
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+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170088.516158 # average WriteReq mshr uncacheable latency
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+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 109030.863516 # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 14328 # number of replacements
-system.l2c.tags.tagsinuse 791.177993 # Cycle average of tags in use
-system.l2c.tags.total_refs 163940 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 15120 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 10.842593 # Average number of references to valid blocks.
+system.l2c.tags.replacements 13679 # number of replacements
+system.l2c.tags.tagsinuse 785.030982 # Cycle average of tags in use
+system.l2c.tags.total_refs 164295 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 14481 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 11.345556 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 732.189847 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 7.660754 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 7.418431 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 7.928491 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 7.181835 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 7.391664 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 6.508374 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 7.134486 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 7.764111 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.715029 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0 0.007481 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1 0.007245 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2 0.007743 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3 0.007014 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4 0.007218 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5 0.006356 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6 0.006967 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7 0.007582 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.772635 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 792 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 650 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 2105170 # Number of tag accesses
-system.l2c.tags.data_accesses 2105170 # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks 77576 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 77576 # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0 276 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1 259 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 279 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 261 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 303 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 269 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 291 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 289 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 2227 # number of UpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu3 1773 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4 1863 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5 1769 # number of ReadExReq hits
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-system.l2c.ReadExReq_hits::cpu7 1757 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 14238 # number of ReadExReq hits
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-system.l2c.ReadSharedReq_hits::cpu3 11049 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu4 10672 # number of ReadSharedReq hits
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-system.l2c.ReadSharedReq_hits::cpu6 11141 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu7 10949 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 87155 # number of ReadSharedReq hits
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-system.l2c.demand_hits::cpu7 12706 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu6 12891 # number of overall hits
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-system.l2c.UpgradeReq_misses::cpu7 1987 # number of UpgradeReq misses
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-system.l2c.ReadExReq_misses::cpu5 4594 # number of ReadExReq misses
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-system.l2c.ReadExReq_misses::cpu7 4557 # number of ReadExReq misses
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-system.l2c.overall_misses::cpu6 5233 # number of overall misses
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-system.l2c.WritebackDirty_accesses::total 77576 # number of WritebackDirty accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu6 2321 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu6 0.874623 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7 0.873023 # miss rate for UpgradeReq accesses
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-system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69021.739069 # average ReadSharedReq miss latency
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-system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69281.724377 # average ReadSharedReq miss latency
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system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 53883.459930 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 53797.322458 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 53787.708108 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 53824.577558 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 53807.612671 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 53775.355556 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 53766.751387 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 53809.574379 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 53806.527929 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59102.244094 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59354.937500 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59851.245707 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59219.962963 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58804.469281 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59213.835735 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59609.813725 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58991.884154 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59266.536035 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 52764.098533 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 52785.315368 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 52765.784326 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 52785.004688 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 52769.356762 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 52816.364564 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 52783.700823 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 52838.805102 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 52788.573706 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 54295.560625 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 54792.270414 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54559.892541 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 54609.213696 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 54556.747044 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 54641.302997 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 54897.485358 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 54617.265818 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 54621.150483 # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 53315.849081 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 53506.356509 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 53405.474259 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 53436.149279 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 53392.965693 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 53470.330714 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 53544.547726 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 53467.336006 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 53442.272686 # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.879091 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.882378 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.889944 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.876223 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.877383 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.875213 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.869163 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.871599 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.877624 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.725119 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.720530 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.715941 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.726428 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.723000 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.713980 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.724926 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.723835 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.721698 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.060427 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062878 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.060402 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.063992 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.058874 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.061413 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.059630 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.060577 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.061023 # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0 0.300678 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1 0.295507 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2 0.295355 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3 0.298878 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4 0.293178 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.298154 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.297961 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.299051 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.297344 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.300678 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.295507 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.295355 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.298878 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4 0.293178 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5 0.298154 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6 0.297961 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7 0.299051 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.297344 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 20793.145295 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 20771.712555 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 20719.084384 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 20737.336893 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 20718.154568 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 20760.129440 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 20722.885454 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 20708.580488 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20741.143139 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 24285.835384 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 23942.015331 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 23976.722977 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 23906.158397 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 24418.595347 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 23905.807618 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 24097.867653 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 23975.594157 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 24063.749388 # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 60435.688761 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 60163.767857 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 60832.001429 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 60240.191892 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59677.107715 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 60108.402266 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 60324.903930 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59915.208870 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 60212.795426 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 28924.888314 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 28923.019456 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 28812.467104 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 28927.107937 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 29001.001324 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 28657.440231 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 28750.695083 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 28638.138827 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 28828.827873 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 28924.888314 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 28923.019456 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 28812.467104 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 28927.107937 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 29001.001324 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 28657.440231 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 28750.695083 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 28638.138827 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 28828.827873 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 53478.342438 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 53528.071198 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 53575.323140 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 53520.679490 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 53508.103980 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 53534.804641 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 53571.977818 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 53563.064046 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 53534.903328 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 55252.493333 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 55271.636595 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 55356.153069 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 55111.633630 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 55462.967617 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 55437.218047 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 55650.921251 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 55411.013699 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 55369.106167 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 54107.738936 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 54151.346895 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 54220.779326 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 54082.192716 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 54197.260682 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 54205.591315 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 54312.268558 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 54219.151482 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 54186.935729 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.snoop_filter.tot_requests 127545 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 121489 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests 125196 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 119242 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq 78710 # Transaction distribution
-system.membus.trans_dist::ReadResp 84594 # Transaction distribution
-system.membus.trans_dist::WriteReq 43645 # Transaction distribution
-system.membus.trans_dist::WriteResp 43644 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 6662 # Transaction distribution
-system.membus.trans_dist::CleanEvict 1288 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 60944 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 50160 # Transaction distribution
-system.membus.trans_dist::ReadExReq 49324 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3261 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 5890 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428122 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 428122 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1134381 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1134381 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 56843 # Total snoops (count)
-system.membus.snoop_fanout::samples 246442 # Request fanout histogram
+system.membus.trans_dist::ReadReq 79046 # Transaction distribution
+system.membus.trans_dist::ReadResp 84668 # Transaction distribution
+system.membus.trans_dist::WriteReq 43599 # Transaction distribution
+system.membus.trans_dist::WriteResp 43596 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 6347 # Transaction distribution
+system.membus.trans_dist::CleanEvict 1243 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 60999 # Transaction distribution
+system.membus.trans_dist::ReadExReq 49250 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3150 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 5631 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 377529 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 377529 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1090828 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1090828 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 56847 # Total snoops (count)
+system.membus.snoop_fanout::samples 245688 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 246442 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 245688 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 246442 # Request fanout histogram
-system.membus.reqLayer0.occupancy 292771939 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 54.1 # Layer utilization (%)
-system.membus.respLayer0.occupancy 296967000 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 54.9 # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests 667370 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 284034 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 336982 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 12889 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 5997 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 6892 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 78711 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 370868 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 5 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43646 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43643 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 84238 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 20479 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29389 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29387 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 162232 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 162225 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 292173 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122572 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122851 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122953 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122545 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122770 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122967 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122678 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 981914 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1769628 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1794530 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1801428 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1802844 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1789097 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1796324 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1791880 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1784489 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14330220 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 335082 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 628739 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.148986 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.990092 # Request fanout histogram
+system.membus.snoop_fanout::total 245688 # Request fanout histogram
+system.membus.reqLayer0.occupancy 290283631 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 54.2 # Layer utilization (%)
+system.membus.respLayer0.occupancy 245575000 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 45.9 # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests 665524 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 283935 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 335837 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 12315 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 5744 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 6571 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 79051 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 371557 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43601 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43596 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 84007 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 105887 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29231 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29230 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 162413 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 162411 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 292528 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133547 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133251 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133734 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133419 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133559 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133487 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133484 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133586 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1068067 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1785416 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1780080 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1798067 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1787232 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1784031 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1801672 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1781660 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1785403 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14303561 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 335445 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 626448 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.148675 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.987271 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 176143 28.02% 28.02% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 257926 41.02% 69.04% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 134453 21.38% 90.42% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 47224 7.51% 97.93% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 11211 1.78% 99.72% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 1632 0.26% 99.98% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 146 0.02% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 174709 27.89% 27.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 258191 41.22% 69.10% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 133874 21.37% 90.47% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 46929 7.49% 97.97% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 11007 1.76% 99.72% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 1601 0.26% 99.98% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 133 0.02% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 628739 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 500695190 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 92.6 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 101141048 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 18.7 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 101214213 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 18.7 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 101195728 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 18.7 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 101296930 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 18.7 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 101179412 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 18.7 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 101203668 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 18.7 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 101388789 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 18.7 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 101354632 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 18.7 # Layer utilization (%)
+system.toL2Bus.snoop_fanout::total 626448 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 498178453 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 93.1 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 102533331 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 19.2 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 102040683 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 19.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 102532818 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 19.2 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 102294677 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 19.1 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 102527849 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 19.2 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 102329742 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 19.1 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 102510939 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 19.2 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 102349372 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 19.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
index ffbbc56b2..36475e393 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
@@ -1,1811 +1,1811 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000534 # Number of seconds simulated
-sim_ticks 534039500 # Number of ticks simulated
-final_tick 534039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000530 # Number of seconds simulated
+sim_ticks 530176500 # Number of ticks simulated
+final_tick 530176500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 46952087 # Simulator tick rate (ticks/s)
-host_mem_usage 215976 # Number of bytes of host memory used
-host_seconds 11.37 # Real time elapsed on the host
+host_tick_rate 118834220 # Simulator tick rate (ticks/s)
+host_mem_usage 236308 # Number of bytes of host memory used
+host_seconds 4.46 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 80135 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 83816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 79566 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 82290 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 82935 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 84320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 79631 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 84304 # Number of bytes read from this memory
-system.physmem.bytes_read::total 656997 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 418368 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5512 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5388 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5320 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5503 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5449 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5363 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5499 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5488 # Number of bytes written to this memory
-system.physmem.bytes_written::total 461890 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 10898 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10988 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10833 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 10911 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 10989 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10862 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10835 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10972 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 87288 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6537 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5512 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5388 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5320 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5503 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5449 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5363 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5499 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5488 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 50059 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 150054444 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 156947192 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 148988979 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 154089726 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 155297501 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 157890943 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 149110693 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 157860982 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1230240460 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 783402726 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 10321334 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 10089141 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 9961810 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 10304481 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 10203365 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 10042328 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 10296991 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 10276393 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 864898570 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 783402726 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 160375777 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 167036333 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 158950789 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 164394207 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 165500867 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 167933271 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 159407684 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 168137376 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2095139030 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0 78184 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 80178 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 79911 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 80308 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 82157 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 80611 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 79164 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 81441 # Number of bytes read from this memory
+system.physmem.bytes_read::total 641954 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 404160 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5485 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5400 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5418 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5526 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5422 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5458 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5386 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5538 # Number of bytes written to this memory
+system.physmem.bytes_written::total 447793 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 10774 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 10815 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10863 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 11071 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 10904 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 10870 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 10935 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 10881 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87113 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6315 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5485 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5400 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5418 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5526 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5422 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5458 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5386 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5538 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 49948 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 147467872 # Total read bandwidth from this memory (bytes/s)
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system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18667.071166 # average overall mshr miss latency
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+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109084.551928 # average overall mshr uncacheable latency
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-system.cpu1.num_writes 54883 # number of write accesses completed
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system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id
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system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 110873.913728 # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu2.num_writes 55057 # number of write accesses completed
-system.cpu2.l1c.tags.replacements 22416 # number of replacements
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system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
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+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18685.023140 # average overall mshr miss latency
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+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73999.014129 # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73999.014129 # average ReadReq mshr uncacheable latency
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+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 109100.896286 # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 109100.896286 # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu3.num_writes 54937 # number of write accesses completed
-system.cpu3.l1c.tags.replacements 22308 # number of replacements
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-system.cpu3.l1c.tags.sampled_refs 22699 # Sample count of references to valid blocks.
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system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.l1c.overall_avg_miss_latency::cpu3 21662.739202 # average overall miss latency
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system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
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+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109711.326774 # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu4.num_writes 54610 # number of write accesses completed
-system.cpu4.l1c.tags.replacements 21998 # number of replacements
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system.cpu4.l1c.tags.total_refs 13326 # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs 22393 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.595097 # Average number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs 22839 # Sample count of references to valid blocks.
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system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu4.l1c.overall_avg_miss_latency::total 21742.815108 # average overall miss latency
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system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu4.l1c.writebacks::total 9749 # number of writebacks
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-system.cpu4.l1c.ReadReq_mshr_misses::total 36223 # number of ReadReq MSHR misses
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-system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15299 # number of overall MSHR uncacheable misses
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-system.cpu4.l1c.demand_mshr_miss_latency::total 1244176793 # number of demand (read+write) MSHR miss cycles
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-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953065 # mshr miss rate for WriteReq accesses
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-system.cpu4.l1c.demand_mshr_miss_rate::total 0.860461 # mshr miss rate for demand accesses
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-system.cpu4.l1c.overall_mshr_miss_rate::total 0.860461 # mshr miss rate for overall accesses
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-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15231.467410 # average ReadReq mshr miss latency
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-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157867.607667 # average WriteReq mshr uncacheable latency
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+system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable
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+system.cpu4.l1c.demand_mshr_miss_latency::total 1127698160 # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1127698160 # number of overall MSHR miss cycles
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+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 21734.563182 # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 21734.563182 # average WriteReq mshr miss latency
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+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18716.981909 # average overall mshr miss latency
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+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 74115.395682 # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74115.395682 # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174329.806969 # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174329.806969 # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 109883.176614 # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 109883.176614 # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.num_reads 99530 # number of read accesses completed
-system.cpu5.num_writes 55068 # number of write accesses completed
-system.cpu5.l1c.tags.replacements 22260 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 393.692529 # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs 13670 # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs 22641 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.603772 # Average number of references to valid blocks.
+system.cpu5.num_reads 99011 # number of read accesses completed
+system.cpu5.num_writes 55007 # number of write accesses completed
+system.cpu5.l1c.tags.replacements 22453 # number of replacements
+system.cpu5.l1c.tags.tagsinuse 391.576438 # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs 13255 # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs 22854 # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs 0.579986 # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5 393.692529 # Average occupied blocks per requestor
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-system.cpu5.l1c.tags.occ_percent::total 0.768931 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses 337364 # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses 337364 # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5 8908 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total 8908 # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5 1154 # number of WriteReq hits
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-system.cpu5.l1c.overall_hits::total 10062 # number of overall hits
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-system.cpu5.l1c.ReadReq_misses::total 36264 # number of ReadReq misses
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-system.cpu5.l1c.WriteReq_misses::total 23895 # number of WriteReq misses
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-system.cpu5.l1c.demand_misses::total 60159 # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5 60159 # number of overall misses
-system.cpu5.l1c.overall_misses::total 60159 # number of overall misses
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-system.cpu5.l1c.overall_miss_latency::total 1311476260 # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5 45172 # number of ReadReq accesses(hits+misses)
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-system.cpu5.l1c.ReadReq_miss_rate::total 0.802798 # miss rate for ReadReq accesses
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-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16423.064030 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 16423.064030 # average ReadReq miss latency
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-system.cpu5.l1c.WriteReq_avg_miss_latency::total 29960.672358 # average WriteReq miss latency
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-system.cpu5.l1c.demand_avg_miss_latency::total 21800.167224 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 21800.167224 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 21800.167224 # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs 800309 # number of cycles access was blocked
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+system.cpu5.l1c.tags.occ_percent::total 0.764798 # Average percentage of cache occupancy
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+system.cpu5.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
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+system.cpu5.l1c.ReadReq_hits::total 8524 # number of ReadReq hits
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+system.cpu5.l1c.overall_miss_rate::total 0.861999 # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 17695.112117 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 17695.112117 # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 22627.363176 # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 22627.363176 # average WriteReq miss latency
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+system.cpu5.l1c.demand_avg_miss_latency::total 19648.488587 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 19648.488587 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 19648.488587 # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs 717184 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 61932 # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs 58708 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.922383 # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.216120 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks 9774 # number of writebacks
-system.cpu5.l1c.writebacks::total 9774 # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36264 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total 36264 # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23895 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total 23895 # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5 60159 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total 60159 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5 60159 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total 60159 # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9698 # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9698 # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5363 # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5363 # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15061 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15061 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 559302994 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total 559302994 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 692016266 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total 692016266 # number of WriteReq MSHR miss cycles
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-system.cpu5.l1c.demand_mshr_miss_latency::total 1251319260 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1251319260 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 1251319260 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 697234186 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 697234186 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 847695253 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 847695253 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1544929439 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1544929439 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.802798 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.802798 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953930 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953930 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.856710 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total 0.856710 # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.856710 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total 0.856710 # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15423.091606 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15423.091606 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 28960.714208 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 28960.714208 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20800.200469 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20800.200469 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20800.200469 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20800.200469 # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 71894.636626 # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71894.636626 # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 158063.630990 # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158063.630990 # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 102578.144811 # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 102578.144811 # average overall mshr uncacheable latency
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+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 109725.556928 # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu6.num_writes 54955 # number of write accesses completed
-system.cpu6.l1c.tags.replacements 22371 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 392.789220 # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs 13659 # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs 22773 # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs 0.599789 # Average number of references to valid blocks.
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system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu6.l1c.demand_avg_miss_latency::total 21549.576008 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 21549.576008 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 21549.576008 # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs 794028 # number of cycles access was blocked
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+system.cpu6.l1c.overall_avg_miss_latency::cpu6 19623.339965 # average overall miss latency
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system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs 62044 # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs 59177 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.797821 # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.214746 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks 9773 # number of writebacks
-system.cpu6.l1c.writebacks::total 9773 # number of writebacks
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-system.cpu6.l1c.WriteReq_mshr_misses::total 23715 # number of WriteReq MSHR misses
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-system.cpu6.l1c.demand_mshr_misses::total 60494 # number of demand (read+write) MSHR misses
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-system.cpu6.l1c.overall_mshr_misses::total 60494 # number of overall MSHR misses
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-system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5502 # number of WriteReq MSHR uncacheable
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-system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15245 # number of overall MSHR uncacheable misses
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-system.cpu6.l1c.demand_mshr_miss_latency::total 1243127051 # number of demand (read+write) MSHR miss cycles
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-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702205139 # number of ReadReq MSHR uncacheable cycles
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-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 875087157 # number of WriteReq MSHR uncacheable cycles
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-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1577292296 # number of overall MSHR uncacheable cycles
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-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807088 # mshr miss rate for ReadReq accesses
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-system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952104 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858339 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total 0.858339 # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858339 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total 0.858339 # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15192.641018 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15192.641018 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 28857.554586 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 28857.554586 # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20549.592538 # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20549.592538 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20549.592538 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20549.592538 # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 72072.784461 # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72072.784461 # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 159048.919847 # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159048.919847 # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103462.925287 # average overall mshr uncacheable latency
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+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18623.373040 # average overall mshr miss latency
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+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 109417.822036 # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu7.num_writes 55186 # number of write accesses completed
-system.cpu7.l1c.tags.replacements 22105 # number of replacements
-system.cpu7.l1c.tags.tagsinuse 391.370136 # Cycle average of tags in use
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-system.cpu7.l1c.tags.sampled_refs 22490 # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs 0.604491 # Average number of references to valid blocks.
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+system.cpu7.l1c.tags.sampled_refs 22650 # Sample count of references to valid blocks.
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system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7 391.370136 # Average occupied blocks per requestor
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-system.cpu7.l1c.tags.occ_task_id_blocks::1024 385 # Occupied blocks per task id
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system.cpu7.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024 0.751953 # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses 337196 # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses 337196 # Number of data accesses
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-system.cpu7.l1c.ReadReq_avg_miss_latency::total 16272.073361 # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 29894.649981 # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 29894.649981 # average WriteReq miss latency
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-system.cpu7.l1c.demand_avg_miss_latency::total 21679.720684 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 21679.720684 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 21679.720684 # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs 800916 # number of cycles access was blocked
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+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 22424.487749 # average WriteReq miss latency
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+system.cpu7.l1c.overall_avg_miss_latency::cpu7 19585.816390 # average overall miss latency
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+system.cpu7.l1c.blocked_cycles::no_mshrs 716334 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs 62109 # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs 58812 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks 9688 # number of writebacks
-system.cpu7.l1c.writebacks::total 9688 # number of writebacks
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-system.cpu7.l1c.ReadReq_mshr_misses::total 36327 # number of ReadReq MSHR misses
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-system.cpu7.l1c.WriteReq_mshr_misses::total 23913 # number of WriteReq MSHR misses
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-system.cpu7.l1c.demand_mshr_misses::total 60240 # number of demand (read+write) MSHR misses
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-system.cpu7.l1c.overall_mshr_misses::total 60240 # number of overall MSHR misses
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-system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5490 # number of WriteReq MSHR uncacheable
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-system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15298 # number of overall MSHR uncacheable misses
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-system.cpu7.l1c.ReadReq_mshr_miss_latency::total 554789609 # number of ReadReq MSHR miss cycles
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-system.cpu7.l1c.demand_mshr_miss_latency::total 1245748374 # number of demand (read+write) MSHR miss cycles
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-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 704741576 # number of ReadReq MSHR uncacheable cycles
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-system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1573689727 # number of overall MSHR uncacheable cycles
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-system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953925 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858438 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total 0.858438 # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858438 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total 0.858438 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15272.100889 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15272.100889 # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 28894.691799 # average WriteReq mshr miss latency
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-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20679.753884 # average overall mshr miss latency
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system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.UpgradeReq_hits::cpu7 273 # number of UpgradeReq hits
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.l2c.overall_mshr_uncacheable_latency::total 6401510764 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.875820 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.880992 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.875430 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882277 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.884632 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.886402 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.883681 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.883433 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.881612 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726527 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.713794 # mshr miss rate for ReadExReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.734118 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.728843 # mshr miss rate for ReadExReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721715 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.724662 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.063363 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.067407 # mshr miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.063476 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.061017 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.065821 # mshr miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.063430 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063565 # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0 0.295868 # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu4 0.301007 # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu6 0.295190 # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::total 0.298202 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0 0.295868 # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu3 0.295692 # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::total 0.298202 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 51820.502247 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 51833.867780 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 51855.473994 # average UpgradeReq mshr miss latency
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 51804.842637 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 51837.290138 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 51859.671649 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 51753.155631 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 51831.174608 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 52384.680018 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 52396.991893 # average ReadExReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::total 52393.925931 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 58581.380822 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 57851.861004 # average ReadSharedReq mshr miss latency
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-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58523.644022 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58044.042735 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 57528.255937 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58513.831006 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58347.084584 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58201.100783 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 53246.480663 # average overall mshr miss latency
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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51355.455046 # average ReadReq mshr uncacheable latency
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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51338.964862 # average ReadReq mshr uncacheable latency
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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51335.275480 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51301.669657 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51334.431525 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53016.913643 # average WriteReq mshr uncacheable latency
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-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 53328.894925 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53198.964928 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53109.600294 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53001.749394 # average WriteReq mshr uncacheable latency
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-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53104.918200 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53163.089516 # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 51953.584482 # average overall mshr uncacheable latency
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-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 51968.753092 # average overall mshr uncacheable latency
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-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 51918.408937 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52047.761580 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 51948.726678 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 51988.024595 # average overall mshr uncacheable latency
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.876830 # mshr miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.883282 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.886558 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.869204 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.872900 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.880454 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.878139 # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.727244 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.721145 # mshr miss rate for ReadExReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::total 0.720996 # mshr miss rate for ReadExReq accesses
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+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062949 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.063005 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062554 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.062125 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.059985 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.057467 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.065743 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.061804 # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0 0.298516 # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::cpu2 0.298591 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3 0.294239 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4 0.295122 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.293600 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.296565 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.302322 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.296690 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.298516 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.294678 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.298591 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.294239 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4 0.295122 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5 0.293600 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6 0.296565 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7 0.302322 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.296690 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 19237.777613 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 19269.184185 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 19290.727058 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 19303.659712 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 19276.070014 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 19248.586311 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 19230.378578 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 19251.534192 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19263.681397 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 22354.528063 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 22422.961857 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 22275.815054 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 22547.604718 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 22884.830516 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 22625.916073 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 22633.139407 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 22492.943404 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 22529.055513 # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59120.613960 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 58754.313187 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59471.547067 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58655.411034 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58813.765035 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 58747.060993 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58985.702096 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59138.512752 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58962.207481 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 27160.820857 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 27398.361362 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 27340.736392 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 27523.495153 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 27759.439279 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 27394.718914 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 27140.101522 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 27606.438284 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 27414.190686 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 27160.820857 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 27398.361362 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 27340.736392 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 27523.495153 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 27759.439279 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 27394.718914 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 27140.101522 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 27606.438284 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 27414.190686 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51836.922617 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51834.520021 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51837.208150 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51831.934617 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51793.861967 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51846.302571 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51891.205644 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51793.501639 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51833.236869 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53272.199599 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 53730.930556 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54048.480716 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53785.831524 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53636.094044 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53581.986259 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 53652.224285 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53756.660347 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53682.780686 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 52355.251201 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 52512.033543 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 52626.282695 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 52528.620274 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 52451.299750 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 52468.690165 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52513.652579 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 52504.088105 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 52495.065513 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 78245 # Transaction distribution
-system.membus.trans_dist::ReadResp 84100 # Transaction distribution
-system.membus.trans_dist::WriteReq 43522 # Transaction distribution
-system.membus.trans_dist::WriteResp 43520 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 6537 # Transaction distribution
-system.membus.trans_dist::CleanEvict 1268 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 61107 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 50201 # Transaction distribution
-system.membus.trans_dist::ReadExReq 48942 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3181 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 5862 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 426485 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 426485 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1118817 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1118817 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 56662 # Total snoops (count)
-system.membus.snoop_fanout::samples 253744 # Request fanout histogram
+system.membus.trans_dist::ReadReq 78306 # Transaction distribution
+system.membus.trans_dist::ReadResp 84006 # Transaction distribution
+system.membus.trans_dist::WriteReq 43633 # Transaction distribution
+system.membus.trans_dist::WriteResp 43633 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 6315 # Transaction distribution
+system.membus.trans_dist::CleanEvict 1254 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 60980 # Transaction distribution
+system.membus.trans_dist::ReadExReq 48711 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3097 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 5709 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 375644 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 375644 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1089674 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1089674 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 56426 # Total snoops (count)
+system.membus.snoop_fanout::samples 252331 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 253744 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 252331 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 253744 # Request fanout histogram
-system.membus.reqLayer0.occupancy 292620525 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 54.8 # Layer utilization (%)
-system.membus.respLayer0.occupancy 295409000 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 55.3 # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests 663684 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 282033 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 335738 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 12570 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 5835 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 6735 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 78248 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 369469 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43523 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43520 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 83531 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 20342 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29636 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29633 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 160854 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 160848 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 291239 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 121995 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122071 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122139 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122334 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122013 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 121723 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122513 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122322 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 977110 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1766349 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778610 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1781270 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1785072 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1775296 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1771667 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1779976 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1778751 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14216991 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 333737 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 624990 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.150519 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.991140 # Request fanout histogram
+system.membus.snoop_fanout::total 252331 # Request fanout histogram
+system.membus.reqLayer0.occupancy 290210873 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 54.7 # Layer utilization (%)
+system.membus.respLayer0.occupancy 244257000 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 46.1 # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests 663692 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 283641 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 333885 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 12353 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 5692 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 6661 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 78309 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 370176 # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43636 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43632 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 83900 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 105566 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29367 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29367 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 161854 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 161852 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 291888 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133128 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133137 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133276 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133136 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 132901 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133285 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133385 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 132788 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1065036 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1790740 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1793737 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1783183 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1779785 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1777562 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1801715 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1799686 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1764480 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14290888 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 334512 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 624442 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.148246 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.987708 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 174852 27.98% 27.98% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 256379 41.02% 69.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 133497 21.36% 90.36% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 47307 7.57% 97.93% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 11157 1.79% 99.71% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 1650 0.26% 99.98% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 145 0.02% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 174331 27.92% 27.92% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 257461 41.23% 69.15% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 132941 21.29% 90.44% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 47060 7.54% 97.97% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 10899 1.75% 99.72% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 1610 0.26% 99.98% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 136 0.02% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 624990 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 497290718 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 93.1 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 100872915 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 18.9 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 100601006 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 18.8 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 101141480 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 18.9 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 100780789 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 18.9 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 100568051 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 18.8 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 100691951 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 18.9 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 101210192 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 19.0 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 100872512 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 18.9 # Layer utilization (%)
+system.toL2Bus.snoop_fanout::total 624442 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 496537925 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 93.7 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 101982318 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 19.2 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 102105458 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 19.3 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 101942894 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 19.2 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 101777352 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 19.2 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 101724075 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 19.2 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 101820787 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 19.2 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 102063169 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 19.3 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 101980781 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 19.2 # Layer utilization (%)
---------- End Simulation Statistics ----------