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-rw-r--r--tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt572
1 files changed, 289 insertions, 283 deletions
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 51d70d56c..39b06f58a 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,43 +1,43 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.134742 # Number of seconds simulated
-sim_ticks 134741611500 # Number of ticks simulated
-final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.134921 # Number of seconds simulated
+sim_ticks 134921160500 # Number of ticks simulated
+final_tick 134921160500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 968280 # Simulator instruction rate (inst/s)
-host_op_rate 968280 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1476869211 # Simulator tick rate (ticks/s)
-host_mem_usage 256564 # Number of bytes of host memory used
-host_seconds 91.23 # Real time elapsed on the host
+host_inst_rate 1080841 # Simulator instruction rate (inst/s)
+host_op_rate 1080841 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1650749081 # Simulator tick rate (ticks/s)
+host_mem_usage 262472 # Number of bytes of host memory used
+host_seconds 81.73 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 367360 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10138112 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10505472 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 367360 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 367360 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7320448 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7320448 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 5740 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 158408 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 164148 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 114382 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 114382 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2726403 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 75241137 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 77967540 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2726403 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2726403 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 54329527 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 54329527 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 54329527 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2726403 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 75241137 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 132297067 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst 369920 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10155520 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10525440 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 369920 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 369920 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7371264 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7371264 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 5780 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 158680 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 164460 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 115176 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 115176 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2741749 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 75270031 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 78011781 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2741749 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2741749 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 54633862 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 54633862 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 54633862 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2741749 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 75270031 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 132645642 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -72,8 +72,8 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 134741611500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 269483223 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 134921160500 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 269842321 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88340673 # Number of instructions committed
@@ -92,7 +92,7 @@ system.cpu.num_mem_refs 34987415 # nu
system.cpu.num_load_insts 20366786 # Number of load instructions
system.cpu.num_store_insts 14620629 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 269483223 # Number of busy cycles
+system.cpu.num_busy_cycles 269842321 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 13754477 # Number of branches fetched
@@ -131,24 +131,24 @@ system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 88438073 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 200248 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4078.397630 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 4078.334496 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 983457500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4078.397630 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.995703 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.995703 # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle 990170500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4078.334496 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.995687 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.995687 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 3595 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 445 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 3604 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
@@ -165,14 +165,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n
system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
system.cpu.dcache.overall_misses::total 204344 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2138978000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2138978000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 8279807000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 8279807000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 10418785000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 10418785000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 10418785000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 10418785000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2178421500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2178421500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 8412226500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 8412226500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 10590648000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 10590648000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 10590648000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 10590648000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
@@ -189,22 +189,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857
system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35200.243557 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 35200.243557 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57667.657998 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 57667.657998 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 50986.498258 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 50986.498258 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35849.348320 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 35849.348320 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58589.940659 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 58589.940659 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 51827.545707 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 51827.545707 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 51827.545707 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 51827.545707 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 168278 # number of writebacks
-system.cpu.dcache.writebacks::total 168278 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 167988 # number of writebacks
+system.cpu.dcache.writebacks::total 167988 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
@@ -213,14 +213,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344
system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078212000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078212000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8136229000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8136229000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10214441000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10214441000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10214441000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10214441000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2117655500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2117655500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8268648500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8268648500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10386304000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10386304000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10386304000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10386304000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
@@ -229,33 +229,33 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34200.243557 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34200.243557 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56667.657998 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56667.657998 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34849.348320 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34849.348320 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57589.940659 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57589.940659 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50827.545707 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 50827.545707 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50827.545707 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 50827.545707 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 74391 # number of replacements
-system.cpu.icache.tags.tagsinuse 1870.507754 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 1870.340281 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1870.507754 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.913334 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.913334 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 1870.340281 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.913252 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.913252 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses
system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits
@@ -268,12 +268,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n
system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses
system.cpu.icache.overall_misses::total 76436 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1275518500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1275518500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1275518500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 1275518500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 1275518500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 1275518500 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 1283204500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 1283204500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 1283204500 # number of demand (read+write) miss cycles
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-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130882 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 130882 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 5740 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 5740 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27526 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27526 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 5740 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 158408 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 164148 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 5740 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 158408 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 164148 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6478722500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6478722500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284466000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284466000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1362730000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1362730000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284466000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7841452500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 8125918500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284466000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7841452500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 8125918500 # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks 115177 # number of writebacks
+system.cpu.l2cache.writebacks::total 115177 # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 106 # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total 106 # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130913 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 130913 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 5780 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 5780 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27767 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27767 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 5780 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 158680 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 164460 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 5780 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 158680 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 164460 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6611157500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6611157500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 292172000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 292172000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1402294000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1402294000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 292172000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8013451500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 8305623500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 292172000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8013451500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 8305623500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911574 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911574 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075096 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452984 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452984 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.584614 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.584614 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.485170 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.485170 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49558.536585 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49558.536585 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49507.011553 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49507.011553 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911790 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911790 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.075619 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075619 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456950 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456950 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.075619 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.776534 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.585725 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.075619 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.776534 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.585725 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.389572 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.389572 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50548.788927 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50548.788927 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.178845 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.178845 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50548.788927 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.702672 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50502.392679 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50548.788927 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.702672 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50502.392679 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 3875 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3875 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 4055 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4055 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 282660 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 283165 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 49586 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 50825 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution
@@ -507,53 +507,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9652928 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23847808 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 33500736 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 131998 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 7320448 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 412778 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.009388 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.096434 # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23829248 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 33482176 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 133742 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 7371328 # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples 414522 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.009782 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.098421 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 408903 99.06% 99.06% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 3875 0.94% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 410467 99.02% 99.02% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 4055 0.98% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 412778 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 520378500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 414522 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 520088500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 33266 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 114382 # Transaction distribution
-system.membus.trans_dist::CleanEvict 13845 # Transaction distribution
-system.membus.trans_dist::ReadExReq 130882 # Transaction distribution
-system.membus.trans_dist::ReadExResp 130882 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 33266 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 456523 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 456523 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825920 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 17825920 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoop_filter.tot_requests 294252 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 129792 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp 33547 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 115176 # Transaction distribution
+system.membus.trans_dist::CleanEvict 14616 # Transaction distribution
+system.membus.trans_dist::ReadExReq 130913 # Transaction distribution
+system.membus.trans_dist::ReadExResp 130913 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 33547 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 458712 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 458712 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17896704 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 17896704 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 292375 # Request fanout histogram
+system.membus.snoop_fanout::samples 164460 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 292375 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 164460 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 292375 # Request fanout histogram
-system.membus.reqLayer0.occupancy 750324500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 164460 # Request fanout histogram
+system.membus.reqLayer0.occupancy 755151000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 820740000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 822300000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
---------- End Simulation Statistics ----------