diff options
Diffstat (limited to 'tests/quick/se/50.vortex/ref/alpha/tru64')
-rw-r--r-- | tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt | 14 | ||||
-rw-r--r-- | tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt | 21 |
2 files changed, 25 insertions, 10 deletions
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index d7757f328..f25ed6812 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1535738 # Simulator instruction rate (inst/s) -host_op_rate 1535737 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 768748978 # Simulator tick rate (ticks/s) -host_mem_usage 246592 # Number of bytes of host memory used -host_seconds 57.52 # Real time elapsed on the host +host_inst_rate 3085186 # Simulator instruction rate (inst/s) +host_op_rate 3085185 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1544361453 # Simulator tick rate (ticks/s) +host_mem_usage 293364 # Number of bytes of host memory used +host_seconds 28.63 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 2072610067 # Wr system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 44221003000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 88442007 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 108714711 # Transaction distribution system.membus.trans_dist::ReadResp 108714711 # Transaction distribution system.membus.trans_dist::WriteReq 14613377 # Transaction distribution diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 4daa87195..b00dd906e 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.134742 # Nu sim_ticks 134741611500 # Number of ticks simulated final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 882134 # Simulator instruction rate (inst/s) -host_op_rate 882134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1345475029 # Simulator tick rate (ticks/s) -host_mem_usage 255564 # Number of bytes of host memory used -host_seconds 100.14 # Real time elapsed on the host +host_inst_rate 1731648 # Simulator instruction rate (inst/s) +host_op_rate 1731647 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2641194476 # Simulator tick rate (ticks/s) +host_mem_usage 302344 # Number of bytes of host memory used +host_seconds 51.02 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 367360 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10138112 # Number of bytes read from this memory system.physmem.bytes_read::total 10505472 # Number of bytes read from this memory @@ -36,6 +37,7 @@ system.physmem.bw_total::writebacks 54329527 # To system.physmem.bw_total::cpu.inst 2726403 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 75241137 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 132297067 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,6 +72,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 134741611500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 269483223 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -128,6 +131,7 @@ system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 200248 # number of replacements system.cpu.dcache.tags.tagsinuse 4078.397630 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. @@ -144,6 +148,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3595 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits @@ -232,6 +237,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258 system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 74391 # number of replacements system.cpu.icache.tags.tagsinuse 1870.507754 # Cycle average of tags in use system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. @@ -249,6 +255,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -317,6 +324,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15687.405149 system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 131998 # number of replacements system.cpu.l2cache.tags.tagsinuse 30708.485304 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 247404 # Total number of references to valid blocks. @@ -339,6 +347,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 122 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4751004 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4751004 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 168278 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 168278 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 74391 # number of WritebackClean hits @@ -485,6 +494,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 3875 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3875 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 282660 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution @@ -517,6 +527,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 114654000 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 33266 # Transaction distribution system.membus.trans_dist::WritebackDirty 114382 # Transaction distribution system.membus.trans_dist::CleanEvict 13845 # Transaction distribution |