diff options
Diffstat (limited to 'tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt | 537 |
1 files changed, 277 insertions, 260 deletions
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 90d753109..22fc38403 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.127293 # Number of seconds simulated -sim_ticks 127293406500 # Number of ticks simulated -final_tick 127293406500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 127292683500 # Number of ticks simulated +final_tick 127292683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 627920 # Simulator instruction rate (inst/s) -host_op_rate 801678 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1135795886 # Simulator tick rate (ticks/s) -host_mem_usage 312172 # Number of bytes of host memory used -host_seconds 112.07 # Real time elapsed on the host +host_inst_rate 884807 # Simulator instruction rate (inst/s) +host_op_rate 1129650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1600449674 # Simulator tick rate (ticks/s) +host_mem_usage 320712 # Number of bytes of host memory used +host_seconds 79.54 # Real time elapsed on the host sim_insts 70373629 # Number of instructions simulated sim_ops 89847363 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 252800 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory -system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory -system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 8177280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 252800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 252800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5511360 # Number of bytes written to this memory +system.physmem.bytes_written::total 5511360 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3950 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory -system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62253656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64260736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 42187385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 42187385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 42187385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62253656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106448121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 127770 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86115 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86115 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1985974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62254010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64239984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1985974 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1985974 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43296754 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43296754 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43296754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1985974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62254010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 107536738 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 254586813 # number of cpu cycles simulated +system.cpu.numCycles 254585367 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373629 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 43422001 # nu system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 254586812.998000 # Number of busy cycles +system.cpu.num_busy_cycles 254585366.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 13741486 # Number of branches fetched @@ -215,53 +215,53 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690084 # Class of executed instruction system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.389329 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4076.389202 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42608158 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061071000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389329 # Average occupied blocks per requestor +system.cpu.dcache.tags.avg_refs 266.304316 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1061071500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389202 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 857 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3190 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22749839 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22749839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 22749833 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22749833 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83618 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83618 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42492708 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42492708 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42576331 # number of overall hits -system.cpu.dcache.overall_hits::total 42576331 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 30228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 30228 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 42492702 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42492702 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42576320 # number of overall hits +system.cpu.dcache.overall_hits::total 42576320 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 30234 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 30234 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 137260 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137260 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 177381 # number of overall misses -system.cpu.dcache.overall_misses::total 177381 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 517066000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 517066000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689116000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689116000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6206182000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6206182000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6206182000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6206182000 # number of overall miss cycles +system.cpu.dcache.SoftPFReq_misses::cpu.data 40126 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40126 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 137266 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137266 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 177392 # number of overall misses +system.cpu.dcache.overall_misses::total 177392 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 516863000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 516863000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689129500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689129500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6205992500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6205992500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6205992500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6205992500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -280,20 +280,20 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324266 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.324266 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45214.789451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34987.862285 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17095.422372 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17095.422372 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.538194 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.538194 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45211.432547 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45211.432547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34984.624448 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34984.624448 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,14 +302,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks -system.cpu.dcache.writebacks::total 128239 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1120 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1120 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1120 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1120 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1120 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 128193 # number of writebacks +system.cpu.dcache.writebacks::total 128193 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1126 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1126 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1126 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1126 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1126 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -320,16 +320,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136140 system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 457995500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 457995500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5528568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5528568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1058278000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1058278000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5986563500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5986563500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7044841500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7044841500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 472117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 472117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5582097500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5582097500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1070376500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1070376500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6054214500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6054214500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7124591000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7124591000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -340,24 +340,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15734.351381 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15734.351381 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51653.412064 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51653.412064 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44357.364406 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44357.364406 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43973.582342 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43973.582342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16219.492923 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16219.492923 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52153.538194 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52153.538194 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44864.468941 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44864.468941 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44470.504628 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44470.504628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44529.250366 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44529.250366 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1733.672960 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1733.672092 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672960 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672092 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id @@ -380,12 +380,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413935000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413935000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413935000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413935000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413935000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413935000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 412325000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 412325000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 412325000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 412325000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 412325000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 412325000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses @@ -398,12 +398,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21892.056272 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21892.056272 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21892.056272 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21892.056272 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21806.907129 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21806.907129 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21806.907129 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21806.907129 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,117 +418,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 385573000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 385573000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 385573000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 385573000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 385573000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 385573000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393417000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 393417000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393417000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 393417000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393417000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 393417000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20392.056272 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20392.056272 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20806.907129 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20806.907129 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 94693 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30351.005772 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 94651 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30350.488546 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 114091 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 125746 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.907313 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27796.867853 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.768393 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.369526 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.848293 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.042797 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.926239 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27670.394493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.496373 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.597680 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.844433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.036545 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.045245 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.926223 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15103 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13917 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 607 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1360 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13873 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2689980 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128239 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128239 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 3016794 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3016794 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 128193 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128193 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14916 # number of demand (read+write) hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14958 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 14958 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31426 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 31426 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 14958 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 36178 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 51094 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14916 # number of overall hits +system.cpu.l2cache.demand_hits::total 51136 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 14958 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 36178 # number of overall hits -system.cpu.l2cache.overall_hits::total 51094 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3992 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21540 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 25532 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 51136 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3992 # number of demand (read+write) misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3950 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3950 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21540 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 21540 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3950 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 123820 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 127812 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses +system.cpu.l2cache.demand_misses::total 127770 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3950 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses -system.cpu.l2cache.overall_misses::total 127812 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210047000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1133331500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1343378500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371640000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5371640000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 210047000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6504971500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6715018500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 210047000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6504971500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6715018500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 128239 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 128239 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 127770 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371653500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5371653500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 207971500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 207971500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1133068500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1133068500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 207971500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6504722000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6712693500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 207971500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6504722000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6712693500 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 128193 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128193 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 18908 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 52966 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.211128 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.406676 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.355233 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955602 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.955602 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.211128 # miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.208906 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.208906 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.406676 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.406676 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.208906 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.773885 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.714409 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.714174 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.208906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52616.983968 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52615.204271 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52615.482532 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52518.967540 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52518.967540 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52538.247582 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52538.247582 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.714174 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52519.099531 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52519.099531 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.012658 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.012658 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52602.994429 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52602.994429 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.012658 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52533.694072 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52537.320967 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.012658 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52533.694072 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52537.320967 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,105 +543,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83909 # number of writebacks -system.cpu.l2cache.writebacks::total 83909 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3992 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21540 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 25532 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 86115 # number of writebacks +system.cpu.l2cache.writebacks::total 86115 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1102 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1102 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3992 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3950 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3950 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21540 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21540 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3950 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 127812 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 127770 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3950 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 161778000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 873989500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1035767500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4142346500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4142346500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161778000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5016336000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5178114000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161778000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5016336000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5178114000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 127770 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4348853500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4348853500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168471500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168471500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917668500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917668500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168471500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266522000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5434993500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168471500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266522000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5434993500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.208906 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406676 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.714174 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40525.551102 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40575.185701 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40567.425192 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.714174 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42519.099531 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42519.099531 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.012658 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.012658 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42602.994429 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42602.994429 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 214308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 49439 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473302 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 526908 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18444224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 19654336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 94651 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 446349 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.212056 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.408765 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 307145 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 351698 78.79% 78.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 94651 21.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 446349 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 304042000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 25532 # Transaction distribution -system.membus.trans_dist::ReadResp 25532 # Transaction distribution -system.membus.trans_dist::Writeback 83909 # Transaction distribution +system.membus.trans_dist::ReadResp 25490 # Transaction distribution +system.membus.trans_dist::Writeback 86115 # Transaction distribution +system.membus.trans_dist::CleanEvict 6526 # Transaction distribution system.membus.trans_dist::ReadExReq 102280 # Transaction distribution system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 25490 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348181 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 348181 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13688640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13688640 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214640 # Request fanout histogram +system.membus.snoop_fanout::samples 220592 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214640 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 220592 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214640 # Request fanout histogram -system.membus.reqLayer0.occupancy 566253984 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 220592 # Request fanout histogram +system.membus.reqLayer0.occupancy 568748288 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 642220500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 641607492 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |