diff options
Diffstat (limited to 'tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt | 1370 |
1 files changed, 685 insertions, 685 deletions
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index b70e9a80a..00105c43e 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,689 +1,689 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.128204 # Number of seconds simulated -sim_ticks 128204299500 # Number of ticks simulated -final_tick 128204299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 442445 # Simulator instruction rate (inst/s) -host_op_rate 564877 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 806030069 # Simulator tick rate (ticks/s) -host_mem_usage 262052 # Number of bytes of host memory used -host_seconds 159.06 # Real time elapsed on the host -sim_insts 70373651 # Number of instructions simulated -sim_ops 89847385 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 233344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7939200 # Number of bytes read from this memory -system.physmem.bytes_read::total 8172544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 233344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 233344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5534528 # Number of bytes written to this memory -system.physmem.bytes_written::total 5534528 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124050 # Number of read requests responded to by this memory -system.physmem.num_reads::total 127696 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86477 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86477 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1820095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 61926160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 63746255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1820095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1820095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43169597 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43169597 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43169597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1820095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 61926160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106915853 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 256408599 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70373651 # Number of instructions committed -system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528528 # number of integer instructions -system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141328435 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written -system.cpu.num_fp_register_reads 36 # number of times the floating registers were read -system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written -system.cpu.num_mem_refs 43422001 # number of memory refs -system.cpu.num_load_insts 22866262 # Number of load instructions -system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 256408598.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741468 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::MemRead 22866242 25.21% 77.33% # Class of executed instruction -system.cpu.op_class::MemWrite 20555707 22.67% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 20 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690106 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4075.864194 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42601590 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.263266 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1116590500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4075.864194 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995084 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995084 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 774 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22743326 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22743326 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83557 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83557 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42486195 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42486195 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42569752 # number of overall hits -system.cpu.dcache.overall_hits::total 42569752 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 36741 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 36741 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40187 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40187 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 143773 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 143773 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 183960 # number of overall misses -system.cpu.dcache.overall_misses::total 183960 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 594992500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 594992500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6509368500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6509368500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7104361000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7104361000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7104361000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7104361000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001613 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001613 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324759 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324759 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003373 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003373 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004303 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004303 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16194.238045 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16194.238045 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60817.031355 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60817.031355 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49413.735541 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49413.735541 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38619.053055 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38619.053055 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 127926 # number of writebacks -system.cpu.dcache.writebacks::total 127926 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7633 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7633 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7633 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7633 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7633 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7633 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 504199000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 504199000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6402336500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6402336500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1220892000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1220892000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6906535500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6906535500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8127427500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8127427500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17321.664147 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17321.664147 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59817.031355 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59817.031355 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51173.275212 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51173.275212 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50731.126047 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50731.126047 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50797.056838 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50797.056838 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1732.169683 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1732.169683 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.845786 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.845786 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits -system.cpu.icache.overall_hits::total 78126184 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses -system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 429951000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 429951000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 429951000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 429951000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 429951000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 429951000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.105141 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22739.105141 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.105141 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22739.105141 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.105141 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22739.105141 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16890 # number of writebacks -system.cpu.icache.writebacks::total 16890 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 411043000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 411043000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 411043000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 411043000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 411043000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 411043000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.105141 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.105141 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 96062 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31698.825375 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 219067 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 128830 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.700435 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 20554489000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 380.240484 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373230 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.211662 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011604 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.031780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.923987 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.967371 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 798 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 14304 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 16713 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 800 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2912846 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2912846 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 127926 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 127926 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4712 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15262 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 15262 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31236 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 31236 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 15262 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 35948 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 51210 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 15262 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 35948 # number of overall hits -system.cpu.l2cache.overall_hits::total 51210 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 102320 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102320 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3646 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3646 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21730 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21730 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3646 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 124050 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 127696 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3646 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 124050 # number of overall misses -system.cpu.l2cache.overall_misses::total 127696 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6192310500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6192310500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 221047500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 221047500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1315278500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1315278500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 221047500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7507589000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7728636500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 221047500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7507589000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7728636500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 127926 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 127926 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 15790 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 18908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 52966 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955976 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955976 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192828 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192828 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.410263 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.410263 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192828 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775322 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.713760 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192828 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775322 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.713760 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60519.062744 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60519.062744 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60627.399890 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60627.399890 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60528.232858 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60528.232858 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60627.399890 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60520.669085 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60523.716483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60627.399890 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60520.669085 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60523.716483 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 86477 # number of writebacks -system.cpu.l2cache.writebacks::total 86477 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102320 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102320 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3646 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3646 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21730 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21730 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3646 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124050 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 127696 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3646 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124050 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 127696 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5169110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5169110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184587500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184587500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1097978500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1097978500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184587500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6267089000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6451676500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184587500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6267089000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6451676500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955976 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955976 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192828 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.410263 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.410263 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775322 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.713760 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775322 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.713760 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50519.062744 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50519.062744 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50627.399890 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50627.399890 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50528.232858 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50528.232858 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50627.399890 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50627.399890 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3224 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214403 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 37561 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18427136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 20718208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 96062 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5534528 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 274968 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025367 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.157929 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 268023 97.47% 97.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6915 2.51% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 274968 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 320665000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 220672 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 93041 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 25376 # Transaction distribution -system.membus.trans_dist::WritebackDirty 86477 # Transaction distribution -system.membus.trans_dist::CleanEvict 6466 # Transaction distribution -system.membus.trans_dist::ReadExReq 102320 # Transaction distribution -system.membus.trans_dist::ReadExResp 102320 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 25376 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348335 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 348335 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13707072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13707072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 127704 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 127704 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 127704 # Request fanout histogram -system.membus.reqLayer0.occupancy 569386372 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 638480000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +sim_seconds 0.128204 +sim_ticks 128204299500 +final_tick 128204299500 +sim_freq 1000000000000 +host_inst_rate 533817 +host_op_rate 681535 +host_tick_rate 972489774 +host_mem_usage 290320 +host_seconds 131.83 +sim_insts 70373651 +sim_ops 89847385 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.physmem.bytes_read::cpu.inst 233344 +system.physmem.bytes_read::cpu.data 7939200 +system.physmem.bytes_read::total 8172544 +system.physmem.bytes_inst_read::cpu.inst 233344 +system.physmem.bytes_inst_read::total 233344 +system.physmem.bytes_written::writebacks 5534528 +system.physmem.bytes_written::total 5534528 +system.physmem.num_reads::cpu.inst 3646 +system.physmem.num_reads::cpu.data 124050 +system.physmem.num_reads::total 127696 +system.physmem.num_writes::writebacks 86477 +system.physmem.num_writes::total 86477 +system.physmem.bw_read::cpu.inst 1820095 +system.physmem.bw_read::cpu.data 61926160 +system.physmem.bw_read::total 63746255 +system.physmem.bw_inst_read::cpu.inst 1820095 +system.physmem.bw_inst_read::total 1820095 +system.physmem.bw_write::writebacks 43169597 +system.physmem.bw_write::total 43169597 +system.physmem.bw_total::writebacks 43169597 +system.physmem.bw_total::cpu.inst 1820095 +system.physmem.bw_total::cpu.data 61926160 +system.physmem.bw_total::total 106915853 +system.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 1946 +system.cpu.pwrStateResidencyTicks::ON 128204299500 +system.cpu.numCycles 256408599 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 70373651 +system.cpu.committedOps 89847385 +system.cpu.num_int_alu_accesses 81528528 +system.cpu.num_fp_alu_accesses 56 +system.cpu.num_func_calls 3311620 +system.cpu.num_conditional_control_insts 9253630 +system.cpu.num_int_insts 81528528 +system.cpu.num_fp_insts 56 +system.cpu.num_int_register_reads 141328435 +system.cpu.num_int_register_writes 53916335 +system.cpu.num_fp_register_reads 36 +system.cpu.num_fp_register_writes 20 +system.cpu.num_cc_register_reads 334802072 +system.cpu.num_cc_register_writes 36877111 +system.cpu.num_mem_refs 43422001 +system.cpu.num_load_insts 22866262 +system.cpu.num_store_insts 20555739 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 256408599 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 13741468 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 47187979 52.03% 52.03% +system.cpu.op_class::IntMult 80119 0.09% 52.12% +system.cpu.op_class::IntDiv 0 0.00% 52.12% +system.cpu.op_class::FloatAdd 0 0.00% 52.12% +system.cpu.op_class::FloatCmp 0 0.00% 52.12% +system.cpu.op_class::FloatCvt 0 0.00% 52.12% +system.cpu.op_class::FloatMult 0 0.00% 52.12% +system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% +system.cpu.op_class::FloatDiv 0 0.00% 52.12% +system.cpu.op_class::FloatMisc 0 0.00% 52.12% +system.cpu.op_class::FloatSqrt 0 0.00% 52.12% +system.cpu.op_class::SimdAdd 0 0.00% 52.12% +system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% +system.cpu.op_class::SimdAlu 0 0.00% 52.12% +system.cpu.op_class::SimdCmp 0 0.00% 52.12% +system.cpu.op_class::SimdCvt 0 0.00% 52.12% +system.cpu.op_class::SimdMisc 0 0.00% 52.12% +system.cpu.op_class::SimdMult 0 0.00% 52.12% +system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% +system.cpu.op_class::SimdShift 0 0.00% 52.12% +system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% +system.cpu.op_class::SimdSqrt 0 0.00% 52.12% +system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% +system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% +system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% +system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% +system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% +system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% +system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% +system.cpu.op_class::MemRead 22866242 25.21% 77.33% +system.cpu.op_class::MemWrite 20555707 22.67% 100.00% +system.cpu.op_class::FloatMemRead 20 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 90690106 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu.dcache.tags.replacements 155902 +system.cpu.dcache.tags.tagsinuse 4075.864194 +system.cpu.dcache.tags.total_refs 42601590 +system.cpu.dcache.tags.sampled_refs 159998 +system.cpu.dcache.tags.avg_refs 266.263266 +system.cpu.dcache.tags.warmup_cycle 1116590500 +system.cpu.dcache.tags.occ_blocks::cpu.data 4075.864194 +system.cpu.dcache.tags.occ_percent::cpu.data 0.995084 +system.cpu.dcache.tags.occ_percent::total 0.995084 +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 774 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 85731098 +system.cpu.dcache.tags.data_accesses 85731098 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu.dcache.ReadReq_hits::cpu.data 22743326 +system.cpu.dcache.ReadReq_hits::total 22743326 +system.cpu.dcache.WriteReq_hits::cpu.data 19742869 +system.cpu.dcache.WriteReq_hits::total 19742869 +system.cpu.dcache.SoftPFReq_hits::cpu.data 83557 +system.cpu.dcache.SoftPFReq_hits::total 83557 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 +system.cpu.dcache.LoadLockedReq_hits::total 15919 +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 +system.cpu.dcache.StoreCondReq_hits::total 15919 +system.cpu.dcache.demand_hits::cpu.data 42486195 +system.cpu.dcache.demand_hits::total 42486195 +system.cpu.dcache.overall_hits::cpu.data 42569752 +system.cpu.dcache.overall_hits::total 42569752 +system.cpu.dcache.ReadReq_misses::cpu.data 36741 +system.cpu.dcache.ReadReq_misses::total 36741 +system.cpu.dcache.WriteReq_misses::cpu.data 107032 +system.cpu.dcache.WriteReq_misses::total 107032 +system.cpu.dcache.SoftPFReq_misses::cpu.data 40187 +system.cpu.dcache.SoftPFReq_misses::total 40187 +system.cpu.dcache.demand_misses::cpu.data 143773 +system.cpu.dcache.demand_misses::total 143773 +system.cpu.dcache.overall_misses::cpu.data 183960 +system.cpu.dcache.overall_misses::total 183960 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 594992500 +system.cpu.dcache.ReadReq_miss_latency::total 594992500 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6509368500 +system.cpu.dcache.WriteReq_miss_latency::total 6509368500 +system.cpu.dcache.demand_miss_latency::cpu.data 7104361000 +system.cpu.dcache.demand_miss_latency::total 7104361000 +system.cpu.dcache.overall_miss_latency::cpu.data 7104361000 +system.cpu.dcache.overall_miss_latency::total 7104361000 +system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 +system.cpu.dcache.ReadReq_accesses::total 22780067 +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 +system.cpu.dcache.WriteReq_accesses::total 19849901 +system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 +system.cpu.dcache.SoftPFReq_accesses::total 123744 +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 +system.cpu.dcache.LoadLockedReq_accesses::total 15919 +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 +system.cpu.dcache.StoreCondReq_accesses::total 15919 +system.cpu.dcache.demand_accesses::cpu.data 42629968 +system.cpu.dcache.demand_accesses::total 42629968 +system.cpu.dcache.overall_accesses::cpu.data 42753712 +system.cpu.dcache.overall_accesses::total 42753712 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001613 +system.cpu.dcache.ReadReq_miss_rate::total 0.001613 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 +system.cpu.dcache.WriteReq_miss_rate::total 0.005392 +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324759 +system.cpu.dcache.SoftPFReq_miss_rate::total 0.324759 +system.cpu.dcache.demand_miss_rate::cpu.data 0.003373 +system.cpu.dcache.demand_miss_rate::total 0.003373 +system.cpu.dcache.overall_miss_rate::cpu.data 0.004303 +system.cpu.dcache.overall_miss_rate::total 0.004303 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16194.238045 +system.cpu.dcache.ReadReq_avg_miss_latency::total 16194.238045 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60817.031355 +system.cpu.dcache.WriteReq_avg_miss_latency::total 60817.031355 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49413.735541 +system.cpu.dcache.demand_avg_miss_latency::total 49413.735541 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38619.053055 +system.cpu.dcache.overall_avg_miss_latency::total 38619.053055 +system.cpu.dcache.blocked_cycles::no_mshrs 0 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 0 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.writebacks::writebacks 127926 +system.cpu.dcache.writebacks::total 127926 +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7633 +system.cpu.dcache.ReadReq_mshr_hits::total 7633 +system.cpu.dcache.demand_mshr_hits::cpu.data 7633 +system.cpu.dcache.demand_mshr_hits::total 7633 +system.cpu.dcache.overall_mshr_hits::cpu.data 7633 +system.cpu.dcache.overall_mshr_hits::total 7633 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 +system.cpu.dcache.ReadReq_mshr_misses::total 29108 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 +system.cpu.dcache.WriteReq_mshr_misses::total 107032 +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 +system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 +system.cpu.dcache.demand_mshr_misses::cpu.data 136140 +system.cpu.dcache.demand_mshr_misses::total 136140 +system.cpu.dcache.overall_mshr_misses::cpu.data 159998 +system.cpu.dcache.overall_mshr_misses::total 159998 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 504199000 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 504199000 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6402336500 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6402336500 +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1220892000 +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1220892000 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6906535500 +system.cpu.dcache.demand_mshr_miss_latency::total 6906535500 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8127427500 +system.cpu.dcache.overall_mshr_miss_latency::total 8127427500 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 +system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 +system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17321.664147 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17321.664147 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59817.031355 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59817.031355 +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51173.275212 +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51173.275212 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50731.126047 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50731.126047 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50797.056838 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50797.056838 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu.icache.tags.replacements 16890 +system.cpu.icache.tags.tagsinuse 1732.169683 +system.cpu.icache.tags.total_refs 78126184 +system.cpu.icache.tags.sampled_refs 18908 +system.cpu.icache.tags.avg_refs 4131.911572 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 1732.169683 +system.cpu.icache.tags.occ_percent::cpu.inst 0.845786 +system.cpu.icache.tags.occ_percent::total 0.845786 +system.cpu.icache.tags.occ_task_id_blocks::1024 2018 +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 +system.cpu.icache.tags.age_task_id_blocks_1024::1 22 +system.cpu.icache.tags.age_task_id_blocks_1024::3 294 +system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 +system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 +system.cpu.icache.tags.tag_accesses 156309092 +system.cpu.icache.tags.data_accesses 156309092 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu.icache.ReadReq_hits::cpu.inst 78126184 +system.cpu.icache.ReadReq_hits::total 78126184 +system.cpu.icache.demand_hits::cpu.inst 78126184 +system.cpu.icache.demand_hits::total 78126184 +system.cpu.icache.overall_hits::cpu.inst 78126184 +system.cpu.icache.overall_hits::total 78126184 +system.cpu.icache.ReadReq_misses::cpu.inst 18908 +system.cpu.icache.ReadReq_misses::total 18908 +system.cpu.icache.demand_misses::cpu.inst 18908 +system.cpu.icache.demand_misses::total 18908 +system.cpu.icache.overall_misses::cpu.inst 18908 +system.cpu.icache.overall_misses::total 18908 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 429951000 +system.cpu.icache.ReadReq_miss_latency::total 429951000 +system.cpu.icache.demand_miss_latency::cpu.inst 429951000 +system.cpu.icache.demand_miss_latency::total 429951000 +system.cpu.icache.overall_miss_latency::cpu.inst 429951000 +system.cpu.icache.overall_miss_latency::total 429951000 +system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 +system.cpu.icache.ReadReq_accesses::total 78145092 +system.cpu.icache.demand_accesses::cpu.inst 78145092 +system.cpu.icache.demand_accesses::total 78145092 +system.cpu.icache.overall_accesses::cpu.inst 78145092 +system.cpu.icache.overall_accesses::total 78145092 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 +system.cpu.icache.ReadReq_miss_rate::total 0.000242 +system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 +system.cpu.icache.demand_miss_rate::total 0.000242 +system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 +system.cpu.icache.overall_miss_rate::total 0.000242 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.105141 +system.cpu.icache.ReadReq_avg_miss_latency::total 22739.105141 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.105141 +system.cpu.icache.demand_avg_miss_latency::total 22739.105141 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.105141 +system.cpu.icache.overall_avg_miss_latency::total 22739.105141 +system.cpu.icache.blocked_cycles::no_mshrs 0 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 0 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs nan +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 16890 +system.cpu.icache.writebacks::total 16890 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 +system.cpu.icache.ReadReq_mshr_misses::total 18908 +system.cpu.icache.demand_mshr_misses::cpu.inst 18908 +system.cpu.icache.demand_mshr_misses::total 18908 +system.cpu.icache.overall_mshr_misses::cpu.inst 18908 +system.cpu.icache.overall_mshr_misses::total 18908 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 411043000 +system.cpu.icache.ReadReq_mshr_miss_latency::total 411043000 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 411043000 +system.cpu.icache.demand_mshr_miss_latency::total 411043000 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 411043000 +system.cpu.icache.overall_mshr_miss_latency::total 411043000 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 +system.cpu.icache.demand_mshr_miss_rate::total 0.000242 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 +system.cpu.icache.overall_mshr_miss_rate::total 0.000242 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.105141 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.105141 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.105141 +system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.105141 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.105141 +system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.105141 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu.l2cache.tags.replacements 96062 +system.cpu.l2cache.tags.tagsinuse 31698.825375 +system.cpu.l2cache.tags.total_refs 219067 +system.cpu.l2cache.tags.sampled_refs 128830 +system.cpu.l2cache.tags.avg_refs 1.700435 +system.cpu.l2cache.tags.warmup_cycle 20554489000 +system.cpu.l2cache.tags.occ_blocks::writebacks 380.240484 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373230 +system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.211662 +system.cpu.l2cache.tags.occ_percent::writebacks 0.011604 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.031780 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.923987 +system.cpu.l2cache.tags.occ_percent::total 0.967371 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 798 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 14304 +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 16713 +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 800 +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 +system.cpu.l2cache.tags.tag_accesses 2912846 +system.cpu.l2cache.tags.data_accesses 2912846 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu.l2cache.WritebackDirty_hits::writebacks 127926 +system.cpu.l2cache.WritebackDirty_hits::total 127926 +system.cpu.l2cache.WritebackClean_hits::writebacks 15790 +system.cpu.l2cache.WritebackClean_hits::total 15790 +system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 +system.cpu.l2cache.ReadExReq_hits::total 4712 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15262 +system.cpu.l2cache.ReadCleanReq_hits::total 15262 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31236 +system.cpu.l2cache.ReadSharedReq_hits::total 31236 +system.cpu.l2cache.demand_hits::cpu.inst 15262 +system.cpu.l2cache.demand_hits::cpu.data 35948 +system.cpu.l2cache.demand_hits::total 51210 +system.cpu.l2cache.overall_hits::cpu.inst 15262 +system.cpu.l2cache.overall_hits::cpu.data 35948 +system.cpu.l2cache.overall_hits::total 51210 +system.cpu.l2cache.ReadExReq_misses::cpu.data 102320 +system.cpu.l2cache.ReadExReq_misses::total 102320 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3646 +system.cpu.l2cache.ReadCleanReq_misses::total 3646 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21730 +system.cpu.l2cache.ReadSharedReq_misses::total 21730 +system.cpu.l2cache.demand_misses::cpu.inst 3646 +system.cpu.l2cache.demand_misses::cpu.data 124050 +system.cpu.l2cache.demand_misses::total 127696 +system.cpu.l2cache.overall_misses::cpu.inst 3646 +system.cpu.l2cache.overall_misses::cpu.data 124050 +system.cpu.l2cache.overall_misses::total 127696 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6192310500 +system.cpu.l2cache.ReadExReq_miss_latency::total 6192310500 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 221047500 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 221047500 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1315278500 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1315278500 +system.cpu.l2cache.demand_miss_latency::cpu.inst 221047500 +system.cpu.l2cache.demand_miss_latency::cpu.data 7507589000 +system.cpu.l2cache.demand_miss_latency::total 7728636500 +system.cpu.l2cache.overall_miss_latency::cpu.inst 221047500 +system.cpu.l2cache.overall_miss_latency::cpu.data 7507589000 +system.cpu.l2cache.overall_miss_latency::total 7728636500 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 127926 +system.cpu.l2cache.WritebackDirty_accesses::total 127926 +system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 +system.cpu.l2cache.WritebackClean_accesses::total 15790 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 +system.cpu.l2cache.ReadExReq_accesses::total 107032 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 +system.cpu.l2cache.ReadCleanReq_accesses::total 18908 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 +system.cpu.l2cache.ReadSharedReq_accesses::total 52966 +system.cpu.l2cache.demand_accesses::cpu.inst 18908 +system.cpu.l2cache.demand_accesses::cpu.data 159998 +system.cpu.l2cache.demand_accesses::total 178906 +system.cpu.l2cache.overall_accesses::cpu.inst 18908 +system.cpu.l2cache.overall_accesses::cpu.data 159998 +system.cpu.l2cache.overall_accesses::total 178906 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955976 +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955976 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192828 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192828 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.410263 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.410263 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192828 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775322 +system.cpu.l2cache.demand_miss_rate::total 0.713760 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192828 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775322 +system.cpu.l2cache.overall_miss_rate::total 0.713760 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60519.062744 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60519.062744 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60627.399890 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60627.399890 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60528.232858 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60528.232858 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60627.399890 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60520.669085 +system.cpu.l2cache.demand_avg_miss_latency::total 60523.716483 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60627.399890 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60520.669085 +system.cpu.l2cache.overall_avg_miss_latency::total 60523.716483 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.writebacks::writebacks 86477 +system.cpu.l2cache.writebacks::total 86477 +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 +system.cpu.l2cache.CleanEvict_mshr_misses::total 105 +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102320 +system.cpu.l2cache.ReadExReq_mshr_misses::total 102320 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3646 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3646 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21730 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21730 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3646 +system.cpu.l2cache.demand_mshr_misses::cpu.data 124050 +system.cpu.l2cache.demand_mshr_misses::total 127696 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3646 +system.cpu.l2cache.overall_mshr_misses::cpu.data 124050 +system.cpu.l2cache.overall_mshr_misses::total 127696 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5169110500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5169110500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184587500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184587500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1097978500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1097978500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184587500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6267089000 +system.cpu.l2cache.demand_mshr_miss_latency::total 6451676500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184587500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6267089000 +system.cpu.l2cache.overall_mshr_miss_latency::total 6451676500 +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955976 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955976 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192828 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192828 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.410263 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.410263 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192828 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775322 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.713760 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192828 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775322 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.713760 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50519.062744 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50519.062744 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50627.399890 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50627.399890 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50528.232858 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50528.232858 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50627.399890 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50520.669085 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50523.716483 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50627.399890 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50520.669085 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50523.716483 +system.cpu.toL2Bus.snoop_filter.tot_requests 351698 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 +system.cpu.toL2Bus.snoop_filter.tot_snoops 3224 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3194 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu.toL2Bus.trans_dist::ReadResp 71874 +system.cpu.toL2Bus.trans_dist::WritebackDirty 214403 +system.cpu.toL2Bus.trans_dist::WritebackClean 16890 +system.cpu.toL2Bus.trans_dist::CleanEvict 37561 +system.cpu.toL2Bus.trans_dist::ReadExReq 107032 +system.cpu.toL2Bus.trans_dist::ReadExResp 107032 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 +system.cpu.toL2Bus.pkt_count::total 530604 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18427136 +system.cpu.toL2Bus.pkt_size::total 20718208 +system.cpu.toL2Bus.snoops 96062 +system.cpu.toL2Bus.snoopTraffic 5534528 +system.cpu.toL2Bus.snoop_fanout::samples 274968 +system.cpu.toL2Bus.snoop_fanout::mean 0.025367 +system.cpu.toL2Bus.snoop_fanout::stdev 0.157929 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 268023 97.47% 97.47% +system.cpu.toL2Bus.snoop_fanout::1 6915 2.51% 99.99% +system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 274968 +system.cpu.toL2Bus.reqLayer0.occupancy 320665000 +system.cpu.toL2Bus.reqLayer0.utilization 0.3 +system.cpu.toL2Bus.respLayer0.occupancy 28362000 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 239997000 +system.cpu.toL2Bus.respLayer1.utilization 0.2 +system.membus.snoop_filter.tot_requests 220672 +system.membus.snoop_filter.hit_single_requests 93041 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.membus.trans_dist::ReadResp 25376 +system.membus.trans_dist::WritebackDirty 86477 +system.membus.trans_dist::CleanEvict 6466 +system.membus.trans_dist::ReadExReq 102320 +system.membus.trans_dist::ReadExResp 102320 +system.membus.trans_dist::ReadSharedReq 25376 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348335 +system.membus.pkt_count::total 348335 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13707072 +system.membus.pkt_size::total 13707072 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 127704 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 127704 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 127704 +system.membus.reqLayer0.occupancy 569386372 +system.membus.reqLayer0.utilization 0.4 +system.membus.respLayer1.occupancy 638480000 +system.membus.respLayer1.utilization 0.5 ---------- End Simulation Statistics ---------- |