diff options
Diffstat (limited to 'tests/quick/se/50.vortex/ref/arm')
3 files changed, 80 insertions, 65 deletions
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini index e7e819a35..6aaddcbd1 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -96,14 +96,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +117,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +130,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +195,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +216,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +229,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,7 +257,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -325,14 +329,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +350,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +363,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -411,7 +417,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false @@ -442,6 +448,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +460,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +468,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +483,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +491,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout index 34991f400..c41441e64 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-ti gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:22 -gem5 executing on e108600-lin, pid 23076 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-timing +gem5 compiled Nov 29 2016 19:03:48 +gem5 started Nov 29 2016 19:04:15 +gem5 executing on zizzer, pid 5745 +command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 128076834500 because target called exit() +Exiting @ tick 128204299500 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index ae3fac096..8b755992a 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.128202 # Number of seconds simulated -sim_ticks 128202163500 # Number of ticks simulated -final_tick 128202163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.128204 # Number of seconds simulated +sim_ticks 128204299500 # Number of ticks simulated +final_tick 128204299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1220543 # Simulator instruction rate (inst/s) -host_op_rate 1558290 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2223504943 # Simulator tick rate (ticks/s) -host_mem_usage 279580 # Number of bytes of host memory used -host_seconds 57.66 # Real time elapsed on the host +host_inst_rate 442445 # Simulator instruction rate (inst/s) +host_op_rate 564877 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 806030069 # Simulator tick rate (ticks/s) +host_mem_usage 262052 # Number of bytes of host memory used +host_seconds 159.06 # Real time elapsed on the host sim_insts 70373651 # Number of instructions simulated sim_ops 89847385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 233344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7939200 # Number of bytes read from this memory system.physmem.bytes_read::total 8172544 # Number of bytes read from this memory @@ -26,20 +26,20 @@ system.physmem.num_reads::cpu.data 124050 # Nu system.physmem.num_reads::total 127696 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86477 # Number of write requests responded to by this memory system.physmem.num_writes::total 86477 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1820125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 61927192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 63747317 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1820125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1820125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43170317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43170317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43170317 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1820125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 61927192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106917634 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 1820095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 61926160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 63746255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1820095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1820095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43169597 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43169597 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43169597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1820095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 61926160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106915853 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 128202163500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 256404327 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 128204299500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 256408599 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373651 # Number of instructions committed @@ -182,7 +182,7 @@ system.cpu.num_mem_refs 43422001 # nu system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 256404326.998000 # Number of busy cycles +system.cpu.num_busy_cycles 256408598.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 13741468 # Number of branches fetched @@ -225,14 +225,14 @@ system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690106 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4075.863858 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4075.864194 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42601590 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 266.263266 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1116590500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4075.863858 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4075.864194 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995084 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995084 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -242,7 +242,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 22743326 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22743326 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits @@ -361,16 +361,16 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50731.126047 system.cpu.dcache.demand_avg_mshr_miss_latency::total 50731.126047 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50797.056838 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 50797.056838 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1732.172375 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1732.169683 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1732.172375 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.845787 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.845787 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1732.169683 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.845786 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.845786 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id @@ -379,7 +379,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits @@ -448,16 +448,16 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.105141 system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 96062 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31698.820174 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31698.825375 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 219067 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 128830 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.700435 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 20553705000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 380.243921 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373654 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.202598 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 20554489000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 380.240484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373230 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.211662 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011604 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.031780 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.923987 # Average percentage of cache occupancy @@ -471,7 +471,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 800 system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2912846 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2912846 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 127926 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 127926 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits @@ -618,7 +618,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 system.cpu.toL2Bus.snoop_filter.tot_snoops 3224 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214403 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution @@ -658,7 +658,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 25376 # Transaction distribution system.membus.trans_dist::WritebackDirty 86477 # Transaction distribution system.membus.trans_dist::CleanEvict 6466 # Transaction distribution |