diff options
Diffstat (limited to 'tests/quick/se/50.vortex/ref/sparc/linux')
-rw-r--r-- | tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt | 124 | ||||
-rw-r--r-- | tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt | 535 |
2 files changed, 659 insertions, 0 deletions
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index e69de29bb..75464de1f 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,124 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.068149 # Number of seconds simulated +sim_ticks 68148677000 # Number of ticks simulated +final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1339454 # Simulator instruction rate (inst/s) +host_op_rate 1356797 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 679186650 # Simulator tick rate (ticks/s) +host_mem_usage 246572 # Number of bytes of host memory used +host_seconds 100.34 # Real time elapsed on the host +sim_insts 134398959 # Number of instructions simulated +sim_ops 136139187 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 538214320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory +system.physmem.bytes_read::total 685773680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 538214320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 538214320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory +system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 134553580 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory +system.physmem.num_reads::total 171784880 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory +system.physmem.num_other::total 15916 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7897648842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2165256414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10062905256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7897648842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7897648842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1318924357 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1318924357 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7897648842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3484180771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11381829614 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 136297355 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 134398959 # Number of instructions committed +system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses +system.cpu.num_func_calls 1709332 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls +system.cpu.num_int_insts 115187757 # number of integer instructions +system.cpu.num_fp_insts 2326976 # number of float instructions +system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read +system.cpu.num_int_register_writes 113147731 # number of times the integer registers were written +system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written +system.cpu.num_mem_refs 58160261 # number of memory refs +system.cpu.num_load_insts 37275864 # Number of load instructions +system.cpu.num_store_insts 20884397 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 136297354.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 12719094 # Number of branches fetched +system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction +system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction +system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 136293808 # Class of executed instruction +system.membus.trans_dist::ReadReq 171784880 # Transaction distribution +system.membus.trans_dist::ReadResp 171784880 # Transaction distribution +system.membus.trans_dist::WriteReq 20864304 # Transaction distribution +system.membus.trans_dist::WriteResp 20864304 # Transaction distribution +system.membus.trans_dist::SwapReq 15916 # Transaction distribution +system.membus.trans_dist::SwapResp 15916 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 385330200 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 775783958 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 192665100 # Request fanout histogram +system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram +system.membus.snoop_fanout::1 134553580 69.84% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 192665100 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index e69de29bb..18f2ca2b3 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,535 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.203116 # Number of seconds simulated +sim_ticks 203115946500 # Number of ticks simulated +final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 790551 # Simulator instruction rate (inst/s) +host_op_rate 800787 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1194752753 # Simulator tick rate (ticks/s) +host_mem_usage 255284 # Number of bytes of host memory used +host_seconds 170.01 # Real time elapsed on the host +sim_insts 134398959 # Number of instructions simulated +sim_ops 136139187 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory +system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory +system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122318 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130522 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory +system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2585006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38541297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41126303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 406231893 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 134398959 # Number of instructions committed +system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses +system.cpu.num_func_calls 1709332 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls +system.cpu.num_int_insts 115187757 # number of integer instructions +system.cpu.num_fp_insts 2326976 # number of float instructions +system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read +system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written +system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written +system.cpu.num_mem_refs 58160261 # number of memory refs +system.cpu.num_load_insts 37275864 # Number of load instructions +system.cpu.num_store_insts 20884397 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 406231892.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 12719094 # Number of branches fetched +system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction +system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction +system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 136293808 # Class of executed instruction +system.cpu.dcache.tags.replacements 146583 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits +system.cpu.dcache.overall_hits::total 57944940 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses +system.cpu.dcache.overall_misses::total 150664 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623315500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1623315500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6329554000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7952869500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7952869500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7952869500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7952869500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35677.263736 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35677.263736 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.459587 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.459587 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52785.466336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59508.630729 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59508.630729 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 85270 # number of writebacks +system.cpu.l2cache.writebacks::total 85270 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21054 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21054 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8204 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 130522 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8204 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 122318 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130522 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 406421500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 406421500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042294000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042294000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055544000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6461965500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055544000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6461965500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962778 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962778 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462725 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462725 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.386499 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.386499 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.734871 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.734871 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 41378816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 99022 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 436725 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 433112 99.17% 99.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 29258 # Transaction distribution +system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution +system.membus.trans_dist::CleanEvict 10301 # Transaction distribution +system.membus.trans_dist::ReadExReq 101264 # Transaction distribution +system.membus.trans_dist::ReadExResp 101264 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13810688 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 226093 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 226093 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 226093 # Request fanout histogram +system.membus.reqLayer0.occupancy 568574500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 652610000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |