diff options
Diffstat (limited to 'tests/quick/se/50.vortex/ref')
6 files changed, 0 insertions, 2262 deletions
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 381569cba..e69de29bb 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,152 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.044221 # Number of seconds simulated -sim_ticks 44221003000 # Number of ticks simulated -final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1271644 # Simulator instruction rate (inst/s) -host_op_rate 1271643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 636550745 # Simulator tick rate (ticks/s) -host_mem_usage 229384 # Number of bytes of host memory used -host_seconds 69.47 # Real time elapsed on the host -sim_insts 88340673 # Number of instructions simulated -sim_ops 88340673 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory -system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory -system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory -system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory -system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.data_hits 34890015 # DTB hits -system.cpu.dtb.data_misses 97400 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 34987415 # DTB accesses -system.cpu.itb.fetch_hits 88438073 # ITB hits -system.cpu.itb.fetch_misses 3934 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 88442007 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 88442007 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88340673 # Number of instructions committed -system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses -system.cpu.num_func_calls 3321606 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls -system.cpu.num_int_insts 78039444 # number of integer instructions -system.cpu.num_fp_insts 267757 # number of float instructions -system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read -system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written -system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read -system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written -system.cpu.num_mem_refs 34987415 # number of memory refs -system.cpu.num_load_insts 20366786 # Number of load instructions -system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 88442007 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 13754477 # Number of branches fetched -system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction -system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction -system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 88438073 # Class of executed instruction -system.membus.trans_dist::ReadReq 108714711 # Transaction distribution -system.membus.trans_dist::ReadResp 108714711 # Transaction distribution -system.membus.trans_dist::WriteReq 14613377 # Transaction distribution -system.membus.trans_dist::WriteResp 14613377 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 123328088 # Request fanout histogram -system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram -system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 123328088 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index e76d0cce6..e69de29bb 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,546 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.134742 # Number of seconds simulated -sim_ticks 134741611500 # Number of ticks simulated -final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1303886 # Simulator instruction rate (inst/s) -host_op_rate 1303885 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1988750581 # Simulator tick rate (ticks/s) -host_mem_usage 260188 # Number of bytes of host memory used -host_seconds 67.75 # Real time elapsed on the host -sim_insts 88340673 # Number of instructions simulated -sim_ops 88340673 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 367360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10138112 # Number of bytes read from this memory -system.physmem.bytes_read::total 10505472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 367360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 367360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7320448 # Number of bytes written to this memory -system.physmem.bytes_written::total 7320448 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5740 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158408 # Number of read requests responded to by this memory -system.physmem.num_reads::total 164148 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114382 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114382 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2726403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75241137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 77967540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2726403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2726403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54329527 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54329527 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54329527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2726403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75241137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 132297067 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.data_hits 34890015 # DTB hits -system.cpu.dtb.data_misses 97400 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 34987415 # DTB accesses -system.cpu.itb.fetch_hits 88438074 # ITB hits -system.cpu.itb.fetch_misses 3934 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 88442008 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 269483223 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88340673 # Number of instructions committed -system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses -system.cpu.num_func_calls 3321606 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls -system.cpu.num_int_insts 78039444 # number of integer instructions -system.cpu.num_fp_insts 267757 # number of float instructions -system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read -system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written -system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read -system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written -system.cpu.num_mem_refs 34987415 # number of memory refs -system.cpu.num_load_insts 20366786 # Number of load instructions -system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 269483223 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 13754477 # Number of branches fetched -system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction -system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction -system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 88438073 # Class of executed instruction -system.cpu.dcache.tags.replacements 200248 # number of replacements -system.cpu.dcache.tags.tagsinuse 4078.397630 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 983457500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4078.397630 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995703 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995703 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3595 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits -system.cpu.dcache.overall_hits::total 34685671 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses -system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2138978000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2138978000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8279807000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8279807000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10418785000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10418785000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10418785000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10418785000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 122 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4751004 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4751004 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 168278 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168278 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 74391 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 74391 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12696 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12696 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 70696 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 70696 # 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miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.584614 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.075096 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775203 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.584614 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.485170 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.485170 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59558.536585 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59558.536585 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59507.011553 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59507.011553 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59503.609547 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59503.609547 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 114382 # number of writebacks -system.cpu.l2cache.writebacks::total 114382 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130882 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130882 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 5740 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 5740 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27526 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27526 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5740 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158408 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 164148 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5740 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158408 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 164148 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6478722500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6478722500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284466000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284466000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1362730000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1362730000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284466000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7841452500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8125918500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284466000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7841452500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8125918500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911574 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911574 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075096 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452984 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452984 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.584614 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.584614 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.485170 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.485170 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49558.536585 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49558.536585 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49507.011553 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49507.011553 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3875 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3875 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 282660 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 49586 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 60766 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 227263 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9652928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23847808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33500736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 131998 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 412778 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009388 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.096434 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 408903 99.06% 99.06% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3875 0.94% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 412778 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 520378500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 33266 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114382 # Transaction distribution -system.membus.trans_dist::CleanEvict 13845 # Transaction distribution -system.membus.trans_dist::ReadExReq 130882 # Transaction distribution -system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33266 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 456523 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 456523 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17825920 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 292375 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 292375 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 292375 # Request fanout histogram -system.membus.reqLayer0.occupancy 750324500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 820740000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index bcdad61b2..e69de29bb 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,243 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.048960 # Number of seconds simulated -sim_ticks 48960022500 # Number of ticks simulated -final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 991674 # Simulator instruction rate (inst/s) -host_op_rate 1268214 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 684673258 # Simulator tick rate (ticks/s) -host_mem_usage 242788 # Number of bytes of host memory used -host_seconds 71.51 # Real time elapsed on the host -sim_insts 70913204 # Number of instructions simulated -sim_ops 90688159 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 312580364 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory -system.physmem.bytes_read::total 419153709 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 312580364 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 312580364 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory -system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 78145091 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory -system.physmem.num_reads::total 101064821 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory -system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6384399925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2176742157 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8561142083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6384399925 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6384399925 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1606621218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1606621218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6384399925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3783363376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10167763301 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 97920046 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70913204 # Number of instructions committed -system.cpu.committedOps 90688159 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528528 # number of integer instructions -system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141479386 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written -system.cpu.num_fp_register_reads 36 # number of times the floating registers were read -system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 266608097 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written -system.cpu.num_mem_refs 43422001 # number of memory refs -system.cpu.num_load_insts 22866262 # Number of load instructions -system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 97920045.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741468 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction -system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690106 # Class of executed instruction -system.membus.trans_dist::ReadReq 100925158 # Transaction distribution -system.membus.trans_dist::ReadResp 100941077 # Transaction distribution -system.membus.trans_dist::WriteReq 19849901 # Transaction distribution -system.membus.trans_dist::WriteResp 19849901 # Transaction distribution -system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution -system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 241861282 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 497813920 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 120930641 # Request fanout histogram -system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::1 78145091 64.62% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 120930641 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 2518d4d22..e69de29bb 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,662 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.128077 # Number of seconds simulated -sim_ticks 128076834500 # Number of ticks simulated -final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 775777 # Simulator instruction rate (inst/s) -host_op_rate 990450 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1411878896 # Simulator tick rate (ticks/s) -host_mem_usage 277764 # Number of bytes of host memory used -host_seconds 90.71 # Real time elapsed on the host -sim_insts 70373651 # Number of instructions simulated -sim_ops 89847385 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory -system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory -system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123832 # Number of read requests responded to by this memory -system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1820407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 61878856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 63699263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 256153669 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70373651 # Number of instructions committed -system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528528 # number of integer instructions -system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141328550 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written -system.cpu.num_fp_register_reads 36 # number of times the floating registers were read -system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written -system.cpu.num_mem_refs 43422001 # number of memory refs -system.cpu.num_load_insts 22866262 # Number of load instructions -system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 256153668.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741468 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction -system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690106 # Class of executed instruction -system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83609 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83609 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42486230 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42486230 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42569839 # number of overall hits -system.cpu.dcache.overall_hits::total 42569839 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 36706 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 36706 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40135 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40135 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 143738 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 143738 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 183873 # number of overall misses -system.cpu.dcache.overall_misses::total 183873 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 577584000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 577584000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6405138000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6405138000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6982722000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6982722000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6982722000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6982722000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001611 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001611 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324339 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324339 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003372 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003372 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004301 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004301 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15735.411104 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15735.411104 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59843.205770 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59843.205770 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48579.512725 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48579.512725 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37975.787636 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37975.787636 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 128175 # number of writebacks -system.cpu.dcache.writebacks::total 128175 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7598 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7598 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7598 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7598 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7598 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7598 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 495022500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 495022500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6298106000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6298106000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1201109000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1201109000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793128500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6793128500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7994237500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7994237500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17006.407173 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17006.407173 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency -system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits -system.cpu.icache.overall_hits::total 78126184 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses -system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 426200500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 426200500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 426200500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 426200500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22540.749947 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22540.749947 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22540.749947 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22540.749947 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16890 # number of writebacks -system.cpu.icache.writebacks::total 16890 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 407292500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 407292500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 407292500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 407292500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 407292500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 407292500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 95333 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.027343 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.847125 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.033211 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.045472 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.925808 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1225 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13921 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15196 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 624 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949768 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3017503 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3017503 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 128175 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15265 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 15265 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31415 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 31415 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 15265 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 36166 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 51431 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 15265 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 36166 # number of overall hits -system.cpu.l2cache.overall_hits::total 51431 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 102281 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3643 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3643 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21551 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21551 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3643 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 123832 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 127475 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3643 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 123832 # number of overall misses -system.cpu.l2cache.overall_misses::total 127475 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6087670500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6087670500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217265500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 217265500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1284434000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1284434000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 217265500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7372104500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7589370000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 217265500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7372104500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7589370000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 128175 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 128175 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 15790 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 18908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 52966 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955611 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955611 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192670 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192670 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.406884 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.406884 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192670 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.773960 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.712525 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192670 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.773960 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.712525 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59519.074901 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59519.074901 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59639.171013 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59639.171013 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59599.740151 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59599.740151 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59536.144342 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59536.144342 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 86150 # number of writebacks -system.cpu.l2cache.writebacks::total 86150 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3643 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3643 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21551 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21551 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3643 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123832 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 127475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3643 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123832 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 127475 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5064860500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5064860500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 180835500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 180835500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1068924000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1068924000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180835500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6133784500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6314620000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180835500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6133784500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6314620000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192670 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406884 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406884 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.712525 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.712525 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49519.074901 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49519.074901 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49639.171013 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49639.171013 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49599.740151 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49599.740151 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18443072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 20734144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 95333 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 274239 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025051 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.156979 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 267399 97.51% 97.51% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6810 2.48% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 274239 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 320914000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 25194 # Transaction distribution -system.membus.trans_dist::WritebackDirty 86150 # Transaction distribution -system.membus.trans_dist::CleanEvict 6168 # Transaction distribution -system.membus.trans_dist::ReadExReq 102281 # Transaction distribution -system.membus.trans_dist::ReadExResp 102281 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 25194 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 347268 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 347268 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13672000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13672000 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 219817 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 219817 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 219817 # Request fanout histogram -system.membus.reqLayer0.occupancy 568080092 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 637375000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 3ed030f96..e69de29bb 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,124 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.068149 # Number of seconds simulated -sim_ticks 68148677000 # Number of ticks simulated -final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1843276 # Simulator instruction rate (inst/s) -host_op_rate 1867142 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 934655607 # Simulator tick rate (ticks/s) -host_mem_usage 225200 # Number of bytes of host memory used -host_seconds 72.91 # Real time elapsed on the host -sim_insts 134398959 # Number of instructions simulated -sim_ops 136139187 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 538214320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory -system.physmem.bytes_read::total 685773680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 538214320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 538214320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory -system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 134553580 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171784880 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory -system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory -system.physmem.num_other::total 15916 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7897648842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2165256414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10062905256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7897648842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7897648842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1318924357 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1318924357 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7897648842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3484180771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11381829614 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 136297355 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398959 # Number of instructions committed -system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses -system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187757 # number of integer instructions -system.cpu.num_fp_insts 2326976 # number of float instructions -system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147731 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160261 # number of memory refs -system.cpu.num_load_insts 37275864 # Number of load instructions -system.cpu.num_store_insts 20884397 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 136297354.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719094 # Number of branches fetched -system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction -system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293808 # Class of executed instruction -system.membus.trans_dist::ReadReq 171784880 # Transaction distribution -system.membus.trans_dist::ReadResp 171784880 # Transaction distribution -system.membus.trans_dist::WriteReq 20864304 # Transaction distribution -system.membus.trans_dist::WriteResp 20864304 # Transaction distribution -system.membus.trans_dist::SwapReq 15916 # Transaction distribution -system.membus.trans_dist::SwapResp 15916 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 385330200 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 775783958 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 192665100 # Request fanout histogram -system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram -system.membus.snoop_fanout::1 134553580 69.84% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 192665100 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 97bc2f274..e69de29bb 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,535 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.203116 # Number of seconds simulated -sim_ticks 203115946500 # Number of ticks simulated -final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1277402 # Simulator instruction rate (inst/s) -host_op_rate 1293942 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1930526358 # Simulator tick rate (ticks/s) -host_mem_usage 259920 # Number of bytes of host memory used -host_seconds 105.21 # Real time elapsed on the host -sim_insts 134398959 # Number of instructions simulated -sim_ops 136139187 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory -system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory -system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122318 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130522 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory -system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2585006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38541297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41126303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 406231893 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398959 # Number of instructions committed -system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses -system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187757 # number of integer instructions -system.cpu.num_fp_insts 2326976 # number of float instructions -system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160261 # number of memory refs -system.cpu.num_load_insts 37275864 # Number of load instructions -system.cpu.num_store_insts 20884397 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 406231892.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719094 # Number of branches fetched -system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction -system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293808 # Class of executed instruction -system.cpu.dcache.tags.replacements 146583 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits -system.cpu.dcache.overall_hits::total 57944940 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses -system.cpu.dcache.overall_misses::total 150664 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623315500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1623315500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6329554000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7952869500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7952869500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7952869500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7952869500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35677.263736 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35677.263736 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.459587 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.459587 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52785.466336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks -system.cpu.dcache.writebacks::total 123865 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577815500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577815500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 426000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 426000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802205500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7802205500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802205500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7802205500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency -system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.978604 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # 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number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses -system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2835239000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2835239000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2835239000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2835239000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2835239000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2835239000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 134553581 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15159.760245 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15159.760245 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 184976 # number of writebacks -system.cpu.icache.writebacks::total 184976 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2648215000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2648215000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2648215000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2648215000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2648215000 # 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average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 99022 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1304.666895 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.802282 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.099178 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.039815 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.941275 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31043 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5588812 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5588812 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3915 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3915 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178820 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 178820 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24446 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 24446 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 178820 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 28361 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 207181 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 178820 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 28361 # number of overall hits -system.cpu.l2cache.overall_hits::total 207181 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 101264 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101264 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8204 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 8204 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21054 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21054 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 122318 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 130522 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 8204 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 122318 # number of overall misses -system.cpu.l2cache.overall_misses::total 130522 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6025890000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6025890000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 488461500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 488461500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1252834000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1252834000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 488461500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7278724000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7767185500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 488461500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7278724000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7767185500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 123865 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 123865 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 184923 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45500 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 45500 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 150679 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 337703 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962778 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.962778 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043866 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043866 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462725 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462725 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043866 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.811779 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.386499 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043866 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.811779 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.386499 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.734871 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.734871 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59539.431984 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59539.431984 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747126 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747126 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59508.630729 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59508.630729 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 85270 # number of writebacks -system.cpu.l2cache.writebacks::total 85270 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21054 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21054 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8204 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122318 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 130522 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8204 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122318 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 130522 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 406421500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 406421500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042294000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042294000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055544000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6461965500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055544000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6461965500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962778 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962778 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462725 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462725 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.386499 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.386499 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.734871 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.734871 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 41378816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 99022 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 436725 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 433112 99.17% 99.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 29258 # Transaction distribution -system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution -system.membus.trans_dist::CleanEvict 10301 # Transaction distribution -system.membus.trans_dist::ReadExReq 101264 # Transaction distribution -system.membus.trans_dist::ReadExResp 101264 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13810688 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 226093 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 226093 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 226093 # Request fanout histogram -system.membus.reqLayer0.occupancy 568574500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 652610000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |