diff options
Diffstat (limited to 'tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory')
| -rw-r--r-- | tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats | 482 | ||||
| -rw-r--r-- | tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt | 116 |
2 files changed, 125 insertions, 473 deletions
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats index bcd995136..a927269a7 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats @@ -1,4 +1,4 @@ -Real time: Feb/02/2013 08:14:08 +Real time: Jun/08/2013 14:12:22 Profiler Stats -------------- @@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.56 -Virtual_time_in_minutes: 0.00933333 -Virtual_time_in_hours: 0.000155556 -Virtual_time_in_days: 6.48148e-06 +Virtual_time_in_seconds: 0.55 +Virtual_time_in_minutes: 0.00916667 +Virtual_time_in_hours: 0.000152778 +Virtual_time_in_days: 6.36574e-06 Ruby_current_time: 318321 Ruby_start_time: 0 Ruby_cycles: 318321 -mbytes_resident: 49.3398 -mbytes_total: 265.707 -resident_ratio: 0.185751 - -ruby_cycles_executed: [ 318322 ] +mbytes_resident: 51.1211 +mbytes_total: 139.629 +resident_ratio: 0.366177 Busy Controller Counts: L1Cache-0:0 @@ -61,7 +59,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -82,11 +79,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10276 -page_faults: 11 +page_reclaims: 9776 +page_faults: 0 swaps: 0 -block_inputs: 16 -block_outputs: 248 +block_inputs: 8 +block_outputs: 80 Network Stats ------------- @@ -160,458 +157,3 @@ links_utilized_percent_switch_3: 2.05746 outgoing_messages_switch_3_link_2_Response_Data: 786 56592 [ 0 786 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Response_Control: 84 672 [ 0 84 0 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [44 ] 44 -Ifetch [67 ] 67 -Store [898 ] 898 -Inv [563 ] 563 -L1_Replacement [10398 ] 10398 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_GET_INSTR [0 ] 0 -Data [0 ] 0 -Data_Exclusive [41 ] 41 -DataS_fromL1 [0 ] 0 -Data_all_Acks [874 ] 874 -Ack [0 ] 0 -Ack_all [1 ] 1 -WB_Ack [755 ] 755 -PF_Load [0 ] 0 -PF_Ifetch [0 ] 0 -PF_Store [0 ] 0 - - - Transitions - -NP Load [42 ] 42 -NP Ifetch [56 ] 56 -NP Store [818 ] 818 -NP Inv [1 ] 1 -NP L1_Replacement [0 ] 0 -NP PF_Load [0 ] 0 -NP PF_Ifetch [0 ] 0 -NP PF_Store [0 ] 0 - -I Load [0 ] 0 -I Ifetch [0 ] 0 -I Store [0 ] 0 -I Inv [0 ] 0 -I L1_Replacement [145 ] 145 -I PF_Load [0 ] 0 -I PF_Ifetch [0 ] 0 -I PF_Store [0 ] 0 - -S Load [0 ] 0 -S Ifetch [0 ] 0 -S Store [1 ] 1 -S Inv [31 ] 31 -S L1_Replacement [11 ] 11 -S PF_Load [0 ] 0 -S PF_Store [0 ] 0 - -E Load [0 ] 0 -E Ifetch [0 ] 0 -E Store [2 ] 2 -E Inv [4 ] 4 -E L1_Replacement [34 ] 34 -E Fwd_GETX [0 ] 0 -E Fwd_GETS [0 ] 0 -E Fwd_GET_INSTR [0 ] 0 -E PF_Load [0 ] 0 -E PF_Store [0 ] 0 - -M Load [2 ] 2 -M Ifetch [0 ] 0 -M Store [77 ] 77 -M Inv [97 ] 97 -M L1_Replacement [722 ] 722 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_GET_INSTR [0 ] 0 -M PF_Load [0 ] 0 -M PF_Store [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS Inv [14 ] 14 -IS L1_Replacement [374 ] 374 -IS Data_Exclusive [41 ] 41 -IS DataS_fromL1 [0 ] 0 -IS Data_all_Acks [43 ] 43 -IS PF_Load [0 ] 0 -IS PF_Store [0 ] 0 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM Inv [0 ] 0 -IM L1_Replacement [9112 ] 9112 -IM Data [0 ] 0 -IM Data_all_Acks [817 ] 817 -IM Ack [0 ] 0 -IM PF_Load [0 ] 0 -IM PF_Store [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM Inv [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Ack [0 ] 0 -SM Ack_all [1 ] 1 -SM PF_Load [0 ] 0 -SM PF_Store [0 ] 0 - -IS_I Load [0 ] 0 -IS_I Ifetch [0 ] 0 -IS_I Store [0 ] 0 -IS_I Inv [0 ] 0 -IS_I L1_Replacement [0 ] 0 -IS_I Data_Exclusive [0 ] 0 -IS_I DataS_fromL1 [0 ] 0 -IS_I Data_all_Acks [14 ] 14 -IS_I PF_Load [0 ] 0 -IS_I PF_Store [0 ] 0 - -M_I Load [0 ] 0 -M_I Ifetch [10 ] 10 -M_I Store [0 ] 0 -M_I Inv [416 ] 416 -M_I L1_Replacement [0 ] 0 -M_I Fwd_GETX [0 ] 0 -M_I Fwd_GETS [0 ] 0 -M_I Fwd_GET_INSTR [0 ] 0 -M_I WB_Ack [340 ] 340 -M_I PF_Load [0 ] 0 -M_I PF_Store [0 ] 0 - -SINK_WB_ACK Load [0 ] 0 -SINK_WB_ACK Ifetch [1 ] 1 -SINK_WB_ACK Store [0 ] 0 -SINK_WB_ACK Inv [0 ] 0 -SINK_WB_ACK L1_Replacement [0 ] 0 -SINK_WB_ACK WB_Ack [415 ] 415 -SINK_WB_ACK PF_Load [0 ] 0 -SINK_WB_ACK PF_Store [0 ] 0 - -PF_IS Load [0 ] 0 -PF_IS Ifetch [0 ] 0 -PF_IS Store [0 ] 0 -PF_IS Inv [0 ] 0 -PF_IS L1_Replacement [0 ] 0 -PF_IS Data_Exclusive [0 ] 0 -PF_IS DataS_fromL1 [0 ] 0 -PF_IS Data_all_Acks [0 ] 0 -PF_IS PF_Load [0 ] 0 -PF_IS PF_Store [0 ] 0 - -PF_IM Load [0 ] 0 -PF_IM Ifetch [0 ] 0 -PF_IM Store [0 ] 0 -PF_IM Inv [0 ] 0 -PF_IM L1_Replacement [0 ] 0 -PF_IM Data [0 ] 0 -PF_IM Data_all_Acks [0 ] 0 -PF_IM Ack [0 ] 0 -PF_IM PF_Load [0 ] 0 -PF_IM PF_Store [0 ] 0 - -PF_SM Load [0 ] 0 -PF_SM Ifetch [0 ] 0 -PF_SM Store [0 ] 0 -PF_SM Inv [0 ] 0 -PF_SM L1_Replacement [0 ] 0 -PF_SM Ack [0 ] 0 -PF_SM Ack_all [0 ] 0 - -PF_IS_I Load [0 ] 0 -PF_IS_I Store [0 ] 0 -PF_IS_I Inv [0 ] 0 -PF_IS_I L1_Replacement [0 ] 0 -PF_IS_I Data_Exclusive [0 ] 0 -PF_IS_I DataS_fromL1 [0 ] 0 -PF_IS_I Data_all_Acks [0 ] 0 - - --- L2Cache --- - - Event Counts - -L1_GET_INSTR [56 ] 56 -L1_GETS [42 ] 42 -L1_GETX [818 ] 818 -L1_UPGRADE [1 ] 1 -L1_PUTX [345 ] 345 -L1_PUTX_old [796 ] 796 -Fwd_L1_GETX [0 ] 0 -Fwd_L1_GETS [0 ] 0 -Fwd_L1_GET_INSTR [0 ] 0 -L2_Replacement [291 ] 291 -L2_Replacement_clean [1216 ] 1216 -Mem_Data [873 ] 873 -Mem_Ack [869 ] 869 -WB_Data [495 ] 495 -WB_Data_clean [18 ] 18 -Ack [0 ] 0 -Ack_all [50 ] 50 -Unblock [0 ] 0 -Unblock_Cancel [0 ] 0 -Exclusive_Unblock [858 ] 858 -MEM_Inv [0 ] 0 - - - Transitions - -NP L1_GET_INSTR [46 ] 46 -NP L1_GETS [41 ] 41 -NP L1_GETX [787 ] 787 -NP L1_PUTX [0 ] 0 -NP L1_PUTX_old [302 ] 302 - -SS L1_GET_INSTR [0 ] 0 -SS L1_GETS [1 ] 1 -SS L1_GETX [9 ] 9 -SS L1_UPGRADE [1 ] 1 -SS L1_PUTX [0 ] 0 -SS L1_PUTX_old [0 ] 0 -SS L2_Replacement [0 ] 0 -SS L2_Replacement_clean [46 ] 46 -SS MEM_Inv [0 ] 0 - -M L1_GET_INSTR [10 ] 10 -M L1_GETS [0 ] 0 -M L1_GETX [22 ] 22 -M L1_PUTX [0 ] 0 -M L1_PUTX_old [0 ] 0 -M L2_Replacement [291 ] 291 -M L2_Replacement_clean [16 ] 16 -M MEM_Inv [0 ] 0 - -MT L1_GET_INSTR [0 ] 0 -MT L1_GETS [0 ] 0 -MT L1_GETX [0 ] 0 -MT L1_PUTX [340 ] 340 -MT L1_PUTX_old [0 ] 0 -MT L2_Replacement [0 ] 0 -MT L2_Replacement_clean [517 ] 517 -MT MEM_Inv [0 ] 0 - -M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [0 ] 0 -M_I L1_GETX [0 ] 0 -M_I L1_UPGRADE [0 ] 0 -M_I L1_PUTX [0 ] 0 -M_I L1_PUTX_old [113 ] 113 -M_I Mem_Ack [869 ] 869 -M_I MEM_Inv [0 ] 0 - -MT_I L1_GET_INSTR [0 ] 0 -MT_I L1_GETS [0 ] 0 -MT_I L1_GETX [0 ] 0 -MT_I L1_UPGRADE [0 ] 0 -MT_I L1_PUTX [0 ] 0 -MT_I L1_PUTX_old [0 ] 0 -MT_I WB_Data [0 ] 0 -MT_I WB_Data_clean [0 ] 0 -MT_I Ack_all [0 ] 0 -MT_I MEM_Inv [0 ] 0 - -MCT_I L1_GET_INSTR [0 ] 0 -MCT_I L1_GETS [0 ] 0 -MCT_I L1_GETX [0 ] 0 -MCT_I L1_UPGRADE [0 ] 0 -MCT_I L1_PUTX [0 ] 0 -MCT_I L1_PUTX_old [210 ] 210 -MCT_I WB_Data [495 ] 495 -MCT_I WB_Data_clean [18 ] 18 -MCT_I Ack_all [4 ] 4 - -I_I L1_GET_INSTR [0 ] 0 -I_I L1_GETS [0 ] 0 -I_I L1_GETX [0 ] 0 -I_I L1_UPGRADE [0 ] 0 -I_I L1_PUTX [0 ] 0 -I_I L1_PUTX_old [0 ] 0 -I_I Ack [0 ] 0 -I_I Ack_all [46 ] 46 - -S_I L1_GET_INSTR [0 ] 0 -S_I L1_GETS [0 ] 0 -S_I L1_GETX [0 ] 0 -S_I L1_UPGRADE [0 ] 0 -S_I L1_PUTX [0 ] 0 -S_I L1_PUTX_old [0 ] 0 -S_I Ack [0 ] 0 -S_I Ack_all [0 ] 0 -S_I MEM_Inv [0 ] 0 - -ISS L1_GET_INSTR [0 ] 0 -ISS L1_GETS [0 ] 0 -ISS L1_GETX [0 ] 0 -ISS L1_PUTX [0 ] 0 -ISS L1_PUTX_old [0 ] 0 -ISS L2_Replacement [0 ] 0 -ISS L2_Replacement_clean [11 ] 11 -ISS Mem_Data [41 ] 41 -ISS MEM_Inv [0 ] 0 - -IS L1_GET_INSTR [0 ] 0 -IS L1_GETS [0 ] 0 -IS L1_GETX [0 ] 0 -IS L1_PUTX [0 ] 0 -IS L1_PUTX_old [0 ] 0 -IS L2_Replacement [0 ] 0 -IS L2_Replacement_clean [57 ] 57 -IS Mem_Data [46 ] 46 -IS MEM_Inv [0 ] 0 - -IM L1_GET_INSTR [0 ] 0 -IM L1_GETS [0 ] 0 -IM L1_GETX [0 ] 0 -IM L1_PUTX [0 ] 0 -IM L1_PUTX_old [0 ] 0 -IM L2_Replacement [0 ] 0 -IM L2_Replacement_clean [219 ] 219 -IM Mem_Data [786 ] 786 -IM MEM_Inv [0 ] 0 - -SS_MB L1_GET_INSTR [0 ] 0 -SS_MB L1_GETS [0 ] 0 -SS_MB L1_GETX [0 ] 0 -SS_MB L1_UPGRADE [0 ] 0 -SS_MB L1_PUTX [0 ] 0 -SS_MB L1_PUTX_old [0 ] 0 -SS_MB L2_Replacement [0 ] 0 -SS_MB L2_Replacement_clean [0 ] 0 -SS_MB Unblock_Cancel [0 ] 0 -SS_MB Exclusive_Unblock [10 ] 10 -SS_MB MEM_Inv [0 ] 0 - -MT_MB L1_GET_INSTR [0 ] 0 -MT_MB L1_GETS [0 ] 0 -MT_MB L1_GETX [0 ] 0 -MT_MB L1_UPGRADE [0 ] 0 -MT_MB L1_PUTX [5 ] 5 -MT_MB L1_PUTX_old [171 ] 171 -MT_MB L2_Replacement [0 ] 0 -MT_MB L2_Replacement_clean [350 ] 350 -MT_MB Unblock_Cancel [0 ] 0 -MT_MB Exclusive_Unblock [848 ] 848 -MT_MB MEM_Inv [0 ] 0 - -MT_IIB L1_GET_INSTR [0 ] 0 -MT_IIB L1_GETS [0 ] 0 -MT_IIB L1_GETX [0 ] 0 -MT_IIB L1_UPGRADE [0 ] 0 -MT_IIB L1_PUTX [0 ] 0 -MT_IIB L1_PUTX_old [0 ] 0 -MT_IIB L2_Replacement [0 ] 0 -MT_IIB L2_Replacement_clean [0 ] 0 -MT_IIB WB_Data [0 ] 0 -MT_IIB WB_Data_clean [0 ] 0 -MT_IIB Unblock [0 ] 0 -MT_IIB MEM_Inv [0 ] 0 - -MT_IB L1_GET_INSTR [0 ] 0 -MT_IB L1_GETS [0 ] 0 -MT_IB L1_GETX [0 ] 0 -MT_IB L1_UPGRADE [0 ] 0 -MT_IB L1_PUTX [0 ] 0 -MT_IB L1_PUTX_old [0 ] 0 -MT_IB L2_Replacement [0 ] 0 -MT_IB L2_Replacement_clean [0 ] 0 -MT_IB WB_Data [0 ] 0 -MT_IB WB_Data_clean [0 ] 0 -MT_IB Unblock_Cancel [0 ] 0 -MT_IB MEM_Inv [0 ] 0 - -MT_SB L1_GET_INSTR [0 ] 0 -MT_SB L1_GETS [0 ] 0 -MT_SB L1_GETX [0 ] 0 -MT_SB L1_UPGRADE [0 ] 0 -MT_SB L1_PUTX [0 ] 0 -MT_SB L1_PUTX_old [0 ] 0 -MT_SB L2_Replacement [0 ] 0 -MT_SB L2_Replacement_clean [0 ] 0 -MT_SB Unblock [0 ] 0 -MT_SB MEM_Inv [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 1660 - memory_reads: 874 - memory_writes: 786 - memory_refreshes: 2210 - memory_total_request_delays: 601 - memory_delays_per_request: 0.362048 - memory_delays_in_input_queue: 44 - memory_delays_behind_head_of_bank_queue: 2 - memory_delays_stalled_at_head_of_bank_queue: 555 - memory_stalls_for_bank_busy: 169 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 30 - memory_stalls_for_bus: 188 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 104 - memory_stalls_for_read_read_turnaround: 64 - accesses_per_bank: 42 51 50 73 73 71 65 49 54 41 50 44 58 48 47 63 57 47 58 57 41 49 46 49 57 45 42 49 45 53 48 38 - - --- Directory --- - - Event Counts - -Fetch [874 ] 874 -Data [786 ] 786 -Memory_Data [874 ] 874 -Memory_Ack [786 ] 786 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -CleanReplacement [84 ] 84 - - - Transitions - -I Fetch [874 ] 874 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -ID Fetch [0 ] 0 -ID Data [0 ] 0 -ID Memory_Data [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 - -ID_W Fetch [0 ] 0 -ID_W Data [0 ] 0 -ID_W Memory_Ack [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 - -M Data [786 ] 786 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 -M CleanReplacement [84 ] 84 - -IM Fetch [0 ] 0 -IM Data [0 ] 0 -IM Memory_Data [874 ] 874 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 - -MI Fetch [0 ] 0 -MI Data [0 ] 0 -MI Memory_Ack [786 ] 786 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 - -M_DRD Data [0 ] 0 -M_DRD DMA_READ [0 ] 0 -M_DRD DMA_WRITE [0 ] 0 - -M_DRDI Fetch [0 ] 0 -M_DRDI Data [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 -M_DRDI DMA_READ [0 ] 0 -M_DRDI DMA_WRITE [0 ] 0 - -M_DWR Data [0 ] 0 -M_DWR DMA_READ [0 ] 0 -M_DWR DMA_WRITE [0 ] 0 - -M_DWRI Fetch [0 ] 0 -M_DWRI Data [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 -M_DWRI DMA_READ [0 ] 0 -M_DWRI DMA_WRITE [0 ] 0 - diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt index 00381e46a..8eb1e41c8 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000318 # Nu sim_ticks 318321 # Number of ticks simulated final_tick 318321 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1383719 # Simulator tick rate (ticks/s) -host_mem_usage 149800 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_tick_rate 2084436 # Simulator tick rate (ticks/s) +host_mem_usage 142984 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host system.ruby.l2_cntrl0.L2cache.demand_hits 43 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 874 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 917 # Number of cache demand accesses @@ -25,5 +25,115 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.dir_cntrl0.memBuffer.memReq 1660 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 874 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 786 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 2210 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 555 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 44 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 601 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.362048 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 169 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 188 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 104 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 64 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 30 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 42 2.53% 2.53% | 51 3.07% 5.60% | 50 3.01% 8.61% | 73 4.40% 13.01% | 73 4.40% 17.41% | 71 4.28% 21.69% | 65 3.92% 25.60% | 49 2.95% 28.55% | 54 3.25% 31.81% | 41 2.47% 34.28% | 50 3.01% 37.29% | 44 2.65% 39.94% | 58 3.49% 43.43% | 48 2.89% 46.33% | 47 2.83% 49.16% | 63 3.80% 52.95% | 57 3.43% 56.39% | 47 2.83% 59.22% | 58 3.49% 62.71% | 57 3.43% 66.14% | 41 2.47% 68.61% | 49 2.95% 71.57% | 46 2.77% 74.34% | 49 2.95% 77.29% | 57 3.43% 80.72% | 45 2.71% 83.43% | 42 2.53% 85.96% | 49 2.95% 88.92% | 45 2.71% 91.63% | 53 3.19% 94.82% | 48 2.89% 97.71% | 38 2.29% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1660 # Number of accesses per bank + +system.ruby.l2_cntrl0.L1_GET_INSTR 56 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETS 42 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 818 0.00% 0.00% +system.ruby.l2_cntrl0.L1_UPGRADE 1 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX 345 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX_old 796 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 291 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement_clean 1216 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Data 873 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Ack 869 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data 495 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data_clean 18 0.00% 0.00% +system.ruby.l2_cntrl0.Ack_all 50 0.00% 0.00% +system.ruby.l2_cntrl0.Exclusive_Unblock 858 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GET_INSTR 46 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 41 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 787 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_PUTX_old 302 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GETS 1 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GETX 9 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_UPGRADE 1 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L2_Replacement_clean 46 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GET_INSTR 10 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 22 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 291 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement_clean 16 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_PUTX 340 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement_clean 517 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.L1_PUTX_old 113 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.Mem_Ack 869 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.L1_PUTX_old 210 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.WB_Data 495 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.WB_Data_clean 18 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.Ack_all 4 0.00% 0.00% +system.ruby.l2_cntrl0.I_I.Ack_all 46 0.00% 0.00% +system.ruby.l2_cntrl0.ISS.L2_Replacement_clean 11 0.00% 0.00% +system.ruby.l2_cntrl0.ISS.Mem_Data 41 0.00% 0.00% +system.ruby.l2_cntrl0.IS.L2_Replacement_clean 57 0.00% 0.00% +system.ruby.l2_cntrl0.IS.Mem_Data 46 0.00% 0.00% +system.ruby.l2_cntrl0.IM.L2_Replacement_clean 219 0.00% 0.00% +system.ruby.l2_cntrl0.IM.Mem_Data 786 0.00% 0.00% +system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 10 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.L1_PUTX 5 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.L1_PUTX_old 171 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.L2_Replacement_clean 350 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 848 0.00% 0.00% +system.ruby.l1_cntrl0.Load 44 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 67 0.00% 0.00% +system.ruby.l1_cntrl0.Store 898 0.00% 0.00% +system.ruby.l1_cntrl0.Inv 563 0.00% 0.00% +system.ruby.l1_cntrl0.L1_Replacement 10398 0.00% 0.00% +system.ruby.l1_cntrl0.Data_Exclusive 41 0.00% 0.00% +system.ruby.l1_cntrl0.Data_all_Acks 874 0.00% 0.00% +system.ruby.l1_cntrl0.Ack_all 1 0.00% 0.00% +system.ruby.l1_cntrl0.WB_Ack 755 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Load 42 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Ifetch 56 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Store 818 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Inv 1 0.00% 0.00% +system.ruby.l1_cntrl0.I.L1_Replacement 145 0.00% 0.00% +system.ruby.l1_cntrl0.S.Store 1 0.00% 0.00% +system.ruby.l1_cntrl0.S.Inv 31 0.00% 0.00% +system.ruby.l1_cntrl0.S.L1_Replacement 11 0.00% 0.00% +system.ruby.l1_cntrl0.E.Store 2 0.00% 0.00% +system.ruby.l1_cntrl0.E.Inv 4 0.00% 0.00% +system.ruby.l1_cntrl0.E.L1_Replacement 34 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 2 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 77 0.00% 0.00% +system.ruby.l1_cntrl0.M.Inv 97 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_Replacement 722 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Inv 14 0.00% 0.00% +system.ruby.l1_cntrl0.IS.L1_Replacement 374 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_Exclusive 41 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_all_Acks 43 0.00% 0.00% +system.ruby.l1_cntrl0.IM.L1_Replacement 9112 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data_all_Acks 817 0.00% 0.00% +system.ruby.l1_cntrl0.SM.Ack_all 1 0.00% 0.00% +system.ruby.l1_cntrl0.IS_I.Data_all_Acks 14 0.00% 0.00% +system.ruby.l1_cntrl0.M_I.Ifetch 10 0.00% 0.00% +system.ruby.l1_cntrl0.M_I.Inv 416 0.00% 0.00% +system.ruby.l1_cntrl0.M_I.WB_Ack 340 0.00% 0.00% +system.ruby.l1_cntrl0.SINK_WB_ACK.Ifetch 1 0.00% 0.00% +system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack 415 0.00% 0.00% +system.ruby.dir_cntrl0.Fetch 874 0.00% 0.00% +system.ruby.dir_cntrl0.Data 786 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 874 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 786 0.00% 0.00% +system.ruby.dir_cntrl0.CleanReplacement 84 0.00% 0.00% +system.ruby.dir_cntrl0.I.Fetch 874 0.00% 0.00% +system.ruby.dir_cntrl0.M.Data 786 0.00% 0.00% +system.ruby.dir_cntrl0.M.CleanReplacement 84 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 874 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 786 0.00% 0.00% ---------- End Simulation Statistics ---------- |