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-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini7
-rwxr-xr-xtests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout12
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt900
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini7
-rwxr-xr-xtests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout12
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt873
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini7
-rwxr-xr-xtests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout12
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt957
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini7
-rwxr-xr-xtests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout12
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt925
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini7
-rwxr-xr-xtests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout12
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt626
15 files changed, 2181 insertions, 2195 deletions
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
index fcbaa0b2a..49022a9e3 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
@@ -55,8 +55,7 @@ eventq_index=0
num_cpus=1
system=system
wakeup_frequency=10
-cpuDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1]
+cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.dvfs_handler]
type=DVFSHandler
@@ -371,6 +370,7 @@ eventq_index=0
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
@@ -378,7 +378,7 @@ system=system
using_network_tester=false
using_ruby_tester=true
version=0
-slave=system.cpu.cpuDataPort[0] system.cpu.cpuInstPort[0]
+slave=system.cpu.cpuInstDataPort[0]
[system.ruby.l1_cntrl0.unblockFromL1Cache]
type=MessageBuffer
@@ -1113,6 +1113,7 @@ randomization=false
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
index 8708a45b4..4a72c4f44 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
@@ -1,13 +1,11 @@
-Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
-Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:41:13
-gem5 started Nov 15 2015 14:41:38
-gem5 executing on ribera.cs.wisc.edu, pid 32148
-command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level
+gem5 compiled Dec 11 2015 20:05:44
+gem5 started Dec 11 2015 20:06:16
+gem5 executing on zizzer, pid 37019
+command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 41751 because Ruby Tester completed
+Exiting @ tick 43191 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
index 8246454e6..7165361fa 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
@@ -1,44 +1,44 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000042 # Number of seconds simulated
-sim_ticks 41751 # Number of ticks simulated
-final_tick 41751 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000043 # Number of seconds simulated
+sim_ticks 43191 # Number of ticks simulated
+final_tick 43191 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 456955 # Simulator tick rate (ticks/s)
-host_mem_usage 445744 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 266014 # Simulator tick rate (ticks/s)
+host_mem_usage 386184 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55552 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 55552 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49728 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 49728 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 868 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 868 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 777 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 777 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1330554957 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1330554957 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1191061292 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1191061292 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 2521616249 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 2521616249 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 868 # Number of read requests accepted
-system.mem_ctrls.writeReqs 777 # Number of write requests accepted
-system.mem_ctrls.readBursts 868 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 777 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 45760 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 9792 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 40448 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 55552 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 49728 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 123 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 57728 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 57728 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 51904 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 51904 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 902 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 902 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 811 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 811 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 1336574749 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 1336574749 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 1201731842 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 1201731842 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 2538306592 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 2538306592 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 902 # Number of read requests accepted
+system.mem_ctrls.writeReqs 811 # Number of write requests accepted
+system.mem_ctrls.readBursts 902 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 811 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 47168 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 10560 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 41728 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 57728 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 51904 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 165 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 130 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 232 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 213 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 219 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 51 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 230 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 227 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 48 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
@@ -51,10 +51,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 196 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 191 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 198 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 47 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 201 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 202 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 203 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 46 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
@@ -69,23 +69,23 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 41665 # Total gap between requests
+system.mem_ctrls.totGap 43109 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 868 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 902 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 777 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 439 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 276 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 811 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 456 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 281 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
@@ -132,23 +132,23 @@ system.mem_ctrls.wrQLenPdf::12 1 # Wh
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 24 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 43 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22 42 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 42 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25 43 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 45 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
@@ -180,71 +180,76 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 89 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 943.460674 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 892.281841 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 207.277759 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 1 1.12% 1.12% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 1 1.12% 2.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 4 4.49% 6.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 3 3.37% 10.11% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 4 4.49% 14.61% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 6 6.74% 21.35% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 70 78.65% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 89 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 39 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 18.128205 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 17.885323 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 3.442608 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 4 10.26% 10.26% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 17 43.59% 53.85% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 12 30.77% 84.62% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 2 5.13% 89.74% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23 3 7.69% 97.44% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35 1 2.56% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 39 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 39 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.205128 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.194457 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.614709 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 35 89.74% 89.74% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 4 10.26% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 39 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 8953 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 22538 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3575 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 12.52 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 94 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 928 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 868.246553 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 227.729324 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 1 1.06% 1.06% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 2 2.13% 3.19% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 3 3.19% 6.38% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 1 1.06% 7.45% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 4 4.26% 11.70% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 3 3.19% 14.89% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 2 2.13% 17.02% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 3 3.19% 20.21% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 75 79.79% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 94 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 18.125000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 17.875881 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 3.480256 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 4 10.00% 10.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 17 42.50% 52.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 12 30.00% 82.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21 2 5.00% 87.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::22-23 3 7.50% 95.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-25 1 2.50% 97.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.300000 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.280005 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 0.853349 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 1 2.50% 90.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 1 2.50% 92.50% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 3 7.50% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 8956 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 22959 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 3685 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 12.15 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 31.52 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 1096.02 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 968.79 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1330.55 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1191.06 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 31.15 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 1092.08 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 966.13 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 1336.57 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 1201.73 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 16.13 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 8.56 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 7.57 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.65 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.68 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 630 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 624 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 88.11 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 95.41 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 25.33 # Average gap between requests
-system.mem_ctrls.pageHitRate 91.60 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 642600 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 357000 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls.busUtil 16.08 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 8.53 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 7.55 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 1.63 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 25.46 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 647 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 644 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 87.79 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 94.57 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 25.17 # Average gap between requests
+system.mem_ctrls.pageHitRate 91.04 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 665280 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 369600 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 8311680 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 6034176 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 6231168 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 26710200 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 26706780 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 87000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 44685456 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 1140.080520 # Core power per rank (mW)
+system.mem_ctrls_0.totalEnergy 44914308 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 1146.065527 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 19 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 37890 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 37885 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
@@ -263,48 +268,48 @@ system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 #
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 4 # delay histogram for all message
system.ruby.delayHist::max_bucket 39 # delay histogram for all message
-system.ruby.delayHist::samples 6487 # delay histogram for all message
-system.ruby.delayHist::mean 2.607369 # delay histogram for all message
-system.ruby.delayHist::stdev 5.331776 # delay histogram for all message
-system.ruby.delayHist | 4997 77.03% 77.03% | 72 1.11% 78.14% | 1050 16.19% 94.33% | 14 0.22% 94.54% | 300 4.62% 99.17% | 2 0.03% 99.20% | 2 0.03% 99.23% | 47 0.72% 99.95% | 0 0.00% 99.95% | 3 0.05% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 6487 # delay histogram for all message
+system.ruby.delayHist::samples 6720 # delay histogram for all message
+system.ruby.delayHist::mean 2.675000 # delay histogram for all message
+system.ruby.delayHist::stdev 5.399947 # delay histogram for all message
+system.ruby.delayHist | 5144 76.55% 76.55% | 51 0.76% 77.31% | 1138 16.93% 94.24% | 8 0.12% 94.36% | 323 4.81% 99.17% | 6 0.09% 99.26% | 0 0.00% 99.26% | 43 0.64% 99.90% | 0 0.00% 99.90% | 7 0.10% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 6720 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 988
-system.ruby.outstanding_req_hist::mean 15.694332
-system.ruby.outstanding_req_hist::gmean 15.587555
-system.ruby.outstanding_req_hist::stdev 1.214439
-system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 4 0.40% 1.11% | 2 0.20% 1.32% | 5 0.51% 1.82% | 157 15.89% 17.71% | 813 82.29% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 988
+system.ruby.outstanding_req_hist::samples 1041
+system.ruby.outstanding_req_hist::mean 15.700288
+system.ruby.outstanding_req_hist::gmean 15.598621
+system.ruby.outstanding_req_hist::stdev 1.186661
+system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.19% 0.29% | 2 0.19% 0.48% | 2 0.19% 0.67% | 4 0.38% 1.06% | 2 0.19% 1.25% | 5 0.48% 1.73% | 167 16.04% 17.77% | 856 82.23% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 1041
system.ruby.latency_hist::bucket_size 128
system.ruby.latency_hist::max_bucket 1279
-system.ruby.latency_hist::samples 973
-system.ruby.latency_hist::mean 670.474820
-system.ruby.latency_hist::gmean 404.512965
-system.ruby.latency_hist::stdev 282.511489
-system.ruby.latency_hist | 123 12.64% 12.64% | 25 2.57% 15.21% | 6 0.62% 15.83% | 4 0.41% 16.24% | 32 3.29% 19.53% | 325 33.40% 52.93% | 378 38.85% 91.78% | 43 4.42% 96.20% | 29 2.98% 99.18% | 8 0.82% 100.00%
-system.ruby.latency_hist::total 973
+system.ruby.latency_hist::samples 1025
+system.ruby.latency_hist::mean 658.597073
+system.ruby.latency_hist::gmean 361.484818
+system.ruby.latency_hist::stdev 297.350955
+system.ruby.latency_hist | 154 15.02% 15.02% | 24 2.34% 17.37% | 5 0.49% 17.85% | 4 0.39% 18.24% | 32 3.12% 21.37% | 302 29.46% 50.83% | 418 40.78% 91.61% | 49 4.78% 96.39% | 28 2.73% 99.12% | 9 0.88% 100.00%
+system.ruby.latency_hist::total 1025
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
-system.ruby.hit_latency_hist::samples 67
+system.ruby.hit_latency_hist::samples 89
system.ruby.hit_latency_hist::mean 1
system.ruby.hit_latency_hist::gmean 1
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 67 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 67
+system.ruby.hit_latency_hist | 0 0.00% 0.00% | 89 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist::total 89
system.ruby.miss_latency_hist::bucket_size 128
system.ruby.miss_latency_hist::max_bucket 1279
-system.ruby.miss_latency_hist::samples 906
-system.ruby.miss_latency_hist::mean 719.983444
-system.ruby.miss_latency_hist::gmean 630.548999
-system.ruby.miss_latency_hist::stdev 223.799725
-system.ruby.miss_latency_hist | 56 6.18% 6.18% | 25 2.76% 8.94% | 6 0.66% 9.60% | 4 0.44% 10.04% | 32 3.53% 13.58% | 325 35.87% 49.45% | 378 41.72% 91.17% | 43 4.75% 95.92% | 29 3.20% 99.12% | 8 0.88% 100.00%
-system.ruby.miss_latency_hist::total 906
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 66 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 852 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 918 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 56 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 57 # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples 936
+system.ruby.miss_latency_hist::mean 721.125000
+system.ruby.miss_latency_hist::gmean 632.888578
+system.ruby.miss_latency_hist::stdev 227.503250
+system.ruby.miss_latency_hist | 65 6.94% 6.94% | 24 2.56% 9.51% | 5 0.53% 10.04% | 4 0.43% 10.47% | 32 3.42% 13.89% | 302 32.26% 46.15% | 418 44.66% 90.81% | 49 5.24% 96.05% | 28 2.99% 99.04% | 9 0.96% 100.00%
+system.ruby.miss_latency_hist::total 936
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 89 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 875 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 964 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 64 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 64 # Number of cache demand accesses
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
@@ -314,342 +319,331 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 1 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 88 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store
-system.ruby.l2_cntrl0.L2cache.demand_hits 38 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 868 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 906 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 80 # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store
+system.ruby.l2_cntrl0.L2cache.demand_hits 34 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 904 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 938 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 11.787742
-system.ruby.network.routers0.msg_count.Control::0 908
-system.ruby.network.routers0.msg_count.Request_Control::2 264
-system.ruby.network.routers0.msg_count.Response_Data::1 906
-system.ruby.network.routers0.msg_count.Response_Control::1 831
-system.ruby.network.routers0.msg_count.Response_Control::2 850
-system.ruby.network.routers0.msg_count.Writeback_Data::0 745
-system.ruby.network.routers0.msg_count.Writeback_Data::1 215
-system.ruby.network.routers0.msg_count.Writeback_Control::0 39
-system.ruby.network.routers0.msg_bytes.Control::0 7264
-system.ruby.network.routers0.msg_bytes.Request_Control::2 2112
-system.ruby.network.routers0.msg_bytes.Response_Data::1 65232
-system.ruby.network.routers0.msg_bytes.Response_Control::1 6648
-system.ruby.network.routers0.msg_bytes.Response_Control::2 6800
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0 53640
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1 15480
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 312
-system.ruby.network.routers1.percent_links_utilized 21.738401
-system.ruby.network.routers1.msg_count.Control::0 1774
-system.ruby.network.routers1.msg_count.Request_Control::2 264
-system.ruby.network.routers1.msg_count.Response_Data::1 2551
-system.ruby.network.routers1.msg_count.Response_Control::1 1782
-system.ruby.network.routers1.msg_count.Response_Control::2 850
-system.ruby.network.routers1.msg_count.Writeback_Data::0 745
-system.ruby.network.routers1.msg_count.Writeback_Data::1 215
-system.ruby.network.routers1.msg_count.Writeback_Control::0 38
-system.ruby.network.routers1.msg_bytes.Control::0 14192
-system.ruby.network.routers1.msg_bytes.Request_Control::2 2112
-system.ruby.network.routers1.msg_bytes.Response_Data::1 183672
-system.ruby.network.routers1.msg_bytes.Response_Control::1 14256
-system.ruby.network.routers1.msg_bytes.Response_Control::2 6800
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-system.ruby.network.routers1.msg_bytes.Writeback_Data::1 15480
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 304
-system.ruby.network.routers2.percent_links_utilized 9.954253
-system.ruby.network.routers2.msg_count.Control::0 868
-system.ruby.network.routers2.msg_count.Response_Data::1 1645
-system.ruby.network.routers2.msg_count.Response_Control::1 951
-system.ruby.network.routers2.msg_bytes.Control::0 6944
-system.ruby.network.routers2.msg_bytes.Response_Data::1 118440
-system.ruby.network.routers2.msg_bytes.Response_Control::1 7608
-system.ruby.network.routers3.percent_links_utilized 14.493864
-system.ruby.network.routers3.msg_count.Control::0 1775
-system.ruby.network.routers3.msg_count.Request_Control::2 264
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-system.ruby.network.routers3.msg_count.Writeback_Control::0 38
-system.ruby.network.routers3.msg_bytes.Control::0 14200
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-system.ruby.network.routers3.msg_bytes.Writeback_Control::0 304
-system.ruby.network.msg_count.Control 5325
-system.ruby.network.msg_count.Request_Control 792
-system.ruby.network.msg_count.Response_Data 7653
-system.ruby.network.msg_count.Response_Control 7896
-system.ruby.network.msg_count.Writeback_Data 2880
-system.ruby.network.msg_count.Writeback_Control 115
-system.ruby.network.msg_byte.Control 42600
-system.ruby.network.msg_byte.Request_Control 6336
-system.ruby.network.msg_byte.Response_Data 551016
-system.ruby.network.msg_byte.Response_Control 63168
-system.ruby.network.msg_byte.Writeback_Data 207360
-system.ruby.network.msg_byte.Writeback_Control 920
-system.ruby.network.routers0.throttle0.link_utilization 11.017700
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 264
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 906
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-system.ruby.network.routers0.throttle1.link_utilization 12.557783
-system.ruby.network.routers0.throttle1.msg_count.Control::0 908
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-system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 850
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-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 39
-system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7264
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-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 312
-system.ruby.network.routers1.throttle0.link_utilization 22.940768
-system.ruby.network.routers1.throttle0.msg_count.Control::0 906
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 868
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 913
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 850
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-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 215
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 38
-system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7248
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 62496
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system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 696
system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0
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-system.ruby.delayVCHist.vnet_0 | 1391 54.79% 54.79% | 17 0.67% 55.45% | 768 30.25% 85.70% | 9 0.35% 86.06% | 300 11.82% 97.87% | 2 0.08% 97.95% | 2 0.08% 98.03% | 47 1.85% 99.88% | 0 0.00% 99.88% | 3 0.12% 100.00% # delay histogram for vnet_0
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-system.ruby.delayVCHist.vnet_1::stdev 2.345078 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 3317 90.04% 90.04% | 25 0.68% 90.72% | 16 0.43% 91.15% | 39 1.06% 92.21% | 232 6.30% 98.51% | 50 1.36% 99.86% | 5 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
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+system.ruby.delayVCHist.vnet_0 | 1406 53.66% 53.66% | 9 0.34% 54.01% | 823 31.41% 85.42% | 4 0.15% 85.57% | 323 12.33% 97.90% | 5 0.19% 98.09% | 0 0.00% 98.09% | 43 1.64% 99.73% | 0 0.00% 99.73% | 7 0.27% 100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total 2620 # delay histogram for vnet_0
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+system.ruby.delayVCHist.vnet_1::stdev 2.428600 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 3460 90.53% 90.53% | 42 1.10% 91.63% | 315 8.24% 99.87% | 4 0.10% 99.97% | 0 0.00% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
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system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 264 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean 0.015152 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 0.173746 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 262 99.24% 99.24% | 0 0.00% 99.24% | 2 0.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 264 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples 278 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2 | 278 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total 278 # delay histogram for vnet_2
system.ruby.LD.latency_hist::bucket_size 128
system.ruby.LD.latency_hist::max_bucket 1279
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-system.ruby.LD.latency_hist::gmean 498.811687
-system.ruby.LD.latency_hist::stdev 228.289227
-system.ruby.LD.latency_hist | 3 6.98% 6.98% | 0 0.00% 6.98% | 0 0.00% 6.98% | 0 0.00% 6.98% | 1 2.33% 9.30% | 15 34.88% 44.19% | 20 46.51% 90.70% | 1 2.33% 93.02% | 3 6.98% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist::total 43
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+system.ruby.LD.latency_hist::gmean 207.168110
+system.ruby.LD.latency_hist::stdev 333.448910
+system.ruby.LD.latency_hist | 8 21.62% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 13 35.14% 56.76% | 14 37.84% 94.59% | 2 5.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist::total 37
system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
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system.ruby.LD.hit_latency_hist::mean 1
system.ruby.LD.hit_latency_hist::gmean 1
-system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist::total 3
+system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist::total 7
system.ruby.LD.miss_latency_hist::bucket_size 128
system.ruby.LD.miss_latency_hist::max_bucket 1279
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-system.ruby.LD.miss_latency_hist::gmean 794.843938
-system.ruby.LD.miss_latency_hist::stdev 101.785594
-system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.50% 2.50% | 15 37.50% 40.00% | 20 50.00% 90.00% | 1 2.50% 92.50% | 3 7.50% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist::total 40
+system.ruby.LD.miss_latency_hist::samples 30
+system.ruby.LD.miss_latency_hist::mean 765.833333
+system.ruby.LD.miss_latency_hist::gmean 719.114834
+system.ruby.LD.miss_latency_hist::stdev 153.429099
+system.ruby.LD.miss_latency_hist | 1 3.33% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 13 43.33% 46.67% | 14 46.67% 93.33% | 2 6.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist::total 30
system.ruby.ST.latency_hist::bucket_size 128
system.ruby.ST.latency_hist::max_bucket 1279
-system.ruby.ST.latency_hist::samples 873
-system.ruby.ST.latency_hist::mean 703.712486
-system.ruby.ST.latency_hist::gmean 443.583948
-system.ruby.ST.latency_hist::stdev 252.870649
-system.ruby.ST.latency_hist | 83 9.51% 9.51% | 7 0.80% 10.31% | 4 0.46% 10.77% | 4 0.46% 11.23% | 31 3.55% 14.78% | 310 35.51% 50.29% | 358 41.01% 91.29% | 42 4.81% 96.11% | 26 2.98% 99.08% | 8 0.92% 100.00%
-system.ruby.ST.latency_hist::total 873
+system.ruby.ST.latency_hist::samples 925
+system.ruby.ST.latency_hist::mean 697.631351
+system.ruby.ST.latency_hist::gmean 404.802159
+system.ruby.ST.latency_hist::stdev 266.794551
+system.ruby.ST.latency_hist | 101 10.92% 10.92% | 7 0.76% 11.68% | 4 0.43% 12.11% | 4 0.43% 12.54% | 32 3.46% 16.00% | 289 31.24% 47.24% | 404 43.68% 90.92% | 47 5.08% 96.00% | 28 3.03% 99.03% | 9 0.97% 100.00%
+system.ruby.ST.latency_hist::total 925
system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
-system.ruby.ST.hit_latency_hist::samples 63
+system.ruby.ST.hit_latency_hist::samples 82
system.ruby.ST.hit_latency_hist::mean 1
system.ruby.ST.hit_latency_hist::gmean 1
-system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 63 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 63
+system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 82 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.hit_latency_hist::total 82
system.ruby.ST.miss_latency_hist::bucket_size 128
system.ruby.ST.miss_latency_hist::max_bucket 1279
-system.ruby.ST.miss_latency_hist::samples 810
-system.ruby.ST.miss_latency_hist::mean 758.367901
-system.ruby.ST.miss_latency_hist::gmean 712.609684
-system.ruby.ST.miss_latency_hist::stdev 165.763918
-system.ruby.ST.miss_latency_hist | 20 2.47% 2.47% | 7 0.86% 3.33% | 4 0.49% 3.83% | 4 0.49% 4.32% | 31 3.83% 8.15% | 310 38.27% 46.42% | 358 44.20% 90.62% | 42 5.19% 95.80% | 26 3.21% 99.01% | 8 0.99% 100.00%
-system.ruby.ST.miss_latency_hist::total 810
+system.ruby.ST.miss_latency_hist::samples 843
+system.ruby.ST.miss_latency_hist::mean 765.393832
+system.ruby.ST.miss_latency_hist::gmean 725.861277
+system.ruby.ST.miss_latency_hist::stdev 162.026380
+system.ruby.ST.miss_latency_hist | 19 2.25% 2.25% | 7 0.83% 3.08% | 4 0.47% 3.56% | 4 0.47% 4.03% | 32 3.80% 7.83% | 289 34.28% 42.11% | 404 47.92% 90.04% | 47 5.58% 95.61% | 28 3.32% 98.93% | 9 1.07% 100.00%
+system.ruby.ST.miss_latency_hist::total 843
system.ruby.IFETCH.latency_hist::bucket_size 64
system.ruby.IFETCH.latency_hist::max_bucket 639
-system.ruby.IFETCH.latency_hist::samples 57
-system.ruby.IFETCH.latency_hist::mean 105.245614
-system.ruby.IFETCH.latency_hist::gmean 84.136461
-system.ruby.IFETCH.latency_hist::stdev 62.237816
-system.ruby.IFETCH.latency_hist | 15 26.32% 26.32% | 22 38.60% 64.91% | 16 28.07% 92.98% | 2 3.51% 96.49% | 1 1.75% 98.25% | 1 1.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 57
-system.ruby.IFETCH.hit_latency_hist::bucket_size 1
-system.ruby.IFETCH.hit_latency_hist::max_bucket 9
-system.ruby.IFETCH.hit_latency_hist::samples 1
-system.ruby.IFETCH.hit_latency_hist::mean 1
-system.ruby.IFETCH.hit_latency_hist::gmean 1
-system.ruby.IFETCH.hit_latency_hist::stdev nan
-system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist::total 1
+system.ruby.IFETCH.latency_hist::samples 63
+system.ruby.IFETCH.latency_hist::mean 107.476190
+system.ruby.IFETCH.latency_hist::gmean 95.146533
+system.ruby.IFETCH.latency_hist::stdev 52.448702
+system.ruby.IFETCH.latency_hist | 11 17.46% 17.46% | 34 53.97% 71.43% | 15 23.81% 95.24% | 2 3.17% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist::total 63
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
-system.ruby.IFETCH.miss_latency_hist::samples 56
-system.ruby.IFETCH.miss_latency_hist::mean 107.107143
-system.ruby.IFETCH.miss_latency_hist::gmean 91.066566
-system.ruby.IFETCH.miss_latency_hist::stdev 61.178926
-system.ruby.IFETCH.miss_latency_hist | 14 25.00% 25.00% | 22 39.29% 64.29% | 16 28.57% 92.86% | 2 3.57% 96.43% | 1 1.79% 98.21% | 1 1.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist::total 56
-system.ruby.Directory_Controller.Fetch 868 0.00% 0.00%
-system.ruby.Directory_Controller.Data 777 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 868 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 777 0.00% 0.00%
+system.ruby.IFETCH.miss_latency_hist::samples 63
+system.ruby.IFETCH.miss_latency_hist::mean 107.476190
+system.ruby.IFETCH.miss_latency_hist::gmean 95.146533
+system.ruby.IFETCH.miss_latency_hist::stdev 52.448702
+system.ruby.IFETCH.miss_latency_hist | 11 17.46% 17.46% | 34 53.97% 71.43% | 15 23.81% 95.24% | 2 3.17% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist::total 63
+system.ruby.Directory_Controller.Fetch 902 0.00% 0.00%
+system.ruby.Directory_Controller.Data 811 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 902 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 811 0.00% 0.00%
system.ruby.Directory_Controller.CleanReplacement 87 0.00% 0.00%
-system.ruby.Directory_Controller.I.Fetch 868 0.00% 0.00%
-system.ruby.Directory_Controller.M.Data 777 0.00% 0.00%
+system.ruby.Directory_Controller.I.Fetch 902 0.00% 0.00%
+system.ruby.Directory_Controller.M.Data 811 0.00% 0.00%
system.ruby.Directory_Controller.M.CleanReplacement 87 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 868 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 777 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 43 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 65 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 875 0.00% 0.00%
-system.ruby.L1Cache_Controller.Inv 264 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 12024 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_Exclusive 40 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_all_Acks 866 0.00% 0.00%
-system.ruby.L1Cache_Controller.WB_Ack 782 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Load 40 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Ifetch 56 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Store 812 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Inv 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement 112 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Ifetch 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Inv 40 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement 9 0.00% 0.00%
-system.ruby.L1Cache_Controller.E.Inv 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement 39 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 3 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Store 63 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Inv 64 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement 745 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Inv 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement 555 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive 40 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks 49 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement 10564 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks 810 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_I.Ifetch 8 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_I.Inv 151 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack 631 0.00% 0.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 151 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GET_INSTR 56 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 40 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 810 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 632 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 902 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 811 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 37 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 67 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 927 0.00% 0.00%
+system.ruby.L1Cache_Controller.Inv 278 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 12331 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data_Exclusive 30 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data_all_Acks 906 0.00% 0.00%
+system.ruby.L1Cache_Controller.WB_Ack 808 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Load 30 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Ifetch 64 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Store 845 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement 121 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Inv 54 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement 3 0.00% 0.00%
+system.ruby.L1Cache_Controller.E.Inv 5 0.00% 0.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement 25 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 7 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 82 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Inv 57 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement 785 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Inv 6 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement 386 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive 30 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks 57 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement 11011 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks 843 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 6 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_I.Ifetch 3 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_I.Inv 156 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack 652 0.00% 0.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 156 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GET_INSTR 64 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 30 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 844 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 653 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_PUTX_old 267 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 574 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean 530 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Data 868 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Ack 864 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data 203 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean 12 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack_all 49 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 850 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 40 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 780 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_PUTX_old 135 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GET_INSTR 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 22 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 574 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean 26 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX 632 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 216 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 16 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack 864 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 116 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data 203 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 12 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 9 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data 40 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 93 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 123 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data 780 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 842 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 603 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean 569 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Data 902 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Ack 898 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data 208 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.Ack_all 65 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 873 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 61 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 29 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 814 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_PUTX_old 134 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 60 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GET_INSTR 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 27 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 603 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean 18 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX 653 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 219 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 22 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack 898 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 111 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data 208 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all 60 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 6 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data 29 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 121 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data 60 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 125 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data 813 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 20 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 870 0.00% 0.00%
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
index 150b166fb..e3b78cdef 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
@@ -55,8 +55,7 @@ eventq_index=0
num_cpus=1
system=system
wakeup_frequency=10
-cpuDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1]
+cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.dvfs_handler]
type=DVFSHandler
@@ -357,6 +356,7 @@ eventq_index=0
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
@@ -364,7 +364,7 @@ system=system
using_network_tester=false
using_ruby_tester=true
version=0
-slave=system.cpu.cpuDataPort[0] system.cpu.cpuInstPort[0]
+slave=system.cpu.cpuInstDataPort[0]
[system.ruby.l1_cntrl0.triggerQueue]
type=MessageBuffer
@@ -1105,6 +1105,7 @@ randomization=false
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
index fd3b08a0c..5739a0e00 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
@@ -1,13 +1,11 @@
-Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:46:21
-gem5 started Nov 15 2015 14:46:44
-gem5 executing on ribera.cs.wisc.edu, pid 1173
-command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
+gem5 compiled Dec 11 2015 20:10:49
+gem5 started Dec 11 2015 20:11:27
+gem5 executing on zizzer, pid 42474
+command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 53711 because Ruby Tester completed
+Exiting @ tick 54211 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index 4699f60db..91f19eaef 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
@@ -1,44 +1,44 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000054 # Number of seconds simulated
-sim_ticks 53711 # Number of ticks simulated
-final_tick 53711 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 54211 # Number of ticks simulated
+final_tick 54211 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 378504 # Simulator tick rate (ticks/s)
-host_mem_usage 447852 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
+host_tick_rate 209714 # Simulator tick rate (ticks/s)
+host_mem_usage 387824 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54528 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 54528 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 48448 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 48448 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 852 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 852 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 757 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 757 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1015211037 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1015211037 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 902012623 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 902012623 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1917223660 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1917223660 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 852 # Number of read requests accepted
-system.mem_ctrls.writeReqs 757 # Number of write requests accepted
-system.mem_ctrls.readBursts 852 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 757 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 45632 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 8896 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 40448 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 54528 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 48448 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 94 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 54016 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 48256 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 48256 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 844 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 844 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 754 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 754 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 996402944 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 996402944 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 890151445 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 890151445 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1886554389 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 1886554389 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 844 # Number of read requests accepted
+system.mem_ctrls.writeReqs 754 # Number of write requests accepted
+system.mem_ctrls.readBursts 844 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 754 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 46720 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 7296 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 42112 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 54016 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 48256 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 77 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 212 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 231 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 224 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 46 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 210 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 227 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 250 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
@@ -51,9 +51,9 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 190 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 201 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 199 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 189 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 208 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 219 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 42 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
@@ -69,23 +69,23 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 53660 # Total gap between requests
+system.mem_ctrls.totGap 54170 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 852 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 844 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 757 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 567 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 143 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 754 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 587 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 140 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 3 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
@@ -131,24 +131,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 23 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 24 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 37 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15 21 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 23 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 37 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 37 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 37 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22 38 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 37 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 37 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 38 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 37 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 37 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 36 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 36 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 2 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
@@ -180,73 +180,72 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 94 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 889.191489 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 796.949082 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 278.173972 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 2 2.13% 2.13% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 4 4.26% 6.38% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 5 5.32% 11.70% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 3 3.19% 14.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 1 1.06% 15.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 2 2.13% 18.09% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 2 2.13% 20.21% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 5 5.32% 25.53% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 70 74.47% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 94 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 36 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 19.277778 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 18.954063 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 4.046947 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 3 8.33% 8.33% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 9 25.00% 33.33% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 11 30.56% 63.89% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 5 13.89% 77.78% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23 6 16.67% 94.44% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-25 1 2.78% 97.22% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::38-39 1 2.78% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 36 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 36 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 17.555556 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 17.508645 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 1.297127 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 13 36.11% 36.11% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 1 2.78% 38.89% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 12 33.33% 72.22% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 9 25.00% 97.22% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 1 2.78% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 36 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 5835 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 19382 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3565 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 8.18 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 97 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 888.742268 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 795.135498 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 283.200947 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 8 8.25% 8.25% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 2 2.06% 10.31% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 3 3.09% 13.40% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 2 2.06% 15.46% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 4 4.12% 19.59% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 1 1.03% 20.62% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 2 2.06% 22.68% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 75 77.32% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 97 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 19.052632 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 18.749953 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 3.938359 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 2 5.26% 5.26% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 13 34.21% 39.47% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 9 23.68% 63.16% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21 8 21.05% 84.21% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::22-23 4 10.53% 94.74% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-25 1 2.63% 97.37% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::38-39 1 2.63% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 17.315789 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 17.271887 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 1.254296 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 16 42.11% 42.11% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 2 5.26% 47.37% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 13 34.21% 81.58% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 6 15.79% 97.37% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20 1 2.63% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 6080 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 19950 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 3650 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 8.33 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 27.18 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 849.58 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 753.07 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1015.21 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 902.01 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 27.33 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 861.82 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 776.82 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 996.40 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 890.15 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 12.52 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 6.64 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 5.88 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.35 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 24.46 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 622 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 625 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 87.24 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 94.27 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 33.35 # Average gap between requests
-system.mem_ctrls.pageHitRate 90.62 # Row buffer hit rate, read and write combined
+system.mem_ctrls.busUtil 12.80 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 6.73 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 6.07 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 1.34 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 24.81 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 637 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 650 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 87.26 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 96.01 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 33.90 # Average gap between requests
+system.mem_ctrls.pageHitRate 91.47 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 650160 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 361200 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7700160 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 5816448 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 7725120 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 5723136 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 32013252 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 103800 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 49696380 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 1057.909997 # Core power per rank (mW)
+system.mem_ctrls_0.totalEnergy 49628028 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 1056.454956 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 19 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
@@ -269,354 +268,362 @@ system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 #
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 972
-system.ruby.outstanding_req_hist::mean 15.762346
-system.ruby.outstanding_req_hist::gmean 15.655254
-system.ruby.outstanding_req_hist::stdev 1.201656
-system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.51% | 2 0.21% 0.72% | 4 0.41% 1.13% | 2 0.21% 1.34% | 3 0.31% 1.65% | 94 9.67% 11.32% | 862 88.68% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 972
+system.ruby.outstanding_req_hist::samples 985
+system.ruby.outstanding_req_hist::mean 15.747208
+system.ruby.outstanding_req_hist::gmean 15.641156
+system.ruby.outstanding_req_hist::stdev 1.199617
+system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 4 0.41% 1.12% | 2 0.20% 1.32% | 3 0.30% 1.62% | 110 11.17% 12.79% | 859 87.21% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 985
system.ruby.latency_hist::bucket_size 256
system.ruby.latency_hist::max_bucket 2559
-system.ruby.latency_hist::samples 957
-system.ruby.latency_hist::mean 881.794148
-system.ruby.latency_hist::gmean 495.949804
-system.ruby.latency_hist::stdev 359.464211
-system.ruby.latency_hist | 135 14.11% 14.11% | 6 0.63% 14.73% | 4 0.42% 15.15% | 442 46.19% 61.34% | 349 36.47% 97.81% | 21 2.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 957
+system.ruby.latency_hist::samples 970
+system.ruby.latency_hist::mean 876.382474
+system.ruby.latency_hist::gmean 454.463576
+system.ruby.latency_hist::stdev 370.932806
+system.ruby.latency_hist | 146 15.05% 15.05% | 6 0.62% 15.67% | 4 0.41% 16.08% | 388 40.00% 56.08% | 418 43.09% 99.18% | 8 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist::total 970
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
-system.ruby.hit_latency_hist::samples 75
+system.ruby.hit_latency_hist::samples 92
system.ruby.hit_latency_hist::mean 1
system.ruby.hit_latency_hist::gmean 1
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 75 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 75
+system.ruby.hit_latency_hist | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist::total 92
system.ruby.miss_latency_hist::bucket_size 256
system.ruby.miss_latency_hist::max_bucket 2559
-system.ruby.miss_latency_hist::samples 882
-system.ruby.miss_latency_hist::mean 956.691610
-system.ruby.miss_latency_hist::gmean 840.701090
-system.ruby.miss_latency_hist::stdev 261.829138
-system.ruby.miss_latency_hist | 60 6.80% 6.80% | 6 0.68% 7.48% | 4 0.45% 7.94% | 442 50.11% 58.05% | 349 39.57% 97.62% | 21 2.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist::total 882
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 75 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 832 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 907 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 50 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 3 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 76 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 3 # Number of times a load aliased with a pending store
-system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 852 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 882 # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples 878
+system.ruby.miss_latency_hist::mean 968.108200
+system.ruby.miss_latency_hist::gmean 862.901849
+system.ruby.miss_latency_hist::stdev 251.425992
+system.ruby.miss_latency_hist | 54 6.15% 6.15% | 6 0.68% 6.83% | 4 0.46% 7.29% | 388 44.19% 51.48% | 418 47.61% 99.09% | 8 0.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist::total 878
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 90 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 836 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 926 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 2 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 44 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 46 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 75 # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 2 # Number of times a load aliased with a pending store
+system.ruby.l2_cntrl0.L2cache.demand_hits 36 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 844 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 880 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
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-system.ruby.LD.latency_hist::stdev 318.769653
-system.ruby.LD.latency_hist | 5 10.00% 10.00% | 0 0.00% 10.00% | 0 0.00% 10.00% | 30 60.00% 70.00% | 13 26.00% 96.00% | 2 4.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist::total 50
+system.ruby.network.routers0.percent_links_utilized 8.888879
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-system.ruby.L1Cache_Controller.L1_Replacement 79286 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 89 0.00% 0.00%
-system.ruby.L1Cache_Controller.Exclusive_Data 793 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack_Data 877 0.00% 0.00%
+system.ruby.IFETCH.miss_latency_hist::samples 44
+system.ruby.IFETCH.miss_latency_hist::mean 73.340909
+system.ruby.IFETCH.miss_latency_hist::gmean 65.579350
+system.ruby.IFETCH.miss_latency_hist::stdev 35.479403
+system.ruby.IFETCH.miss_latency_hist | 2 4.55% 4.55% | 14 31.82% 36.36% | 21 47.73% 84.09% | 1 2.27% 86.36% | 4 9.09% 95.45% | 2 4.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist::total 44
+system.ruby.Directory_Controller.GETX 761 0.00% 0.00%
+system.ruby.Directory_Controller.GETS 83 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 755 0.00% 0.00%
+system.ruby.Directory_Controller.Unblock 77 0.00% 0.00%
+system.ruby.Directory_Controller.Last_Unblock 5 0.00% 0.00%
+system.ruby.Directory_Controller.Exclusive_Unblock 760 0.00% 0.00%
+system.ruby.Directory_Controller.Dirty_Writeback 754 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 843 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 754 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 691 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETS 78 0.00% 0.00%
+system.ruby.Directory_Controller.I.Memory_Ack 754 0.00% 0.00%
+system.ruby.Directory_Controller.S.GETX 70 0.00% 0.00%
+system.ruby.Directory_Controller.S.GETS 5 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 755 0.00% 0.00%
+system.ruby.Directory_Controller.IS.Unblock 77 0.00% 0.00%
+system.ruby.Directory_Controller.IS.Memory_Data 78 0.00% 0.00%
+system.ruby.Directory_Controller.SS.Last_Unblock 5 0.00% 0.00%
+system.ruby.Directory_Controller.SS.Memory_Data 5 0.00% 0.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock 760 0.00% 0.00%
+system.ruby.Directory_Controller.MM.Memory_Data 760 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback 754 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 56 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 59 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 880 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 80012 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 83 0.00% 0.00%
+system.ruby.L1Cache_Controller.Exclusive_Data 795 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack_Data 874 0.00% 0.00%
system.ruby.L1Cache_Controller.All_acks 786 0.00% 0.00%
-system.ruby.L1Cache_Controller.Use_Timeout 792 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 46 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 50 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 786 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement 87 0.00% 0.00%
+system.ruby.L1Cache_Controller.Use_Timeout 795 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 48 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 44 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 788 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement 81 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 2 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement 6 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement 4 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Use_Timeout 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Load 3 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Store 59 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement 784 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Load 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Store 11 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement 31474 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout 785 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement 44509 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement 7 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement 5 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Use_Timeout 9 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Load 4 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Store 68 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement 787 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Load 2 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Store 15 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement 30902 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout 786 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement 45597 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Exclusive_Data 786 0.00% 0.00%
-system.ruby.L1Cache_Controller.OM.L1_Replacement 57 0.00% 0.00%
+system.ruby.L1Cache_Controller.OM.L1_Replacement 45 0.00% 0.00%
system.ruby.L1Cache_Controller.OM.All_acks 786 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement 2365 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data 89 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 87 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement 2588 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 83 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data 9 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 81 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Load 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Ifetch 10 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Ifetch 13 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Store 8 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 790 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 96 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 786 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 790 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS_only 87 0.00% 0.00%
-system.ruby.L2Cache_Controller.All_Acks 763 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data 852 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA 87 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 790 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Ack 758 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 88 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 793 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 844 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 89 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 763 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 87 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTX 790 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement 86 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 23 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 758 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 87 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 790 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Data 89 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Unblock 88 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGM.Data 763 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.All_Acks 763 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 763 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 23 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.MI.Writeback_Ack 758 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 793 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 92 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 788 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 794 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS_only 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.All_Acks 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data 843 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 793 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_Ack 754 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 82 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 795 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 836 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 83 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 761 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTX 794 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 9 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 27 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 755 0.00% 0.00%
+system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 793 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Data 83 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Unblock 82 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGM.Data 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.All_Acks 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 26 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 9 0.00% 0.00%
+system.ruby.L2Cache_Controller.MI.Writeback_Ack 754 0.00% 0.00%
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
index 7525ba3b1..91457f746 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
@@ -55,8 +55,7 @@ eventq_index=0
num_cpus=1
system=system
wakeup_frequency=10
-cpuDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1]
+cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.dvfs_handler]
type=DVFSHandler
@@ -421,6 +420,7 @@ eventq_index=0
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
@@ -428,7 +428,7 @@ system=system
using_network_tester=false
using_ruby_tester=true
version=0
-slave=system.cpu.cpuDataPort[0] system.cpu.cpuInstPort[0]
+slave=system.cpu.cpuInstDataPort[0]
[system.ruby.l2_cntrl0]
type=L2Cache_Controller
@@ -1669,6 +1669,7 @@ randomization=false
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
index 37f2fa418..f6fb164f9 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
@@ -1,13 +1,11 @@
-Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:51:28
-gem5 started Nov 15 2015 14:51:52
-gem5 executing on ribera.cs.wisc.edu, pid 2888
-command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
+gem5 compiled Dec 11 2015 20:15:50
+gem5 started Dec 11 2015 20:16:20
+gem5 executing on zizzer, pid 47648
+command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 53241 because Ruby Tester completed
+Exiting @ tick 50141 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
index 56ffc198c..22d2e6b72 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
@@ -1,44 +1,44 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000053 # Number of seconds simulated
-sim_ticks 53241 # Number of ticks simulated
-final_tick 53241 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000050 # Number of seconds simulated
+sim_ticks 50141 # Number of ticks simulated
+final_tick 50141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 626475 # Simulator tick rate (ticks/s)
-host_mem_usage 446792 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 455774 # Simulator tick rate (ticks/s)
+host_mem_usage 387088 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 54016 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49216 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 49216 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 844 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 844 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 769 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 769 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1014556451 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1014556451 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 924400368 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 924400368 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1938956819 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1938956819 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 845 # Number of read requests accepted
-system.mem_ctrls.writeReqs 769 # Number of write requests accepted
-system.mem_ctrls.readBursts 845 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 769 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 44800 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 9280 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 41856 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 54080 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 49216 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 145 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 91 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 50624 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 50624 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 46016 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 46016 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 791 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 791 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 719 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 719 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 1009632835 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 1009632835 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 917731996 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 917731996 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1927364831 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 1927364831 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 791 # Number of read requests accepted
+system.mem_ctrls.writeReqs 719 # Number of write requests accepted
+system.mem_ctrls.readBursts 791 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 719 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 42944 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 7680 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 39296 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 50624 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 46016 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 211 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 230 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 216 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 208 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 221 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 189 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 53 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
@@ -51,10 +51,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 195 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 213 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 203 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 43 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 189 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 195 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 180 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 50 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
@@ -69,24 +69,24 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 53206 # Total gap between requests
+system.mem_ctrls.totGap 50084 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 845 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 791 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 769 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 596 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 104 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 719 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 557 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 111 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2 3 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -131,24 +131,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 25 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 44 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 20 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 42 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
@@ -180,71 +180,69 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 91 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 926.241758 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 851.755825 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 236.278712 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 2 2.20% 2.20% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 3 3.30% 5.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 1 1.10% 6.59% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 3 3.30% 9.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 3 3.30% 13.19% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 4 4.40% 17.58% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 3 3.30% 20.88% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 72 79.12% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 91 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 17.325000 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 17.063768 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 3.661214 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 9 22.50% 22.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 70.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 8 20.00% 90.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 2 5.00% 95.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23 1 2.50% 97.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-37 1 2.50% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.350000 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.325620 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.948683 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 34 85.00% 85.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 2 5.00% 90.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 1 2.50% 92.50% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 2 5.00% 97.50% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 1 2.50% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 7789 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 21089 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3500 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 11.13 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 89 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 910.382022 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 810.808230 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 274.216052 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 2 2.25% 2.25% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 5 5.62% 7.87% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 2 2.25% 10.11% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 1 1.12% 11.24% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 1 1.12% 12.36% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 2 2.25% 14.61% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 1 1.12% 15.73% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 3 3.37% 19.10% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 72 80.90% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 89 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 17.394737 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 17.106045 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 3.831163 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 8 21.05% 21.05% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 18 47.37% 68.42% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 7 18.42% 86.84% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21 3 7.89% 94.74% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::22-23 1 2.63% 97.37% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::36-37 1 2.63% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.157895 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.145372 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 0.678883 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 36 94.74% 94.74% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 2 5.26% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 8848 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 21597 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 3355 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 13.19 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 30.13 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 841.46 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 786.16 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1015.76 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 924.40 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 32.19 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 856.46 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 783.71 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 1009.63 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 917.73 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 12.72 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 6.57 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 6.14 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.26 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.08 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 611 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 649 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 87.29 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 95.72 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 32.97 # Average gap between requests
-system.mem_ctrls.pageHitRate 91.44 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 627480 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 348600 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7712640 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 5920128 # Energy for write commands per rank (pJ)
+system.mem_ctrls.busUtil 12.81 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 6.69 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 6.12 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 1.30 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 25.17 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 582 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 610 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 86.74 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 95.61 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 33.17 # Average gap between requests
+system.mem_ctrls.pageHitRate 91.06 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 642600 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 357000 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 7775040 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 6003072 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 32011200 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 105600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 49777008 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 1059.626362 # Core power per rank (mW)
+system.mem_ctrls_0.actBackEnergy 32001624 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 114000 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 49944696 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 1063.196015 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 22 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
@@ -267,335 +265,334 @@ system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 #
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 1000
-system.ruby.outstanding_req_hist::mean 15.805000
-system.ruby.outstanding_req_hist::gmean 15.701069
-system.ruby.outstanding_req_hist::stdev 1.178288
-system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 4 0.40% 1.10% | 2 0.20% 1.30% | 3 0.30% 1.60% | 58 5.80% 7.40% | 926 92.60% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 1000
+system.ruby.outstanding_req_hist::samples 961
+system.ruby.outstanding_req_hist::mean 15.762747
+system.ruby.outstanding_req_hist::gmean 15.654325
+system.ruby.outstanding_req_hist::stdev 1.209298
+system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.52% | 2 0.21% 0.73% | 4 0.42% 1.14% | 2 0.21% 1.35% | 3 0.31% 1.66% | 91 9.47% 11.13% | 854 88.87% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 961
system.ruby.latency_hist::bucket_size 256
system.ruby.latency_hist::max_bucket 2559
-system.ruby.latency_hist::samples 985
-system.ruby.latency_hist::mean 848.757360
-system.ruby.latency_hist::gmean 399.302244
-system.ruby.latency_hist::stdev 414.190992
-system.ruby.latency_hist | 190 19.29% 19.29% | 6 0.61% 19.90% | 5 0.51% 20.41% | 342 34.72% 55.13% | 403 40.91% 96.04% | 39 3.96% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 985
+system.ruby.latency_hist::samples 946
+system.ruby.latency_hist::mean 831.747357
+system.ruby.latency_hist::gmean 353.331206
+system.ruby.latency_hist::stdev 440.661399
+system.ruby.latency_hist | 208 21.99% 21.99% | 7 0.74% 22.73% | 5 0.53% 23.26% | 262 27.70% 50.95% | 409 43.23% 94.19% | 55 5.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist::total 946
system.ruby.hit_latency_hist::bucket_size 256
system.ruby.hit_latency_hist::max_bucket 2559
-system.ruby.hit_latency_hist::samples 141
-system.ruby.hit_latency_hist::mean 184.574468
-system.ruby.hit_latency_hist::gmean 5.430666
-system.ruby.hit_latency_hist::stdev 386.473899
-system.ruby.hit_latency_hist | 116 82.27% 82.27% | 0 0.00% 82.27% | 0 0.00% 82.27% | 19 13.48% 95.74% | 4 2.84% 98.58% | 2 1.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 141
+system.ruby.hit_latency_hist::samples 156
+system.ruby.hit_latency_hist::mean 161.115385
+system.ruby.hit_latency_hist::gmean 5.208817
+system.ruby.hit_latency_hist::stdev 361.858143
+system.ruby.hit_latency_hist | 132 84.62% 84.62% | 0 0.00% 84.62% | 0 0.00% 84.62% | 17 10.90% 95.51% | 6 3.85% 99.36% | 1 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist::total 156
system.ruby.miss_latency_hist::bucket_size 256
system.ruby.miss_latency_hist::max_bucket 2559
-system.ruby.miss_latency_hist::samples 844
-system.ruby.miss_latency_hist::mean 959.716825
-system.ruby.miss_latency_hist::gmean 818.679034
-system.ruby.miss_latency_hist::stdev 298.884250
-system.ruby.miss_latency_hist | 74 8.77% 8.77% | 6 0.71% 9.48% | 5 0.59% 10.07% | 323 38.27% 48.34% | 399 47.27% 95.62% | 37 4.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist::total 844
-system.ruby.Directory.incomplete_times 844
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 97 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 841 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 938 # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples 790
+system.ruby.miss_latency_hist::mean 964.175949
+system.ruby.miss_latency_hist::gmean 812.519909
+system.ruby.miss_latency_hist::stdev 316.811320
+system.ruby.miss_latency_hist | 76 9.62% 9.62% | 7 0.89% 10.51% | 5 0.63% 11.14% | 245 31.01% 42.15% | 403 51.01% 93.16% | 54 6.84% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist::total 790
+system.ruby.Directory.incomplete_times 790
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 105 # Number of cache demand hits
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+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 893 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 47 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 48 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 84 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load
-system.ruby.l2_cntrl0.L2cache.demand_hits 42 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 846 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 888 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_misses 54 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 55 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 6 # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 74 # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store
+system.ruby.l2_cntrl0.L2cache.demand_hits 48 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 793 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 841 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
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system.ruby.network.routers0.msg_count.Response_Control::4 1
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system.ruby.network.routers0.msg_bytes.Response_Control::4 8
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system.ruby.network.routers1.msg_count.Response_Control::4 1
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system.ruby.network.routers1.msg_bytes.Response_Control::4 8
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system.ruby.network.msg_count.Response_Control 3
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-system.ruby.LD.latency_hist | 11 21.15% 21.15% | 0 0.00% 21.15% | 0 0.00% 21.15% | 14 26.92% 48.08% | 26 50.00% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 256
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 2559
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 760
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1005.751316
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 939.114914
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 221.956577
-system.ruby.ST.Directory.miss_type_mach_latency_hist | 30 3.95% 3.95% | 6 0.79% 4.74% | 5 0.66% 5.39% | 310 40.79% 46.18% | 373 49.08% 95.26% | 36 4.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total 760
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 708
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1019.083333
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 946.557722
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 233.252272
+system.ruby.ST.Directory.miss_type_mach_latency_hist | 29 4.10% 4.10% | 6 0.85% 4.94% | 5 0.71% 5.65% | 231 32.63% 38.28% | 387 54.66% 92.94% | 50 7.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total 708
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 1
@@ -606,105 +603,107 @@ system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00%
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 1
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 4
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 39
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 4
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 23
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 22.930627
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::stdev 2
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 3 75.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 4
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 43
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 61.046512
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 58.593153
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 17.654021
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 39.53% 39.53% | 1 2.33% 41.86% | 21 48.84% 90.70% | 3 6.98% 97.67% | 0 0.00% 97.67% | 1 2.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 43
-system.ruby.Directory_Controller.GETX 762 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 84 0.00% 0.00%
-system.ruby.Directory_Controller.Lockdown 15 0.00% 0.00%
-system.ruby.Directory_Controller.Unlockdown 15 0.00% 0.00%
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 7
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 23.428571
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 23.382968
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::stdev 1.511858
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 14.29% 14.29% | 6 85.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 7
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 46
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 78.065217
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 68.721309
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 50.161252
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 15 32.61% 32.61% | 25 54.35% 86.96% | 0 0.00% 86.96% | 3 6.52% 93.48% | 0 0.00% 93.48% | 2 4.35% 97.83% | 0 0.00% 97.83% | 0 0.00% 97.83% | 1 2.17% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 46
+system.ruby.Directory_Controller.GETX 710 0.00% 0.00%
+system.ruby.Directory_Controller.GETS 85 0.00% 0.00%
+system.ruby.Directory_Controller.Lockdown 17 0.00% 0.00%
+system.ruby.Directory_Controller.Unlockdown 17 0.00% 0.00%
system.ruby.Directory_Controller.Data_Owner 1 0.00% 0.00%
-system.ruby.Directory_Controller.Data_All_Tokens 768 0.00% 0.00%
-system.ruby.Directory_Controller.Ack_Owner_All_Tokens 68 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 844 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 769 0.00% 0.00%
-system.ruby.Directory_Controller.O.GETX 761 0.00% 0.00%
-system.ruby.Directory_Controller.O.GETS 84 0.00% 0.00%
-system.ruby.Directory_Controller.NO.GETX 1 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Lockdown 3 0.00% 0.00%
+system.ruby.Directory_Controller.Data_All_Tokens 718 0.00% 0.00%
+system.ruby.Directory_Controller.Ack_Owner_All_Tokens 65 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 790 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 719 0.00% 0.00%
+system.ruby.Directory_Controller.O.GETX 708 0.00% 0.00%
+system.ruby.Directory_Controller.O.GETS 83 0.00% 0.00%
+system.ruby.Directory_Controller.NO.GETX 2 0.00% 0.00%
+system.ruby.Directory_Controller.NO.Lockdown 7 0.00% 0.00%
system.ruby.Directory_Controller.NO.Data_Owner 1 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Data_All_Tokens 768 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 68 0.00% 0.00%
-system.ruby.Directory_Controller.L.Unlockdown 15 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.Memory_Ack 769 0.00% 0.00%
-system.ruby.Directory_Controller.L_NO_W.Memory_Data 12 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Lockdown 12 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data 832 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 52 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 48 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 886 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 23140 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_Shared 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_All_Tokens 895 0.00% 0.00%
+system.ruby.Directory_Controller.NO.Data_All_Tokens 718 0.00% 0.00%
+system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 65 0.00% 0.00%
+system.ruby.Directory_Controller.L.Unlockdown 17 0.00% 0.00%
+system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00%
+system.ruby.Directory_Controller.O_W.Memory_Ack 719 0.00% 0.00%
+system.ruby.Directory_Controller.L_NO_W.Memory_Data 10 0.00% 0.00%
+system.ruby.Directory_Controller.NO_W.Lockdown 10 0.00% 0.00%
+system.ruby.Directory_Controller.NO_W.Memory_Data 780 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 46 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 55 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 847 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 22253 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data_Shared 10 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data_All_Tokens 844 0.00% 0.00%
system.ruby.L1Cache_Controller.Ack 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 30 0.00% 0.00%
-system.ruby.L1Cache_Controller.Request_Timeout 23 0.00% 0.00%
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 878 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Load 44 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Ifetch 47 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Store 796 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Data_All_Tokens 15 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock 15 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Ifetch 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Store 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement 6 0.00% 0.00%
+system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 34 0.00% 0.00%
+system.ruby.L1Cache_Controller.Request_Timeout 61 0.00% 0.00%
+system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 829 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Load 39 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Ifetch 54 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Store 747 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Data_All_Tokens 14 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock 14 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Store 2 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement 8 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 1 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L1_Replacement 79 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 3 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.Load 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Store 75 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement 797 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Store 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement 519 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Store 79 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement 748 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Store 1 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement 551 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock 1 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 80 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Load 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Store 12 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement 10558 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Store 18 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement 10451 0.00% 0.00%
system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 798 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement 10590 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data_All_Tokens 795 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 749 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement 9900 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data_All_Tokens 746 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Ack 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock 12 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Request_Timeout 21 0.00% 0.00%
-system.ruby.L1Cache_Controller.SM.Data_All_Tokens 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement 591 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_Shared 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_All_Tokens 84 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Request_Timeout 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 91 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 797 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 822 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock 10 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Request_Timeout 55 0.00% 0.00%
+system.ruby.L1Cache_Controller.SM.Data_All_Tokens 2 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement 516 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data_Shared 10 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data_All_Tokens 82 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 5 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Request_Timeout 6 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 93 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 748 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 770 0.00% 0.00%
system.ruby.L2Cache_Controller.Writeback_Shared_Data 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_All_Tokens 881 0.00% 0.00%
-system.ruby.L2Cache_Controller.Persistent_GETX 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.Persistent_GETS 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 84 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_All_Tokens 833 0.00% 0.00%
+system.ruby.L2Cache_Controller.Persistent_GETX 11 0.00% 0.00%
+system.ruby.L2Cache_Controller.Persistent_GETS 6 0.00% 0.00%
+system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 17 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 83 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 707 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 825 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 36 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 773 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 17 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 39 0.00% 0.00%
system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.L1_GETX 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.O.L1_GETX 2 0.00% 0.00%
system.ruby.L2Cache_Controller.O.L2_Replacement 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 35 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 821 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETX 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETS 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 7 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 10 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 38 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 769 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 14 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETX 11 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETS 6 0.00% 0.00%
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
index 860c1b559..c18dbade3 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
@@ -55,8 +55,7 @@ eventq_index=0
num_cpus=1
system=system
wakeup_frequency=10
-cpuDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1]
+cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.dvfs_handler]
type=DVFSHandler
@@ -444,6 +443,7 @@ eventq_index=0
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
@@ -451,7 +451,7 @@ system=system
using_network_tester=false
using_ruby_tester=true
version=0
-slave=system.cpu.cpuDataPort[0] system.cpu.cpuInstPort[0]
+slave=system.cpu.cpuInstDataPort[0]
[system.ruby.l1_cntrl0.triggerQueue]
type=MessageBuffer
@@ -1153,6 +1153,7 @@ randomization=false
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
index 97d28f02f..0e5bf2d7e 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
@@ -1,13 +1,11 @@
-Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:35:53
-gem5 started Nov 15 2015 14:36:13
-gem5 executing on ribera.cs.wisc.edu, pid 30617
-command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
+gem5 compiled Dec 11 2015 20:00:36
+gem5 started Dec 11 2015 20:01:07
+gem5 executing on zizzer, pid 31713
+command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 29631 because Ruby Tester completed
+Exiting @ tick 29561 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index 811637401..7065b4fe2 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
@@ -1,44 +1,44 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000030 # Number of seconds simulated
-sim_ticks 29631 # Number of ticks simulated
-final_tick 29631 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 29561 # Number of ticks simulated
+final_tick 29561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 374763 # Simulator tick rate (ticks/s)
-host_mem_usage 446704 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_tick_rate 249798 # Simulator tick rate (ticks/s)
+host_mem_usage 387096 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55872 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 55872 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49984 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 49984 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 873 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 873 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 781 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 781 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1885592791 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1885592791 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1686881982 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1686881982 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 3572474773 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 3572474773 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 873 # Number of read requests accepted
-system.mem_ctrls.writeReqs 781 # Number of write requests accepted
-system.mem_ctrls.readBursts 873 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 781 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 45696 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 10176 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 41088 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 55872 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 49984 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 113 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56000 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 56000 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 50560 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 50560 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 875 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 875 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 790 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 790 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 1894387876 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 1894387876 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 1710361625 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 1710361625 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 3604749501 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 3604749501 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 876 # Number of read requests accepted
+system.mem_ctrls.writeReqs 790 # Number of write requests accepted
+system.mem_ctrls.readBursts 876 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 790 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 46720 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 9344 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 41728 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 56064 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 50560 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 108 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 201 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 228 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 232 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 53 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 202 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 231 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 235 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 62 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
@@ -51,10 +51,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 181 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 200 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 216 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 45 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 184 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 201 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 215 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 52 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
@@ -69,24 +69,24 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 29604 # Total gap between requests
+system.mem_ctrls.totGap 29529 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 873 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 876 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 781 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 412 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 289 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 13 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 790 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 418 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 290 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2 22 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -131,25 +131,25 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 26 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 22 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 52 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 61 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 41 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
@@ -180,70 +180,72 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 89 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 957.842697 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 925.208115 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 187.944921 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 4 4.49% 4.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 1 1.12% 5.62% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 1 1.12% 6.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 5 5.62% 12.36% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 1 1.12% 13.48% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 77 86.52% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 89 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples 91 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 952.967033 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 882.848619 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 223.022742 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 2 2.20% 2.20% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 2 2.20% 4.40% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 2 2.20% 6.59% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 1 1.10% 7.69% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 2 2.20% 9.89% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 1 1.10% 10.99% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 81 89.01% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 91 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 17.575000 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 17.282559 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 3.868926 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 10 25.00% 25.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 14 35.00% 60.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 10 25.00% 85.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 4 10.00% 95.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 17.800000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 17.518113 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 3.824348 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 8 20.00% 20.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 16 40.00% 60.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 8 20.00% 80.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21 6 15.00% 95.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::22-23 1 2.50% 97.50% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::38-39 1 2.50% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.050000 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.048573 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.220721 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 38 95.00% 95.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 2 5.00% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.300000 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.268271 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 1.114013 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 36 90.00% 90.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 2 5.00% 95.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::21 2 5.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 8764 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 22330 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3570 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 12.27 # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat 8835 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 22705 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 3650 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 12.10 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 31.27 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 1542.17 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 1386.66 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1885.59 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1686.88 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 31.10 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 1580.46 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 1411.59 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 1896.55 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 1710.36 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 22.88 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 12.05 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 10.83 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.73 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 24.84 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 626 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 637 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 87.68 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 95.36 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 17.90 # Average gap between requests
-system.mem_ctrls.pageHitRate 91.39 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 551880 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 306600 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7026240 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 5318784 # Energy for write commands per rank (pJ)
+system.mem_ctrls.busUtil 23.38 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 12.35 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 11.03 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 1.74 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 24.79 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 640 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 647 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 87.67 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 94.87 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 17.72 # Average gap between requests
+system.mem_ctrls.pageHitRate 91.15 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 567000 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 315000 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 7176000 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 5432832 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 16099308 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 16101360 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 48600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 30877092 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 1307.354221 # Core power per rank (mW)
+system.mem_ctrls_0.totalEnergy 31166472 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 1319.439143 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 780 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 22841 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 22844 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
@@ -262,268 +264,268 @@ system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 #
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 1005
-system.ruby.outstanding_req_hist::mean 15.587065
-system.ruby.outstanding_req_hist::gmean 15.474770
-system.ruby.outstanding_req_hist::stdev 1.278707
-system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 3 0.30% 0.80% | 3 0.30% 1.09% | 6 0.60% 1.69% | 5 0.50% 2.19% | 239 23.78% 25.97% | 744 74.03% 100.00% | 0 0.00% 100.00%
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+system.ruby.outstanding_req_hist::gmean 15.456992
+system.ruby.outstanding_req_hist::stdev 1.265135
+system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.19% 0.29% | 2 0.19% 0.49% | 3 0.29% 0.78% | 3 0.29% 1.07% | 6 0.58% 1.66% | 3 0.29% 1.95% | 271 26.39% 28.33% | 736 71.67% 100.00% | 0 0.00% 100.00%
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system.ruby.latency_hist::bucket_size 128
system.ruby.latency_hist::max_bucket 1279
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-system.ruby.latency_hist::gmean 252.592392
-system.ruby.latency_hist::stdev 232.151200
-system.ruby.latency_hist | 190 19.19% 19.19% | 9 0.91% 20.10% | 5 0.51% 20.61% | 142 14.34% 34.95% | 561 56.67% 91.62% | 42 4.24% 95.86% | 16 1.62% 97.47% | 25 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.hit_latency_hist::bucket_size 128
-system.ruby.hit_latency_hist::max_bucket 1279
-system.ruby.hit_latency_hist::samples 120
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-system.ruby.hit_latency_hist::gmean 4.686569
-system.ruby.hit_latency_hist::stdev 196.031167
-system.ruby.hit_latency_hist | 101 84.17% 84.17% | 0 0.00% 84.17% | 0 0.00% 84.17% | 8 6.67% 90.83% | 9 7.50% 98.33% | 2 1.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 120
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+system.ruby.latency_hist::gmean 221.913062
+system.ruby.latency_hist::stdev 245.259624
+system.ruby.latency_hist | 227 22.43% 22.43% | 13 1.28% 23.72% | 6 0.59% 24.31% | 123 12.15% 36.46% | 525 51.88% 88.34% | 73 7.21% 95.55% | 35 3.46% 99.01% | 10 0.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.hit_latency_hist | 117 83.57% 83.57% | 3 2.14% 85.71% | 1 0.71% 86.43% | 0 0.00% 86.43% | 0 0.00% 86.43% | 0 0.00% 86.43% | 4 2.86% 89.29% | 5 3.57% 92.86% | 8 5.71% 98.57% | 2 1.43% 100.00%
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system.ruby.miss_latency_hist::bucket_size 128
system.ruby.miss_latency_hist::max_bucket 1279
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-system.ruby.miss_latency_hist::gmean 437.780939
-system.ruby.miss_latency_hist::stdev 184.718401
-system.ruby.miss_latency_hist | 89 10.23% 10.23% | 9 1.03% 11.26% | 5 0.57% 11.84% | 134 15.40% 27.24% | 552 63.45% 90.69% | 40 4.60% 95.29% | 16 1.84% 97.13% | 25 2.87% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.miss_latency_hist | 107 12.27% 12.27% | 12 1.38% 13.65% | 6 0.69% 14.33% | 114 13.07% 27.41% | 515 59.06% 86.47% | 73 8.37% 94.84% | 35 4.01% 98.85% | 10 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 77 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 864 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 941 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 48 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 49 # Number of cache demand accesses
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system.ruby.l1_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits
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-system.ruby.l1_cntrl0.L2cache.demand_accesses 912 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 2 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 82 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store
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+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 8 # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 72 # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 4 # Number of times a load aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 3 # Number of times a load aliased with a pending load
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
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system.ruby.LD.latency_hist::max_bucket 1279
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system.ruby.LD.miss_latency_hist::max_bucket 1279
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system.ruby.ST.latency_hist::max_bucket 1279
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system.ruby.IFETCH.hit_latency_hist::bucket_size 2
system.ruby.IFETCH.hit_latency_hist::max_bucket 19
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system.ruby.L2Cache.hit_mach_latency_hist::samples 39
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system.ruby.L2Cache.hit_mach_latency_hist::total 39
system.ruby.Directory.miss_mach_latency_hist::bucket_size 128
system.ruby.Directory.miss_mach_latency_hist::max_bucket 1279
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-system.ruby.Directory.miss_mach_latency_hist | 89 10.23% 10.23% | 9 1.03% 11.26% | 5 0.57% 11.84% | 134 15.40% 27.24% | 552 63.45% 90.69% | 40 4.60% 95.29% | 16 1.84% 97.13% | 25 2.87% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist::total 870
+system.ruby.Directory.miss_mach_latency_hist::samples 872
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+system.ruby.Directory.miss_mach_latency_hist | 107 12.27% 12.27% | 12 1.38% 13.65% | 6 0.69% 14.33% | 114 13.07% 27.41% | 515 59.06% 86.47% | 73 8.37% 94.84% | 35 4.01% 98.85% | 10 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 4
@@ -531,154 +533,141 @@ system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 4
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-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 1
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-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 72
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev nan
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 1
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 128
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 1279
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 47
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-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 112.817024
-system.ruby.LD.Directory.miss_type_mach_latency_hist | 1 2.13% 2.13% | 0 0.00% 2.13% | 0 0.00% 2.13% | 8 17.02% 19.15% | 34 72.34% 91.49% | 2 4.26% 95.74% | 2 4.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total 47
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+system.ruby.L1Cache_Controller.MMT.L1_to_L2 130 0.00% 0.00%
+system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 30 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI_F.Writeback_Ack 2 0.00% 0.00%
system.ruby.L1Cache_Controller.IM_F.Exclusive_Data 2 0.00% 0.00%
system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers 2 0.00% 0.00%
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
index a1a0f9e3b..b74242b8f 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
@@ -55,8 +55,7 @@ eventq_index=0
num_cpus=1
system=system
wakeup_frequency=10
-cpuDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1]
+cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.dvfs_handler]
type=DVFSHandler
@@ -340,6 +339,7 @@ eventq_index=0
icache=system.ruby.l1_cntrl0.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
@@ -347,7 +347,7 @@ system=system
using_network_tester=false
using_ruby_tester=true
version=0
-slave=system.cpu.cpuDataPort[0] system.cpu.cpuInstPort[0]
+slave=system.cpu.cpuInstDataPort[0]
[system.ruby.memctrl_clk_domain]
type=DerivedClockDomain
@@ -936,6 +936,7 @@ randomization=false
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
index 38918c59c..80d0304fa 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
@@ -1,13 +1,11 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:36
-gem5 executing on ribera.cs.wisc.edu, pid 29062
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:29
+gem5 executing on zizzer, pid 26182
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 37801 because Ruby Tester completed
+Exiting @ tick 37741 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index e9c37efa5..9784c36a4 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
@@ -1,44 +1,44 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000038 # Number of seconds simulated
-sim_ticks 37801 # Number of ticks simulated
-final_tick 37801 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 37741 # Number of ticks simulated
+final_tick 37741 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 573737 # Simulator tick rate (ticks/s)
-host_mem_usage 444464 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_tick_rate 420656 # Simulator tick rate (ticks/s)
+host_mem_usage 384732 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 61504 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 61504 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 61312 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 61312 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 961 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 961 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 958 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 958 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1627046904 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1627046904 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1621967673 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1621967673 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 3249014576 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 3249014576 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 961 # Number of read requests accepted
-system.mem_ctrls.writeReqs 958 # Number of write requests accepted
-system.mem_ctrls.readBursts 961 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 958 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 53184 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 8320 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 52736 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 61504 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 61312 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 112 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60992 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 60992 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 60800 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 60800 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 953 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 953 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 950 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 950 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 1616067407 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 1616067407 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 1610980101 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 1610980101 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 3227047508 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 3227047508 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 953 # Number of read requests accepted
+system.mem_ctrls.writeReqs 950 # Number of write requests accepted
+system.mem_ctrls.readBursts 953 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 950 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 52800 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 8192 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 51456 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 60992 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 60800 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 117 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 284 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 229 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 263 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 55 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 259 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 251 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 261 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 54 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
@@ -51,10 +51,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 279 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 228 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 259 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 58 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 255 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 246 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 250 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 53 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
@@ -69,23 +69,23 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 37739 # Total gap between requests
+system.mem_ctrls.totGap 37680 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 961 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 953 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 958 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 472 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 358 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 950 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 469 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 355 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
@@ -133,23 +133,23 @@ system.mem_ctrls.wrQLenPdf::13 1 # Wh
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 35 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 53 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 52 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 52 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 54 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 33 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 51 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 51 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 51 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 53 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 51 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 51 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 51 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 73 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 70 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 51 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
@@ -180,64 +180,66 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 109 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 961.174312 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 916.871548 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 196.872813 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 3 2.75% 2.75% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 2 1.83% 4.59% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 1 0.92% 5.50% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 3 2.75% 8.26% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 2 1.83% 10.09% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 3 2.75% 12.84% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 95 87.16% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 109 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 51 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 16.176471 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 16.043156 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 2.718131 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 10 19.61% 19.61% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 40 78.43% 98.04% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35 1 1.96% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 51 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 51 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.156863 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.152882 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.367290 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 43 84.31% 84.31% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 8 15.69% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 51 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 10313 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 26102 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 4155 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 12.41 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 107 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 956.411215 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 902.763557 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 202.735209 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 1 0.93% 0.93% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 3 2.80% 3.74% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 1 0.93% 4.67% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 2 1.87% 6.54% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 4 3.74% 10.28% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 2 1.87% 12.15% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 1 0.93% 13.08% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 93 86.92% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 107 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 50 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 16.240000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 16.100110 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 2.766859 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 11 22.00% 22.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 37 74.00% 96.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 1 2.00% 98.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35 1 2.00% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 50 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 50 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.080000 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.077788 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 0.274048 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 46 92.00% 92.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 4 8.00% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 50 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 10350 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 26025 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 4125 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 12.55 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 31.41 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 1406.95 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 1395.10 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1627.05 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1621.97 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 31.55 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 1399.01 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 1363.40 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 1616.07 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 1610.98 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 21.89 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 10.99 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 10.90 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.72 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.90 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 725 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 817 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 87.24 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 96.57 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 19.67 # Average gap between requests
-system.mem_ctrls.pageHitRate 91.95 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 695520 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 8561280 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 7039872 # Energy for write commands per rank (pJ)
+system.mem_ctrls.busUtil 21.58 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 10.93 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 10.65 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 1.73 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 26.18 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 719 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 799 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 87.15 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 95.92 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 19.80 # Average gap between requests
+system.mem_ctrls.pageHitRate 91.56 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 687960 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 382200 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 8548800 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 6822144 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 21405780 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 65400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 40188492 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 1279.725258 # Core power per rank (mW)
+system.mem_ctrls_0.totalEnergy 39946524 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 1272.020252 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
@@ -260,247 +262,247 @@ system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 #
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
-system.ruby.delayHist::samples 1919 # delay histogram for all message
-system.ruby.delayHist::mean 0.195935 # delay histogram for all message
-system.ruby.delayHist::stdev 1.060802 # delay histogram for all message
-system.ruby.delayHist | 1855 96.66% 96.66% | 0 0.00% 96.66% | 1 0.05% 96.72% | 0 0.00% 96.72% | 2 0.10% 96.82% | 0 0.00% 96.82% | 61 3.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 1919 # delay histogram for all message
+system.ruby.delayHist::samples 1903 # delay histogram for all message
+system.ruby.delayHist::mean 0.196532 # delay histogram for all message
+system.ruby.delayHist::stdev 1.062331 # delay histogram for all message
+system.ruby.delayHist | 1839 96.64% 96.64% | 0 0.00% 96.64% | 2 0.11% 96.74% | 0 0.00% 96.74% | 1 0.05% 96.79% | 0 0.00% 96.79% | 61 3.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 1903 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 1017
-system.ruby.outstanding_req_hist::mean 15.607670
-system.ruby.outstanding_req_hist::gmean 15.500838
-system.ruby.outstanding_req_hist::stdev 1.236128
-system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.29% | 2 0.20% 0.49% | 2 0.20% 0.69% | 4 0.39% 1.08% | 3 0.29% 1.38% | 3 0.29% 1.67% | 233 22.91% 24.58% | 767 75.42% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 1017
+system.ruby.outstanding_req_hist::samples 1005
+system.ruby.outstanding_req_hist::mean 15.609950
+system.ruby.outstanding_req_hist::gmean 15.502410
+system.ruby.outstanding_req_hist::stdev 1.236521
+system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 4 0.40% 1.09% | 3 0.30% 1.39% | 4 0.40% 1.79% | 233 23.18% 24.98% | 754 75.02% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 1005
system.ruby.latency_hist::bucket_size 128
system.ruby.latency_hist::max_bucket 1279
-system.ruby.latency_hist::samples 1003
-system.ruby.latency_hist::mean 586.918245
-system.ruby.latency_hist::gmean 576.888257
-system.ruby.latency_hist::stdev 98.601394
-system.ruby.latency_hist | 2 0.20% 0.20% | 9 0.90% 1.10% | 6 0.60% 1.69% | 138 13.76% 15.45% | 667 66.50% 81.95% | 127 12.66% 94.62% | 42 4.19% 98.80% | 12 1.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 1003
+system.ruby.latency_hist::samples 992
+system.ruby.latency_hist::mean 594.351815
+system.ruby.latency_hist::gmean 584.578373
+system.ruby.latency_hist::stdev 96.099439
+system.ruby.latency_hist | 2 0.20% 0.20% | 9 0.91% 1.11% | 6 0.60% 1.71% | 111 11.19% 12.90% | 654 65.93% 78.83% | 154 15.52% 94.35% | 49 4.94% 99.29% | 7 0.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist::total 992
system.ruby.hit_latency_hist::bucket_size 128
system.ruby.hit_latency_hist::max_bucket 1279
-system.ruby.hit_latency_hist::samples 42
-system.ruby.hit_latency_hist::mean 502
-system.ruby.hit_latency_hist::gmean 497.343988
-system.ruby.hit_latency_hist::stdev 68.792371
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.38% 2.38% | 20 47.62% 50.00% | 20 47.62% 97.62% | 1 2.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 42
+system.ruby.hit_latency_hist::samples 39
+system.ruby.hit_latency_hist::mean 492.692308
+system.ruby.hit_latency_hist::gmean 488.844837
+system.ruby.hit_latency_hist::stdev 62.931522
+system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.56% 2.56% | 22 56.41% 58.97% | 15 38.46% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist::total 39
system.ruby.miss_latency_hist::bucket_size 128
system.ruby.miss_latency_hist::max_bucket 1279
-system.ruby.miss_latency_hist::samples 961
-system.ruby.miss_latency_hist::mean 590.629553
-system.ruby.miss_latency_hist::gmean 580.641121
-system.ruby.miss_latency_hist::stdev 98.062205
-system.ruby.miss_latency_hist | 2 0.21% 0.21% | 9 0.94% 1.14% | 5 0.52% 1.66% | 118 12.28% 13.94% | 647 67.33% 81.27% | 126 13.11% 94.38% | 42 4.37% 98.75% | 12 1.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist::total 961
-system.ruby.Directory.incomplete_times 961
-system.ruby.l1_cntrl0.cacheMemory.demand_hits 42 # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses 963 # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses 1005 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 6 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 127 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store
+system.ruby.miss_latency_hist::samples 953
+system.ruby.miss_latency_hist::mean 598.512067
+system.ruby.miss_latency_hist::gmean 588.872583
+system.ruby.miss_latency_hist::stdev 94.945507
+system.ruby.miss_latency_hist | 2 0.21% 0.21% | 9 0.94% 1.15% | 5 0.52% 1.68% | 89 9.34% 11.02% | 639 67.05% 78.07% | 153 16.05% 94.12% | 49 5.14% 99.27% | 7 0.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist::total 953
+system.ruby.Directory.incomplete_times 953
+system.ruby.l1_cntrl0.cacheMemory.demand_hits 39 # Number of cache demand hits
+system.ruby.l1_cntrl0.cacheMemory.demand_misses 955 # Number of cache demand misses
+system.ruby.l1_cntrl0.cacheMemory.demand_accesses 994 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 129 # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store
system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 12.694109
-system.ruby.network.routers0.msg_count.Control::2 961
-system.ruby.network.routers0.msg_count.Data::2 959
-system.ruby.network.routers0.msg_count.Response_Data::4 961
-system.ruby.network.routers0.msg_count.Writeback_Control::3 958
-system.ruby.network.routers0.msg_bytes.Control::2 7688
-system.ruby.network.routers0.msg_bytes.Data::2 69048
-system.ruby.network.routers0.msg_bytes.Response_Data::4 69192
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7664
-system.ruby.network.routers1.percent_links_utilized 12.691463
-system.ruby.network.routers1.msg_count.Control::2 961
-system.ruby.network.routers1.msg_count.Data::2 958
-system.ruby.network.routers1.msg_count.Response_Data::4 961
-system.ruby.network.routers1.msg_count.Writeback_Control::3 958
-system.ruby.network.routers1.msg_bytes.Control::2 7688
-system.ruby.network.routers1.msg_bytes.Data::2 68976
-system.ruby.network.routers1.msg_bytes.Response_Data::4 69192
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7664
-system.ruby.network.routers2.percent_links_utilized 12.691463
-system.ruby.network.routers2.msg_count.Control::2 961
-system.ruby.network.routers2.msg_count.Data::2 958
-system.ruby.network.routers2.msg_count.Response_Data::4 961
-system.ruby.network.routers2.msg_count.Writeback_Control::3 958
-system.ruby.network.routers2.msg_bytes.Control::2 7688
-system.ruby.network.routers2.msg_bytes.Data::2 68976
-system.ruby.network.routers2.msg_bytes.Response_Data::4 69192
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7664
-system.ruby.network.msg_count.Control 2883
-system.ruby.network.msg_count.Data 2875
-system.ruby.network.msg_count.Response_Data 2883
-system.ruby.network.msg_count.Writeback_Control 2874
-system.ruby.network.msg_byte.Control 23064
-system.ruby.network.msg_byte.Data 207000
-system.ruby.network.msg_byte.Response_Data 207576
-system.ruby.network.msg_byte.Writeback_Control 22992
-system.ruby.network.routers0.throttle0.link_utilization 12.707336
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 961
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 958
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 69192
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 7664
-system.ruby.network.routers0.throttle1.link_utilization 12.680881
-system.ruby.network.routers0.throttle1.msg_count.Control::2 961
-system.ruby.network.routers0.throttle1.msg_count.Data::2 959
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2 7688
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2 69048
-system.ruby.network.routers1.throttle0.link_utilization 12.675591
-system.ruby.network.routers1.throttle0.msg_count.Control::2 961
-system.ruby.network.routers1.throttle0.msg_count.Data::2 958
-system.ruby.network.routers1.throttle0.msg_bytes.Control::2 7688
-system.ruby.network.routers1.throttle0.msg_bytes.Data::2 68976
-system.ruby.network.routers1.throttle1.link_utilization 12.707336
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-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 958
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 69192
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 7664
-system.ruby.network.routers2.throttle0.link_utilization 12.707336
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 961
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 958
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 69192
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 7664
-system.ruby.network.routers2.throttle1.link_utilization 12.675591
-system.ruby.network.routers2.throttle1.msg_count.Control::2 961
-system.ruby.network.routers2.throttle1.msg_count.Data::2 958
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7688
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2 68976
+system.ruby.network.routers0.percent_links_utilized 12.606979
+system.ruby.network.routers0.msg_count.Control::2 953
+system.ruby.network.routers0.msg_count.Data::2 951
+system.ruby.network.routers0.msg_count.Response_Data::4 953
+system.ruby.network.routers0.msg_count.Writeback_Control::3 950
+system.ruby.network.routers0.msg_bytes.Control::2 7624
+system.ruby.network.routers0.msg_bytes.Data::2 68472
+system.ruby.network.routers0.msg_bytes.Response_Data::4 68616
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.routers1.percent_links_utilized 12.605654
+system.ruby.network.routers1.msg_count.Control::2 953
+system.ruby.network.routers1.msg_count.Data::2 950
+system.ruby.network.routers1.msg_count.Response_Data::4 953
+system.ruby.network.routers1.msg_count.Writeback_Control::3 950
+system.ruby.network.routers1.msg_bytes.Control::2 7624
+system.ruby.network.routers1.msg_bytes.Data::2 68400
+system.ruby.network.routers1.msg_bytes.Response_Data::4 68616
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.routers2.percent_links_utilized 12.605654
+system.ruby.network.routers2.msg_count.Control::2 953
+system.ruby.network.routers2.msg_count.Data::2 950
+system.ruby.network.routers2.msg_count.Response_Data::4 953
+system.ruby.network.routers2.msg_count.Writeback_Control::3 950
+system.ruby.network.routers2.msg_bytes.Control::2 7624
+system.ruby.network.routers2.msg_bytes.Data::2 68400
+system.ruby.network.routers2.msg_bytes.Response_Data::4 68616
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.msg_count.Control 2859
+system.ruby.network.msg_count.Data 2851
+system.ruby.network.msg_count.Response_Data 2859
+system.ruby.network.msg_count.Writeback_Control 2850
+system.ruby.network.msg_byte.Control 22872
+system.ruby.network.msg_byte.Data 205272
+system.ruby.network.msg_byte.Response_Data 205848
+system.ruby.network.msg_byte.Writeback_Control 22800
+system.ruby.network.routers0.throttle0.link_utilization 12.621552
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 953
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 950
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 68616
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.routers0.throttle1.link_utilization 12.592406
+system.ruby.network.routers0.throttle1.msg_count.Control::2 953
+system.ruby.network.routers0.throttle1.msg_count.Data::2 951
+system.ruby.network.routers0.throttle1.msg_bytes.Control::2 7624
+system.ruby.network.routers0.throttle1.msg_bytes.Data::2 68472
+system.ruby.network.routers1.throttle0.link_utilization 12.589756
+system.ruby.network.routers1.throttle0.msg_count.Control::2 953
+system.ruby.network.routers1.throttle0.msg_count.Data::2 950
+system.ruby.network.routers1.throttle0.msg_bytes.Control::2 7624
+system.ruby.network.routers1.throttle0.msg_bytes.Data::2 68400
+system.ruby.network.routers1.throttle1.link_utilization 12.621552
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 953
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 950
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 68616
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.routers2.throttle0.link_utilization 12.621552
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 953
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 950
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 68616
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.routers2.throttle1.link_utilization 12.589756
+system.ruby.network.routers2.throttle1.msg_count.Control::2 953
+system.ruby.network.routers2.throttle1.msg_count.Data::2 950
+system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7624
+system.ruby.network.routers2.throttle1.msg_bytes.Data::2 68400
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 961 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 961 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 961 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples 953 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 953 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total 953 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 958 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean 0.392484 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 1.475833 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 894 93.32% 93.32% | 0 0.00% 93.32% | 1 0.10% 93.42% | 0 0.00% 93.42% | 2 0.21% 93.63% | 0 0.00% 93.63% | 61 6.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 958 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples 950 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean 0.393684 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev 1.477888 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2 | 886 93.26% 93.26% | 0 0.00% 93.26% | 2 0.21% 93.47% | 0 0.00% 93.47% | 1 0.11% 93.58% | 0 0.00% 93.58% | 61 6.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total 950 # delay histogram for vnet_2
system.ruby.LD.latency_hist::bucket_size 128
system.ruby.LD.latency_hist::max_bucket 1279
-system.ruby.LD.latency_hist::samples 47
-system.ruby.LD.latency_hist::mean 581.170213
-system.ruby.LD.latency_hist::gmean 573.743591
-system.ruby.LD.latency_hist::stdev 97.598850
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-system.ruby.LD.hit_latency_hist::max_bucket 639
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system.ruby.LD.miss_latency_hist::bucket_size 128
system.ruby.LD.miss_latency_hist::max_bucket 1279
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-system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 21.74% 21.74% | 29 63.04% 84.78% | 4 8.70% 93.48% | 2 4.35% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.ST.latency_hist::bucket_size 128
system.ruby.ST.latency_hist::max_bucket 1279
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-system.ruby.ST.latency_hist::gmean 576.890095
-system.ruby.ST.latency_hist::stdev 99.206221
-system.ruby.ST.latency_hist | 2 0.22% 0.22% | 9 1.00% 1.22% | 6 0.66% 1.88% | 116 12.85% 14.73% | 602 66.67% 81.40% | 120 13.29% 94.68% | 37 4.10% 98.78% | 11 1.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.ST.latency_hist::gmean 581.152835
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+system.ruby.ST.latency_hist | 2 0.22% 0.22% | 9 1.01% 1.23% | 6 0.67% 1.91% | 103 11.55% 13.45% | 591 66.26% 79.71% | 135 15.13% 94.84% | 39 4.37% 99.22% | 7 0.78% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist::total 892
system.ruby.ST.hit_latency_hist::bucket_size 128
system.ruby.ST.hit_latency_hist::max_bucket 1279
-system.ruby.ST.hit_latency_hist::samples 41
-system.ruby.ST.hit_latency_hist::mean 504.829268
-system.ruby.ST.hit_latency_hist::gmean 500.427879
-system.ruby.ST.hit_latency_hist::stdev 67.127454
-system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.44% 2.44% | 19 46.34% 48.78% | 20 48.78% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 41
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+system.ruby.ST.hit_latency_hist::gmean 487.637688
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+system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.63% 2.63% | 22 57.89% 60.53% | 14 36.84% 97.37% | 1 2.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.hit_latency_hist::total 38
system.ruby.ST.miss_latency_hist::bucket_size 128
system.ruby.ST.miss_latency_hist::max_bucket 1279
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-system.ruby.ST.miss_latency_hist::gmean 580.804835
-system.ruby.ST.miss_latency_hist::stdev 98.803760
-system.ruby.ST.miss_latency_hist | 2 0.23% 0.23% | 9 1.04% 1.28% | 5 0.58% 1.86% | 97 11.25% 13.11% | 582 67.52% 80.63% | 119 13.81% 94.43% | 37 4.29% 98.72% | 11 1.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.ST.miss_latency_hist | 2 0.23% 0.23% | 9 1.05% 1.29% | 5 0.59% 1.87% | 81 9.48% 11.36% | 577 67.56% 78.92% | 134 15.69% 94.61% | 39 4.57% 99.18% | 7 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist::total 854
system.ruby.IFETCH.latency_hist::bucket_size 128
system.ruby.IFETCH.latency_hist::max_bucket 1279
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-system.ruby.IFETCH.latency_hist::gmean 579.659874
-system.ruby.IFETCH.latency_hist::stdev 90.344820
-system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 20.75% 20.75% | 36 67.92% 88.68% | 3 5.66% 94.34% | 3 5.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 53
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+system.ruby.IFETCH.latency_hist::mean 623.140000
+system.ruby.IFETCH.latency_hist::gmean 615.727796
+system.ruby.IFETCH.latency_hist::stdev 99.820044
+system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.00% 10.00% | 30 60.00% 70.00% | 9 18.00% 88.00% | 6 12.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist::total 50
+system.ruby.IFETCH.hit_latency_hist::bucket_size 64
+system.ruby.IFETCH.hit_latency_hist::max_bucket 639
+system.ruby.IFETCH.hit_latency_hist::samples 1
+system.ruby.IFETCH.hit_latency_hist::mean 537
+system.ruby.IFETCH.hit_latency_hist::gmean 537.000000
+system.ruby.IFETCH.hit_latency_hist::stdev nan
+system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist::total 1
system.ruby.IFETCH.miss_latency_hist::bucket_size 128
system.ruby.IFETCH.miss_latency_hist::max_bucket 1279
-system.ruby.IFETCH.miss_latency_hist::samples 53
-system.ruby.IFETCH.miss_latency_hist::mean 586.075472
-system.ruby.IFETCH.miss_latency_hist::gmean 579.659874
-system.ruby.IFETCH.miss_latency_hist::stdev 90.344820
-system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 20.75% 20.75% | 36 67.92% 88.68% | 3 5.66% 94.34% | 3 5.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist::total 53
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+system.ruby.IFETCH.miss_latency_hist::mean 624.897959
+system.ruby.IFETCH.miss_latency_hist::gmean 617.449297
+system.ruby.IFETCH.miss_latency_hist::stdev 100.069402
+system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.20% 10.20% | 29 59.18% 69.39% | 9 18.37% 87.76% | 6 12.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist::total 49
system.ruby.Directory.miss_mach_latency_hist::bucket_size 128
system.ruby.Directory.miss_mach_latency_hist::max_bucket 1279
-system.ruby.Directory.miss_mach_latency_hist::samples 961
-system.ruby.Directory.miss_mach_latency_hist::mean 590.629553
-system.ruby.Directory.miss_mach_latency_hist::gmean 580.641121
-system.ruby.Directory.miss_mach_latency_hist::stdev 98.062205
-system.ruby.Directory.miss_mach_latency_hist | 2 0.21% 0.21% | 9 0.94% 1.14% | 5 0.52% 1.66% | 118 12.28% 13.94% | 647 67.33% 81.27% | 126 13.11% 94.38% | 42 4.37% 98.75% | 12 1.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist::total 961
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+system.ruby.Directory.miss_mach_latency_hist::gmean 588.872583
+system.ruby.Directory.miss_mach_latency_hist::stdev 94.945507
+system.ruby.Directory.miss_mach_latency_hist | 2 0.21% 0.21% | 9 0.94% 1.15% | 5 0.52% 1.68% | 89 9.34% 11.02% | 639 67.05% 78.07% | 153 16.05% 94.12% | 49 5.14% 99.27% | 7 0.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist::total 953
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 128
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 1279
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 46
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 585.413043
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 578.708439
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 94.193082
-system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 21.74% 21.74% | 29 63.04% 84.78% | 4 8.70% 93.48% | 2 4.35% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total 46
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+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 620.660000
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 616.355454
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 75.297399
+system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 33 66.00% 72.00% | 10 20.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::total 50
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 128
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 1279
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 862
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 591.187935
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 580.804835
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 98.803760
-system.ruby.ST.Directory.miss_type_mach_latency_hist | 2 0.23% 0.23% | 9 1.04% 1.28% | 5 0.58% 1.86% | 97 11.25% 13.11% | 582 67.52% 80.63% | 119 13.81% 94.43% | 37 4.29% 98.72% | 11 1.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total 862
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 854
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 595.701405
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 585.707367
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 95.367967
+system.ruby.ST.Directory.miss_type_mach_latency_hist | 2 0.23% 0.23% | 9 1.05% 1.29% | 5 0.59% 1.87% | 81 9.48% 11.36% | 577 67.56% 78.92% | 134 15.69% 94.61% | 39 4.57% 99.18% | 7 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total 854
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 128
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 1279
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 53
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 586.075472
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 579.659874
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 90.344820
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 20.75% 20.75% | 36 67.92% 88.68% | 3 5.66% 94.34% | 3 5.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 53
-system.ruby.Directory_Controller.GETX 961 0.00% 0.00%
-system.ruby.Directory_Controller.PUTX 958 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 961 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 958 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETX 961 0.00% 0.00%
-system.ruby.Directory_Controller.M.PUTX 958 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 961 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 958 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 47 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 53 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 905 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 961 0.00% 0.00%
-system.ruby.L1Cache_Controller.Replacement 960 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 958 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 46 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 53 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 864 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Store 41 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Replacement 960 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack 958 0.00% 0.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 49
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 624.897959
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 617.449297
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 100.069402
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.20% 10.20% | 29 59.18% 69.39% | 9 18.37% 87.76% | 6 12.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 49
+system.ruby.Directory_Controller.GETX 953 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 950 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 953 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 950 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 953 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 950 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 953 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 950 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 50 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 51 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 893 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 953 0.00% 0.00%
+system.ruby.L1Cache_Controller.Replacement 952 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 950 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 50 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 50 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 855 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 1 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 38 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Replacement 952 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack 950 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 99 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data 862 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data 854 0.00% 0.00%
---------- End Simulation Statistics ----------