diff options
Diffstat (limited to 'tests/quick/se/60.rubytest/ref')
10 files changed, 531 insertions, 3454 deletions
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats index bcd995136..a927269a7 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats @@ -1,4 +1,4 @@ -Real time: Feb/02/2013 08:14:08 +Real time: Jun/08/2013 14:12:22 Profiler Stats -------------- @@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.56 -Virtual_time_in_minutes: 0.00933333 -Virtual_time_in_hours: 0.000155556 -Virtual_time_in_days: 6.48148e-06 +Virtual_time_in_seconds: 0.55 +Virtual_time_in_minutes: 0.00916667 +Virtual_time_in_hours: 0.000152778 +Virtual_time_in_days: 6.36574e-06 Ruby_current_time: 318321 Ruby_start_time: 0 Ruby_cycles: 318321 -mbytes_resident: 49.3398 -mbytes_total: 265.707 -resident_ratio: 0.185751 - -ruby_cycles_executed: [ 318322 ] +mbytes_resident: 51.1211 +mbytes_total: 139.629 +resident_ratio: 0.366177 Busy Controller Counts: L1Cache-0:0 @@ -61,7 +59,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -82,11 +79,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10276 -page_faults: 11 +page_reclaims: 9776 +page_faults: 0 swaps: 0 -block_inputs: 16 -block_outputs: 248 +block_inputs: 8 +block_outputs: 80 Network Stats ------------- @@ -160,458 +157,3 @@ links_utilized_percent_switch_3: 2.05746 outgoing_messages_switch_3_link_2_Response_Data: 786 56592 [ 0 786 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Response_Control: 84 672 [ 0 84 0 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [44 ] 44 -Ifetch [67 ] 67 -Store [898 ] 898 -Inv [563 ] 563 -L1_Replacement [10398 ] 10398 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_GET_INSTR [0 ] 0 -Data [0 ] 0 -Data_Exclusive [41 ] 41 -DataS_fromL1 [0 ] 0 -Data_all_Acks [874 ] 874 -Ack [0 ] 0 -Ack_all [1 ] 1 -WB_Ack [755 ] 755 -PF_Load [0 ] 0 -PF_Ifetch [0 ] 0 -PF_Store [0 ] 0 - - - Transitions - -NP Load [42 ] 42 -NP Ifetch [56 ] 56 -NP Store [818 ] 818 -NP Inv [1 ] 1 -NP L1_Replacement [0 ] 0 -NP PF_Load [0 ] 0 -NP PF_Ifetch [0 ] 0 -NP PF_Store [0 ] 0 - -I Load [0 ] 0 -I Ifetch [0 ] 0 -I Store [0 ] 0 -I Inv [0 ] 0 -I L1_Replacement [145 ] 145 -I PF_Load [0 ] 0 -I PF_Ifetch [0 ] 0 -I PF_Store [0 ] 0 - -S Load [0 ] 0 -S Ifetch [0 ] 0 -S Store [1 ] 1 -S Inv [31 ] 31 -S L1_Replacement [11 ] 11 -S PF_Load [0 ] 0 -S PF_Store [0 ] 0 - -E Load [0 ] 0 -E Ifetch [0 ] 0 -E Store [2 ] 2 -E Inv [4 ] 4 -E L1_Replacement [34 ] 34 -E Fwd_GETX [0 ] 0 -E Fwd_GETS [0 ] 0 -E Fwd_GET_INSTR [0 ] 0 -E PF_Load [0 ] 0 -E PF_Store [0 ] 0 - -M Load [2 ] 2 -M Ifetch [0 ] 0 -M Store [77 ] 77 -M Inv [97 ] 97 -M L1_Replacement [722 ] 722 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_GET_INSTR [0 ] 0 -M PF_Load [0 ] 0 -M PF_Store [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS Inv [14 ] 14 -IS L1_Replacement [374 ] 374 -IS Data_Exclusive [41 ] 41 -IS DataS_fromL1 [0 ] 0 -IS Data_all_Acks [43 ] 43 -IS PF_Load [0 ] 0 -IS PF_Store [0 ] 0 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM Inv [0 ] 0 -IM L1_Replacement [9112 ] 9112 -IM Data [0 ] 0 -IM Data_all_Acks [817 ] 817 -IM Ack [0 ] 0 -IM PF_Load [0 ] 0 -IM PF_Store [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM Inv [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Ack [0 ] 0 -SM Ack_all [1 ] 1 -SM PF_Load [0 ] 0 -SM PF_Store [0 ] 0 - -IS_I Load [0 ] 0 -IS_I Ifetch [0 ] 0 -IS_I Store [0 ] 0 -IS_I Inv [0 ] 0 -IS_I L1_Replacement [0 ] 0 -IS_I Data_Exclusive [0 ] 0 -IS_I DataS_fromL1 [0 ] 0 -IS_I Data_all_Acks [14 ] 14 -IS_I PF_Load [0 ] 0 -IS_I PF_Store [0 ] 0 - -M_I Load [0 ] 0 -M_I Ifetch [10 ] 10 -M_I Store [0 ] 0 -M_I Inv [416 ] 416 -M_I L1_Replacement [0 ] 0 -M_I Fwd_GETX [0 ] 0 -M_I Fwd_GETS [0 ] 0 -M_I Fwd_GET_INSTR [0 ] 0 -M_I WB_Ack [340 ] 340 -M_I PF_Load [0 ] 0 -M_I PF_Store [0 ] 0 - -SINK_WB_ACK Load [0 ] 0 -SINK_WB_ACK Ifetch [1 ] 1 -SINK_WB_ACK Store [0 ] 0 -SINK_WB_ACK Inv [0 ] 0 -SINK_WB_ACK L1_Replacement [0 ] 0 -SINK_WB_ACK WB_Ack [415 ] 415 -SINK_WB_ACK PF_Load [0 ] 0 -SINK_WB_ACK PF_Store [0 ] 0 - -PF_IS Load [0 ] 0 -PF_IS Ifetch [0 ] 0 -PF_IS Store [0 ] 0 -PF_IS Inv [0 ] 0 -PF_IS L1_Replacement [0 ] 0 -PF_IS Data_Exclusive [0 ] 0 -PF_IS DataS_fromL1 [0 ] 0 -PF_IS Data_all_Acks [0 ] 0 -PF_IS PF_Load [0 ] 0 -PF_IS PF_Store [0 ] 0 - -PF_IM Load [0 ] 0 -PF_IM Ifetch [0 ] 0 -PF_IM Store [0 ] 0 -PF_IM Inv [0 ] 0 -PF_IM L1_Replacement [0 ] 0 -PF_IM Data [0 ] 0 -PF_IM Data_all_Acks [0 ] 0 -PF_IM Ack [0 ] 0 -PF_IM PF_Load [0 ] 0 -PF_IM PF_Store [0 ] 0 - -PF_SM Load [0 ] 0 -PF_SM Ifetch [0 ] 0 -PF_SM Store [0 ] 0 -PF_SM Inv [0 ] 0 -PF_SM L1_Replacement [0 ] 0 -PF_SM Ack [0 ] 0 -PF_SM Ack_all [0 ] 0 - -PF_IS_I Load [0 ] 0 -PF_IS_I Store [0 ] 0 -PF_IS_I Inv [0 ] 0 -PF_IS_I L1_Replacement [0 ] 0 -PF_IS_I Data_Exclusive [0 ] 0 -PF_IS_I DataS_fromL1 [0 ] 0 -PF_IS_I Data_all_Acks [0 ] 0 - - --- L2Cache --- - - Event Counts - -L1_GET_INSTR [56 ] 56 -L1_GETS [42 ] 42 -L1_GETX [818 ] 818 -L1_UPGRADE [1 ] 1 -L1_PUTX [345 ] 345 -L1_PUTX_old [796 ] 796 -Fwd_L1_GETX [0 ] 0 -Fwd_L1_GETS [0 ] 0 -Fwd_L1_GET_INSTR [0 ] 0 -L2_Replacement [291 ] 291 -L2_Replacement_clean [1216 ] 1216 -Mem_Data [873 ] 873 -Mem_Ack [869 ] 869 -WB_Data [495 ] 495 -WB_Data_clean [18 ] 18 -Ack [0 ] 0 -Ack_all [50 ] 50 -Unblock [0 ] 0 -Unblock_Cancel [0 ] 0 -Exclusive_Unblock [858 ] 858 -MEM_Inv [0 ] 0 - - - Transitions - -NP L1_GET_INSTR [46 ] 46 -NP L1_GETS [41 ] 41 -NP L1_GETX [787 ] 787 -NP L1_PUTX [0 ] 0 -NP L1_PUTX_old [302 ] 302 - -SS L1_GET_INSTR [0 ] 0 -SS L1_GETS [1 ] 1 -SS L1_GETX [9 ] 9 -SS L1_UPGRADE [1 ] 1 -SS L1_PUTX [0 ] 0 -SS L1_PUTX_old [0 ] 0 -SS L2_Replacement [0 ] 0 -SS L2_Replacement_clean [46 ] 46 -SS MEM_Inv [0 ] 0 - -M L1_GET_INSTR [10 ] 10 -M L1_GETS [0 ] 0 -M L1_GETX [22 ] 22 -M L1_PUTX [0 ] 0 -M L1_PUTX_old [0 ] 0 -M L2_Replacement [291 ] 291 -M L2_Replacement_clean [16 ] 16 -M MEM_Inv [0 ] 0 - -MT L1_GET_INSTR [0 ] 0 -MT L1_GETS [0 ] 0 -MT L1_GETX [0 ] 0 -MT L1_PUTX [340 ] 340 -MT L1_PUTX_old [0 ] 0 -MT L2_Replacement [0 ] 0 -MT L2_Replacement_clean [517 ] 517 -MT MEM_Inv [0 ] 0 - -M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [0 ] 0 -M_I L1_GETX [0 ] 0 -M_I L1_UPGRADE [0 ] 0 -M_I L1_PUTX [0 ] 0 -M_I L1_PUTX_old [113 ] 113 -M_I Mem_Ack [869 ] 869 -M_I MEM_Inv [0 ] 0 - -MT_I L1_GET_INSTR [0 ] 0 -MT_I L1_GETS [0 ] 0 -MT_I L1_GETX [0 ] 0 -MT_I L1_UPGRADE [0 ] 0 -MT_I L1_PUTX [0 ] 0 -MT_I L1_PUTX_old [0 ] 0 -MT_I WB_Data [0 ] 0 -MT_I WB_Data_clean [0 ] 0 -MT_I Ack_all [0 ] 0 -MT_I MEM_Inv [0 ] 0 - -MCT_I L1_GET_INSTR [0 ] 0 -MCT_I L1_GETS [0 ] 0 -MCT_I L1_GETX [0 ] 0 -MCT_I L1_UPGRADE [0 ] 0 -MCT_I L1_PUTX [0 ] 0 -MCT_I L1_PUTX_old [210 ] 210 -MCT_I WB_Data [495 ] 495 -MCT_I WB_Data_clean [18 ] 18 -MCT_I Ack_all [4 ] 4 - -I_I L1_GET_INSTR [0 ] 0 -I_I L1_GETS [0 ] 0 -I_I L1_GETX [0 ] 0 -I_I L1_UPGRADE [0 ] 0 -I_I L1_PUTX [0 ] 0 -I_I L1_PUTX_old [0 ] 0 -I_I Ack [0 ] 0 -I_I Ack_all [46 ] 46 - -S_I L1_GET_INSTR [0 ] 0 -S_I L1_GETS [0 ] 0 -S_I L1_GETX [0 ] 0 -S_I L1_UPGRADE [0 ] 0 -S_I L1_PUTX [0 ] 0 -S_I L1_PUTX_old [0 ] 0 -S_I Ack [0 ] 0 -S_I Ack_all [0 ] 0 -S_I MEM_Inv [0 ] 0 - -ISS L1_GET_INSTR [0 ] 0 -ISS L1_GETS [0 ] 0 -ISS L1_GETX [0 ] 0 -ISS L1_PUTX [0 ] 0 -ISS L1_PUTX_old [0 ] 0 -ISS L2_Replacement [0 ] 0 -ISS L2_Replacement_clean [11 ] 11 -ISS Mem_Data [41 ] 41 -ISS MEM_Inv [0 ] 0 - -IS L1_GET_INSTR [0 ] 0 -IS L1_GETS [0 ] 0 -IS L1_GETX [0 ] 0 -IS L1_PUTX [0 ] 0 -IS L1_PUTX_old [0 ] 0 -IS L2_Replacement [0 ] 0 -IS L2_Replacement_clean [57 ] 57 -IS Mem_Data [46 ] 46 -IS MEM_Inv [0 ] 0 - -IM L1_GET_INSTR [0 ] 0 -IM L1_GETS [0 ] 0 -IM L1_GETX [0 ] 0 -IM L1_PUTX [0 ] 0 -IM L1_PUTX_old [0 ] 0 -IM L2_Replacement [0 ] 0 -IM L2_Replacement_clean [219 ] 219 -IM Mem_Data [786 ] 786 -IM MEM_Inv [0 ] 0 - -SS_MB L1_GET_INSTR [0 ] 0 -SS_MB L1_GETS [0 ] 0 -SS_MB L1_GETX [0 ] 0 -SS_MB L1_UPGRADE [0 ] 0 -SS_MB L1_PUTX [0 ] 0 -SS_MB L1_PUTX_old [0 ] 0 -SS_MB L2_Replacement [0 ] 0 -SS_MB L2_Replacement_clean [0 ] 0 -SS_MB Unblock_Cancel [0 ] 0 -SS_MB Exclusive_Unblock [10 ] 10 -SS_MB MEM_Inv [0 ] 0 - -MT_MB L1_GET_INSTR [0 ] 0 -MT_MB L1_GETS [0 ] 0 -MT_MB L1_GETX [0 ] 0 -MT_MB L1_UPGRADE [0 ] 0 -MT_MB L1_PUTX [5 ] 5 -MT_MB L1_PUTX_old [171 ] 171 -MT_MB L2_Replacement [0 ] 0 -MT_MB L2_Replacement_clean [350 ] 350 -MT_MB Unblock_Cancel [0 ] 0 -MT_MB Exclusive_Unblock [848 ] 848 -MT_MB MEM_Inv [0 ] 0 - -MT_IIB L1_GET_INSTR [0 ] 0 -MT_IIB L1_GETS [0 ] 0 -MT_IIB L1_GETX [0 ] 0 -MT_IIB L1_UPGRADE [0 ] 0 -MT_IIB L1_PUTX [0 ] 0 -MT_IIB L1_PUTX_old [0 ] 0 -MT_IIB L2_Replacement [0 ] 0 -MT_IIB L2_Replacement_clean [0 ] 0 -MT_IIB WB_Data [0 ] 0 -MT_IIB WB_Data_clean [0 ] 0 -MT_IIB Unblock [0 ] 0 -MT_IIB MEM_Inv [0 ] 0 - -MT_IB L1_GET_INSTR [0 ] 0 -MT_IB L1_GETS [0 ] 0 -MT_IB L1_GETX [0 ] 0 -MT_IB L1_UPGRADE [0 ] 0 -MT_IB L1_PUTX [0 ] 0 -MT_IB L1_PUTX_old [0 ] 0 -MT_IB L2_Replacement [0 ] 0 -MT_IB L2_Replacement_clean [0 ] 0 -MT_IB WB_Data [0 ] 0 -MT_IB WB_Data_clean [0 ] 0 -MT_IB Unblock_Cancel [0 ] 0 -MT_IB MEM_Inv [0 ] 0 - -MT_SB L1_GET_INSTR [0 ] 0 -MT_SB L1_GETS [0 ] 0 -MT_SB L1_GETX [0 ] 0 -MT_SB L1_UPGRADE [0 ] 0 -MT_SB L1_PUTX [0 ] 0 -MT_SB L1_PUTX_old [0 ] 0 -MT_SB L2_Replacement [0 ] 0 -MT_SB L2_Replacement_clean [0 ] 0 -MT_SB Unblock [0 ] 0 -MT_SB MEM_Inv [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 1660 - memory_reads: 874 - memory_writes: 786 - memory_refreshes: 2210 - memory_total_request_delays: 601 - memory_delays_per_request: 0.362048 - memory_delays_in_input_queue: 44 - memory_delays_behind_head_of_bank_queue: 2 - memory_delays_stalled_at_head_of_bank_queue: 555 - memory_stalls_for_bank_busy: 169 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 30 - memory_stalls_for_bus: 188 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 104 - memory_stalls_for_read_read_turnaround: 64 - accesses_per_bank: 42 51 50 73 73 71 65 49 54 41 50 44 58 48 47 63 57 47 58 57 41 49 46 49 57 45 42 49 45 53 48 38 - - --- Directory --- - - Event Counts - -Fetch [874 ] 874 -Data [786 ] 786 -Memory_Data [874 ] 874 -Memory_Ack [786 ] 786 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -CleanReplacement [84 ] 84 - - - Transitions - -I Fetch [874 ] 874 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -ID Fetch [0 ] 0 -ID Data [0 ] 0 -ID Memory_Data [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 - -ID_W Fetch [0 ] 0 -ID_W Data [0 ] 0 -ID_W Memory_Ack [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 - -M Data [786 ] 786 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 -M CleanReplacement [84 ] 84 - -IM Fetch [0 ] 0 -IM Data [0 ] 0 -IM Memory_Data [874 ] 874 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 - -MI Fetch [0 ] 0 -MI Data [0 ] 0 -MI Memory_Ack [786 ] 786 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 - -M_DRD Data [0 ] 0 -M_DRD DMA_READ [0 ] 0 -M_DRD DMA_WRITE [0 ] 0 - -M_DRDI Fetch [0 ] 0 -M_DRDI Data [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 -M_DRDI DMA_READ [0 ] 0 -M_DRDI DMA_WRITE [0 ] 0 - -M_DWR Data [0 ] 0 -M_DWR DMA_READ [0 ] 0 -M_DWR DMA_WRITE [0 ] 0 - -M_DWRI Fetch [0 ] 0 -M_DWRI Data [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 -M_DWRI DMA_READ [0 ] 0 -M_DWRI DMA_WRITE [0 ] 0 - diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt index 00381e46a..8eb1e41c8 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000318 # Nu sim_ticks 318321 # Number of ticks simulated final_tick 318321 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1383719 # Simulator tick rate (ticks/s) -host_mem_usage 149800 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_tick_rate 2084436 # Simulator tick rate (ticks/s) +host_mem_usage 142984 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host system.ruby.l2_cntrl0.L2cache.demand_hits 43 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 874 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 917 # Number of cache demand accesses @@ -25,5 +25,115 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.dir_cntrl0.memBuffer.memReq 1660 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 874 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 786 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 2210 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 555 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 44 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 601 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.362048 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 169 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 188 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 104 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 64 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 30 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 42 2.53% 2.53% | 51 3.07% 5.60% | 50 3.01% 8.61% | 73 4.40% 13.01% | 73 4.40% 17.41% | 71 4.28% 21.69% | 65 3.92% 25.60% | 49 2.95% 28.55% | 54 3.25% 31.81% | 41 2.47% 34.28% | 50 3.01% 37.29% | 44 2.65% 39.94% | 58 3.49% 43.43% | 48 2.89% 46.33% | 47 2.83% 49.16% | 63 3.80% 52.95% | 57 3.43% 56.39% | 47 2.83% 59.22% | 58 3.49% 62.71% | 57 3.43% 66.14% | 41 2.47% 68.61% | 49 2.95% 71.57% | 46 2.77% 74.34% | 49 2.95% 77.29% | 57 3.43% 80.72% | 45 2.71% 83.43% | 42 2.53% 85.96% | 49 2.95% 88.92% | 45 2.71% 91.63% | 53 3.19% 94.82% | 48 2.89% 97.71% | 38 2.29% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1660 # Number of accesses per bank + +system.ruby.l2_cntrl0.L1_GET_INSTR 56 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETS 42 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 818 0.00% 0.00% +system.ruby.l2_cntrl0.L1_UPGRADE 1 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX 345 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX_old 796 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 291 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement_clean 1216 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Data 873 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Ack 869 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data 495 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data_clean 18 0.00% 0.00% +system.ruby.l2_cntrl0.Ack_all 50 0.00% 0.00% +system.ruby.l2_cntrl0.Exclusive_Unblock 858 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GET_INSTR 46 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 41 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 787 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_PUTX_old 302 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GETS 1 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GETX 9 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_UPGRADE 1 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L2_Replacement_clean 46 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GET_INSTR 10 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 22 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 291 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement_clean 16 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_PUTX 340 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement_clean 517 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.L1_PUTX_old 113 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.Mem_Ack 869 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.L1_PUTX_old 210 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.WB_Data 495 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.WB_Data_clean 18 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.Ack_all 4 0.00% 0.00% +system.ruby.l2_cntrl0.I_I.Ack_all 46 0.00% 0.00% +system.ruby.l2_cntrl0.ISS.L2_Replacement_clean 11 0.00% 0.00% +system.ruby.l2_cntrl0.ISS.Mem_Data 41 0.00% 0.00% +system.ruby.l2_cntrl0.IS.L2_Replacement_clean 57 0.00% 0.00% +system.ruby.l2_cntrl0.IS.Mem_Data 46 0.00% 0.00% +system.ruby.l2_cntrl0.IM.L2_Replacement_clean 219 0.00% 0.00% +system.ruby.l2_cntrl0.IM.Mem_Data 786 0.00% 0.00% +system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 10 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.L1_PUTX 5 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.L1_PUTX_old 171 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.L2_Replacement_clean 350 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 848 0.00% 0.00% +system.ruby.l1_cntrl0.Load 44 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 67 0.00% 0.00% +system.ruby.l1_cntrl0.Store 898 0.00% 0.00% +system.ruby.l1_cntrl0.Inv 563 0.00% 0.00% +system.ruby.l1_cntrl0.L1_Replacement 10398 0.00% 0.00% +system.ruby.l1_cntrl0.Data_Exclusive 41 0.00% 0.00% +system.ruby.l1_cntrl0.Data_all_Acks 874 0.00% 0.00% +system.ruby.l1_cntrl0.Ack_all 1 0.00% 0.00% +system.ruby.l1_cntrl0.WB_Ack 755 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Load 42 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Ifetch 56 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Store 818 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Inv 1 0.00% 0.00% +system.ruby.l1_cntrl0.I.L1_Replacement 145 0.00% 0.00% +system.ruby.l1_cntrl0.S.Store 1 0.00% 0.00% +system.ruby.l1_cntrl0.S.Inv 31 0.00% 0.00% +system.ruby.l1_cntrl0.S.L1_Replacement 11 0.00% 0.00% +system.ruby.l1_cntrl0.E.Store 2 0.00% 0.00% +system.ruby.l1_cntrl0.E.Inv 4 0.00% 0.00% +system.ruby.l1_cntrl0.E.L1_Replacement 34 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 2 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 77 0.00% 0.00% +system.ruby.l1_cntrl0.M.Inv 97 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_Replacement 722 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Inv 14 0.00% 0.00% +system.ruby.l1_cntrl0.IS.L1_Replacement 374 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_Exclusive 41 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_all_Acks 43 0.00% 0.00% +system.ruby.l1_cntrl0.IM.L1_Replacement 9112 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data_all_Acks 817 0.00% 0.00% +system.ruby.l1_cntrl0.SM.Ack_all 1 0.00% 0.00% +system.ruby.l1_cntrl0.IS_I.Data_all_Acks 14 0.00% 0.00% +system.ruby.l1_cntrl0.M_I.Ifetch 10 0.00% 0.00% +system.ruby.l1_cntrl0.M_I.Inv 416 0.00% 0.00% +system.ruby.l1_cntrl0.M_I.WB_Ack 340 0.00% 0.00% +system.ruby.l1_cntrl0.SINK_WB_ACK.Ifetch 1 0.00% 0.00% +system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack 415 0.00% 0.00% +system.ruby.dir_cntrl0.Fetch 874 0.00% 0.00% +system.ruby.dir_cntrl0.Data 786 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 874 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 786 0.00% 0.00% +system.ruby.dir_cntrl0.CleanReplacement 84 0.00% 0.00% +system.ruby.dir_cntrl0.I.Fetch 874 0.00% 0.00% +system.ruby.dir_cntrl0.M.Data 786 0.00% 0.00% +system.ruby.dir_cntrl0.M.CleanReplacement 84 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 874 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 786 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats index 6a1258780..b47558017 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats @@ -1,26 +1,24 @@ -Real time: Feb/02/2013 08:16:59 +Real time: Jun/08/2013 14:14:03 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.74 -Virtual_time_in_minutes: 0.0123333 -Virtual_time_in_hours: 0.000205556 -Virtual_time_in_days: 8.56481e-06 +Virtual_time_in_seconds: 0.8 +Virtual_time_in_minutes: 0.0133333 +Virtual_time_in_hours: 0.000222222 +Virtual_time_in_days: 9.25926e-06 Ruby_current_time: 327361 Ruby_start_time: 0 Ruby_cycles: 327361 -mbytes_resident: 49.6445 -mbytes_total: 265.777 -resident_ratio: 0.186849 - -ruby_cycles_executed: [ 327362 ] +mbytes_resident: 52.7734 +mbytes_total: 140.672 +resident_ratio: 0.375208 Busy Controller Counts: L1Cache-0:0 @@ -61,7 +59,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -82,7 +79,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 9414 +page_reclaims: 10707 page_faults: 0 swaps: 0 block_inputs: 0 @@ -164,1246 +161,3 @@ links_utilized_percent_switch_3: 1.93247 outgoing_messages_switch_3_link_2_Writeback_Control: 925 7400 [ 0 845 80 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Unblock_Control: 852 6816 [ 0 0 852 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [44 ] 44 -Ifetch [192 ] 192 -Store [1001 ] 1001 -L1_Replacement [465203 ] 465203 -Own_GETX [0 ] 0 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_DMA [0 ] 0 -Inv [0 ] 0 -Ack [0 ] 0 -Data [0 ] 0 -Exclusive_Data [907 ] 907 -Writeback_Ack [0 ] 0 -Writeback_Ack_Data [903 ] 903 -Writeback_Nack [0 ] 0 -All_acks [813 ] 813 -Use_Timeout [905 ] 905 - - - Transitions - -I Load [38 ] 38 -I Ifetch [56 ] 56 -I Store [814 ] 814 -I L1_Replacement [0 ] 0 -I Inv [0 ] 0 - -S Load [0 ] 0 -S Ifetch [0 ] 0 -S Store [0 ] 0 -S L1_Replacement [0 ] 0 -S Fwd_GETS [0 ] 0 -S Fwd_DMA [0 ] 0 -S Inv [0 ] 0 - -O Load [0 ] 0 -O Ifetch [0 ] 0 -O Store [0 ] 0 -O L1_Replacement [0 ] 0 -O Fwd_GETX [0 ] 0 -O Fwd_GETS [0 ] 0 -O Fwd_DMA [0 ] 0 - -M Load [0 ] 0 -M Ifetch [0 ] 0 -M Store [0 ] 0 -M L1_Replacement [92 ] 92 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_DMA [0 ] 0 - -M_W Load [0 ] 0 -M_W Ifetch [0 ] 0 -M_W Store [0 ] 0 -M_W L1_Replacement [1319 ] 1319 -M_W Own_GETX [0 ] 0 -M_W Fwd_GETX [0 ] 0 -M_W Fwd_GETS [0 ] 0 -M_W Fwd_DMA [0 ] 0 -M_W Inv [0 ] 0 -M_W Use_Timeout [93 ] 93 - -MM Load [6 ] 6 -MM Ifetch [0 ] 0 -MM Store [66 ] 66 -MM L1_Replacement [811 ] 811 -MM Fwd_GETX [0 ] 0 -MM Fwd_GETS [0 ] 0 -MM Fwd_DMA [0 ] 0 - -MM_W Load [0 ] 0 -MM_W Ifetch [0 ] 0 -MM_W Store [6 ] 6 -MM_W L1_Replacement [29843 ] 29843 -MM_W Own_GETX [0 ] 0 -MM_W Fwd_GETX [0 ] 0 -MM_W Fwd_GETS [0 ] 0 -MM_W Fwd_DMA [0 ] 0 -MM_W Inv [0 ] 0 -MM_W Use_Timeout [812 ] 812 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM L1_Replacement [399867 ] 399867 -IM Inv [0 ] 0 -IM Ack [0 ] 0 -IM Data [0 ] 0 -IM Exclusive_Data [813 ] 813 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Fwd_GETS [0 ] 0 -SM Fwd_DMA [0 ] 0 -SM Inv [0 ] 0 -SM Ack [0 ] 0 -SM Data [0 ] 0 -SM Exclusive_Data [0 ] 0 - -OM Load [0 ] 0 -OM Ifetch [0 ] 0 -OM Store [0 ] 0 -OM L1_Replacement [17168 ] 17168 -OM Own_GETX [0 ] 0 -OM Fwd_GETX [0 ] 0 -OM Fwd_GETS [0 ] 0 -OM Fwd_DMA [0 ] 0 -OM Ack [0 ] 0 -OM All_acks [813 ] 813 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS L1_Replacement [16103 ] 16103 -IS Inv [0 ] 0 -IS Data [0 ] 0 -IS Exclusive_Data [94 ] 94 - -SI Load [0 ] 0 -SI Ifetch [0 ] 0 -SI Store [0 ] 0 -SI L1_Replacement [0 ] 0 -SI Fwd_GETS [0 ] 0 -SI Fwd_DMA [0 ] 0 -SI Inv [0 ] 0 -SI Writeback_Ack [0 ] 0 -SI Writeback_Ack_Data [0 ] 0 -SI Writeback_Nack [0 ] 0 - -OI Load [0 ] 0 -OI Ifetch [0 ] 0 -OI Store [0 ] 0 -OI L1_Replacement [0 ] 0 -OI Fwd_GETX [0 ] 0 -OI Fwd_GETS [0 ] 0 -OI Fwd_DMA [0 ] 0 -OI Writeback_Ack [0 ] 0 -OI Writeback_Ack_Data [0 ] 0 -OI Writeback_Nack [0 ] 0 - -MI Load [0 ] 0 -MI Ifetch [136 ] 136 -MI Store [115 ] 115 -MI L1_Replacement [0 ] 0 -MI Fwd_GETX [0 ] 0 -MI Fwd_GETS [0 ] 0 -MI Fwd_DMA [0 ] 0 -MI Writeback_Ack [0 ] 0 -MI Writeback_Ack_Data [903 ] 903 -MI Writeback_Nack [0 ] 0 - -II Load [0 ] 0 -II Ifetch [0 ] 0 -II Store [0 ] 0 -II L1_Replacement [0 ] 0 -II Inv [0 ] 0 -II Writeback_Ack [0 ] 0 -II Writeback_Ack_Data [0 ] 0 -II Writeback_Nack [0 ] 0 - - --- L2Cache --- - - Event Counts - -L1_GETS [127 ] 127 -L1_GETX [895 ] 895 -L1_PUTO [0 ] 0 -L1_PUTX [2308 ] 2308 -L1_PUTS_only [0 ] 0 -L1_PUTS [0 ] 0 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_DMA [0 ] 0 -Own_GETX [0 ] 0 -Inv [0 ] 0 -IntAck [0 ] 0 -ExtAck [0 ] 0 -All_Acks [766 ] 766 -Data [766 ] 766 -Data_Exclusive [88 ] 88 -L1_WBCLEANDATA [86 ] 86 -L1_WBDIRTYDATA [817 ] 817 -Writeback_Ack [845 ] 845 -Writeback_Nack [0 ] 0 -Unblock [0 ] 0 -Exclusive_Unblock [906 ] 906 -DmaAck [0 ] 0 -L2_Replacement [847 ] 847 - - - Transitions - -NP L1_GETS [88 ] 88 -NP L1_GETX [767 ] 767 -NP L1_PUTO [0 ] 0 -NP L1_PUTX [0 ] 0 -NP L1_PUTS [0 ] 0 -NP Inv [0 ] 0 - -I L1_GETS [0 ] 0 -I L1_GETX [0 ] 0 -I L1_PUTO [0 ] 0 -I L1_PUTX [0 ] 0 -I L1_PUTS [0 ] 0 -I Inv [0 ] 0 -I L2_Replacement [0 ] 0 - -ILS L1_GETS [0 ] 0 -ILS L1_GETX [0 ] 0 -ILS L1_PUTO [0 ] 0 -ILS L1_PUTX [0 ] 0 -ILS L1_PUTS_only [0 ] 0 -ILS L1_PUTS [0 ] 0 -ILS Inv [0 ] 0 -ILS L2_Replacement [0 ] 0 - -ILX L1_GETS [0 ] 0 -ILX L1_GETX [0 ] 0 -ILX L1_PUTO [0 ] 0 -ILX L1_PUTX [903 ] 903 -ILX L1_PUTS_only [0 ] 0 -ILX L1_PUTS [0 ] 0 -ILX Fwd_GETX [0 ] 0 -ILX Fwd_GETS [0 ] 0 -ILX Fwd_DMA [0 ] 0 -ILX Inv [0 ] 0 -ILX Data [0 ] 0 -ILX L2_Replacement [0 ] 0 - -ILO L1_GETS [0 ] 0 -ILO L1_GETX [0 ] 0 -ILO L1_PUTO [0 ] 0 -ILO L1_PUTX [0 ] 0 -ILO L1_PUTS [0 ] 0 -ILO Fwd_GETX [0 ] 0 -ILO Fwd_GETS [0 ] 0 -ILO Fwd_DMA [0 ] 0 -ILO Inv [0 ] 0 -ILO Data [0 ] 0 -ILO L2_Replacement [0 ] 0 - -ILOX L1_GETS [0 ] 0 -ILOX L1_GETX [0 ] 0 -ILOX L1_PUTO [0 ] 0 -ILOX L1_PUTX [0 ] 0 -ILOX L1_PUTS [0 ] 0 -ILOX Fwd_GETX [0 ] 0 -ILOX Fwd_GETS [0 ] 0 -ILOX Fwd_DMA [0 ] 0 -ILOX Data [0 ] 0 - -ILOS L1_GETS [0 ] 0 -ILOS L1_GETX [0 ] 0 -ILOS L1_PUTO [0 ] 0 -ILOS L1_PUTX [0 ] 0 -ILOS L1_PUTS_only [0 ] 0 -ILOS L1_PUTS [0 ] 0 -ILOS Fwd_GETX [0 ] 0 -ILOS Fwd_GETS [0 ] 0 -ILOS Fwd_DMA [0 ] 0 -ILOS Data [0 ] 0 -ILOS L2_Replacement [0 ] 0 - -ILOSX L1_GETS [0 ] 0 -ILOSX L1_GETX [0 ] 0 -ILOSX L1_PUTO [0 ] 0 -ILOSX L1_PUTX [0 ] 0 -ILOSX L1_PUTS_only [0 ] 0 -ILOSX L1_PUTS [0 ] 0 -ILOSX Fwd_GETX [0 ] 0 -ILOSX Fwd_GETS [0 ] 0 -ILOSX Fwd_DMA [0 ] 0 -ILOSX Data [0 ] 0 - -S L1_GETS [0 ] 0 -S L1_GETX [0 ] 0 -S L1_PUTX [0 ] 0 -S L1_PUTS [0 ] 0 -S Inv [0 ] 0 -S L2_Replacement [0 ] 0 - -O L1_GETS [0 ] 0 -O L1_GETX [0 ] 0 -O L1_PUTX [0 ] 0 -O Fwd_GETX [0 ] 0 -O Fwd_GETS [0 ] 0 -O Fwd_DMA [0 ] 0 -O L2_Replacement [0 ] 0 - -OLS L1_GETS [0 ] 0 -OLS L1_GETX [0 ] 0 -OLS L1_PUTX [0 ] 0 -OLS L1_PUTS_only [0 ] 0 -OLS L1_PUTS [0 ] 0 -OLS Fwd_GETX [0 ] 0 -OLS Fwd_GETS [0 ] 0 -OLS Fwd_DMA [0 ] 0 -OLS L2_Replacement [0 ] 0 - -OLSX L1_GETS [0 ] 0 -OLSX L1_GETX [0 ] 0 -OLSX L1_PUTO [0 ] 0 -OLSX L1_PUTX [0 ] 0 -OLSX L1_PUTS_only [0 ] 0 -OLSX L1_PUTS [0 ] 0 -OLSX Fwd_GETX [0 ] 0 -OLSX Fwd_GETS [0 ] 0 -OLSX Fwd_DMA [0 ] 0 -OLSX L2_Replacement [0 ] 0 - -SLS L1_GETS [0 ] 0 -SLS L1_GETX [0 ] 0 -SLS L1_PUTX [0 ] 0 -SLS L1_PUTS_only [0 ] 0 -SLS L1_PUTS [0 ] 0 -SLS Inv [0 ] 0 -SLS L2_Replacement [0 ] 0 - -M L1_GETS [6 ] 6 -M L1_GETX [47 ] 47 -M L1_PUTO [0 ] 0 -M L1_PUTX [0 ] 0 -M L1_PUTS [0 ] 0 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_DMA [0 ] 0 -M L2_Replacement [847 ] 847 - -IFGX L1_GETS [0 ] 0 -IFGX L1_GETX [0 ] 0 -IFGX L1_PUTO [0 ] 0 -IFGX L1_PUTX [0 ] 0 -IFGX L1_PUTS_only [0 ] 0 -IFGX L1_PUTS [0 ] 0 -IFGX Fwd_GETX [0 ] 0 -IFGX Fwd_GETS [0 ] 0 -IFGX Fwd_DMA [0 ] 0 -IFGX Inv [0 ] 0 -IFGX Data [0 ] 0 -IFGX Data_Exclusive [0 ] 0 -IFGX L2_Replacement [0 ] 0 - -IFGS L1_GETS [0 ] 0 -IFGS L1_GETX [0 ] 0 -IFGS L1_PUTO [0 ] 0 -IFGS L1_PUTX [0 ] 0 -IFGS L1_PUTS_only [0 ] 0 -IFGS L1_PUTS [0 ] 0 -IFGS Fwd_GETX [0 ] 0 -IFGS Fwd_GETS [0 ] 0 -IFGS Fwd_DMA [0 ] 0 -IFGS Inv [0 ] 0 -IFGS Data [0 ] 0 -IFGS Data_Exclusive [0 ] 0 -IFGS L2_Replacement [0 ] 0 - -ISFGS L1_GETS [0 ] 0 -ISFGS L1_GETX [0 ] 0 -ISFGS L1_PUTO [0 ] 0 -ISFGS L1_PUTX [0 ] 0 -ISFGS L1_PUTS_only [0 ] 0 -ISFGS L1_PUTS [0 ] 0 -ISFGS Fwd_GETX [0 ] 0 -ISFGS Fwd_GETS [0 ] 0 -ISFGS Fwd_DMA [0 ] 0 -ISFGS Inv [0 ] 0 -ISFGS Data [0 ] 0 -ISFGS L2_Replacement [0 ] 0 - -IFGXX L1_GETS [0 ] 0 -IFGXX L1_GETX [0 ] 0 -IFGXX L1_PUTO [0 ] 0 -IFGXX L1_PUTX [0 ] 0 -IFGXX L1_PUTS_only [0 ] 0 -IFGXX L1_PUTS [0 ] 0 -IFGXX Fwd_GETX [0 ] 0 -IFGXX Fwd_GETS [0 ] 0 -IFGXX Fwd_DMA [0 ] 0 -IFGXX Inv [0 ] 0 -IFGXX IntAck [0 ] 0 -IFGXX All_Acks [0 ] 0 -IFGXX Data_Exclusive [0 ] 0 -IFGXX L2_Replacement [0 ] 0 - -OFGX L1_GETS [0 ] 0 -OFGX L1_GETX [0 ] 0 -OFGX L1_PUTO [0 ] 0 -OFGX L1_PUTX [0 ] 0 -OFGX L1_PUTS_only [0 ] 0 -OFGX L1_PUTS [0 ] 0 -OFGX Fwd_GETX [0 ] 0 -OFGX Fwd_GETS [0 ] 0 -OFGX Fwd_DMA [0 ] 0 -OFGX Inv [0 ] 0 -OFGX L2_Replacement [0 ] 0 - -OLSF L1_GETS [0 ] 0 -OLSF L1_GETX [0 ] 0 -OLSF L1_PUTO [0 ] 0 -OLSF L1_PUTX [0 ] 0 -OLSF L1_PUTS_only [0 ] 0 -OLSF L1_PUTS [0 ] 0 -OLSF Fwd_GETX [0 ] 0 -OLSF Fwd_GETS [0 ] 0 -OLSF Fwd_DMA [0 ] 0 -OLSF Inv [0 ] 0 -OLSF IntAck [0 ] 0 -OLSF All_Acks [0 ] 0 -OLSF L2_Replacement [0 ] 0 - -ILOW L1_GETS [0 ] 0 -ILOW L1_GETX [0 ] 0 -ILOW L1_PUTO [0 ] 0 -ILOW L1_PUTX [0 ] 0 -ILOW L1_PUTS_only [0 ] 0 -ILOW L1_PUTS [0 ] 0 -ILOW Fwd_GETX [0 ] 0 -ILOW Fwd_GETS [0 ] 0 -ILOW Fwd_DMA [0 ] 0 -ILOW Inv [0 ] 0 -ILOW L1_WBCLEANDATA [0 ] 0 -ILOW L1_WBDIRTYDATA [0 ] 0 -ILOW Unblock [0 ] 0 -ILOW L2_Replacement [0 ] 0 - -ILOXW L1_GETS [0 ] 0 -ILOXW L1_GETX [0 ] 0 -ILOXW L1_PUTO [0 ] 0 -ILOXW L1_PUTX [0 ] 0 -ILOXW L1_PUTS_only [0 ] 0 -ILOXW L1_PUTS [0 ] 0 -ILOXW Fwd_GETX [0 ] 0 -ILOXW Fwd_GETS [0 ] 0 -ILOXW Fwd_DMA [0 ] 0 -ILOXW Inv [0 ] 0 -ILOXW L1_WBCLEANDATA [0 ] 0 -ILOXW L1_WBDIRTYDATA [0 ] 0 -ILOXW Unblock [0 ] 0 -ILOXW L2_Replacement [0 ] 0 - -ILOSW L1_GETS [0 ] 0 -ILOSW L1_GETX [0 ] 0 -ILOSW L1_PUTO [0 ] 0 -ILOSW L1_PUTX [0 ] 0 -ILOSW L1_PUTS_only [0 ] 0 -ILOSW L1_PUTS [0 ] 0 -ILOSW Fwd_GETX [0 ] 0 -ILOSW Fwd_GETS [0 ] 0 -ILOSW Fwd_DMA [0 ] 0 -ILOSW Inv [0 ] 0 -ILOSW L1_WBCLEANDATA [0 ] 0 -ILOSW L1_WBDIRTYDATA [0 ] 0 -ILOSW Unblock [0 ] 0 -ILOSW L2_Replacement [0 ] 0 - -ILOSXW L1_GETS [0 ] 0 -ILOSXW L1_GETX [0 ] 0 -ILOSXW L1_PUTO [0 ] 0 -ILOSXW L1_PUTX [0 ] 0 -ILOSXW L1_PUTS_only [0 ] 0 -ILOSXW L1_PUTS [0 ] 0 -ILOSXW Fwd_GETX [0 ] 0 -ILOSXW Fwd_GETS [0 ] 0 -ILOSXW Fwd_DMA [0 ] 0 -ILOSXW Inv [0 ] 0 -ILOSXW L1_WBCLEANDATA [0 ] 0 -ILOSXW L1_WBDIRTYDATA [0 ] 0 -ILOSXW Unblock [0 ] 0 -ILOSXW L2_Replacement [0 ] 0 - -SLSW L1_GETS [0 ] 0 -SLSW L1_GETX [0 ] 0 -SLSW L1_PUTO [0 ] 0 -SLSW L1_PUTX [0 ] 0 -SLSW L1_PUTS_only [0 ] 0 -SLSW L1_PUTS [0 ] 0 -SLSW Fwd_GETX [0 ] 0 -SLSW Fwd_GETS [0 ] 0 -SLSW Fwd_DMA [0 ] 0 -SLSW Inv [0 ] 0 -SLSW Unblock [0 ] 0 -SLSW L2_Replacement [0 ] 0 - -OLSW L1_GETS [0 ] 0 -OLSW L1_GETX [0 ] 0 -OLSW L1_PUTO [0 ] 0 -OLSW L1_PUTX [0 ] 0 -OLSW L1_PUTS_only [0 ] 0 -OLSW L1_PUTS [0 ] 0 -OLSW Fwd_GETX [0 ] 0 -OLSW Fwd_GETS [0 ] 0 -OLSW Fwd_DMA [0 ] 0 -OLSW Inv [0 ] 0 -OLSW Unblock [0 ] 0 -OLSW L2_Replacement [0 ] 0 - -ILSW L1_GETS [0 ] 0 -ILSW L1_GETX [0 ] 0 -ILSW L1_PUTO [0 ] 0 -ILSW L1_PUTX [0 ] 0 -ILSW L1_PUTS_only [0 ] 0 -ILSW L1_PUTS [0 ] 0 -ILSW Fwd_GETX [0 ] 0 -ILSW Fwd_GETS [0 ] 0 -ILSW Fwd_DMA [0 ] 0 -ILSW Inv [0 ] 0 -ILSW L1_WBCLEANDATA [0 ] 0 -ILSW Unblock [0 ] 0 -ILSW L2_Replacement [0 ] 0 - -IW L1_GETS [0 ] 0 -IW L1_GETX [0 ] 0 -IW L1_PUTO [0 ] 0 -IW L1_PUTX [0 ] 0 -IW L1_PUTS_only [0 ] 0 -IW L1_PUTS [0 ] 0 -IW Fwd_GETX [0 ] 0 -IW Fwd_GETS [0 ] 0 -IW Fwd_DMA [0 ] 0 -IW Inv [0 ] 0 -IW L1_WBCLEANDATA [0 ] 0 -IW L2_Replacement [0 ] 0 - -OW L1_GETS [0 ] 0 -OW L1_GETX [0 ] 0 -OW L1_PUTO [0 ] 0 -OW L1_PUTX [0 ] 0 -OW L1_PUTS_only [0 ] 0 -OW L1_PUTS [0 ] 0 -OW Fwd_GETX [0 ] 0 -OW Fwd_GETS [0 ] 0 -OW Fwd_DMA [0 ] 0 -OW Inv [0 ] 0 -OW Unblock [0 ] 0 -OW L2_Replacement [0 ] 0 - -SW L1_GETS [0 ] 0 -SW L1_GETX [0 ] 0 -SW L1_PUTO [0 ] 0 -SW L1_PUTX [0 ] 0 -SW L1_PUTS_only [0 ] 0 -SW L1_PUTS [0 ] 0 -SW Fwd_GETX [0 ] 0 -SW Fwd_GETS [0 ] 0 -SW Fwd_DMA [0 ] 0 -SW Inv [0 ] 0 -SW Unblock [0 ] 0 -SW L2_Replacement [0 ] 0 - -OXW L1_GETS [0 ] 0 -OXW L1_GETX [0 ] 0 -OXW L1_PUTO [0 ] 0 -OXW L1_PUTX [0 ] 0 -OXW L1_PUTS_only [0 ] 0 -OXW L1_PUTS [0 ] 0 -OXW Fwd_GETX [0 ] 0 -OXW Fwd_GETS [0 ] 0 -OXW Fwd_DMA [0 ] 0 -OXW Inv [0 ] 0 -OXW Unblock [0 ] 0 -OXW L2_Replacement [0 ] 0 - -OLSXW L1_GETS [0 ] 0 -OLSXW L1_GETX [0 ] 0 -OLSXW L1_PUTO [0 ] 0 -OLSXW L1_PUTX [0 ] 0 -OLSXW L1_PUTS_only [0 ] 0 -OLSXW L1_PUTS [0 ] 0 -OLSXW Fwd_GETX [0 ] 0 -OLSXW Fwd_GETS [0 ] 0 -OLSXW Fwd_DMA [0 ] 0 -OLSXW Inv [0 ] 0 -OLSXW Unblock [0 ] 0 -OLSXW L2_Replacement [0 ] 0 - -ILXW L1_GETS [33 ] 33 -ILXW L1_GETX [0 ] 0 -ILXW L1_PUTO [0 ] 0 -ILXW L1_PUTX [0 ] 0 -ILXW L1_PUTS_only [0 ] 0 -ILXW L1_PUTS [0 ] 0 -ILXW Fwd_GETX [0 ] 0 -ILXW Fwd_GETS [0 ] 0 -ILXW Fwd_DMA [0 ] 0 -ILXW Inv [0 ] 0 -ILXW Data [0 ] 0 -ILXW L1_WBCLEANDATA [86 ] 86 -ILXW L1_WBDIRTYDATA [817 ] 817 -ILXW Unblock [0 ] 0 -ILXW L2_Replacement [0 ] 0 - -IFLS L1_GETS [0 ] 0 -IFLS L1_GETX [0 ] 0 -IFLS L1_PUTO [0 ] 0 -IFLS L1_PUTX [0 ] 0 -IFLS L1_PUTS_only [0 ] 0 -IFLS L1_PUTS [0 ] 0 -IFLS Fwd_GETX [0 ] 0 -IFLS Fwd_GETS [0 ] 0 -IFLS Fwd_DMA [0 ] 0 -IFLS Inv [0 ] 0 -IFLS Unblock [0 ] 0 -IFLS L2_Replacement [0 ] 0 - -IFLO L1_GETS [0 ] 0 -IFLO L1_GETX [0 ] 0 -IFLO L1_PUTO [0 ] 0 -IFLO L1_PUTX [0 ] 0 -IFLO L1_PUTS_only [0 ] 0 -IFLO L1_PUTS [0 ] 0 -IFLO Fwd_GETX [0 ] 0 -IFLO Fwd_GETS [0 ] 0 -IFLO Fwd_DMA [0 ] 0 -IFLO Inv [0 ] 0 -IFLO Unblock [0 ] 0 -IFLO L2_Replacement [0 ] 0 - -IFLOX L1_GETS [0 ] 0 -IFLOX L1_GETX [0 ] 0 -IFLOX L1_PUTO [0 ] 0 -IFLOX L1_PUTX [0 ] 0 -IFLOX L1_PUTS_only [0 ] 0 -IFLOX L1_PUTS [0 ] 0 -IFLOX Fwd_GETX [0 ] 0 -IFLOX Fwd_GETS [0 ] 0 -IFLOX Fwd_DMA [0 ] 0 -IFLOX Inv [0 ] 0 -IFLOX Unblock [0 ] 0 -IFLOX Exclusive_Unblock [0 ] 0 -IFLOX L2_Replacement [0 ] 0 - -IFLOXX L1_GETS [0 ] 0 -IFLOXX L1_GETX [0 ] 0 -IFLOXX L1_PUTO [0 ] 0 -IFLOXX L1_PUTX [0 ] 0 -IFLOXX L1_PUTS_only [0 ] 0 -IFLOXX L1_PUTS [0 ] 0 -IFLOXX Fwd_GETX [0 ] 0 -IFLOXX Fwd_GETS [0 ] 0 -IFLOXX Fwd_DMA [0 ] 0 -IFLOXX Inv [0 ] 0 -IFLOXX Unblock [0 ] 0 -IFLOXX Exclusive_Unblock [0 ] 0 -IFLOXX L2_Replacement [0 ] 0 - -IFLOSX L1_GETS [0 ] 0 -IFLOSX L1_GETX [0 ] 0 -IFLOSX L1_PUTO [0 ] 0 -IFLOSX L1_PUTX [0 ] 0 -IFLOSX L1_PUTS_only [0 ] 0 -IFLOSX L1_PUTS [0 ] 0 -IFLOSX Fwd_GETX [0 ] 0 -IFLOSX Fwd_GETS [0 ] 0 -IFLOSX Fwd_DMA [0 ] 0 -IFLOSX Inv [0 ] 0 -IFLOSX Unblock [0 ] 0 -IFLOSX Exclusive_Unblock [0 ] 0 -IFLOSX L2_Replacement [0 ] 0 - -IFLXO L1_GETS [0 ] 0 -IFLXO L1_GETX [0 ] 0 -IFLXO L1_PUTO [0 ] 0 -IFLXO L1_PUTX [0 ] 0 -IFLXO L1_PUTS_only [0 ] 0 -IFLXO L1_PUTS [0 ] 0 -IFLXO Fwd_GETX [0 ] 0 -IFLXO Fwd_GETS [0 ] 0 -IFLXO Fwd_DMA [0 ] 0 -IFLXO Inv [0 ] 0 -IFLXO Exclusive_Unblock [0 ] 0 -IFLXO L2_Replacement [0 ] 0 - -IGS L1_GETS [0 ] 0 -IGS L1_GETX [0 ] 0 -IGS L1_PUTO [0 ] 0 -IGS L1_PUTX [65 ] 65 -IGS L1_PUTS_only [0 ] 0 -IGS L1_PUTS [0 ] 0 -IGS Fwd_GETX [0 ] 0 -IGS Fwd_GETS [0 ] 0 -IGS Fwd_DMA [0 ] 0 -IGS Own_GETX [0 ] 0 -IGS Inv [0 ] 0 -IGS Data [0 ] 0 -IGS Data_Exclusive [88 ] 88 -IGS Unblock [0 ] 0 -IGS Exclusive_Unblock [87 ] 87 -IGS L2_Replacement [0 ] 0 - -IGM L1_GETS [0 ] 0 -IGM L1_GETX [0 ] 0 -IGM L1_PUTO [0 ] 0 -IGM L1_PUTX [0 ] 0 -IGM L1_PUTS_only [0 ] 0 -IGM L1_PUTS [0 ] 0 -IGM Fwd_GETX [0 ] 0 -IGM Fwd_GETS [0 ] 0 -IGM Fwd_DMA [0 ] 0 -IGM Own_GETX [0 ] 0 -IGM Inv [0 ] 0 -IGM ExtAck [0 ] 0 -IGM Data [766 ] 766 -IGM Data_Exclusive [0 ] 0 -IGM L2_Replacement [0 ] 0 - -IGMLS L1_GETS [0 ] 0 -IGMLS L1_GETX [0 ] 0 -IGMLS L1_PUTO [0 ] 0 -IGMLS L1_PUTX [0 ] 0 -IGMLS L1_PUTS_only [0 ] 0 -IGMLS L1_PUTS [0 ] 0 -IGMLS Inv [0 ] 0 -IGMLS IntAck [0 ] 0 -IGMLS ExtAck [0 ] 0 -IGMLS All_Acks [0 ] 0 -IGMLS Data [0 ] 0 -IGMLS Data_Exclusive [0 ] 0 -IGMLS L2_Replacement [0 ] 0 - -IGMO L1_GETS [0 ] 0 -IGMO L1_GETX [0 ] 0 -IGMO L1_PUTO [0 ] 0 -IGMO L1_PUTX [1324 ] 1324 -IGMO L1_PUTS_only [0 ] 0 -IGMO L1_PUTS [0 ] 0 -IGMO Fwd_GETX [0 ] 0 -IGMO Fwd_GETS [0 ] 0 -IGMO Fwd_DMA [0 ] 0 -IGMO Own_GETX [0 ] 0 -IGMO ExtAck [0 ] 0 -IGMO All_Acks [766 ] 766 -IGMO Exclusive_Unblock [766 ] 766 -IGMO L2_Replacement [0 ] 0 - -IGMIO L1_GETS [0 ] 0 -IGMIO L1_GETX [0 ] 0 -IGMIO L1_PUTO [0 ] 0 -IGMIO L1_PUTX [0 ] 0 -IGMIO L1_PUTS_only [0 ] 0 -IGMIO L1_PUTS [0 ] 0 -IGMIO Fwd_GETX [0 ] 0 -IGMIO Fwd_GETS [0 ] 0 -IGMIO Fwd_DMA [0 ] 0 -IGMIO Own_GETX [0 ] 0 -IGMIO ExtAck [0 ] 0 -IGMIO All_Acks [0 ] 0 - -OGMIO L1_GETS [0 ] 0 -OGMIO L1_GETX [0 ] 0 -OGMIO L1_PUTO [0 ] 0 -OGMIO L1_PUTX [0 ] 0 -OGMIO L1_PUTS_only [0 ] 0 -OGMIO L1_PUTS [0 ] 0 -OGMIO Fwd_GETX [0 ] 0 -OGMIO Fwd_GETS [0 ] 0 -OGMIO Fwd_DMA [0 ] 0 -OGMIO Own_GETX [0 ] 0 -OGMIO ExtAck [0 ] 0 -OGMIO All_Acks [0 ] 0 - -IGMIOF L1_GETS [0 ] 0 -IGMIOF L1_GETX [0 ] 0 -IGMIOF L1_PUTO [0 ] 0 -IGMIOF L1_PUTX [0 ] 0 -IGMIOF L1_PUTS_only [0 ] 0 -IGMIOF L1_PUTS [0 ] 0 -IGMIOF IntAck [0 ] 0 -IGMIOF All_Acks [0 ] 0 -IGMIOF Data_Exclusive [0 ] 0 - -IGMIOFS L1_GETS [0 ] 0 -IGMIOFS L1_GETX [0 ] 0 -IGMIOFS L1_PUTO [0 ] 0 -IGMIOFS L1_PUTX [0 ] 0 -IGMIOFS L1_PUTS_only [0 ] 0 -IGMIOFS L1_PUTS [0 ] 0 -IGMIOFS Fwd_GETX [0 ] 0 -IGMIOFS Fwd_GETS [0 ] 0 -IGMIOFS Fwd_DMA [0 ] 0 -IGMIOFS Inv [0 ] 0 -IGMIOFS Data [0 ] 0 -IGMIOFS L2_Replacement [0 ] 0 - -OGMIOF L1_GETS [0 ] 0 -OGMIOF L1_GETX [0 ] 0 -OGMIOF L1_PUTO [0 ] 0 -OGMIOF L1_PUTX [0 ] 0 -OGMIOF L1_PUTS_only [0 ] 0 -OGMIOF L1_PUTS [0 ] 0 -OGMIOF IntAck [0 ] 0 -OGMIOF All_Acks [0 ] 0 - -II L1_GETS [0 ] 0 -II L1_GETX [0 ] 0 -II L1_PUTO [0 ] 0 -II L1_PUTX [0 ] 0 -II L1_PUTS_only [0 ] 0 -II L1_PUTS [0 ] 0 -II IntAck [0 ] 0 -II All_Acks [0 ] 0 - -MM L1_GETS [0 ] 0 -MM L1_GETX [0 ] 0 -MM L1_PUTO [0 ] 0 -MM L1_PUTX [5 ] 5 -MM L1_PUTS_only [0 ] 0 -MM L1_PUTS [0 ] 0 -MM Fwd_GETX [0 ] 0 -MM Fwd_GETS [0 ] 0 -MM Fwd_DMA [0 ] 0 -MM Inv [0 ] 0 -MM Exclusive_Unblock [47 ] 47 -MM L2_Replacement [0 ] 0 - -SS L1_GETS [0 ] 0 -SS L1_GETX [0 ] 0 -SS L1_PUTO [0 ] 0 -SS L1_PUTX [0 ] 0 -SS L1_PUTS_only [0 ] 0 -SS L1_PUTS [0 ] 0 -SS Fwd_GETX [0 ] 0 -SS Fwd_GETS [0 ] 0 -SS Fwd_DMA [0 ] 0 -SS Inv [0 ] 0 -SS Unblock [0 ] 0 -SS L2_Replacement [0 ] 0 - -OO L1_GETS [0 ] 0 -OO L1_GETX [0 ] 0 -OO L1_PUTO [0 ] 0 -OO L1_PUTX [11 ] 11 -OO L1_PUTS_only [0 ] 0 -OO L1_PUTS [0 ] 0 -OO Fwd_GETX [0 ] 0 -OO Fwd_GETS [0 ] 0 -OO Fwd_DMA [0 ] 0 -OO Inv [0 ] 0 -OO Unblock [0 ] 0 -OO Exclusive_Unblock [6 ] 6 -OO L2_Replacement [0 ] 0 - -OLSS L1_GETS [0 ] 0 -OLSS L1_GETX [0 ] 0 -OLSS L1_PUTO [0 ] 0 -OLSS L1_PUTX [0 ] 0 -OLSS L1_PUTS_only [0 ] 0 -OLSS L1_PUTS [0 ] 0 -OLSS Fwd_GETX [0 ] 0 -OLSS Fwd_GETS [0 ] 0 -OLSS Fwd_DMA [0 ] 0 -OLSS Inv [0 ] 0 -OLSS Unblock [0 ] 0 -OLSS L2_Replacement [0 ] 0 - -OLSXS L1_GETS [0 ] 0 -OLSXS L1_GETX [0 ] 0 -OLSXS L1_PUTO [0 ] 0 -OLSXS L1_PUTX [0 ] 0 -OLSXS L1_PUTS_only [0 ] 0 -OLSXS L1_PUTS [0 ] 0 -OLSXS Fwd_GETX [0 ] 0 -OLSXS Fwd_GETS [0 ] 0 -OLSXS Fwd_DMA [0 ] 0 -OLSXS Inv [0 ] 0 -OLSXS Unblock [0 ] 0 -OLSXS L2_Replacement [0 ] 0 - -SLSS L1_GETS [0 ] 0 -SLSS L1_GETX [0 ] 0 -SLSS L1_PUTO [0 ] 0 -SLSS L1_PUTX [0 ] 0 -SLSS L1_PUTS_only [0 ] 0 -SLSS L1_PUTS [0 ] 0 -SLSS Fwd_GETX [0 ] 0 -SLSS Fwd_GETS [0 ] 0 -SLSS Fwd_DMA [0 ] 0 -SLSS Inv [0 ] 0 -SLSS Unblock [0 ] 0 -SLSS L2_Replacement [0 ] 0 - -OI L1_GETS [0 ] 0 -OI L1_GETX [0 ] 0 -OI L1_PUTO [0 ] 0 -OI L1_PUTX [0 ] 0 -OI L1_PUTS_only [0 ] 0 -OI L1_PUTS [0 ] 0 -OI Fwd_GETX [0 ] 0 -OI Fwd_GETS [0 ] 0 -OI Fwd_DMA [0 ] 0 -OI Writeback_Ack [0 ] 0 -OI Writeback_Nack [0 ] 0 -OI L2_Replacement [0 ] 0 - -MI L1_GETS [0 ] 0 -MI L1_GETX [81 ] 81 -MI L1_PUTO [0 ] 0 -MI L1_PUTX [0 ] 0 -MI L1_PUTS_only [0 ] 0 -MI L1_PUTS [0 ] 0 -MI Fwd_GETX [0 ] 0 -MI Fwd_GETS [0 ] 0 -MI Fwd_DMA [0 ] 0 -MI Writeback_Ack [845 ] 845 -MI L2_Replacement [0 ] 0 - -MII L1_GETS [0 ] 0 -MII L1_GETX [0 ] 0 -MII L1_PUTO [0 ] 0 -MII L1_PUTX [0 ] 0 -MII L1_PUTS_only [0 ] 0 -MII L1_PUTS [0 ] 0 -MII Writeback_Ack [0 ] 0 -MII Writeback_Nack [0 ] 0 -MII L2_Replacement [0 ] 0 - -OLSI L1_GETS [0 ] 0 -OLSI L1_GETX [0 ] 0 -OLSI L1_PUTO [0 ] 0 -OLSI L1_PUTX [0 ] 0 -OLSI L1_PUTS_only [0 ] 0 -OLSI L1_PUTS [0 ] 0 -OLSI Fwd_GETX [0 ] 0 -OLSI Fwd_GETS [0 ] 0 -OLSI Fwd_DMA [0 ] 0 -OLSI Writeback_Ack [0 ] 0 -OLSI L2_Replacement [0 ] 0 - -ILSI L1_GETS [0 ] 0 -ILSI L1_GETX [0 ] 0 -ILSI L1_PUTO [0 ] 0 -ILSI L1_PUTX [0 ] 0 -ILSI L1_PUTS_only [0 ] 0 -ILSI L1_PUTS [0 ] 0 -ILSI IntAck [0 ] 0 -ILSI All_Acks [0 ] 0 -ILSI Writeback_Ack [0 ] 0 -ILSI L2_Replacement [0 ] 0 - -ILOSD L1_GETS [0 ] 0 -ILOSD L1_GETX [0 ] 0 -ILOSD L1_PUTO [0 ] 0 -ILOSD L1_PUTX [0 ] 0 -ILOSD L1_PUTS_only [0 ] 0 -ILOSD L1_PUTS [0 ] 0 -ILOSD Fwd_GETX [0 ] 0 -ILOSD Fwd_GETS [0 ] 0 -ILOSD Fwd_DMA [0 ] 0 -ILOSD Own_GETX [0 ] 0 -ILOSD Inv [0 ] 0 -ILOSD DmaAck [0 ] 0 -ILOSD L2_Replacement [0 ] 0 - -ILOSXD L1_GETS [0 ] 0 -ILOSXD L1_GETX [0 ] 0 -ILOSXD L1_PUTO [0 ] 0 -ILOSXD L1_PUTX [0 ] 0 -ILOSXD L1_PUTS_only [0 ] 0 -ILOSXD L1_PUTS [0 ] 0 -ILOSXD Fwd_GETX [0 ] 0 -ILOSXD Fwd_GETS [0 ] 0 -ILOSXD Fwd_DMA [0 ] 0 -ILOSXD Own_GETX [0 ] 0 -ILOSXD Inv [0 ] 0 -ILOSXD DmaAck [0 ] 0 -ILOSXD L2_Replacement [0 ] 0 - -ILOD L1_GETS [0 ] 0 -ILOD L1_GETX [0 ] 0 -ILOD L1_PUTO [0 ] 0 -ILOD L1_PUTX [0 ] 0 -ILOD L1_PUTS_only [0 ] 0 -ILOD L1_PUTS [0 ] 0 -ILOD Fwd_GETX [0 ] 0 -ILOD Fwd_GETS [0 ] 0 -ILOD Fwd_DMA [0 ] 0 -ILOD Own_GETX [0 ] 0 -ILOD Inv [0 ] 0 -ILOD DmaAck [0 ] 0 -ILOD L2_Replacement [0 ] 0 - -ILXD L1_GETS [0 ] 0 -ILXD L1_GETX [0 ] 0 -ILXD L1_PUTO [0 ] 0 -ILXD L1_PUTX [0 ] 0 -ILXD L1_PUTS_only [0 ] 0 -ILXD L1_PUTS [0 ] 0 -ILXD Fwd_GETX [0 ] 0 -ILXD Fwd_GETS [0 ] 0 -ILXD Fwd_DMA [0 ] 0 -ILXD Own_GETX [0 ] 0 -ILXD Inv [0 ] 0 -ILXD DmaAck [0 ] 0 -ILXD L2_Replacement [0 ] 0 - -ILOXD L1_GETS [0 ] 0 -ILOXD L1_GETX [0 ] 0 -ILOXD L1_PUTO [0 ] 0 -ILOXD L1_PUTX [0 ] 0 -ILOXD L1_PUTS_only [0 ] 0 -ILOXD L1_PUTS [0 ] 0 -ILOXD Fwd_GETX [0 ] 0 -ILOXD Fwd_GETS [0 ] 0 -ILOXD Fwd_DMA [0 ] 0 -ILOXD Own_GETX [0 ] 0 -ILOXD Inv [0 ] 0 -ILOXD DmaAck [0 ] 0 -ILOXD L2_Replacement [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 1619 - memory_reads: 854 - memory_writes: 765 - memory_refreshes: 2273 - memory_total_request_delays: 446 - memory_delays_per_request: 0.275479 - memory_delays_in_input_queue: 26 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 420 - memory_stalls_for_bank_busy: 163 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 32 - memory_stalls_for_bus: 144 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 21 - memory_stalls_for_read_read_turnaround: 60 - accesses_per_bank: 49 44 48 84 49 52 64 51 40 45 48 41 74 47 51 38 56 62 37 58 46 50 55 36 49 71 52 40 42 33 48 59 - - --- Directory --- - - Event Counts - -GETX [837 ] 837 -GETS [88 ] 88 -PUTX [845 ] 845 -PUTO [0 ] 0 -PUTO_SHARERS [0 ] 0 -Unblock [0 ] 0 -Last_Unblock [0 ] 0 -Exclusive_Unblock [852 ] 852 -Clean_Writeback [80 ] 80 -Dirty_Writeback [765 ] 765 -Memory_Data [854 ] 854 -Memory_Ack [765 ] 765 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -DMA_ACK [0 ] 0 -Data [0 ] 0 - - - Transitions - -I GETX [766 ] 766 -I GETS [88 ] 88 -I PUTX [0 ] 0 -I PUTO [0 ] 0 -I Memory_Data [0 ] 0 -I Memory_Ack [760 ] 760 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -S GETX [0 ] 0 -S GETS [0 ] 0 -S PUTX [0 ] 0 -S PUTO [0 ] 0 -S Memory_Data [0 ] 0 -S Memory_Ack [0 ] 0 -S DMA_READ [0 ] 0 -S DMA_WRITE [0 ] 0 - -O GETX [0 ] 0 -O GETS [0 ] 0 -O PUTX [0 ] 0 -O PUTO [0 ] 0 -O PUTO_SHARERS [0 ] 0 -O Memory_Data [0 ] 0 -O Memory_Ack [0 ] 0 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 - -M GETX [0 ] 0 -M GETS [0 ] 0 -M PUTX [845 ] 845 -M PUTO [0 ] 0 -M PUTO_SHARERS [0 ] 0 -M Memory_Data [0 ] 0 -M Memory_Ack [0 ] 0 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 - -IS GETX [0 ] 0 -IS GETS [0 ] 0 -IS PUTX [0 ] 0 -IS PUTO [0 ] 0 -IS PUTO_SHARERS [0 ] 0 -IS Unblock [0 ] 0 -IS Exclusive_Unblock [87 ] 87 -IS Memory_Data [88 ] 88 -IS Memory_Ack [1 ] 1 -IS DMA_READ [0 ] 0 -IS DMA_WRITE [0 ] 0 - -SS GETX [0 ] 0 -SS GETS [0 ] 0 -SS PUTX [0 ] 0 -SS PUTO [0 ] 0 -SS PUTO_SHARERS [0 ] 0 -SS Unblock [0 ] 0 -SS Last_Unblock [0 ] 0 -SS Memory_Data [0 ] 0 -SS Memory_Ack [0 ] 0 -SS DMA_READ [0 ] 0 -SS DMA_WRITE [0 ] 0 - -OO GETX [0 ] 0 -OO GETS [0 ] 0 -OO PUTX [0 ] 0 -OO PUTO [0 ] 0 -OO PUTO_SHARERS [0 ] 0 -OO Unblock [0 ] 0 -OO Last_Unblock [0 ] 0 -OO Memory_Data [0 ] 0 -OO Memory_Ack [0 ] 0 -OO DMA_READ [0 ] 0 -OO DMA_WRITE [0 ] 0 - -MO GETX [0 ] 0 -MO GETS [0 ] 0 -MO PUTX [0 ] 0 -MO PUTO [0 ] 0 -MO PUTO_SHARERS [0 ] 0 -MO Unblock [0 ] 0 -MO Exclusive_Unblock [0 ] 0 -MO Memory_Data [0 ] 0 -MO Memory_Ack [0 ] 0 -MO DMA_READ [0 ] 0 -MO DMA_WRITE [0 ] 0 - -MM GETX [0 ] 0 -MM GETS [0 ] 0 -MM PUTX [0 ] 0 -MM PUTO [0 ] 0 -MM PUTO_SHARERS [0 ] 0 -MM Exclusive_Unblock [765 ] 765 -MM Memory_Data [766 ] 766 -MM Memory_Ack [4 ] 4 -MM DMA_READ [0 ] 0 -MM DMA_WRITE [0 ] 0 - - -MI GETX [71 ] 71 -MI GETS [0 ] 0 -MI PUTX [0 ] 0 -MI PUTO [0 ] 0 -MI PUTO_SHARERS [0 ] 0 -MI Unblock [0 ] 0 -MI Clean_Writeback [80 ] 80 -MI Dirty_Writeback [765 ] 765 -MI Memory_Data [0 ] 0 -MI Memory_Ack [0 ] 0 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 - -MIS GETX [0 ] 0 -MIS GETS [0 ] 0 -MIS PUTX [0 ] 0 -MIS PUTO [0 ] 0 -MIS PUTO_SHARERS [0 ] 0 -MIS Unblock [0 ] 0 -MIS Clean_Writeback [0 ] 0 -MIS Dirty_Writeback [0 ] 0 -MIS Memory_Data [0 ] 0 -MIS Memory_Ack [0 ] 0 -MIS DMA_READ [0 ] 0 -MIS DMA_WRITE [0 ] 0 - -OS GETX [0 ] 0 -OS GETS [0 ] 0 -OS PUTX [0 ] 0 -OS PUTO [0 ] 0 -OS PUTO_SHARERS [0 ] 0 -OS Unblock [0 ] 0 -OS Clean_Writeback [0 ] 0 -OS Dirty_Writeback [0 ] 0 -OS Memory_Data [0 ] 0 -OS Memory_Ack [0 ] 0 -OS DMA_READ [0 ] 0 -OS DMA_WRITE [0 ] 0 - -OSS GETX [0 ] 0 -OSS GETS [0 ] 0 -OSS PUTX [0 ] 0 -OSS PUTO [0 ] 0 -OSS PUTO_SHARERS [0 ] 0 -OSS Unblock [0 ] 0 -OSS Clean_Writeback [0 ] 0 -OSS Dirty_Writeback [0 ] 0 -OSS Memory_Data [0 ] 0 -OSS Memory_Ack [0 ] 0 -OSS DMA_READ [0 ] 0 -OSS DMA_WRITE [0 ] 0 - -XI_M GETX [0 ] 0 -XI_M GETS [0 ] 0 -XI_M PUTX [0 ] 0 -XI_M PUTO [0 ] 0 -XI_M PUTO_SHARERS [0 ] 0 -XI_M Memory_Data [0 ] 0 -XI_M Memory_Ack [0 ] 0 -XI_M DMA_READ [0 ] 0 -XI_M DMA_WRITE [0 ] 0 - -XI_U GETX [0 ] 0 -XI_U GETS [0 ] 0 -XI_U PUTX [0 ] 0 -XI_U PUTO [0 ] 0 -XI_U PUTO_SHARERS [0 ] 0 -XI_U Exclusive_Unblock [0 ] 0 -XI_U Memory_Ack [0 ] 0 -XI_U DMA_READ [0 ] 0 -XI_U DMA_WRITE [0 ] 0 - -OI_D GETX [0 ] 0 -OI_D GETS [0 ] 0 -OI_D PUTX [0 ] 0 -OI_D PUTO [0 ] 0 -OI_D PUTO_SHARERS [0 ] 0 -OI_D DMA_READ [0 ] 0 -OI_D DMA_WRITE [0 ] 0 -OI_D Data [0 ] 0 - -OD GETX [0 ] 0 -OD GETS [0 ] 0 -OD PUTX [0 ] 0 -OD PUTO [0 ] 0 -OD PUTO_SHARERS [0 ] 0 -OD DMA_READ [0 ] 0 -OD DMA_WRITE [0 ] 0 -OD DMA_ACK [0 ] 0 - -MD GETX [0 ] 0 -MD GETS [0 ] 0 -MD PUTX [0 ] 0 -MD PUTO [0 ] 0 -MD PUTO_SHARERS [0 ] 0 -MD DMA_READ [0 ] 0 -MD DMA_WRITE [0 ] 0 -MD DMA_ACK [0 ] 0 - diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index 18d6ea72e..619c6b01e 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000327 # Nu sim_ticks 327361 # Number of ticks simulated final_tick 327361 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 517762 # Simulator tick rate (ticks/s) -host_mem_usage 149964 # Number of bytes of host memory used -host_seconds 0.63 # Real time elapsed on the host +host_tick_rate 849675 # Simulator tick rate (ticks/s) +host_mem_usage 144052 # Number of bytes of host memory used +host_seconds 0.39 # Real time elapsed on the host system.ruby.l2_cntrl0.L2cache.demand_hits 53 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 855 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 908 # Number of cache demand accesses @@ -16,5 +16,104 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 930 system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 56 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 56 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 1619 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 854 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 765 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 2273 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 420 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 26 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 446 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.275479 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 163 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 144 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 21 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 60 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 32 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 49 3.03% 3.03% | 44 2.72% 5.74% | 48 2.96% 8.71% | 84 5.19% 13.90% | 49 3.03% 16.92% | 52 3.21% 20.14% | 64 3.95% 24.09% | 51 3.15% 27.24% | 40 2.47% 29.71% | 45 2.78% 32.49% | 48 2.96% 35.45% | 41 2.53% 37.99% | 74 4.57% 42.56% | 47 2.90% 45.46% | 51 3.15% 48.61% | 38 2.35% 50.96% | 56 3.46% 54.42% | 62 3.83% 58.25% | 37 2.29% 60.53% | 58 3.58% 64.11% | 46 2.84% 66.95% | 50 3.09% 70.04% | 55 3.40% 73.44% | 36 2.22% 75.66% | 49 3.03% 78.69% | 71 4.39% 83.08% | 52 3.21% 86.29% | 40 2.47% 88.76% | 42 2.59% 91.35% | 33 2.04% 93.39% | 48 2.96% 96.36% | 59 3.64% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1619 # Number of accesses per bank + +system.ruby.l2_cntrl0.L1_GETS 127 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 895 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX 2308 0.00% 0.00% +system.ruby.l2_cntrl0.All_Acks 766 0.00% 0.00% +system.ruby.l2_cntrl0.Data 766 0.00% 0.00% +system.ruby.l2_cntrl0.Data_Exclusive 88 0.00% 0.00% +system.ruby.l2_cntrl0.L1_WBCLEANDATA 86 0.00% 0.00% +system.ruby.l2_cntrl0.L1_WBDIRTYDATA 817 0.00% 0.00% +system.ruby.l2_cntrl0.Writeback_Ack 845 0.00% 0.00% +system.ruby.l2_cntrl0.Exclusive_Unblock 906 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 847 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 88 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 767 0.00% 0.00% +system.ruby.l2_cntrl0.ILX.L1_PUTX 903 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETS 6 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 47 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 847 0.00% 0.00% +system.ruby.l2_cntrl0.ILXW.L1_GETS 33 0.00% 0.00% +system.ruby.l2_cntrl0.ILXW.L1_WBCLEANDATA 86 0.00% 0.00% +system.ruby.l2_cntrl0.ILXW.L1_WBDIRTYDATA 817 0.00% 0.00% +system.ruby.l2_cntrl0.IGS.L1_PUTX 65 0.00% 0.00% +system.ruby.l2_cntrl0.IGS.Data_Exclusive 88 0.00% 0.00% +system.ruby.l2_cntrl0.IGS.Exclusive_Unblock 87 0.00% 0.00% +system.ruby.l2_cntrl0.IGM.Data 766 0.00% 0.00% +system.ruby.l2_cntrl0.IGMO.L1_PUTX 1324 0.00% 0.00% +system.ruby.l2_cntrl0.IGMO.All_Acks 766 0.00% 0.00% +system.ruby.l2_cntrl0.IGMO.Exclusive_Unblock 766 0.00% 0.00% +system.ruby.l2_cntrl0.MM.L1_PUTX 5 0.00% 0.00% +system.ruby.l2_cntrl0.MM.Exclusive_Unblock 47 0.00% 0.00% +system.ruby.l2_cntrl0.OO.L1_PUTX 11 0.00% 0.00% +system.ruby.l2_cntrl0.OO.Exclusive_Unblock 6 0.00% 0.00% +system.ruby.l2_cntrl0.MI.L1_GETX 81 0.00% 0.00% +system.ruby.l2_cntrl0.MI.Writeback_Ack 845 0.00% 0.00% +system.ruby.l1_cntrl0.Load 44 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 192 0.00% 0.00% +system.ruby.l1_cntrl0.Store 1001 0.00% 0.00% +system.ruby.l1_cntrl0.L1_Replacement 465203 0.00% 0.00% +system.ruby.l1_cntrl0.Exclusive_Data 907 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack_Data 903 0.00% 0.00% +system.ruby.l1_cntrl0.All_acks 813 0.00% 0.00% +system.ruby.l1_cntrl0.Use_Timeout 905 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 38 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 56 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 814 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_Replacement 92 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.L1_Replacement 1319 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Use_Timeout 93 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Load 6 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Store 66 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L1_Replacement 811 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Store 6 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.L1_Replacement 29843 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Use_Timeout 812 0.00% 0.00% +system.ruby.l1_cntrl0.IM.L1_Replacement 399867 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Exclusive_Data 813 0.00% 0.00% +system.ruby.l1_cntrl0.OM.L1_Replacement 17168 0.00% 0.00% +system.ruby.l1_cntrl0.OM.All_acks 813 0.00% 0.00% +system.ruby.l1_cntrl0.IS.L1_Replacement 16103 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Exclusive_Data 94 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Ifetch 136 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Store 115 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack_Data 903 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 837 0.00% 0.00% +system.ruby.dir_cntrl0.GETS 88 0.00% 0.00% +system.ruby.dir_cntrl0.PUTX 845 0.00% 0.00% +system.ruby.dir_cntrl0.Exclusive_Unblock 852 0.00% 0.00% +system.ruby.dir_cntrl0.Clean_Writeback 80 0.00% 0.00% +system.ruby.dir_cntrl0.Dirty_Writeback 765 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 854 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 765 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETX 766 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETS 88 0.00% 0.00% +system.ruby.dir_cntrl0.I.Memory_Ack 760 0.00% 0.00% +system.ruby.dir_cntrl0.M.PUTX 845 0.00% 0.00% +system.ruby.dir_cntrl0.IS.Exclusive_Unblock 87 0.00% 0.00% +system.ruby.dir_cntrl0.IS.Memory_Data 88 0.00% 0.00% +system.ruby.dir_cntrl0.IS.Memory_Ack 1 0.00% 0.00% +system.ruby.dir_cntrl0.MM.Exclusive_Unblock 765 0.00% 0.00% +system.ruby.dir_cntrl0.MM.Memory_Data 766 0.00% 0.00% +system.ruby.dir_cntrl0.MM.Memory_Ack 4 0.00% 0.00% +system.ruby.dir_cntrl0.MI.GETX 71 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Clean_Writeback 80 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Dirty_Writeback 765 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats index deefac4a6..63a174605 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats @@ -1,4 +1,4 @@ -Real time: Feb/02/2013 08:20:04 +Real time: Jun/08/2013 14:15:47 Profiler Stats -------------- @@ -16,11 +16,9 @@ Ruby_current_time: 225141 Ruby_start_time: 0 Ruby_cycles: 225141 -mbytes_resident: 49.4062 -mbytes_total: 265.762 -resident_ratio: 0.185963 - -ruby_cycles_executed: [ 225142 ] +mbytes_resident: 51.3164 +mbytes_total: 139.676 +resident_ratio: 0.367453 Busy Controller Counts: L1Cache-0:0 @@ -68,7 +66,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -89,7 +86,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10328 +page_reclaims: 10866 page_faults: 0 swaps: 0 block_inputs: 0 @@ -173,805 +170,3 @@ links_utilized_percent_switch_3: 1.99349 outgoing_messages_switch_3_link_2_Writeback_Control: 72 576 [ 0 0 0 0 72 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Persistent_Control: 373 2984 [ 0 0 0 373 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [53 ] 53 -Ifetch [47 ] 47 -Store [893 ] 893 -Atomic [0 ] 0 -L1_Replacement [19950 ] 19950 -Data_Shared [3 ] 3 -Data_Owner [1 ] 1 -Data_All_Tokens [993 ] 993 -Ack [0 ] 0 -Ack_All_Tokens [1 ] 1 -Transient_GETX [0 ] 0 -Transient_Local_GETX [0 ] 0 -Transient_GETS [0 ] 0 -Transient_Local_GETS [0 ] 0 -Transient_GETS_Last_Token [0 ] 0 -Transient_Local_GETS_Last_Token [0 ] 0 -Persistent_GETX [0 ] 0 -Persistent_GETS [0 ] 0 -Persistent_GETS_Last_Token [0 ] 0 -Own_Lock_or_Unlock [373 ] 373 -Request_Timeout [509 ] 509 -Use_TimeoutStarverX [0 ] 0 -Use_TimeoutStarverS [0 ] 0 -Use_TimeoutNoStarvers [906 ] 906 -Use_TimeoutNoStarvers_NoMig [0 ] 0 - - - Transitions - -NP Load [48 ] 48 -NP Ifetch [47 ] 47 -NP Store [816 ] 816 -NP Atomic [0 ] 0 -NP Data_Shared [0 ] 0 -NP Data_Owner [0 ] 0 -NP Data_All_Tokens [87 ] 87 -NP Ack [0 ] 0 -NP Transient_GETX [0 ] 0 -NP Transient_Local_GETX [0 ] 0 -NP Transient_GETS [0 ] 0 -NP Transient_Local_GETS [0 ] 0 -NP Persistent_GETX [0 ] 0 -NP Persistent_GETS [0 ] 0 -NP Persistent_GETS_Last_Token [0 ] 0 -NP Own_Lock_or_Unlock [180 ] 180 - -I Load [0 ] 0 -I Ifetch [0 ] 0 -I Store [0 ] 0 -I Atomic [0 ] 0 -I L1_Replacement [0 ] 0 -I Data_Shared [0 ] 0 -I Data_Owner [0 ] 0 -I Data_All_Tokens [0 ] 0 -I Ack [0 ] 0 -I Transient_GETX [0 ] 0 -I Transient_Local_GETX [0 ] 0 -I Transient_GETS [0 ] 0 -I Transient_Local_GETS [0 ] 0 -I Transient_GETS_Last_Token [0 ] 0 -I Transient_Local_GETS_Last_Token [0 ] 0 -I Persistent_GETX [0 ] 0 -I Persistent_GETS [0 ] 0 -I Persistent_GETS_Last_Token [0 ] 0 -I Own_Lock_or_Unlock [0 ] 0 - -S Load [0 ] 0 -S Ifetch [0 ] 0 -S Store [0 ] 0 -S Atomic [0 ] 0 -S L1_Replacement [3 ] 3 -S Data_Shared [0 ] 0 -S Data_Owner [0 ] 0 -S Data_All_Tokens [0 ] 0 -S Ack [0 ] 0 -S Transient_GETX [0 ] 0 -S Transient_Local_GETX [0 ] 0 -S Transient_GETS [0 ] 0 -S Transient_Local_GETS [0 ] 0 -S Transient_GETS_Last_Token [0 ] 0 -S Transient_Local_GETS_Last_Token [0 ] 0 -S Persistent_GETX [0 ] 0 -S Persistent_GETS [0 ] 0 -S Persistent_GETS_Last_Token [0 ] 0 -S Own_Lock_or_Unlock [0 ] 0 - -O Load [0 ] 0 -O Ifetch [0 ] 0 -O Store [0 ] 0 -O Atomic [0 ] 0 -O L1_Replacement [0 ] 0 -O Data_Shared [0 ] 0 -O Data_All_Tokens [0 ] 0 -O Ack [0 ] 0 -O Ack_All_Tokens [0 ] 0 -O Transient_GETX [0 ] 0 -O Transient_Local_GETX [0 ] 0 -O Transient_GETS [0 ] 0 -O Transient_Local_GETS [0 ] 0 -O Transient_GETS_Last_Token [0 ] 0 -O Transient_Local_GETS_Last_Token [0 ] 0 -O Persistent_GETX [0 ] 0 -O Persistent_GETS [0 ] 0 -O Persistent_GETS_Last_Token [0 ] 0 -O Own_Lock_or_Unlock [0 ] 0 - -M Load [0 ] 0 -M Ifetch [0 ] 0 -M Store [0 ] 0 -M Atomic [0 ] 0 -M L1_Replacement [89 ] 89 -M Transient_GETX [0 ] 0 -M Transient_Local_GETX [0 ] 0 -M Transient_GETS [0 ] 0 -M Transient_Local_GETS [0 ] 0 -M Persistent_GETX [0 ] 0 -M Persistent_GETS [0 ] 0 -M Own_Lock_or_Unlock [18 ] 18 - -MM Load [5 ] 5 -MM Ifetch [0 ] 0 -MM Store [66 ] 66 -MM Atomic [0 ] 0 -MM L1_Replacement [814 ] 814 -MM Transient_GETX [0 ] 0 -MM Transient_Local_GETX [0 ] 0 -MM Transient_GETS [0 ] 0 -MM Transient_Local_GETS [0 ] 0 -MM Persistent_GETX [0 ] 0 -MM Persistent_GETS [0 ] 0 -MM Own_Lock_or_Unlock [15 ] 15 - -M_W Load [0 ] 0 -M_W Ifetch [0 ] 0 -M_W Store [0 ] 0 -M_W Atomic [0 ] 0 -M_W L1_Replacement [468 ] 468 -M_W Transient_GETX [0 ] 0 -M_W Transient_Local_GETX [0 ] 0 -M_W Transient_GETS [0 ] 0 -M_W Transient_Local_GETS [0 ] 0 -M_W Persistent_GETX [0 ] 0 -M_W Persistent_GETS [0 ] 0 -M_W Own_Lock_or_Unlock [1 ] 1 -M_W Use_TimeoutStarverX [0 ] 0 -M_W Use_TimeoutStarverS [0 ] 0 -M_W Use_TimeoutNoStarvers [91 ] 91 -M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 - -MM_W Load [0 ] 0 -MM_W Ifetch [0 ] 0 -MM_W Store [11 ] 11 -MM_W Atomic [0 ] 0 -MM_W L1_Replacement [7711 ] 7711 -MM_W Transient_GETX [0 ] 0 -MM_W Transient_Local_GETX [0 ] 0 -MM_W Transient_GETS [0 ] 0 -MM_W Transient_Local_GETS [0 ] 0 -MM_W Persistent_GETX [0 ] 0 -MM_W Persistent_GETS [0 ] 0 -MM_W Own_Lock_or_Unlock [25 ] 25 -MM_W Use_TimeoutStarverX [0 ] 0 -MM_W Use_TimeoutStarverS [0 ] 0 -MM_W Use_TimeoutNoStarvers [815 ] 815 -MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM Atomic [0 ] 0 -IM L1_Replacement [10210 ] 10210 -IM Data_Shared [0 ] 0 -IM Data_Owner [1 ] 1 -IM Data_All_Tokens [814 ] 814 -IM Ack [0 ] 0 -IM Transient_GETX [0 ] 0 -IM Transient_Local_GETX [0 ] 0 -IM Transient_GETS [0 ] 0 -IM Transient_Local_GETS [0 ] 0 -IM Transient_GETS_Last_Token [0 ] 0 -IM Transient_Local_GETS_Last_Token [0 ] 0 -IM Persistent_GETX [0 ] 0 -IM Persistent_GETS [0 ] 0 -IM Persistent_GETS_Last_Token [0 ] 0 -IM Own_Lock_or_Unlock [114 ] 114 -IM Request_Timeout [443 ] 443 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM Atomic [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Data_Shared [0 ] 0 -SM Data_Owner [0 ] 0 -SM Data_All_Tokens [0 ] 0 -SM Ack [0 ] 0 -SM Transient_GETX [0 ] 0 -SM Transient_Local_GETX [0 ] 0 -SM Transient_GETS [0 ] 0 -SM Transient_Local_GETS [0 ] 0 -SM Transient_GETS_Last_Token [0 ] 0 -SM Transient_Local_GETS_Last_Token [0 ] 0 -SM Persistent_GETX [0 ] 0 -SM Persistent_GETS [0 ] 0 -SM Persistent_GETS_Last_Token [0 ] 0 -SM Own_Lock_or_Unlock [0 ] 0 -SM Request_Timeout [0 ] 0 - -OM Load [0 ] 0 -OM Ifetch [0 ] 0 -OM Store [0 ] 0 -OM Atomic [0 ] 0 -OM L1_Replacement [0 ] 0 -OM Data_Shared [0 ] 0 -OM Data_All_Tokens [0 ] 0 -OM Ack [0 ] 0 -OM Ack_All_Tokens [1 ] 1 -OM Transient_GETX [0 ] 0 -OM Transient_Local_GETX [0 ] 0 -OM Transient_GETS [0 ] 0 -OM Transient_Local_GETS [0 ] 0 -OM Transient_GETS_Last_Token [0 ] 0 -OM Transient_Local_GETS_Last_Token [0 ] 0 -OM Persistent_GETX [0 ] 0 -OM Persistent_GETS [0 ] 0 -OM Persistent_GETS_Last_Token [0 ] 0 -OM Own_Lock_or_Unlock [1 ] 1 -OM Request_Timeout [6 ] 6 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS Atomic [0 ] 0 -IS L1_Replacement [655 ] 655 -IS Data_Shared [3 ] 3 -IS Data_Owner [0 ] 0 -IS Data_All_Tokens [92 ] 92 -IS Ack [0 ] 0 -IS Transient_GETX [0 ] 0 -IS Transient_Local_GETX [0 ] 0 -IS Transient_GETS [0 ] 0 -IS Transient_Local_GETS [0 ] 0 -IS Transient_GETS_Last_Token [0 ] 0 -IS Transient_Local_GETS_Last_Token [0 ] 0 -IS Persistent_GETX [0 ] 0 -IS Persistent_GETS [0 ] 0 -IS Persistent_GETS_Last_Token [0 ] 0 -IS Own_Lock_or_Unlock [19 ] 19 -IS Request_Timeout [60 ] 60 - -I_L Load [0 ] 0 -I_L Ifetch [0 ] 0 -I_L Store [0 ] 0 -I_L Atomic [0 ] 0 -I_L L1_Replacement [0 ] 0 -I_L Data_Shared [0 ] 0 -I_L Data_Owner [0 ] 0 -I_L Data_All_Tokens [0 ] 0 -I_L Ack [0 ] 0 -I_L Transient_GETX [0 ] 0 -I_L Transient_Local_GETX [0 ] 0 -I_L Transient_GETS [0 ] 0 -I_L Transient_Local_GETS [0 ] 0 -I_L Transient_GETS_Last_Token [0 ] 0 -I_L Transient_Local_GETS_Last_Token [0 ] 0 -I_L Persistent_GETX [0 ] 0 -I_L Persistent_GETS [0 ] 0 -I_L Persistent_GETS_Last_Token [0 ] 0 -I_L Own_Lock_or_Unlock [0 ] 0 - -S_L Load [0 ] 0 -S_L Ifetch [0 ] 0 -S_L Store [0 ] 0 -S_L Atomic [0 ] 0 -S_L L1_Replacement [0 ] 0 -S_L Data_Shared [0 ] 0 -S_L Data_Owner [0 ] 0 -S_L Data_All_Tokens [0 ] 0 -S_L Ack [0 ] 0 -S_L Transient_GETX [0 ] 0 -S_L Transient_Local_GETX [0 ] 0 -S_L Transient_GETS [0 ] 0 -S_L Transient_Local_GETS [0 ] 0 -S_L Transient_GETS_Last_Token [0 ] 0 -S_L Transient_Local_GETS_Last_Token [0 ] 0 -S_L Persistent_GETX [0 ] 0 -S_L Persistent_GETS [0 ] 0 -S_L Persistent_GETS_Last_Token [0 ] 0 -S_L Own_Lock_or_Unlock [0 ] 0 - -IM_L Load [0 ] 0 -IM_L Ifetch [0 ] 0 -IM_L Store [0 ] 0 -IM_L Atomic [0 ] 0 -IM_L L1_Replacement [0 ] 0 -IM_L Data_Shared [0 ] 0 -IM_L Data_Owner [0 ] 0 -IM_L Data_All_Tokens [0 ] 0 -IM_L Ack [0 ] 0 -IM_L Transient_GETX [0 ] 0 -IM_L Transient_Local_GETX [0 ] 0 -IM_L Transient_GETS [0 ] 0 -IM_L Transient_Local_GETS [0 ] 0 -IM_L Transient_GETS_Last_Token [0 ] 0 -IM_L Transient_Local_GETS_Last_Token [0 ] 0 -IM_L Persistent_GETX [0 ] 0 -IM_L Persistent_GETS [0 ] 0 -IM_L Own_Lock_or_Unlock [0 ] 0 -IM_L Request_Timeout [0 ] 0 - -SM_L Load [0 ] 0 -SM_L Ifetch [0 ] 0 -SM_L Store [0 ] 0 -SM_L Atomic [0 ] 0 -SM_L L1_Replacement [0 ] 0 -SM_L Data_Shared [0 ] 0 -SM_L Data_Owner [0 ] 0 -SM_L Data_All_Tokens [0 ] 0 -SM_L Ack [0 ] 0 -SM_L Transient_GETX [0 ] 0 -SM_L Transient_Local_GETX [0 ] 0 -SM_L Transient_GETS [0 ] 0 -SM_L Transient_Local_GETS [0 ] 0 -SM_L Transient_GETS_Last_Token [0 ] 0 -SM_L Transient_Local_GETS_Last_Token [0 ] 0 -SM_L Persistent_GETX [0 ] 0 -SM_L Persistent_GETS [0 ] 0 -SM_L Persistent_GETS_Last_Token [0 ] 0 -SM_L Own_Lock_or_Unlock [0 ] 0 -SM_L Request_Timeout [0 ] 0 - -IS_L Load [0 ] 0 -IS_L Ifetch [0 ] 0 -IS_L Store [0 ] 0 -IS_L Atomic [0 ] 0 -IS_L L1_Replacement [0 ] 0 -IS_L Data_Shared [0 ] 0 -IS_L Data_Owner [0 ] 0 -IS_L Data_All_Tokens [0 ] 0 -IS_L Ack [0 ] 0 -IS_L Transient_GETX [0 ] 0 -IS_L Transient_Local_GETX [0 ] 0 -IS_L Transient_GETS [0 ] 0 -IS_L Transient_Local_GETS [0 ] 0 -IS_L Transient_GETS_Last_Token [0 ] 0 -IS_L Transient_Local_GETS_Last_Token [0 ] 0 -IS_L Persistent_GETX [0 ] 0 -IS_L Persistent_GETS [0 ] 0 -IS_L Own_Lock_or_Unlock [0 ] 0 -IS_L Request_Timeout [0 ] 0 - - --- L2Cache --- - - Event Counts - -L1_GETS [95 ] 95 -L1_GETS_Last_Token [0 ] 0 -L1_GETX [816 ] 816 -L1_INV [0 ] 0 -Transient_GETX [0 ] 0 -Transient_GETS [0 ] 0 -Transient_GETS_Last_Token [0 ] 0 -L2_Replacement [817 ] 817 -Writeback_Tokens [0 ] 0 -Writeback_Shared_Data [1 ] 1 -Writeback_All_Tokens [905 ] 905 -Writeback_Owned [0 ] 0 -Data_Shared [0 ] 0 -Data_Owner [0 ] 0 -Data_All_Tokens [0 ] 0 -Ack [0 ] 0 -Ack_All_Tokens [0 ] 0 -Persistent_GETX [163 ] 163 -Persistent_GETS [24 ] 24 -Persistent_GETS_Last_Token [0 ] 0 -Own_Lock_or_Unlock [186 ] 186 - - - Transitions - -NP L1_GETS [91 ] 91 -NP L1_GETX [779 ] 779 -NP L1_INV [0 ] 0 -NP Transient_GETX [0 ] 0 -NP Transient_GETS [0 ] 0 -NP Writeback_Tokens [0 ] 0 -NP Writeback_Shared_Data [0 ] 0 -NP Writeback_All_Tokens [821 ] 821 -NP Writeback_Owned [0 ] 0 -NP Data_Shared [0 ] 0 -NP Data_Owner [0 ] 0 -NP Data_All_Tokens [0 ] 0 -NP Ack [0 ] 0 -NP Persistent_GETX [0 ] 0 -NP Persistent_GETS [0 ] 0 -NP Persistent_GETS_Last_Token [0 ] 0 -NP Own_Lock_or_Unlock [158 ] 158 - -I L1_GETS [1 ] 1 -I L1_GETS_Last_Token [0 ] 0 -I L1_GETX [0 ] 0 -I L1_INV [0 ] 0 -I Transient_GETX [0 ] 0 -I Transient_GETS [0 ] 0 -I Transient_GETS_Last_Token [0 ] 0 -I L2_Replacement [32 ] 32 -I Writeback_Tokens [0 ] 0 -I Writeback_Shared_Data [1 ] 1 -I Writeback_All_Tokens [31 ] 31 -I Writeback_Owned [0 ] 0 -I Data_Shared [0 ] 0 -I Data_Owner [0 ] 0 -I Data_All_Tokens [0 ] 0 -I Ack [0 ] 0 -I Persistent_GETX [0 ] 0 -I Persistent_GETS [0 ] 0 -I Persistent_GETS_Last_Token [0 ] 0 -I Own_Lock_or_Unlock [0 ] 0 - -S L1_GETS [0 ] 0 -S L1_GETS_Last_Token [0 ] 0 -S L1_GETX [0 ] 0 -S L1_INV [0 ] 0 -S Transient_GETX [0 ] 0 -S Transient_GETS [0 ] 0 -S Transient_GETS_Last_Token [0 ] 0 -S L2_Replacement [0 ] 0 -S Writeback_Tokens [0 ] 0 -S Writeback_Shared_Data [0 ] 0 -S Writeback_All_Tokens [0 ] 0 -S Writeback_Owned [0 ] 0 -S Data_Shared [0 ] 0 -S Data_Owner [0 ] 0 -S Data_All_Tokens [0 ] 0 -S Ack [0 ] 0 -S Persistent_GETX [1 ] 1 -S Persistent_GETS [0 ] 0 -S Persistent_GETS_Last_Token [0 ] 0 -S Own_Lock_or_Unlock [0 ] 0 - -O L1_GETS [0 ] 0 -O L1_GETS_Last_Token [0 ] 0 -O L1_GETX [1 ] 1 -O L1_INV [0 ] 0 -O Transient_GETX [0 ] 0 -O Transient_GETS [0 ] 0 -O Transient_GETS_Last_Token [0 ] 0 -O L2_Replacement [0 ] 0 -O Writeback_Tokens [0 ] 0 -O Writeback_Shared_Data [0 ] 0 -O Writeback_All_Tokens [2 ] 2 -O Data_Shared [0 ] 0 -O Data_All_Tokens [0 ] 0 -O Ack [0 ] 0 -O Ack_All_Tokens [0 ] 0 -O Persistent_GETX [0 ] 0 -O Persistent_GETS [0 ] 0 -O Persistent_GETS_Last_Token [0 ] 0 -O Own_Lock_or_Unlock [0 ] 0 - -M L1_GETS [3 ] 3 -M L1_GETX [36 ] 36 -M L1_INV [0 ] 0 -M Transient_GETX [0 ] 0 -M Transient_GETS [0 ] 0 -M L2_Replacement [784 ] 784 -M Persistent_GETX [23 ] 23 -M Persistent_GETS [5 ] 5 -M Own_Lock_or_Unlock [0 ] 0 - -I_L L1_GETS [0 ] 0 -I_L L1_GETX [0 ] 0 -I_L L1_INV [0 ] 0 -I_L Transient_GETX [0 ] 0 -I_L Transient_GETS [0 ] 0 -I_L Transient_GETS_Last_Token [0 ] 0 -I_L L2_Replacement [1 ] 1 -I_L Writeback_Tokens [0 ] 0 -I_L Writeback_Shared_Data [0 ] 0 -I_L Writeback_All_Tokens [51 ] 51 -I_L Writeback_Owned [0 ] 0 -I_L Data_Shared [0 ] 0 -I_L Data_Owner [0 ] 0 -I_L Data_All_Tokens [0 ] 0 -I_L Ack [0 ] 0 -I_L Persistent_GETX [139 ] 139 -I_L Persistent_GETS [19 ] 19 -I_L Own_Lock_or_Unlock [28 ] 28 - -S_L L1_GETS [0 ] 0 -S_L L1_GETS_Last_Token [0 ] 0 -S_L L1_GETX [0 ] 0 -S_L L1_INV [0 ] 0 -S_L Transient_GETX [0 ] 0 -S_L Transient_GETS [0 ] 0 -S_L Transient_GETS_Last_Token [0 ] 0 -S_L L2_Replacement [0 ] 0 -S_L Writeback_Tokens [0 ] 0 -S_L Writeback_Shared_Data [0 ] 0 -S_L Writeback_All_Tokens [0 ] 0 -S_L Writeback_Owned [0 ] 0 -S_L Data_Shared [0 ] 0 -S_L Data_Owner [0 ] 0 -S_L Data_All_Tokens [0 ] 0 -S_L Ack [0 ] 0 -S_L Persistent_GETX [0 ] 0 -S_L Persistent_GETS [0 ] 0 -S_L Persistent_GETS_Last_Token [0 ] 0 -S_L Own_Lock_or_Unlock [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 1655 - memory_reads: 868 - memory_writes: 787 - memory_refreshes: 1564 - memory_total_request_delays: 503 - memory_delays_per_request: 0.303927 - memory_delays_in_input_queue: 34 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 469 - memory_stalls_for_bank_busy: 134 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 39 - memory_stalls_for_bus: 192 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 48 - memory_stalls_for_read_read_turnaround: 56 - accesses_per_bank: 51 47 34 94 74 59 55 45 53 55 62 49 52 51 44 57 49 51 46 44 46 41 54 56 46 55 50 43 43 47 62 40 - - --- Directory --- - - Event Counts - -GETX [789 ] 789 -GETS [94 ] 94 -Lockdown [187 ] 187 -Unlockdown [186 ] 186 -Own_Lock_or_Unlock [0 ] 0 -Own_Lock_or_Unlock_Tokens [0 ] 0 -Data_Owner [0 ] 0 -Data_All_Tokens [799 ] 799 -Ack_Owner [0 ] 0 -Ack_Owner_All_Tokens [72 ] 72 -Tokens [0 ] 0 -Ack_All_Tokens [0 ] 0 -Request_Timeout [0 ] 0 -Memory_Data [868 ] 868 -Memory_Ack [787 ] 787 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -DMA_WRITE_All_Tokens [0 ] 0 - - - Transitions - -O GETX [768 ] 768 -O GETS [86 ] 86 -O Lockdown [14 ] 14 -O Unlockdown [0 ] 0 -O Own_Lock_or_Unlock [0 ] 0 -O Own_Lock_or_Unlock_Tokens [0 ] 0 -O Data_Owner [0 ] 0 -O Data_All_Tokens [0 ] 0 -O Tokens [0 ] 0 -O Ack_All_Tokens [0 ] 0 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 -O DMA_WRITE_All_Tokens [0 ] 0 - -NO GETX [2 ] 2 -NO GETS [4 ] 4 -NO Lockdown [166 ] 166 -NO Unlockdown [0 ] 0 -NO Own_Lock_or_Unlock [0 ] 0 -NO Own_Lock_or_Unlock_Tokens [0 ] 0 -NO Data_Owner [0 ] 0 -NO Data_All_Tokens [787 ] 787 -NO Ack_Owner [0 ] 0 -NO Ack_Owner_All_Tokens [72 ] 72 -NO Tokens [0 ] 0 -NO DMA_READ [0 ] 0 -NO DMA_WRITE [0 ] 0 - -L GETX [10 ] 10 -L GETS [2 ] 2 -L Lockdown [0 ] 0 -L Unlockdown [185 ] 185 -L Own_Lock_or_Unlock [0 ] 0 -L Own_Lock_or_Unlock_Tokens [0 ] 0 -L Data_Owner [0 ] 0 -L Data_All_Tokens [12 ] 12 -L Ack_Owner [0 ] 0 -L Ack_Owner_All_Tokens [0 ] 0 -L Tokens [0 ] 0 -L DMA_READ [0 ] 0 -L DMA_WRITE [0 ] 0 -L DMA_WRITE_All_Tokens [0 ] 0 - -O_W GETX [0 ] 0 -O_W GETS [0 ] 0 -O_W Lockdown [0 ] 0 -O_W Unlockdown [0 ] 0 -O_W Own_Lock_or_Unlock [0 ] 0 -O_W Own_Lock_or_Unlock_Tokens [0 ] 0 -O_W Data_Owner [0 ] 0 -O_W Data_All_Tokens [0 ] 0 -O_W Ack_Owner [0 ] 0 -O_W Tokens [0 ] 0 -O_W Ack_All_Tokens [0 ] 0 -O_W Memory_Data [1 ] 1 -O_W Memory_Ack [787 ] 787 -O_W DMA_READ [0 ] 0 -O_W DMA_WRITE [0 ] 0 -O_W DMA_WRITE_All_Tokens [0 ] 0 - -L_O_W GETX [9 ] 9 -L_O_W GETS [2 ] 2 -L_O_W Lockdown [0 ] 0 -L_O_W Unlockdown [1 ] 1 -L_O_W Own_Lock_or_Unlock [0 ] 0 -L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 -L_O_W Data_Owner [0 ] 0 -L_O_W Data_All_Tokens [0 ] 0 -L_O_W Ack_Owner [0 ] 0 -L_O_W Tokens [0 ] 0 -L_O_W Ack_All_Tokens [0 ] 0 -L_O_W Memory_Data [13 ] 13 -L_O_W Memory_Ack [0 ] 0 -L_O_W DMA_READ [0 ] 0 -L_O_W DMA_WRITE [0 ] 0 -L_O_W DMA_WRITE_All_Tokens [0 ] 0 - -L_NO_W GETX [0 ] 0 -L_NO_W GETS [0 ] 0 -L_NO_W Lockdown [0 ] 0 -L_NO_W Unlockdown [0 ] 0 -L_NO_W Own_Lock_or_Unlock [0 ] 0 -L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 -L_NO_W Data_Owner [0 ] 0 -L_NO_W Data_All_Tokens [0 ] 0 -L_NO_W Ack_Owner [0 ] 0 -L_NO_W Tokens [0 ] 0 -L_NO_W Ack_All_Tokens [0 ] 0 -L_NO_W Memory_Data [7 ] 7 -L_NO_W DMA_READ [0 ] 0 -L_NO_W DMA_WRITE [0 ] 0 -L_NO_W DMA_WRITE_All_Tokens [0 ] 0 - -DR_L_W GETX [0 ] 0 -DR_L_W GETS [0 ] 0 -DR_L_W Lockdown [0 ] 0 -DR_L_W Unlockdown [0 ] 0 -DR_L_W Own_Lock_or_Unlock [0 ] 0 -DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 -DR_L_W Data_Owner [0 ] 0 -DR_L_W Data_All_Tokens [0 ] 0 -DR_L_W Ack_Owner [0 ] 0 -DR_L_W Tokens [0 ] 0 -DR_L_W Ack_All_Tokens [0 ] 0 -DR_L_W Request_Timeout [0 ] 0 -DR_L_W Memory_Data [0 ] 0 -DR_L_W DMA_READ [0 ] 0 -DR_L_W DMA_WRITE [0 ] 0 -DR_L_W DMA_WRITE_All_Tokens [0 ] 0 - -DW_L_W GETX [0 ] 0 -DW_L_W GETS [0 ] 0 -DW_L_W Lockdown [0 ] 0 -DW_L_W Unlockdown [0 ] 0 -DW_L_W Own_Lock_or_Unlock [0 ] 0 -DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 -DW_L_W Data_Owner [0 ] 0 -DW_L_W Data_All_Tokens [0 ] 0 -DW_L_W Ack_Owner [0 ] 0 -DW_L_W Tokens [0 ] 0 -DW_L_W Ack_All_Tokens [0 ] 0 -DW_L_W Request_Timeout [0 ] 0 -DW_L_W Memory_Ack [0 ] 0 -DW_L_W DMA_READ [0 ] 0 -DW_L_W DMA_WRITE [0 ] 0 -DW_L_W DMA_WRITE_All_Tokens [0 ] 0 - -NO_W GETX [0 ] 0 -NO_W GETS [0 ] 0 -NO_W Lockdown [7 ] 7 -NO_W Unlockdown [0 ] 0 -NO_W Own_Lock_or_Unlock [0 ] 0 -NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 -NO_W Data_Owner [0 ] 0 -NO_W Data_All_Tokens [0 ] 0 -NO_W Ack_Owner [0 ] 0 -NO_W Tokens [0 ] 0 -NO_W Ack_All_Tokens [0 ] 0 -NO_W Memory_Data [847 ] 847 -NO_W DMA_READ [0 ] 0 -NO_W DMA_WRITE [0 ] 0 -NO_W DMA_WRITE_All_Tokens [0 ] 0 - -O_DW_W GETX [0 ] 0 -O_DW_W GETS [0 ] 0 -O_DW_W Lockdown [0 ] 0 -O_DW_W Unlockdown [0 ] 0 -O_DW_W Own_Lock_or_Unlock [0 ] 0 -O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 -O_DW_W Data_Owner [0 ] 0 -O_DW_W Data_All_Tokens [0 ] 0 -O_DW_W Ack_Owner [0 ] 0 -O_DW_W Tokens [0 ] 0 -O_DW_W Ack_All_Tokens [0 ] 0 -O_DW_W Request_Timeout [0 ] 0 -O_DW_W Memory_Ack [0 ] 0 -O_DW_W DMA_READ [0 ] 0 -O_DW_W DMA_WRITE [0 ] 0 -O_DW_W DMA_WRITE_All_Tokens [0 ] 0 - -O_DR_W GETX [0 ] 0 -O_DR_W GETS [0 ] 0 -O_DR_W Lockdown [0 ] 0 -O_DR_W Unlockdown [0 ] 0 -O_DR_W Own_Lock_or_Unlock [0 ] 0 -O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 -O_DR_W Data_Owner [0 ] 0 -O_DR_W Data_All_Tokens [0 ] 0 -O_DR_W Ack_Owner [0 ] 0 -O_DR_W Tokens [0 ] 0 -O_DR_W Ack_All_Tokens [0 ] 0 -O_DR_W Request_Timeout [0 ] 0 -O_DR_W Memory_Data [0 ] 0 -O_DR_W DMA_READ [0 ] 0 -O_DR_W DMA_WRITE [0 ] 0 -O_DR_W DMA_WRITE_All_Tokens [0 ] 0 - -O_DW GETX [0 ] 0 -O_DW GETS [0 ] 0 -O_DW Lockdown [0 ] 0 -O_DW Unlockdown [0 ] 0 -O_DW Own_Lock_or_Unlock [0 ] 0 -O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 -O_DW Data_Owner [0 ] 0 -O_DW Data_All_Tokens [0 ] 0 -O_DW Ack_Owner [0 ] 0 -O_DW Ack_Owner_All_Tokens [0 ] 0 -O_DW Tokens [0 ] 0 -O_DW Ack_All_Tokens [0 ] 0 -O_DW Request_Timeout [0 ] 0 -O_DW DMA_READ [0 ] 0 -O_DW DMA_WRITE [0 ] 0 -O_DW DMA_WRITE_All_Tokens [0 ] 0 - -NO_DW GETX [0 ] 0 -NO_DW GETS [0 ] 0 -NO_DW Lockdown [0 ] 0 -NO_DW Unlockdown [0 ] 0 -NO_DW Own_Lock_or_Unlock [0 ] 0 -NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 -NO_DW Data_Owner [0 ] 0 -NO_DW Data_All_Tokens [0 ] 0 -NO_DW Tokens [0 ] 0 -NO_DW Request_Timeout [0 ] 0 -NO_DW DMA_READ [0 ] 0 -NO_DW DMA_WRITE [0 ] 0 -NO_DW DMA_WRITE_All_Tokens [0 ] 0 - -NO_DR GETX [0 ] 0 -NO_DR GETS [0 ] 0 -NO_DR Lockdown [0 ] 0 -NO_DR Unlockdown [0 ] 0 -NO_DR Own_Lock_or_Unlock [0 ] 0 -NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 -NO_DR Data_Owner [0 ] 0 -NO_DR Data_All_Tokens [0 ] 0 -NO_DR Tokens [0 ] 0 -NO_DR Request_Timeout [0 ] 0 -NO_DR DMA_READ [0 ] 0 -NO_DR DMA_WRITE [0 ] 0 -NO_DR DMA_WRITE_All_Tokens [0 ] 0 - -DW_L GETX [0 ] 0 -DW_L GETS [0 ] 0 -DW_L Lockdown [0 ] 0 -DW_L Unlockdown [0 ] 0 -DW_L Own_Lock_or_Unlock [0 ] 0 -DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 -DW_L Data_Owner [0 ] 0 -DW_L Data_All_Tokens [0 ] 0 -DW_L Ack_Owner [0 ] 0 -DW_L Ack_Owner_All_Tokens [0 ] 0 -DW_L Tokens [0 ] 0 -DW_L Request_Timeout [0 ] 0 -DW_L DMA_READ [0 ] 0 -DW_L DMA_WRITE [0 ] 0 -DW_L DMA_WRITE_All_Tokens [0 ] 0 - -DR_L GETX [0 ] 0 -DR_L GETS [0 ] 0 -DR_L Lockdown [0 ] 0 -DR_L Unlockdown [0 ] 0 -DR_L Own_Lock_or_Unlock [0 ] 0 -DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 -DR_L Data_Owner [0 ] 0 -DR_L Data_All_Tokens [0 ] 0 -DR_L Ack_Owner [0 ] 0 -DR_L Ack_Owner_All_Tokens [0 ] 0 -DR_L Tokens [0 ] 0 -DR_L Request_Timeout [0 ] 0 -DR_L DMA_READ [0 ] 0 -DR_L DMA_WRITE [0 ] 0 -DR_L DMA_WRITE_All_Tokens [0 ] 0 - diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index b9333bbb2..d96eb4e42 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000225 # Nu sim_ticks 225141 # Number of ticks simulated final_tick 225141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1225804 # Simulator tick rate (ticks/s) -host_mem_usage 149920 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_tick_rate 1771035 # Simulator tick rate (ticks/s) +host_mem_usage 143032 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host system.ruby.l2_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 872 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 911 # Number of cache demand accesses @@ -16,5 +16,122 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 946 system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 47 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 47 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 1655 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 868 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 787 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 1564 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 469 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 34 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 503 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.303927 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 134 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 192 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 48 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 56 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 39 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 51 3.08% 3.08% | 47 2.84% 5.92% | 34 2.05% 7.98% | 94 5.68% 13.66% | 74 4.47% 18.13% | 59 3.56% 21.69% | 55 3.32% 25.02% | 45 2.72% 27.73% | 53 3.20% 30.94% | 55 3.32% 34.26% | 62 3.75% 38.01% | 49 2.96% 40.97% | 52 3.14% 44.11% | 51 3.08% 47.19% | 44 2.66% 49.85% | 57 3.44% 53.29% | 49 2.96% 56.25% | 51 3.08% 59.34% | 46 2.78% 62.11% | 44 2.66% 64.77% | 46 2.78% 67.55% | 41 2.48% 70.03% | 54 3.26% 73.29% | 56 3.38% 76.68% | 46 2.78% 79.46% | 55 3.32% 82.78% | 50 3.02% 85.80% | 43 2.60% 88.40% | 43 2.60% 91.00% | 47 2.84% 93.84% | 62 3.75% 97.58% | 40 2.42% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1655 # Number of accesses per bank + +system.ruby.l2_cntrl0.L1_GETS 95 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 816 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 817 0.00% 0.00% +system.ruby.l2_cntrl0.Writeback_Shared_Data 1 0.00% 0.00% +system.ruby.l2_cntrl0.Writeback_All_Tokens 905 0.00% 0.00% +system.ruby.l2_cntrl0.Persistent_GETX 163 0.00% 0.00% +system.ruby.l2_cntrl0.Persistent_GETS 24 0.00% 0.00% +system.ruby.l2_cntrl0.Own_Lock_or_Unlock 186 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 91 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 779 0.00% 0.00% +system.ruby.l2_cntrl0.NP.Writeback_All_Tokens 821 0.00% 0.00% +system.ruby.l2_cntrl0.NP.Own_Lock_or_Unlock 158 0.00% 0.00% +system.ruby.l2_cntrl0.I.L1_GETS 1 0.00% 0.00% +system.ruby.l2_cntrl0.I.L2_Replacement 32 0.00% 0.00% +system.ruby.l2_cntrl0.I.Writeback_Shared_Data 1 0.00% 0.00% +system.ruby.l2_cntrl0.I.Writeback_All_Tokens 31 0.00% 0.00% +system.ruby.l2_cntrl0.S.Persistent_GETX 1 0.00% 0.00% +system.ruby.l2_cntrl0.O.L1_GETX 1 0.00% 0.00% +system.ruby.l2_cntrl0.O.Writeback_All_Tokens 2 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETS 3 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 36 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 784 0.00% 0.00% +system.ruby.l2_cntrl0.M.Persistent_GETX 23 0.00% 0.00% +system.ruby.l2_cntrl0.M.Persistent_GETS 5 0.00% 0.00% +system.ruby.l2_cntrl0.I_L.L2_Replacement 1 0.00% 0.00% +system.ruby.l2_cntrl0.I_L.Writeback_All_Tokens 51 0.00% 0.00% +system.ruby.l2_cntrl0.I_L.Persistent_GETX 139 0.00% 0.00% +system.ruby.l2_cntrl0.I_L.Persistent_GETS 19 0.00% 0.00% +system.ruby.l2_cntrl0.I_L.Own_Lock_or_Unlock 28 0.00% 0.00% +system.ruby.l1_cntrl0.Load 53 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 47 0.00% 0.00% +system.ruby.l1_cntrl0.Store 893 0.00% 0.00% +system.ruby.l1_cntrl0.L1_Replacement 19950 0.00% 0.00% +system.ruby.l1_cntrl0.Data_Shared 3 0.00% 0.00% +system.ruby.l1_cntrl0.Data_Owner 1 0.00% 0.00% +system.ruby.l1_cntrl0.Data_All_Tokens 993 0.00% 0.00% +system.ruby.l1_cntrl0.Ack_All_Tokens 1 0.00% 0.00% +system.ruby.l1_cntrl0.Own_Lock_or_Unlock 373 0.00% 0.00% +system.ruby.l1_cntrl0.Request_Timeout 509 0.00% 0.00% +system.ruby.l1_cntrl0.Use_TimeoutNoStarvers 906 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Load 48 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Ifetch 47 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Store 816 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Data_All_Tokens 87 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Own_Lock_or_Unlock 180 0.00% 0.00% +system.ruby.l1_cntrl0.S.L1_Replacement 3 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_Replacement 89 0.00% 0.00% +system.ruby.l1_cntrl0.M.Own_Lock_or_Unlock 18 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Load 5 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Store 66 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L1_Replacement 814 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Own_Lock_or_Unlock 15 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.L1_Replacement 468 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Own_Lock_or_Unlock 1 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Use_TimeoutNoStarvers 91 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Store 11 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.L1_Replacement 7711 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Own_Lock_or_Unlock 25 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Use_TimeoutNoStarvers 815 0.00% 0.00% +system.ruby.l1_cntrl0.IM.L1_Replacement 10210 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data_Owner 1 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data_All_Tokens 814 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Own_Lock_or_Unlock 114 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Request_Timeout 443 0.00% 0.00% +system.ruby.l1_cntrl0.OM.Ack_All_Tokens 1 0.00% 0.00% +system.ruby.l1_cntrl0.OM.Own_Lock_or_Unlock 1 0.00% 0.00% +system.ruby.l1_cntrl0.OM.Request_Timeout 6 0.00% 0.00% +system.ruby.l1_cntrl0.IS.L1_Replacement 655 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_Shared 3 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_All_Tokens 92 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Own_Lock_or_Unlock 19 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Request_Timeout 60 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 789 0.00% 0.00% +system.ruby.dir_cntrl0.GETS 94 0.00% 0.00% +system.ruby.dir_cntrl0.Lockdown 187 0.00% 0.00% +system.ruby.dir_cntrl0.Unlockdown 186 0.00% 0.00% +system.ruby.dir_cntrl0.Data_All_Tokens 799 0.00% 0.00% +system.ruby.dir_cntrl0.Ack_Owner_All_Tokens 72 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 868 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 787 0.00% 0.00% +system.ruby.dir_cntrl0.O.GETX 768 0.00% 0.00% +system.ruby.dir_cntrl0.O.GETS 86 0.00% 0.00% +system.ruby.dir_cntrl0.O.Lockdown 14 0.00% 0.00% +system.ruby.dir_cntrl0.NO.GETX 2 0.00% 0.00% +system.ruby.dir_cntrl0.NO.GETS 4 0.00% 0.00% +system.ruby.dir_cntrl0.NO.Lockdown 166 0.00% 0.00% +system.ruby.dir_cntrl0.NO.Data_All_Tokens 787 0.00% 0.00% +system.ruby.dir_cntrl0.NO.Ack_Owner_All_Tokens 72 0.00% 0.00% +system.ruby.dir_cntrl0.L.GETX 10 0.00% 0.00% +system.ruby.dir_cntrl0.L.GETS 2 0.00% 0.00% +system.ruby.dir_cntrl0.L.Unlockdown 185 0.00% 0.00% +system.ruby.dir_cntrl0.L.Data_All_Tokens 12 0.00% 0.00% +system.ruby.dir_cntrl0.O_W.Memory_Data 1 0.00% 0.00% +system.ruby.dir_cntrl0.O_W.Memory_Ack 787 0.00% 0.00% +system.ruby.dir_cntrl0.L_O_W.GETX 9 0.00% 0.00% +system.ruby.dir_cntrl0.L_O_W.GETS 2 0.00% 0.00% +system.ruby.dir_cntrl0.L_O_W.Unlockdown 1 0.00% 0.00% +system.ruby.dir_cntrl0.L_O_W.Memory_Data 13 0.00% 0.00% +system.ruby.dir_cntrl0.L_NO_W.Memory_Data 7 0.00% 0.00% +system.ruby.dir_cntrl0.NO_W.Lockdown 7 0.00% 0.00% +system.ruby.dir_cntrl0.NO_W.Memory_Data 847 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats index 3336c8aea..822026fbf 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats @@ -1,4 +1,4 @@ -Real time: Feb/02/2013 08:11:05 +Real time: Jun/08/2013 13:29:50 Profiler Stats -------------- @@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.52 -Virtual_time_in_minutes: 0.00866667 -Virtual_time_in_hours: 0.000144444 -Virtual_time_in_days: 6.01852e-06 +Virtual_time_in_seconds: 0.5 +Virtual_time_in_minutes: 0.00833333 +Virtual_time_in_hours: 0.000138889 +Virtual_time_in_days: 5.78704e-06 Ruby_current_time: 172201 Ruby_start_time: 0 Ruby_cycles: 172201 -mbytes_resident: 49.1211 -mbytes_total: 265.684 -resident_ratio: 0.18493 - -ruby_cycles_executed: [ 172202 ] +mbytes_resident: 51.9141 +mbytes_total: 139.598 +resident_ratio: 0.371939 Busy Controller Counts: L1Cache-0:0 @@ -69,7 +67,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -90,11 +87,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10236 -page_faults: 0 +page_reclaims: 13998 +page_faults: 36 swaps: 0 -block_inputs: 0 -block_outputs: 96 +block_inputs: 4432 +block_outputs: 88 Network Stats ------------- @@ -145,749 +142,3 @@ links_utilized_percent_switch_2: 2.61613 outgoing_messages_switch_2_link_1_Writeback_Control: 918 7344 [ 0 0 843 0 0 75 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Unblock_Control: 845 6760 [ 0 0 0 0 0 845 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [52 ] 52 -Ifetch [53 ] 53 -Store [888 ] 888 -L2_Replacement [840 ] 840 -L1_to_L2 [16587 ] 16587 -Trigger_L2_to_L1D [41 ] 41 -Trigger_L2_to_L1I [9 ] 9 -Complete_L2_to_L1 [50 ] 50 -Other_GETX [0 ] 0 -Other_GETS [0 ] 0 -Merged_GETS [0 ] 0 -Other_GETS_No_Mig [0 ] 0 -NC_DMA_GETS [0 ] 0 -Invalidate [0 ] 0 -Ack [0 ] 0 -Shared_Ack [0 ] 0 -Data [0 ] 0 -Shared_Data [0 ] 0 -Exclusive_Data [850 ] 850 -Writeback_Ack [843 ] 843 -Writeback_Nack [0 ] 0 -All_acks [0 ] 0 -All_acks_no_sharers [850 ] 850 -Flush_line [5 ] 5 -Block_Ack [1 ] 1 - - - Transitions - -I Load [46 ] 46 -I Ifetch [40 ] 40 -I Store [762 ] 762 -I L2_Replacement [0 ] 0 -I L1_to_L2 [0 ] 0 -I Trigger_L2_to_L1D [0 ] 0 -I Trigger_L2_to_L1I [0 ] 0 -I Other_GETX [0 ] 0 -I Other_GETS [0 ] 0 -I Other_GETS_No_Mig [0 ] 0 -I NC_DMA_GETS [0 ] 0 -I Invalidate [0 ] 0 -I Flush_line [4 ] 4 - -S Load [0 ] 0 -S Ifetch [0 ] 0 -S Store [0 ] 0 -S L2_Replacement [0 ] 0 -S L1_to_L2 [0 ] 0 -S Trigger_L2_to_L1D [0 ] 0 -S Trigger_L2_to_L1I [0 ] 0 -S Other_GETX [0 ] 0 -S Other_GETS [0 ] 0 -S Other_GETS_No_Mig [0 ] 0 -S NC_DMA_GETS [0 ] 0 -S Invalidate [0 ] 0 -S Flush_line [0 ] 0 - -O Load [0 ] 0 -O Ifetch [0 ] 0 -O Store [0 ] 0 -O L2_Replacement [0 ] 0 -O L1_to_L2 [0 ] 0 -O Trigger_L2_to_L1D [0 ] 0 -O Trigger_L2_to_L1I [0 ] 0 -O Other_GETX [0 ] 0 -O Other_GETS [0 ] 0 -O Merged_GETS [0 ] 0 -O Other_GETS_No_Mig [0 ] 0 -O NC_DMA_GETS [0 ] 0 -O Invalidate [0 ] 0 -O Flush_line [0 ] 0 - -M Load [0 ] 0 -M Ifetch [1 ] 1 -M Store [0 ] 0 -M L2_Replacement [71 ] 71 -M L1_to_L2 [83 ] 83 -M Trigger_L2_to_L1D [11 ] 11 -M Trigger_L2_to_L1I [0 ] 0 -M Other_GETX [0 ] 0 -M Other_GETS [0 ] 0 -M Merged_GETS [0 ] 0 -M Other_GETS_No_Mig [0 ] 0 -M NC_DMA_GETS [0 ] 0 -M Invalidate [0 ] 0 -M Flush_line [0 ] 0 - -MM Load [5 ] 5 -MM Ifetch [0 ] 0 -MM Store [62 ] 62 -MM L2_Replacement [769 ] 769 -MM L1_to_L2 [809 ] 809 -MM Trigger_L2_to_L1D [30 ] 30 -MM Trigger_L2_to_L1I [9 ] 9 -MM Other_GETX [0 ] 0 -MM Other_GETS [0 ] 0 -MM Merged_GETS [0 ] 0 -MM Other_GETS_No_Mig [0 ] 0 -MM NC_DMA_GETS [0 ] 0 -MM Invalidate [0 ] 0 -MM Flush_line [0 ] 0 - -IR Load [0 ] 0 -IR Ifetch [0 ] 0 -IR Store [0 ] 0 -IR L1_to_L2 [0 ] 0 -IR Flush_line [0 ] 0 - -SR Load [0 ] 0 -SR Ifetch [0 ] 0 -SR Store [0 ] 0 -SR L1_to_L2 [0 ] 0 -SR Flush_line [0 ] 0 - -OR Load [0 ] 0 -OR Ifetch [0 ] 0 -OR Store [0 ] 0 -OR L1_to_L2 [0 ] 0 -OR Flush_line [0 ] 0 - -MR Load [0 ] 0 -MR Ifetch [0 ] 0 -MR Store [11 ] 11 -MR L1_to_L2 [90 ] 90 -MR Flush_line [0 ] 0 - -MMR Load [0 ] 0 -MMR Ifetch [9 ] 9 -MMR Store [29 ] 29 -MMR L1_to_L2 [25 ] 25 -MMR Flush_line [1 ] 1 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM L2_Replacement [0 ] 0 -IM L1_to_L2 [9996 ] 9996 -IM Other_GETX [0 ] 0 -IM Other_GETS [0 ] 0 -IM Other_GETS_No_Mig [0 ] 0 -IM NC_DMA_GETS [0 ] 0 -IM Invalidate [0 ] 0 -IM Ack [0 ] 0 -IM Data [0 ] 0 -IM Exclusive_Data [761 ] 761 -IM Flush_line [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM L2_Replacement [0 ] 0 -SM L1_to_L2 [0 ] 0 -SM Other_GETX [0 ] 0 -SM Other_GETS [0 ] 0 -SM Other_GETS_No_Mig [0 ] 0 -SM NC_DMA_GETS [0 ] 0 -SM Invalidate [0 ] 0 -SM Ack [0 ] 0 -SM Data [0 ] 0 -SM Exclusive_Data [0 ] 0 -SM Flush_line [0 ] 0 - -OM Load [0 ] 0 -OM Ifetch [0 ] 0 -OM Store [0 ] 0 -OM L2_Replacement [0 ] 0 -OM L1_to_L2 [0 ] 0 -OM Other_GETX [0 ] 0 -OM Other_GETS [0 ] 0 -OM Merged_GETS [0 ] 0 -OM Other_GETS_No_Mig [0 ] 0 -OM NC_DMA_GETS [0 ] 0 -OM Invalidate [0 ] 0 -OM Ack [0 ] 0 -OM All_acks [0 ] 0 -OM All_acks_no_sharers [0 ] 0 -OM Flush_line [0 ] 0 - -ISM Load [0 ] 0 -ISM Ifetch [0 ] 0 -ISM Store [0 ] 0 -ISM L2_Replacement [0 ] 0 -ISM L1_to_L2 [0 ] 0 -ISM Ack [0 ] 0 -ISM All_acks_no_sharers [0 ] 0 -ISM Flush_line [0 ] 0 - -M_W Load [0 ] 0 -M_W Ifetch [0 ] 0 -M_W Store [0 ] 0 -M_W L2_Replacement [0 ] 0 -M_W L1_to_L2 [306 ] 306 -M_W Ack [0 ] 0 -M_W All_acks_no_sharers [85 ] 85 -M_W Flush_line [0 ] 0 - -MM_W Load [0 ] 0 -MM_W Ifetch [0 ] 0 -MM_W Store [3 ] 3 -MM_W L2_Replacement [0 ] 0 -MM_W L1_to_L2 [4592 ] 4592 -MM_W Ack [0 ] 0 -MM_W All_acks_no_sharers [761 ] 761 -MM_W Flush_line [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS L2_Replacement [0 ] 0 -IS L1_to_L2 [529 ] 529 -IS Other_GETX [0 ] 0 -IS Other_GETS [0 ] 0 -IS Other_GETS_No_Mig [0 ] 0 -IS NC_DMA_GETS [0 ] 0 -IS Invalidate [0 ] 0 -IS Ack [0 ] 0 -IS Shared_Ack [0 ] 0 -IS Data [0 ] 0 -IS Shared_Data [0 ] 0 -IS Exclusive_Data [85 ] 85 -IS Flush_line [0 ] 0 - -SS Load [0 ] 0 -SS Ifetch [0 ] 0 -SS Store [0 ] 0 -SS L2_Replacement [0 ] 0 -SS L1_to_L2 [0 ] 0 -SS Ack [0 ] 0 -SS Shared_Ack [0 ] 0 -SS All_acks [0 ] 0 -SS All_acks_no_sharers [0 ] 0 -SS Flush_line [0 ] 0 - -OI Load [0 ] 0 -OI Ifetch [0 ] 0 -OI Store [0 ] 0 -OI L2_Replacement [0 ] 0 -OI L1_to_L2 [0 ] 0 -OI Other_GETX [0 ] 0 -OI Other_GETS [0 ] 0 -OI Merged_GETS [0 ] 0 -OI Other_GETS_No_Mig [0 ] 0 -OI NC_DMA_GETS [0 ] 0 -OI Invalidate [0 ] 0 -OI Writeback_Ack [0 ] 0 -OI Flush_line [0 ] 0 - -MI Load [1 ] 1 -MI Ifetch [3 ] 3 -MI Store [1 ] 1 -MI L2_Replacement [0 ] 0 -MI L1_to_L2 [0 ] 0 -MI Other_GETX [0 ] 0 -MI Other_GETS [0 ] 0 -MI Merged_GETS [0 ] 0 -MI Other_GETS_No_Mig [0 ] 0 -MI NC_DMA_GETS [0 ] 0 -MI Invalidate [0 ] 0 -MI Writeback_Ack [838 ] 838 -MI Flush_line [0 ] 0 - -II Load [0 ] 0 -II Ifetch [0 ] 0 -II Store [0 ] 0 -II L2_Replacement [0 ] 0 -II L1_to_L2 [0 ] 0 -II Other_GETX [0 ] 0 -II Other_GETS [0 ] 0 -II Other_GETS_No_Mig [0 ] 0 -II NC_DMA_GETS [0 ] 0 -II Invalidate [0 ] 0 -II Writeback_Ack [0 ] 0 -II Writeback_Nack [0 ] 0 -II Flush_line [0 ] 0 - -IT Load [0 ] 0 -IT Ifetch [0 ] 0 -IT Store [0 ] 0 -IT L2_Replacement [0 ] 0 -IT L1_to_L2 [0 ] 0 -IT Complete_L2_to_L1 [0 ] 0 - -ST Load [0 ] 0 -ST Ifetch [0 ] 0 -ST Store [0 ] 0 -ST L2_Replacement [0 ] 0 -ST L1_to_L2 [0 ] 0 -ST Complete_L2_to_L1 [0 ] 0 - -OT Load [0 ] 0 -OT Ifetch [0 ] 0 -OT Store [0 ] 0 -OT L2_Replacement [0 ] 0 -OT L1_to_L2 [0 ] 0 -OT Complete_L2_to_L1 [0 ] 0 - -MT Load [0 ] 0 -MT Ifetch [0 ] 0 -MT Store [2 ] 2 -MT L2_Replacement [0 ] 0 -MT L1_to_L2 [54 ] 54 -MT Complete_L2_to_L1 [11 ] 11 - -MMT Load [0 ] 0 -MMT Ifetch [0 ] 0 -MMT Store [18 ] 18 -MMT L2_Replacement [0 ] 0 -MMT L1_to_L2 [103 ] 103 -MMT Complete_L2_to_L1 [39 ] 39 - -MI_F Load [0 ] 0 -MI_F Ifetch [0 ] 0 -MI_F Store [0 ] 0 -MI_F L1_to_L2 [0 ] 0 -MI_F Writeback_Ack [5 ] 5 -MI_F Flush_line [0 ] 0 - -MM_F Load [0 ] 0 -MM_F Ifetch [0 ] 0 -MM_F Store [0 ] 0 -MM_F L1_to_L2 [0 ] 0 -MM_F Other_GETX [0 ] 0 -MM_F Other_GETS [0 ] 0 -MM_F Merged_GETS [0 ] 0 -MM_F Other_GETS_No_Mig [0 ] 0 -MM_F NC_DMA_GETS [0 ] 0 -MM_F Invalidate [0 ] 0 -MM_F Ack [0 ] 0 -MM_F All_acks [0 ] 0 -MM_F All_acks_no_sharers [0 ] 0 -MM_F Flush_line [0 ] 0 -MM_F Block_Ack [1 ] 1 - -IM_F Load [0 ] 0 -IM_F Ifetch [0 ] 0 -IM_F Store [0 ] 0 -IM_F L2_Replacement [0 ] 0 -IM_F L1_to_L2 [0 ] 0 -IM_F Other_GETX [0 ] 0 -IM_F Other_GETS [0 ] 0 -IM_F Other_GETS_No_Mig [0 ] 0 -IM_F NC_DMA_GETS [0 ] 0 -IM_F Invalidate [0 ] 0 -IM_F Ack [0 ] 0 -IM_F Data [0 ] 0 -IM_F Exclusive_Data [4 ] 4 -IM_F Flush_line [0 ] 0 - -ISM_F Load [0 ] 0 -ISM_F Ifetch [0 ] 0 -ISM_F Store [0 ] 0 -ISM_F L2_Replacement [0 ] 0 -ISM_F L1_to_L2 [0 ] 0 -ISM_F Ack [0 ] 0 -ISM_F All_acks_no_sharers [0 ] 0 -ISM_F Flush_line [0 ] 0 - -SM_F Load [0 ] 0 -SM_F Ifetch [0 ] 0 -SM_F Store [0 ] 0 -SM_F L2_Replacement [0 ] 0 -SM_F L1_to_L2 [0 ] 0 -SM_F Other_GETX [0 ] 0 -SM_F Other_GETS [0 ] 0 -SM_F Other_GETS_No_Mig [0 ] 0 -SM_F NC_DMA_GETS [0 ] 0 -SM_F Invalidate [0 ] 0 -SM_F Ack [0 ] 0 -SM_F Data [0 ] 0 -SM_F Exclusive_Data [0 ] 0 -SM_F Flush_line [0 ] 0 - -OM_F Load [0 ] 0 -OM_F Ifetch [0 ] 0 -OM_F Store [0 ] 0 -OM_F L2_Replacement [0 ] 0 -OM_F L1_to_L2 [0 ] 0 -OM_F Other_GETX [0 ] 0 -OM_F Other_GETS [0 ] 0 -OM_F Merged_GETS [0 ] 0 -OM_F Other_GETS_No_Mig [0 ] 0 -OM_F NC_DMA_GETS [0 ] 0 -OM_F Invalidate [0 ] 0 -OM_F Ack [0 ] 0 -OM_F All_acks [0 ] 0 -OM_F All_acks_no_sharers [0 ] 0 -OM_F Flush_line [0 ] 0 - -MM_WF Load [0 ] 0 -MM_WF Ifetch [0 ] 0 -MM_WF Store [0 ] 0 -MM_WF L2_Replacement [0 ] 0 -MM_WF L1_to_L2 [0 ] 0 -MM_WF Ack [0 ] 0 -MM_WF All_acks_no_sharers [4 ] 4 -MM_WF Flush_line [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 1617 - memory_reads: 850 - memory_writes: 767 - memory_refreshes: 1196 - memory_total_request_delays: 599 - memory_delays_per_request: 0.370439 - memory_delays_in_input_queue: 48 - memory_delays_behind_head_of_bank_queue: 1 - memory_delays_stalled_at_head_of_bank_queue: 550 - memory_stalls_for_bank_busy: 172 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 40 - memory_stalls_for_bus: 204 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 52 - memory_stalls_for_read_read_turnaround: 82 - accesses_per_bank: 60 50 58 80 69 77 71 48 48 38 42 44 39 57 47 44 42 45 53 54 55 41 48 56 29 45 43 51 47 51 42 43 - - --- Directory --- - - Event Counts - -GETX [761 ] 761 -GETS [87 ] 87 -PUT [913 ] 913 -Unblock [0 ] 0 -UnblockS [0 ] 0 -UnblockM [845 ] 845 -Writeback_Clean [0 ] 0 -Writeback_Dirty [0 ] 0 -Writeback_Exclusive_Clean [75 ] 75 -Writeback_Exclusive_Dirty [767 ] 767 -Pf_Replacement [0 ] 0 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -Memory_Data [850 ] 850 -Memory_Ack [767 ] 767 -Ack [0 ] 0 -Shared_Ack [0 ] 0 -Shared_Data [0 ] 0 -Data [0 ] 0 -Exclusive_Data [0 ] 0 -All_acks_and_shared_data [0 ] 0 -All_acks_and_owner_data [0 ] 0 -All_acks_and_data_no_sharers [0 ] 0 -All_Unblocks [0 ] 0 -GETF [5 ] 5 -PUTF [5 ] 5 - - - Transitions - -NX GETX [0 ] 0 -NX GETS [0 ] 0 -NX PUT [0 ] 0 -NX Pf_Replacement [0 ] 0 -NX DMA_READ [0 ] 0 -NX DMA_WRITE [0 ] 0 -NX GETF [0 ] 0 - -NO GETX [0 ] 0 -NO GETS [0 ] 0 -NO PUT [838 ] 838 -NO Pf_Replacement [0 ] 0 -NO DMA_READ [0 ] 0 -NO DMA_WRITE [0 ] 0 -NO GETF [1 ] 1 - -S GETX [0 ] 0 -S GETS [0 ] 0 -S PUT [0 ] 0 -S Pf_Replacement [0 ] 0 -S DMA_READ [0 ] 0 -S DMA_WRITE [0 ] 0 -S GETF [0 ] 0 - -O GETX [0 ] 0 -O GETS [0 ] 0 -O PUT [0 ] 0 -O Pf_Replacement [0 ] 0 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 -O GETF [0 ] 0 - -E GETX [761 ] 761 -E GETS [85 ] 85 -E PUT [0 ] 0 -E DMA_READ [0 ] 0 -E DMA_WRITE [0 ] 0 -E GETF [4 ] 4 - -O_R GETX [0 ] 0 -O_R GETS [0 ] 0 -O_R PUT [0 ] 0 -O_R Pf_Replacement [0 ] 0 -O_R DMA_READ [0 ] 0 -O_R DMA_WRITE [0 ] 0 -O_R Ack [0 ] 0 -O_R All_acks_and_data_no_sharers [0 ] 0 -O_R GETF [0 ] 0 - -S_R GETX [0 ] 0 -S_R GETS [0 ] 0 -S_R PUT [0 ] 0 -S_R Pf_Replacement [0 ] 0 -S_R DMA_READ [0 ] 0 -S_R DMA_WRITE [0 ] 0 -S_R Ack [0 ] 0 -S_R Data [0 ] 0 -S_R All_acks_and_data_no_sharers [0 ] 0 -S_R GETF [0 ] 0 - -NO_R GETX [0 ] 0 -NO_R GETS [0 ] 0 -NO_R PUT [0 ] 0 -NO_R Pf_Replacement [0 ] 0 -NO_R DMA_READ [0 ] 0 -NO_R DMA_WRITE [0 ] 0 -NO_R Ack [0 ] 0 -NO_R Data [0 ] 0 -NO_R Exclusive_Data [0 ] 0 -NO_R All_acks_and_data_no_sharers [0 ] 0 -NO_R GETF [0 ] 0 - -NO_B GETX [0 ] 0 -NO_B GETS [0 ] 0 -NO_B PUT [75 ] 75 -NO_B UnblockS [0 ] 0 -NO_B UnblockM [845 ] 845 -NO_B Pf_Replacement [0 ] 0 -NO_B DMA_READ [0 ] 0 -NO_B DMA_WRITE [0 ] 0 -NO_B GETF [0 ] 0 - -NO_B_X GETX [0 ] 0 -NO_B_X GETS [0 ] 0 -NO_B_X PUT [0 ] 0 -NO_B_X UnblockS [0 ] 0 -NO_B_X UnblockM [0 ] 0 -NO_B_X Pf_Replacement [0 ] 0 -NO_B_X DMA_READ [0 ] 0 -NO_B_X DMA_WRITE [0 ] 0 -NO_B_X GETF [0 ] 0 - -NO_B_S GETX [0 ] 0 -NO_B_S GETS [0 ] 0 -NO_B_S PUT [0 ] 0 -NO_B_S UnblockS [0 ] 0 -NO_B_S UnblockM [0 ] 0 -NO_B_S Pf_Replacement [0 ] 0 -NO_B_S DMA_READ [0 ] 0 -NO_B_S DMA_WRITE [0 ] 0 -NO_B_S GETF [0 ] 0 - -NO_B_S_W GETX [0 ] 0 -NO_B_S_W GETS [0 ] 0 -NO_B_S_W PUT [0 ] 0 -NO_B_S_W UnblockS [0 ] 0 -NO_B_S_W Pf_Replacement [0 ] 0 -NO_B_S_W DMA_READ [0 ] 0 -NO_B_S_W DMA_WRITE [0 ] 0 -NO_B_S_W All_Unblocks [0 ] 0 -NO_B_S_W GETF [0 ] 0 - -O_B GETX [0 ] 0 -O_B GETS [0 ] 0 -O_B PUT [0 ] 0 -O_B UnblockS [0 ] 0 -O_B UnblockM [0 ] 0 -O_B Pf_Replacement [0 ] 0 -O_B DMA_READ [0 ] 0 -O_B DMA_WRITE [0 ] 0 -O_B GETF [0 ] 0 - -NO_B_W GETX [0 ] 0 -NO_B_W GETS [0 ] 0 -NO_B_W PUT [0 ] 0 -NO_B_W UnblockS [0 ] 0 -NO_B_W UnblockM [0 ] 0 -NO_B_W Pf_Replacement [0 ] 0 -NO_B_W DMA_READ [0 ] 0 -NO_B_W DMA_WRITE [0 ] 0 -NO_B_W Memory_Data [846 ] 846 -NO_B_W GETF [0 ] 0 - -O_B_W GETX [0 ] 0 -O_B_W GETS [0 ] 0 -O_B_W PUT [0 ] 0 -O_B_W UnblockS [0 ] 0 -O_B_W Pf_Replacement [0 ] 0 -O_B_W DMA_READ [0 ] 0 -O_B_W DMA_WRITE [0 ] 0 -O_B_W Memory_Data [0 ] 0 -O_B_W GETF [0 ] 0 - -NO_W GETX [0 ] 0 -NO_W GETS [0 ] 0 -NO_W PUT [0 ] 0 -NO_W Pf_Replacement [0 ] 0 -NO_W DMA_READ [0 ] 0 -NO_W DMA_WRITE [0 ] 0 -NO_W Memory_Data [0 ] 0 -NO_W GETF [0 ] 0 - -O_W GETX [0 ] 0 -O_W GETS [0 ] 0 -O_W PUT [0 ] 0 -O_W Pf_Replacement [0 ] 0 -O_W DMA_READ [0 ] 0 -O_W DMA_WRITE [0 ] 0 -O_W Memory_Data [0 ] 0 -O_W GETF [0 ] 0 - -NO_DW_B_W GETX [0 ] 0 -NO_DW_B_W GETS [0 ] 0 -NO_DW_B_W PUT [0 ] 0 -NO_DW_B_W Pf_Replacement [0 ] 0 -NO_DW_B_W DMA_READ [0 ] 0 -NO_DW_B_W DMA_WRITE [0 ] 0 -NO_DW_B_W Ack [0 ] 0 -NO_DW_B_W Data [0 ] 0 -NO_DW_B_W Exclusive_Data [0 ] 0 -NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 -NO_DW_B_W GETF [0 ] 0 - -NO_DR_B_W GETX [0 ] 0 -NO_DR_B_W GETS [0 ] 0 -NO_DR_B_W PUT [0 ] 0 -NO_DR_B_W Pf_Replacement [0 ] 0 -NO_DR_B_W DMA_READ [0 ] 0 -NO_DR_B_W DMA_WRITE [0 ] 0 -NO_DR_B_W Memory_Data [0 ] 0 -NO_DR_B_W Ack [0 ] 0 -NO_DR_B_W Shared_Ack [0 ] 0 -NO_DR_B_W Shared_Data [0 ] 0 -NO_DR_B_W Data [0 ] 0 -NO_DR_B_W Exclusive_Data [0 ] 0 -NO_DR_B_W GETF [0 ] 0 - -NO_DR_B_D GETX [0 ] 0 -NO_DR_B_D GETS [0 ] 0 -NO_DR_B_D PUT [0 ] 0 -NO_DR_B_D Pf_Replacement [0 ] 0 -NO_DR_B_D DMA_READ [0 ] 0 -NO_DR_B_D DMA_WRITE [0 ] 0 -NO_DR_B_D Ack [0 ] 0 -NO_DR_B_D Shared_Ack [0 ] 0 -NO_DR_B_D Shared_Data [0 ] 0 -NO_DR_B_D Data [0 ] 0 -NO_DR_B_D Exclusive_Data [0 ] 0 -NO_DR_B_D All_acks_and_shared_data [0 ] 0 -NO_DR_B_D All_acks_and_owner_data [0 ] 0 -NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 -NO_DR_B_D GETF [0 ] 0 - -NO_DR_B GETX [0 ] 0 -NO_DR_B GETS [0 ] 0 -NO_DR_B PUT [0 ] 0 -NO_DR_B Pf_Replacement [0 ] 0 -NO_DR_B DMA_READ [0 ] 0 -NO_DR_B DMA_WRITE [0 ] 0 -NO_DR_B Ack [0 ] 0 -NO_DR_B Shared_Ack [0 ] 0 -NO_DR_B Shared_Data [0 ] 0 -NO_DR_B Data [0 ] 0 -NO_DR_B Exclusive_Data [0 ] 0 -NO_DR_B All_acks_and_shared_data [0 ] 0 -NO_DR_B All_acks_and_owner_data [0 ] 0 -NO_DR_B All_acks_and_data_no_sharers [0 ] 0 -NO_DR_B GETF [0 ] 0 - -NO_DW_W GETX [0 ] 0 -NO_DW_W GETS [0 ] 0 -NO_DW_W PUT [0 ] 0 -NO_DW_W Pf_Replacement [0 ] 0 -NO_DW_W DMA_READ [0 ] 0 -NO_DW_W DMA_WRITE [0 ] 0 -NO_DW_W Memory_Ack [0 ] 0 -NO_DW_W GETF [0 ] 0 - -O_DR_B_W GETX [0 ] 0 -O_DR_B_W GETS [0 ] 0 -O_DR_B_W PUT [0 ] 0 -O_DR_B_W Pf_Replacement [0 ] 0 -O_DR_B_W DMA_READ [0 ] 0 -O_DR_B_W DMA_WRITE [0 ] 0 -O_DR_B_W Memory_Data [0 ] 0 -O_DR_B_W Ack [0 ] 0 -O_DR_B_W Shared_Ack [0 ] 0 -O_DR_B_W GETF [0 ] 0 - -O_DR_B GETX [0 ] 0 -O_DR_B GETS [0 ] 0 -O_DR_B PUT [0 ] 0 -O_DR_B Pf_Replacement [0 ] 0 -O_DR_B DMA_READ [0 ] 0 -O_DR_B DMA_WRITE [0 ] 0 -O_DR_B Ack [0 ] 0 -O_DR_B Shared_Ack [0 ] 0 -O_DR_B All_acks_and_owner_data [0 ] 0 -O_DR_B All_acks_and_data_no_sharers [0 ] 0 -O_DR_B GETF [0 ] 0 - -WB GETX [0 ] 0 -WB GETS [1 ] 1 -WB PUT [0 ] 0 -WB Unblock [0 ] 0 -WB Writeback_Clean [0 ] 0 -WB Writeback_Dirty [0 ] 0 -WB Writeback_Exclusive_Clean [75 ] 75 -WB Writeback_Exclusive_Dirty [767 ] 767 -WB Pf_Replacement [0 ] 0 -WB DMA_READ [0 ] 0 -WB DMA_WRITE [0 ] 0 -WB GETF [0 ] 0 - -WB_O_W GETX [0 ] 0 -WB_O_W GETS [0 ] 0 -WB_O_W PUT [0 ] 0 -WB_O_W Pf_Replacement [0 ] 0 -WB_O_W DMA_READ [0 ] 0 -WB_O_W DMA_WRITE [0 ] 0 -WB_O_W Memory_Ack [0 ] 0 -WB_O_W GETF [0 ] 0 - -WB_E_W GETX [0 ] 0 -WB_E_W GETS [1 ] 1 -WB_E_W PUT [0 ] 0 -WB_E_W Pf_Replacement [0 ] 0 -WB_E_W DMA_READ [0 ] 0 -WB_E_W DMA_WRITE [0 ] 0 -WB_E_W Memory_Ack [767 ] 767 -WB_E_W GETF [0 ] 0 - -NO_F GETX [0 ] 0 -NO_F GETS [0 ] 0 -NO_F PUT [0 ] 0 -NO_F UnblockM [0 ] 0 -NO_F Pf_Replacement [0 ] 0 -NO_F GETF [0 ] 0 -NO_F PUTF [5 ] 5 - -NO_F_W GETX [0 ] 0 -NO_F_W GETS [0 ] 0 -NO_F_W PUT [0 ] 0 -NO_F_W Pf_Replacement [0 ] 0 -NO_F_W DMA_READ [0 ] 0 -NO_F_W DMA_WRITE [0 ] 0 -NO_F_W Memory_Data [4 ] 4 -NO_F_W GETF [0 ] 0 - diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index ea7e7e040..446bded29 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000172 # Nu sim_ticks 172201 # Number of ticks simulated final_tick 172201 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1283391 # Simulator tick rate (ticks/s) -host_mem_usage 149864 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 1943490 # Simulator tick rate (ticks/s) +host_mem_usage 142952 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host system.ruby.l1_cntrl0.L1Dcache.demand_hits 70 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 848 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 918 # Number of cache demand accesses @@ -16,8 +16,106 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 50 system.ruby.l1_cntrl0.L2cache.demand_hits 49 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 848 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 897 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 1617 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 850 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 767 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 1196 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 550 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 48 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 1 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 599 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.370439 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 172 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 204 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 52 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 82 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 40 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 60 3.71% 3.71% | 50 3.09% 6.80% | 58 3.59% 10.39% | 80 4.95% 15.34% | 69 4.27% 19.60% | 77 4.76% 24.37% | 71 4.39% 28.76% | 48 2.97% 31.73% | 48 2.97% 34.69% | 38 2.35% 37.04% | 42 2.60% 39.64% | 44 2.72% 42.36% | 39 2.41% 44.77% | 57 3.53% 48.30% | 47 2.91% 51.21% | 44 2.72% 53.93% | 42 2.60% 56.52% | 45 2.78% 59.31% | 53 3.28% 62.59% | 54 3.34% 65.92% | 55 3.40% 69.33% | 41 2.54% 71.86% | 48 2.97% 74.83% | 56 3.46% 78.29% | 29 1.79% 80.09% | 45 2.78% 82.87% | 43 2.66% 85.53% | 51 3.15% 88.68% | 47 2.91% 91.59% | 51 3.15% 94.74% | 42 2.60% 97.34% | 43 2.66% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1617 # Number of accesses per bank + system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl0.Load 52 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 53 0.00% 0.00% +system.ruby.l1_cntrl0.Store 888 0.00% 0.00% +system.ruby.l1_cntrl0.L2_Replacement 840 0.00% 0.00% +system.ruby.l1_cntrl0.L1_to_L2 16587 0.00% 0.00% +system.ruby.l1_cntrl0.Trigger_L2_to_L1D 41 0.00% 0.00% +system.ruby.l1_cntrl0.Trigger_L2_to_L1I 9 0.00% 0.00% +system.ruby.l1_cntrl0.Complete_L2_to_L1 50 0.00% 0.00% +system.ruby.l1_cntrl0.Exclusive_Data 850 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack 843 0.00% 0.00% +system.ruby.l1_cntrl0.All_acks_no_sharers 850 0.00% 0.00% +system.ruby.l1_cntrl0.Flush_line 5 0.00% 0.00% +system.ruby.l1_cntrl0.Block_Ack 1 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 46 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 40 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 762 0.00% 0.00% +system.ruby.l1_cntrl0.I.Flush_line 4 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 1 0.00% 0.00% +system.ruby.l1_cntrl0.M.L2_Replacement 71 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_to_L2 83 0.00% 0.00% +system.ruby.l1_cntrl0.M.Trigger_L2_to_L1D 11 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Load 5 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Store 62 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L2_Replacement 769 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L1_to_L2 809 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1D 30 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1I 9 0.00% 0.00% +system.ruby.l1_cntrl0.MR.Store 11 0.00% 0.00% +system.ruby.l1_cntrl0.MR.L1_to_L2 90 0.00% 0.00% +system.ruby.l1_cntrl0.MMR.Ifetch 9 0.00% 0.00% +system.ruby.l1_cntrl0.MMR.Store 29 0.00% 0.00% +system.ruby.l1_cntrl0.MMR.L1_to_L2 25 0.00% 0.00% +system.ruby.l1_cntrl0.MMR.Flush_line 1 0.00% 0.00% +system.ruby.l1_cntrl0.IM.L1_to_L2 9996 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Exclusive_Data 761 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.L1_to_L2 306 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.All_acks_no_sharers 85 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Store 3 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.L1_to_L2 4592 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.All_acks_no_sharers 761 0.00% 0.00% +system.ruby.l1_cntrl0.IS.L1_to_L2 529 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Exclusive_Data 85 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Load 1 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Ifetch 3 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Store 1 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack 838 0.00% 0.00% +system.ruby.l1_cntrl0.MT.Store 2 0.00% 0.00% +system.ruby.l1_cntrl0.MT.L1_to_L2 54 0.00% 0.00% +system.ruby.l1_cntrl0.MT.Complete_L2_to_L1 11 0.00% 0.00% +system.ruby.l1_cntrl0.MMT.Store 18 0.00% 0.00% +system.ruby.l1_cntrl0.MMT.L1_to_L2 103 0.00% 0.00% +system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1 39 0.00% 0.00% +system.ruby.l1_cntrl0.MI_F.Writeback_Ack 5 0.00% 0.00% +system.ruby.l1_cntrl0.MM_F.Block_Ack 1 0.00% 0.00% +system.ruby.l1_cntrl0.IM_F.Exclusive_Data 4 0.00% 0.00% +system.ruby.l1_cntrl0.MM_WF.All_acks_no_sharers 4 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 761 0.00% 0.00% +system.ruby.dir_cntrl0.GETS 87 0.00% 0.00% +system.ruby.dir_cntrl0.PUT 913 0.00% 0.00% +system.ruby.dir_cntrl0.UnblockM 845 0.00% 0.00% +system.ruby.dir_cntrl0.Writeback_Exclusive_Clean 75 0.00% 0.00% +system.ruby.dir_cntrl0.Writeback_Exclusive_Dirty 767 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 850 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 767 0.00% 0.00% +system.ruby.dir_cntrl0.GETF 5 0.00% 0.00% +system.ruby.dir_cntrl0.PUTF 5 0.00% 0.00% +system.ruby.dir_cntrl0.NO.PUT 838 0.00% 0.00% +system.ruby.dir_cntrl0.NO.GETF 1 0.00% 0.00% +system.ruby.dir_cntrl0.E.GETX 761 0.00% 0.00% +system.ruby.dir_cntrl0.E.GETS 85 0.00% 0.00% +system.ruby.dir_cntrl0.E.GETF 4 0.00% 0.00% +system.ruby.dir_cntrl0.NO_B.PUT 75 0.00% 0.00% +system.ruby.dir_cntrl0.NO_B.UnblockM 845 0.00% 0.00% +system.ruby.dir_cntrl0.NO_B_W.Memory_Data 846 0.00% 0.00% +system.ruby.dir_cntrl0.WB.GETS 1 0.00% 0.00% +system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Clean 75 0.00% 0.00% +system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Dirty 767 0.00% 0.00% +system.ruby.dir_cntrl0.WB_E_W.GETS 1 0.00% 0.00% +system.ruby.dir_cntrl0.WB_E_W.Memory_Ack 767 0.00% 0.00% +system.ruby.dir_cntrl0.NO_F.PUTF 5 0.00% 0.00% +system.ruby.dir_cntrl0.NO_F_W.Memory_Data 4 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats index f73b12883..29f0cd3f5 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats @@ -1,4 +1,4 @@ -Real time: Feb/02/2013 08:06:19 +Real time: Jun/08/2013 13:44:09 Profiler Stats -------------- @@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.39 -Virtual_time_in_minutes: 0.0065 -Virtual_time_in_hours: 0.000108333 -Virtual_time_in_days: 4.51389e-06 +Virtual_time_in_seconds: 0.45 +Virtual_time_in_minutes: 0.0075 +Virtual_time_in_hours: 0.000125 +Virtual_time_in_days: 5.20833e-06 Ruby_current_time: 221941 Ruby_start_time: 0 Ruby_cycles: 221941 -mbytes_resident: 49.5742 -mbytes_total: 265.59 -resident_ratio: 0.186701 - -ruby_cycles_executed: [ 221942 ] +mbytes_resident: 50.1211 +mbytes_total: 138.504 +resident_ratio: 0.361931 Busy Controller Counts: L1Cache-0:0 @@ -63,7 +61,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -84,11 +81,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 9328 +page_reclaims: 9501 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 80 +block_outputs: 88 Network Stats ------------- @@ -132,129 +129,3 @@ links_utilized_percent_switch_2: 2.06125 outgoing_messages_switch_2_link_1_Control: 916 7328 [ 0 0 916 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Data: 914 65808 [ 0 0 914 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [42 ] 42 -Ifetch [58 ] 58 -Store [855 ] 855 -Data [916 ] 916 -Fwd_GETX [0 ] 0 -Inv [0 ] 0 -Replacement [914 ] 914 -Writeback_Ack [912 ] 912 -Writeback_Nack [0 ] 0 - - - Transitions - -I Load [42 ] 42 -I Ifetch [56 ] 56 -I Store [819 ] 819 -I Inv [0 ] 0 -I Replacement [0 ] 0 - -II Writeback_Nack [0 ] 0 - -M Load [0 ] 0 -M Ifetch [2 ] 2 -M Store [36 ] 36 -M Fwd_GETX [0 ] 0 -M Inv [0 ] 0 -M Replacement [914 ] 914 - -MI Fwd_GETX [0 ] 0 -MI Inv [0 ] 0 -MI Writeback_Ack [912 ] 912 -MI Writeback_Nack [0 ] 0 - -MII Fwd_GETX [0 ] 0 - -IS Data [98 ] 98 - -IM Data [818 ] 818 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 1830 - memory_reads: 916 - memory_writes: 914 - memory_refreshes: 1542 - memory_total_request_delays: 1930 - memory_delays_per_request: 1.05464 - memory_delays_in_input_queue: 182 - memory_delays_behind_head_of_bank_queue: 3 - memory_delays_stalled_at_head_of_bank_queue: 1745 - memory_stalls_for_bank_busy: 343 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 167 - memory_stalls_for_bus: 617 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 556 - memory_stalls_for_read_read_turnaround: 62 - accesses_per_bank: 64 60 44 96 107 64 62 38 55 54 54 36 48 34 66 48 56 54 60 70 56 62 44 62 48 58 64 72 46 46 36 66 - - --- Directory --- - - Event Counts - -GETX [916 ] 916 -GETS [0 ] 0 -PUTX [914 ] 914 -PUTX_NotOwner [0 ] 0 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -Memory_Data [916 ] 916 -Memory_Ack [914 ] 914 - - - Transitions - -I GETX [916 ] 916 -I PUTX_NotOwner [0 ] 0 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -M GETX [0 ] 0 -M PUTX [914 ] 914 -M PUTX_NotOwner [0 ] 0 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 - -M_DRD GETX [0 ] 0 -M_DRD PUTX [0 ] 0 - -M_DWR GETX [0 ] 0 -M_DWR PUTX [0 ] 0 - -M_DWRI GETX [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 - -M_DRDI GETX [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 - -IM GETX [0 ] 0 -IM GETS [0 ] 0 -IM PUTX [0 ] 0 -IM PUTX_NotOwner [0 ] 0 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 -IM Memory_Data [916 ] 916 - -MI GETX [0 ] 0 -MI GETS [0 ] 0 -MI PUTX [0 ] 0 -MI PUTX_NotOwner [0 ] 0 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 -MI Memory_Ack [914 ] 914 - -ID GETX [0 ] 0 -ID GETS [0 ] 0 -ID PUTX [0 ] 0 -ID PUTX_NotOwner [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 -ID Memory_Data [0 ] 0 - -ID_W GETX [0 ] 0 -ID_W GETS [0 ] 0 -ID_W PUTX [0 ] 0 -ID_W PUTX_NotOwner [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 -ID_W Memory_Ack [0 ] 0 - diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index 967007849..e77006cfe 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -4,11 +4,51 @@ sim_seconds 0.000222 # Nu sim_ticks 221941 # Number of ticks simulated final_tick 221941 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2117650 # Simulator tick rate (ticks/s) -host_mem_usage 149428 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 3023855 # Simulator tick rate (ticks/s) +host_mem_usage 141832 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host system.ruby.l1_cntrl0.cacheMemory.demand_hits 38 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 917 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 955 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 1830 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 916 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 914 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 1542 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1745 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 182 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 3 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 1930 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 1.054645 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 343 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 617 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 556 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 62 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 167 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 64 3.50% 3.50% | 60 3.28% 6.78% | 44 2.40% 9.18% | 96 5.25% 14.43% | 107 5.85% 20.27% | 64 3.50% 23.77% | 62 3.39% 27.16% | 38 2.08% 29.23% | 55 3.01% 32.24% | 54 2.95% 35.19% | 54 2.95% 38.14% | 36 1.97% 40.11% | 48 2.62% 42.73% | 34 1.86% 44.59% | 66 3.61% 48.20% | 48 2.62% 50.82% | 56 3.06% 53.88% | 54 2.95% 56.83% | 60 3.28% 60.11% | 70 3.83% 63.93% | 56 3.06% 66.99% | 62 3.39% 70.38% | 44 2.40% 72.79% | 62 3.39% 76.17% | 48 2.62% 78.80% | 58 3.17% 81.97% | 64 3.50% 85.46% | 72 3.93% 89.40% | 46 2.51% 91.91% | 46 2.51% 94.43% | 36 1.97% 96.39% | 66 3.61% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1830 # Number of accesses per bank + +system.ruby.l1_cntrl0.Load 42 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 58 0.00% 0.00% +system.ruby.l1_cntrl0.Store 855 0.00% 0.00% +system.ruby.l1_cntrl0.Data 916 0.00% 0.00% +system.ruby.l1_cntrl0.Replacement 914 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack 912 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 42 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 56 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 819 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 2 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 36 0.00% 0.00% +system.ruby.l1_cntrl0.M.Replacement 914 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack 912 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data 98 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data 818 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 916 0.00% 0.00% +system.ruby.dir_cntrl0.PUTX 914 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 916 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 914 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETX 916 0.00% 0.00% +system.ruby.dir_cntrl0.M.PUTX 914 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 916 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 914 0.00% 0.00% ---------- End Simulation Statistics ---------- |