diff options
Diffstat (limited to 'tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini')
| -rw-r--r-- | tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini | 53 |
1 files changed, 40 insertions, 13 deletions
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini index 07db75ab6..52ae02408 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler membus monitor physmem boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -57,9 +62,15 @@ voltage=1.000000 [system.cpu] type=TrafficGen clk_domain=system.clk_domain -config_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg +config_file=/work/curdun01/gem5-external.hg/tests/testing/../../tests/quick/se/70.tgen/tgen-dram-ctrl.cfg +default_p_state=UNDEFINED elastic_req=false eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +progress_check=1000000000 system=system port=system.monitor.slave @@ -74,9 +85,14 @@ transition_latency=100000000 [system.membus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -88,6 +104,7 @@ type=CommMonitor bandwidth_bins=20 burst_length_bins=20 clk_domain=system.clk_domain +default_p_state=UNDEFINED disable_addr_dists=true disable_bandwidth_hists=false disable_burst_length_hists=false @@ -100,6 +117,10 @@ itt_bins=20 itt_max_bin=100000 latency_bins=20 outstanding_bins=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null read_addr_mask=18446744073709551615 sample_period=1000000000 system=system @@ -110,27 +131,27 @@ slave=system.cpu.port [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -142,6 +163,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -149,12 +171,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive -range=0:134217727 +power_model=Null +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -176,9 +203,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 |