summaryrefslogtreecommitdiff
path: root/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
diff options
context:
space:
mode:
Diffstat (limited to 'tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt')
-rw-r--r--tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt6
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
index e6e71a4ae..54a9cbbda 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
@@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 8352384426 # Simulator tick rate (ticks/s)
-host_mem_usage 264628 # Number of bytes of host memory used
-host_seconds 11.97 # Real time elapsed on the host
+host_tick_rate 6195134552 # Simulator tick rate (ticks/s)
+host_mem_usage 261500 # Number of bytes of host memory used
+host_seconds 16.14 # Real time elapsed on the host
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory