diff options
Diffstat (limited to 'tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini')
| -rw-r--r-- | tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini index 27a6fb9af..1932695fb 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu membus monitor physmem boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -34,10 +37,12 @@ system_port=system.membus.slave[1] type=SrcClockDomain children=voltage_domain clock=1000 +eventq_index=0 voltage_domain=system.clk_domain.voltage_domain [system.clk_domain.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 [system.cpu] @@ -45,12 +50,14 @@ type=TrafficGen clk_domain=system.clk_domain config_file=tests/quick/se/70.tgen/tgen-simple-mem.cfg elastic_req=false +eventq_index=0 system=system port=system.monitor.slave [system.membus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=16 @@ -69,6 +76,7 @@ disable_itt_dists=false disable_latency_hists=false disable_outstanding_hists=false disable_transaction_hists=false +eventq_index=0 itt_bins=20 itt_max_bin=100000 latency_bins=20 @@ -86,6 +94,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 |