diff options
Diffstat (limited to 'tests/quick/se/70.tgen/ref/null/none')
5 files changed, 224 insertions, 10 deletions
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini new file mode 100644 index 000000000..61b6eb32e --- /dev/null +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini @@ -0,0 +1,116 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu membus monitor physmem +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +voltage=1.000000 + +[system.cpu] +type=TrafficGen +clk_domain=system.clk_domain +config_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg +elastic_req=false +system=system +port=system.monitor.slave + +[system.membus] +type=NoncoherentBus +clk_domain=system.clk_domain +header_cycles=1 +use_default_range=false +width=16 +master=system.physmem.port +slave=system.monitor.master system.system_port + +[system.monitor] +type=CommMonitor +bandwidth_bins=20 +burst_length_bins=20 +clk_domain=system.clk_domain +disable_addr_dists=true +disable_bandwidth_hists=false +disable_burst_length_hists=false +disable_itt_dists=false +disable_latency_hists=false +disable_outstanding_hists=false +disable_transaction_hists=false +itt_bins=20 +itt_max_bin=100000 +latency_bins=20 +outstanding_bins=20 +read_addr_mask=18446744073709551615 +sample_period=1000000000 +trace_file= +transaction_bins=20 +write_addr_mask=18446744073709551615 +master=system.membus.slave[0] +slave=system.cpu.port + +[system.physmem] +type=SimpleDRAM +activation_limit=4 +addr_mapping=RaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +in_addr_map=true +mem_sched_policy=frfcfs +null=false +page_policy=open +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tWTR=7500 +tXAW=40000 +write_buffer_size=32 +write_thresh_perc=70 +port=system.membus.master[0] + diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr index cfdf73ce9..e69de29bb 100755 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr @@ -1 +0,0 @@ -hack: be nice to actually delete the event here diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout index d1faa751a..2426a6cee 100755 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram/simout +Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 6 2012 15:52:45 -gem5 started Aug 6 2012 15:56:03 -gem5 executing on 61f1f4j -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram +gem5 compiled Sep 22 2013 05:53:51 +gem5 started Sep 22 2013 05:53:54 +gem5 executing on zizzer +command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 300940000 because Done +Exiting @ tick 100000000000 because simulate() limit reached diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini new file mode 100644 index 000000000..27a6fb9af --- /dev/null +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini @@ -0,0 +1,95 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu membus monitor physmem +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +voltage=1.000000 + +[system.cpu] +type=TrafficGen +clk_domain=system.clk_domain +config_file=tests/quick/se/70.tgen/tgen-simple-mem.cfg +elastic_req=false +system=system +port=system.monitor.slave + +[system.membus] +type=NoncoherentBus +clk_domain=system.clk_domain +header_cycles=1 +use_default_range=false +width=16 +master=system.physmem.port +slave=system.monitor.master system.system_port + +[system.monitor] +type=CommMonitor +bandwidth_bins=20 +burst_length_bins=20 +clk_domain=system.clk_domain +disable_addr_dists=true +disable_bandwidth_hists=false +disable_burst_length_hists=false +disable_itt_dists=false +disable_latency_hists=false +disable_outstanding_hists=false +disable_transaction_hists=false +itt_bins=20 +itt_max_bin=100000 +latency_bins=20 +outstanding_bins=20 +read_addr_mask=18446744073709551615 +sample_period=1000000000 +trace_file=monitor.ptrc.gz +transaction_bins=20 +write_addr_mask=18446744073709551615 +master=system.membus.slave[0] +slave=system.cpu.port + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout index 727a89c99..efa3fa542 100755 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simout +Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 25 2012 13:56:00 -gem5 started Aug 25 2012 13:58:17 -gem5 executing on Andreas-MacBook-Pro.local -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem +gem5 compiled Sep 22 2013 05:53:51 +gem5 started Sep 22 2013 05:53:54 +gem5 executing on zizzer +command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Exiting @ tick 100000000000 because simulate() limit reached |