diff options
Diffstat (limited to 'tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt | 324 |
1 files changed, 164 insertions, 160 deletions
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 7a58e848d..2c1174f11 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.118763 # Number of seconds simulated -sim_ticks 118762761500 # Number of ticks simulated -final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.118768 # Number of seconds simulated +sim_ticks 118767526500 # Number of ticks simulated +final_tick 118767526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1076459 # Simulator instruction rate (inst/s) -host_op_rate 1076459 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1391065983 # Simulator tick rate (ticks/s) -host_mem_usage 253156 # Number of bytes of host memory used -host_seconds 85.38 # Real time elapsed on the host +host_inst_rate 1126977 # Simulator instruction rate (inst/s) +host_op_rate 1126976 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1456406210 # Simulator tick rate (ticks/s) +host_mem_usage 256508 # Number of bytes of host memory used +host_seconds 81.55 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory system.physmem.bytes_read::total 304960 # Number of bytes read from this memory @@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 167744 # Nu system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1412429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1155379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2567808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1412429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1412429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1412429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1155379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2567808 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 1412373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1155333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2567705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1412373 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1412373 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1412373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1155333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2567705 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -65,8 +65,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 118762761500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 237525523 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 118767526500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 237535053 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -85,7 +85,7 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237525523 # Number of busy cycles +system.cpu.num_busy_cycles 237535053 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched @@ -124,16 +124,16 @@ system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.946319 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1441.932454 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.946319 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352038 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352038 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.932454 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352034 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352034 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id @@ -143,7 +143,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2223 # n system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26856500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26856500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 107103000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 107103000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133959500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133959500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133959500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133959500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27278500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27278500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108825000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108825000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 136103500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 136103500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 136103500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 136103500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56540 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56540 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61271.739130 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61271.739130 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60260.683761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60260.683761 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57428.421053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57428.421053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62256.864989 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62256.864989 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61225.146199 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61225.146199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61225.146199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61225.146199 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -208,14 +208,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26381500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26381500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 105355000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 105355000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131736500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 131736500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 131736500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 131736500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26803500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26803500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 107077000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 107077000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133880500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 133880500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133880500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 133880500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -224,24 +224,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55540 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55540 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60271.739130 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60271.739130 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56428.421053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56428.421053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61256.864989 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61256.864989 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60225.146199 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60225.146199 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60225.146199 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60225.146199 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 6681 # number of replacements -system.cpu.icache.tags.tagsinuse 1417.953327 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1417.939126 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1417.953327 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.692360 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.692360 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1417.939126 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.692353 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.692353 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id @@ -251,7 +251,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 953 system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 239145000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 239145000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 239145000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 239145000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 239145000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 239145000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 241766000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 241766000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 241766000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 241766000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 241766000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 241766000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28101.645123 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28101.645123 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28101.645123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28101.645123 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28409.635723 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28409.635723 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28409.635723 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28409.635723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28409.635723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28409.635723 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,48 +302,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 230635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 230635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 230635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 230635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 230635000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 230635000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 233256000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 233256000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 233256000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 233256000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 233256000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 233256000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27101.645123 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27101.645123 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27409.635723 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27409.635723 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27409.635723 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27409.635723 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27409.635723 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27409.635723 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2073.923151 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.080733 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3172.251150 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 12806 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4765 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.687513 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.795341 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1704.894227 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.233582 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1704.876553 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1467.374597 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052029 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.063291 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 145425 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 145425 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_percent::cpu.data 0.044781 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.096809 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4765 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 346 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1127 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3196 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.145416 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 145333 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 145333 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits @@ -372,18 +370,18 @@ system.cpu.l2cache.demand_misses::total 4765 # nu system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4765 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 102460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 102460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155964000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 155964000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 25110500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 25110500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 155964000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 127570500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 283534500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 155964000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 127570500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 283534500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104182000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 104182000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 158585000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 158585000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 25532500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 25532500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 158585000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 129714500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 288299500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 158585000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 129714500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 288299500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 6681 # number of WritebackClean accesses(hits+misses) @@ -412,18 +410,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.443958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.580720 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.580720 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59505.532240 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59505.532240 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59503.554502 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59503.554502 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59503.567681 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59503.567681 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.580720 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.580720 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60505.532240 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60505.532240 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60503.554502 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60503.554502 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60505.532240 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.166045 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60503.567681 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60505.532240 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.166045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60503.567681 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,18 +440,18 @@ system.cpu.l2cache.demand_mshr_misses::total 4765 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129754000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129754000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 20890500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 20890500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129754000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106130500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 235884500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129754000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106130500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 235884500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 86962000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 86962000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 132375000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 132375000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 21312500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 21312500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132375000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108274500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 240649500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132375000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108274500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 240649500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadCleanReq accesses @@ -466,25 +464,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.580720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.580720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49505.532240 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49505.532240 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49503.554502 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49503.554502 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.580720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.580720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50505.532240 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50505.532240 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50503.554502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50503.554502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50505.532240 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.166045 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.567681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50505.532240 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.166045 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.567681 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution @@ -518,7 +516,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 12765000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 4765 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3043 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution system.membus.trans_dist::ReadExResp 1722 # Transaction distribution |