summaryrefslogtreecommitdiff
path: root/tests/quick/se/70.twolf/ref/alpha
diff options
context:
space:
mode:
Diffstat (limited to 'tests/quick/se/70.twolf/ref/alpha')
-rw-r--r--tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini1
-rwxr-xr-xtests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout13
-rw-r--r--tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini17
-rwxr-xr-xtests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout15
-rw-r--r--tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt10
5 files changed, 37 insertions, 19 deletions
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index eb12f21d7..c40947662 100644
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -24,6 +24,7 @@ mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
readfile=
symbolfile=
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
index 53155afb5..a9560f51a 100755
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -1,12 +1,13 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 19:22:57
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2
+gem5 compiled Nov 15 2015 14:28:00
+gem5 started Nov 15 2015 14:28:27
+gem5 executing on ribera.cs.wisc.edu, pid 29052
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index fe87d7174..2cd90ec33 100644
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -24,6 +24,7 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
readfile=
symbolfile=
@@ -83,6 +84,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@@ -99,6 +101,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -123,6 +126,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@@ -139,6 +143,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -172,6 +177,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@@ -188,6 +194,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -203,12 +210,13 @@ size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@@ -216,6 +224,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout
index 078852d80..2664b9e03 100755
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -1,12 +1,13 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 19:23:43
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
+gem5 compiled Nov 15 2015 14:28:00
+gem5 started Nov 15 2015 14:29:30
+gem5 executing on ribera.cs.wisc.edu, pid 29102
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@@ -23,4 +24,4 @@ Authors: Carl Sechen, Bill Swartz
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 118729316000 because target called exit()
+122 123 124 Exiting @ tick 118762761500 because target called exit()
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index eda01d75f..b07278ba6 100644
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.118763 # Nu
sim_ticks 118762761500 # Number of ticks simulated
final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1561278 # Simulator instruction rate (inst/s)
-host_op_rate 1561278 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2017578166 # Simulator tick rate (ticks/s)
-host_mem_usage 301004 # Number of bytes of host memory used
-host_seconds 58.86 # Real time elapsed on the host
+host_inst_rate 962338 # Simulator instruction rate (inst/s)
+host_op_rate 962338 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1243592305 # Simulator tick rate (ticks/s)
+host_mem_usage 296636 # Number of bytes of host memory used
+host_seconds 95.50 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts