diff options
Diffstat (limited to 'tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt | 644 |
1 files changed, 0 insertions, 644 deletions
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index d21481ee3..e69de29bb 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,644 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.230198 # Number of seconds simulated -sim_ticks 230197694500 # Number of ticks simulated -final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 927075 # Simulator instruction rate (inst/s) -host_op_rate 977372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1241896591 # Simulator tick rate (ticks/s) -host_mem_usage 272260 # Number of bytes of host memory used -host_seconds 185.36 # Real time elapsed on the host -sim_insts 171842484 # Number of instructions simulated -sim_ops 181165371 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory -system.physmem.bytes_read::total 220992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 480700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 479310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 960010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 480700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 480700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 460395389 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 171842484 # Number of instructions committed -system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses -system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls -system.cpu.num_int_insts 143085668 # number of integer instructions -system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 242291225 # number of times the integer registers were read -system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written -system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_cc_register_reads 626384530 # number of times the CC registers were read -system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written -system.cpu.num_mem_refs 40540779 # number of memory refs -system.cpu.num_load_insts 27896144 # Number of load instructions -system.cpu.num_store_insts 12644635 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460395388.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 40300312 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction -system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction -system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction -system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 181650743 # Class of executed instruction -system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.571253 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332903 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332903 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits -system.cpu.dcache.overall_hits::total 40117812 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses -system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39940000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39940000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 67838500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 67838500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 107778500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 107778500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 107778500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 107778500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58052.325581 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58052.325581 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61671.363636 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61671.363636 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60278.803132 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60278.803132 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60245.108999 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 16 # number of writebacks -system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39252000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39252000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66738500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 66738500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105990500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 105990500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 106051500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 106051500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57052.325581 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57052.325581 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency -system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.560526 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses -system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 189857002 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 189857002 # number of overall hits -system.cpu.icache.overall_hits::total 189857002 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses -system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 124592000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 124592000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 124592000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 124592000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 124592000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 124592000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 189860053 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 189860053 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 189860053 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40836.447067 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40836.447067 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40836.447067 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40836.447067 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1506 # number of writebacks -system.cpu.icache.writebacks::total 1506 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121541000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 121541000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121541000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 121541000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121541000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 121541000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.570775 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035675 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.051136 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1448 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1322 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 57 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 57 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1322 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 65 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1387 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits -system.cpu.l2cache.overall_hits::total 1387 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1729 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1729 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses -system.cpu.l2cache.overall_misses::total 3453 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65004500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 65004500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 102968000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 102968000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37629500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 37629500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 102968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 102634000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 205602000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 102968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 102634000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 205602000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1448 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1448 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3051 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 3051 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 689 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 689 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.566699 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.917271 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.917271 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59527.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59527.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59553.499132 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59553.499132 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59540.348101 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59540.348101 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59543.006082 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1729 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1729 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 632 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 632 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54084500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54084500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85678000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85678000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31309500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31309500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85678000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85394000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 171072000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85678000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85394000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 171072000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.566699 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.917271 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49553.499132 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49553.499132 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3618 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11226 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 291648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 407168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4840 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.033471 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179882 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4678 96.65% 96.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 162 3.35% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4840 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4715000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 2361 # Transaction distribution -system.membus.trans_dist::ReadExReq 1092 # Transaction distribution -system.membus.trans_dist::ReadExResp 1092 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 2361 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3453 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3453 # Request fanout histogram -system.membus.reqLayer0.occupancy 3601500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 17265000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |