diff options
Diffstat (limited to 'tests/quick/se/70.twolf/ref/arm/linux/simple-timing')
3 files changed, 30 insertions, 12 deletions
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini index 8e6ac99e1..4f19d94a5 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -24,6 +24,7 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -85,6 +86,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -101,6 +103,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -161,6 +164,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -177,6 +181,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -196,6 +201,7 @@ eventq_index=0 [system.cpu.isa] type=ArmISA +decoderFlavour=Generic eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 @@ -271,6 +277,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -287,6 +294,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -302,12 +310,13 @@ size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -315,6 +324,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout index aba76e9d8..0c6efa8ae 100755 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:39:21 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing +gem5 compiled Nov 15 2015 15:24:37 +gem5 started Nov 15 2015 15:25:11 +gem5 executing on ribera.cs.wisc.edu, pid 11027 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x5d0ed00 info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 @@ -22,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 232072304000 because target called exit() +122 123 124 Exiting @ tick 230197694500 because target called exit() diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 0ec96492a..058efd4de 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.230198 # Nu sim_ticks 230197694500 # Number of ticks simulated final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1005681 # Simulator instruction rate (inst/s) -host_op_rate 1060242 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1347195966 # Simulator tick rate (ticks/s) -host_mem_usage 319496 # Number of bytes of host memory used -host_seconds 170.87 # Real time elapsed on the host +host_inst_rate 733775 # Simulator instruction rate (inst/s) +host_op_rate 773584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 982953876 # Simulator tick rate (ticks/s) +host_mem_usage 313544 # Number of bytes of host memory used +host_seconds 234.19 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts |