diff options
Diffstat (limited to 'tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt | 340 |
1 files changed, 172 insertions, 168 deletions
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 68f4496ce..5920b739e 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.270600 # Number of seconds simulated -sim_ticks 270599529500 # Number of ticks simulated -final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.270605 # Number of seconds simulated +sim_ticks 270604702500 # Number of ticks simulated +final_tick 270604702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1216795 # Simulator instruction rate (inst/s) -host_op_rate 1216796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1702111428 # Simulator tick rate (ticks/s) -host_mem_usage 252676 # Number of bytes of host memory used -host_seconds 158.98 # Real time elapsed on the host +host_inst_rate 1707855 # Simulator instruction rate (inst/s) +host_op_rate 1707857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2389075229 # Simulator tick rate (ticks/s) +host_mem_usage 256284 # Number of bytes of host memory used +host_seconds 113.27 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory system.physmem.bytes_read::total 331072 # Number of bytes read from this memory @@ -22,19 +22,19 @@ system.physmem.bytes_inst_read::total 230208 # Nu system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 850717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 372736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1223453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 850717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 850717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 850717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 372736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1223453 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 270599529500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 541199059 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 270604702500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 541209405 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 193444518 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 76733958 # nu system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles +system.cpu.num_busy_cycles 541209404.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 15132745 # Number of branches fetched @@ -92,16 +92,16 @@ system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1237.152973 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.152973 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302039 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302039 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id @@ -111,7 +111,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits @@ -132,16 +132,16 @@ system.cpu.dcache.demand_misses::cpu.data 1575 # n system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses system.cpu.dcache.overall_misses::total 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31375500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31375500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 67852000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 67852000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 63000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 63000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 99227500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 99227500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 99227500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 99227500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) @@ -162,16 +162,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63003.012048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63003.012048 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000.928505 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000.928505 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 63000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 63000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63001.587302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63001.587302 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -190,16 +190,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1575 system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30877500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30877500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66775000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 66775000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 62000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 62000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 97652500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 97652500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 97652500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 97652500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses @@ -210,26 +210,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62003.012048 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62003.012048 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000.928505 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000.928505 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 62000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 62000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1591.520958 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.520958 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.777110 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.777110 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id @@ -239,7 +239,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 687 system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits @@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 12288 # n system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 339828000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 339828000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 339828000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 339828000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 339828000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 339828000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses @@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27655.273438 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27655.273438 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27655.273438 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27655.273438 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,48 +290,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12288 system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 327540000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 327540000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 327540000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 327540000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 327540000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 327540000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26655.273438 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26655.273438 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3512.345683 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 19055 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5173 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.683549 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.192191 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1237.153491 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.037755 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.107188 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5173 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 719 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 833 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3523 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.157867 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 198997 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 198997 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits @@ -354,18 +352,18 @@ system.cpu.l2cache.demand_misses::total 5173 # nu system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses system.cpu.l2cache.overall_misses::total 5173 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65220000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 65220000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217646500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 217646500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30130000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 30130000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 217646500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 95350000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 312996500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 217646500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 95350000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 312996500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) @@ -394,18 +392,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.373125 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.927644 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.927644 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60507.784265 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60507.784265 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60502.008032 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60502.008032 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60505.799343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60505.799343 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,18 +422,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5173 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54440000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181676500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181676500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25150000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25150000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181676500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 261266500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181676500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79590000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 261266500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses @@ -448,25 +446,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.927644 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.927644 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50507.784265 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50507.784265 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.008032 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.008032 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution @@ -499,7 +497,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 18432000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 5173 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4095 # Transaction distribution system.membus.trans_dist::ReadExReq 1078 # Transaction distribution system.membus.trans_dist::ReadExResp 1078 # Transaction distribution |