diff options
Diffstat (limited to 'tests/quick/se/70.twolf/ref/sparc/linux/simple-timing')
4 files changed, 571 insertions, 554 deletions
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index f82285b56..02b45e3d3 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -204,14 +209,14 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -225,6 +230,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -237,15 +243,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -281,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing drivers= @@ -290,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -321,6 +329,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -332,7 +341,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -340,6 +349,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -348,6 +364,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -355,7 +372,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr index aadc3d011..04cbe4a7c 100755 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout index fcd3cff78..ba3d0f65e 100755 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -3,15 +3,14 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38674 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/sparc/linux/simple-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:39 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64871 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program @@ -25,5 +24,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -info: Increasing stack size by one page. -122 123 124 Exiting @ tick 270599529500 because target called exit() +122 123 124 Exiting @ tick 270604702500 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index a594c0ddc..dadd27923 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,536 +1,536 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.270605 # Number of seconds simulated -sim_ticks 270604702500 # Number of ticks simulated -final_tick 270604702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1830893 # Simulator instruction rate (inst/s) -host_op_rate 1830895 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2561189341 # Simulator tick rate (ticks/s) -host_mem_usage 255916 # Number of bytes of host memory used -host_seconds 105.66 # Real time elapsed on the host -sim_insts 193444518 # Number of instructions simulated -sim_ops 193444756 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory -system.physmem.bytes_read::total 331072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 850717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 372736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1223453 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 850717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 850717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 850717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 372736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1223453 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 401 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 541209405 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 193444518 # Number of instructions committed -system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses -system.cpu.num_func_calls 1957920 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls -system.cpu.num_int_insts 167974806 # number of integer instructions -system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read -system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written -system.cpu.num_mem_refs 76733958 # number of memory refs -system.cpu.num_load_insts 57735091 # Number of load instructions -system.cpu.num_store_insts 18998867 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 541209404.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 15132745 # Number of branches fetched -system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction -system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::MemRead 56837780 29.38% 89.71% # Class of executed instruction -system.cpu.op_class::MemWrite 18800854 9.72% 99.43% # Class of executed instruction -system.cpu.op_class::FloatMemRead 897323 0.46% 99.90% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 198013 0.10% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 193445773 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.152973 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.152973 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.302039 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.302039 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits -system.cpu.dcache.overall_hits::total 76709932 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses -system.cpu.dcache.overall_misses::total 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31375500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31375500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 67852000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 67852000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 63000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 63000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 99227500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 99227500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 99227500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 99227500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63003.012048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63003.012048 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000.928505 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000.928505 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 63000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 63000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63001.587302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63001.587302 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2 # number of writebacks -system.cpu.dcache.writebacks::total 2 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1575 # number of 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-system.cpu.l2cache.demand_mshr_miss_latency::total 261266500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181676500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79590000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 261266500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.927644 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.927644 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50507.784265 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50507.784265 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.008032 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.008032 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5173 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4095 # Transaction distribution -system.membus.trans_dist::ReadExReq 1078 # Transaction distribution -system.membus.trans_dist::ReadExResp 1078 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5173 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5173 # Request fanout histogram -system.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +sim_seconds 0.270605 +sim_ticks 270604702500 +final_tick 270604702500 +sim_freq 1000000000000 +host_inst_rate 850262 +host_op_rate 850263 +host_tick_rate 1189410021 +host_mem_usage 267428 +host_seconds 227.51 +sim_insts 193444518 +sim_ops 193444756 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 270604702500 +system.physmem.bytes_read::cpu.inst 230208 +system.physmem.bytes_read::cpu.data 100864 +system.physmem.bytes_read::total 331072 +system.physmem.bytes_inst_read::cpu.inst 230208 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60.33% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% +system.cpu.op_class::MemRead 56837780 29.38% 89.71% +system.cpu.op_class::MemWrite 18800854 9.72% 99.43% +system.cpu.op_class::FloatMemRead 897323 0.46% 99.90% +system.cpu.op_class::FloatMemWrite 198013 0.10% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 193445773 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 +system.cpu.dcache.tags.replacements 2 +system.cpu.dcache.tags.tagsinuse 1237.152973 +system.cpu.dcache.tags.total_refs 76732337 +system.cpu.dcache.tags.sampled_refs 1576 +system.cpu.dcache.tags.avg_refs 48688.031091 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.152973 +system.cpu.dcache.tags.occ_percent::cpu.data 0.302039 +system.cpu.dcache.tags.occ_percent::total 0.302039 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+system.cpu.dcache.overall_hits::total 76709932 +system.cpu.dcache.ReadReq_misses::cpu.data 498 +system.cpu.dcache.ReadReq_misses::total 498 +system.cpu.dcache.WriteReq_misses::cpu.data 1077 +system.cpu.dcache.WriteReq_misses::total 1077 +system.cpu.dcache.SwapReq_misses::cpu.data 1 +system.cpu.dcache.SwapReq_misses::total 1 +system.cpu.dcache.demand_misses::cpu.data 1575 +system.cpu.dcache.demand_misses::total 1575 +system.cpu.dcache.overall_misses::cpu.data 1575 +system.cpu.dcache.overall_misses::total 1575 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31375500 +system.cpu.dcache.ReadReq_miss_latency::total 31375500 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 67852000 +system.cpu.dcache.WriteReq_miss_latency::total 67852000 +system.cpu.dcache.SwapReq_miss_latency::cpu.data 63000 +system.cpu.dcache.SwapReq_miss_latency::total 63000 +system.cpu.dcache.demand_miss_latency::cpu.data 99227500 +system.cpu.dcache.demand_miss_latency::total 99227500 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+system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.writebacks::writebacks 2 +system.cpu.dcache.writebacks::total 2 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 +system.cpu.dcache.ReadReq_mshr_misses::total 498 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 +system.cpu.dcache.WriteReq_mshr_misses::total 1077 +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 +system.cpu.dcache.SwapReq_mshr_misses::total 1 +system.cpu.dcache.demand_mshr_misses::cpu.data 1575 +system.cpu.dcache.demand_mshr_misses::total 1575 +system.cpu.dcache.overall_mshr_misses::cpu.data 1575 +system.cpu.dcache.overall_mshr_misses::total 1575 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30877500 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30877500 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66775000 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 66775000 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+system.membus.reqLayer0.occupancy 5203000 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 25865000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- |