diff options
Diffstat (limited to 'tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt | 1054 |
1 files changed, 527 insertions, 527 deletions
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 466f07521..225096fb5 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,531 +1,531 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.250992 # Number of seconds simulated -sim_ticks 250991873500 # Number of ticks simulated -final_tick 250991873500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1067110 # Simulator instruction rate (inst/s) -host_op_rate 1788574 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2027966293 # Simulator tick rate (ticks/s) -host_mem_usage 298984 # Number of bytes of host memory used -host_seconds 123.77 # Real time elapsed on the host -sim_insts 132071193 # Number of instructions simulated -sim_ops 221363385 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory -system.physmem.bytes_read::total 303040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 724167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 483203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1207370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 724167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 724167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 724167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 483203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1207370 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 501983747 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 132071193 # Number of instructions committed -system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses -system.cpu.num_func_calls 1595632 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 219019986 # number of integer instructions -system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read -system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read -system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written -system.cpu.num_mem_refs 77165304 # number of memory refs -system.cpu.num_load_insts 56649587 # Number of load instructions -system.cpu.num_store_insts 20515717 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 501983746.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12326938 # Number of branches fetched -system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction -system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction -system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction -system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction -system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::MemRead 55945136 25.27% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 20410230 9.22% 99.63% # Class of executed instruction -system.cpu.op_class::FloatMemRead 704451 0.32% 99.95% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 105487 0.05% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 221363385 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.408611 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.408611 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332863 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332863 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits -system.cpu.dcache.overall_hits::total 77195831 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses -system.cpu.dcache.overall_misses::total 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20253500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20253500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 99266000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 99266000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 119519500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 119519500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 119519500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 119519500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.308869 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.308869 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62906.210393 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62906.210393 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62739.895013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62739.895013 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7 # number of writebacks -system.cpu.dcache.writebacks::total 7 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19926500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19926500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 97688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 117614500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 117614500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 117614500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 117614500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60937.308869 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60937.308869 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61906.210393 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61906.210393 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.237724 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.237724 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.710565 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.710565 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 470 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 422 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses -system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits -system.cpu.icache.overall_hits::total 173489673 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses -system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 203072500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 203072500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 203072500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 203072500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 203072500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 203072500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43262.143161 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43262.143161 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43262.143161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43262.143161 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2836 # number of writebacks -system.cpu.icache.writebacks::total 2836 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198378500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 198378500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198378500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 198378500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198378500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 198378500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42262.143161 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42262.143161 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3195.628328 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4741 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4735 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.001267 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.901516 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1365.726812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.041679 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.097523 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4735 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 947 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3200 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.144501 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 80543 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 80543 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits -system.cpu.l2cache.overall_hits::total 1864 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2840 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses -system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95288500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 95288500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 171853000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 171853000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19362000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 19362000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 171853000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 114650500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 286503500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 171853000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 114650500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 286503500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 327 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.634921 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.634921 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60511.619718 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60511.619718 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60506.250000 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60506.250000 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60507.602957 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60507.602957 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79538500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79538500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 143453000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 143453000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16162000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16162000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143453000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 95700500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 239153500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143453000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 95700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 239153500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.634921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.634921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50511.619718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50511.619718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50506.250000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50506.250000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 4735 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3160 # Transaction distribution -system.membus.trans_dist::ReadExReq 1575 # Transaction distribution -system.membus.trans_dist::ReadExResp 1575 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4735 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4735 # Request fanout histogram -system.membus.reqLayer0.occupancy 4771000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 23675000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +sim_seconds 0.250992 +sim_ticks 250991873500 +final_tick 250991873500 +sim_freq 1000000000000 +host_inst_rate 493841 +host_op_rate 827723 +host_tick_rate 938509817 +host_mem_usage 310112 +host_seconds 267.44 +sim_insts 132071193 +sim_ops 221363385 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.physmem.bytes_read::cpu.inst 181760 +system.physmem.bytes_read::cpu.data 121280 +system.physmem.bytes_read::total 303040 +system.physmem.bytes_inst_read::cpu.inst 181760 +system.physmem.bytes_inst_read::total 181760 +system.physmem.num_reads::cpu.inst 2840 +system.physmem.num_reads::cpu.data 1895 +system.physmem.num_reads::total 4735 +system.physmem.bw_read::cpu.inst 724167 +system.physmem.bw_read::cpu.data 483203 +system.physmem.bw_read::total 1207370 +system.physmem.bw_inst_read::cpu.inst 724167 +system.physmem.bw_inst_read::total 724167 +system.physmem.bw_total::cpu.inst 724167 +system.physmem.bw_total::cpu.data 483203 +system.physmem.bw_total::total 1207370 +system.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.cpu.workload.numSyscalls 400 +system.cpu.pwrStateResidencyTicks::ON 250991873500 +system.cpu.numCycles 501983747 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 132071193 +system.cpu.committedOps 221363385 +system.cpu.num_int_alu_accesses 219019986 +system.cpu.num_fp_alu_accesses 2162459 +system.cpu.num_func_calls 1595632 +system.cpu.num_conditional_control_insts 8268466 +system.cpu.num_int_insts 219019986 +system.cpu.num_fp_insts 2162459 +system.cpu.num_int_register_reads 519996939 +system.cpu.num_int_register_writes 201355989 +system.cpu.num_fp_register_reads 3037165 +system.cpu.num_fp_register_writes 1831403 +system.cpu.num_cc_register_reads 96962463 +system.cpu.num_cc_register_writes 56242058 +system.cpu.num_mem_refs 77165304 +system.cpu.num_load_insts 56649587 +system.cpu.num_store_insts 20515717 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 501983747 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 12326938 +system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% +system.cpu.op_class::IntAlu 134111833 60.58% 61.12% +system.cpu.op_class::IntMult 772953 0.35% 61.47% +system.cpu.op_class::IntDiv 7031501 3.18% 64.64% +system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% +system.cpu.op_class::FloatCmp 0 0.00% 65.14% +system.cpu.op_class::FloatCvt 0 0.00% 65.14% +system.cpu.op_class::FloatMult 0 0.00% 65.14% +system.cpu.op_class::FloatMultAcc 0 0.00% 65.14% +system.cpu.op_class::FloatDiv 0 0.00% 65.14% +system.cpu.op_class::FloatMisc 0 0.00% 65.14% +system.cpu.op_class::FloatSqrt 0 0.00% 65.14% +system.cpu.op_class::SimdAdd 0 0.00% 65.14% +system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% +system.cpu.op_class::SimdAlu 0 0.00% 65.14% +system.cpu.op_class::SimdCmp 0 0.00% 65.14% +system.cpu.op_class::SimdCvt 0 0.00% 65.14% +system.cpu.op_class::SimdMisc 0 0.00% 65.14% +system.cpu.op_class::SimdMult 0 0.00% 65.14% +system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% +system.cpu.op_class::SimdShift 0 0.00% 65.14% +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% +system.cpu.op_class::SimdSqrt 0 0.00% 65.14% +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% +system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% +system.cpu.op_class::MemRead 55945136 25.27% 90.41% +system.cpu.op_class::MemWrite 20410230 9.22% 99.63% +system.cpu.op_class::FloatMemRead 704451 0.32% 99.95% +system.cpu.op_class::FloatMemWrite 105487 0.05% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 221363385 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.cpu.dcache.tags.replacements 41 +system.cpu.dcache.tags.tagsinuse 1363.408611 +system.cpu.dcache.tags.total_refs 77195831 +system.cpu.dcache.tags.sampled_refs 1905 +system.cpu.dcache.tags.avg_refs 40522.745932 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.408611 +system.cpu.dcache.tags.occ_percent::cpu.data 0.332863 +system.cpu.dcache.tags.occ_percent::total 0.332863 +system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 +system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 +system.cpu.dcache.tags.tag_accesses 154397377 +system.cpu.dcache.tags.data_accesses 154397377 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.cpu.dcache.ReadReq_hits::cpu.data 56681678 +system.cpu.dcache.ReadReq_hits::total 56681678 +system.cpu.dcache.WriteReq_hits::cpu.data 20514153 +system.cpu.dcache.WriteReq_hits::total 20514153 +system.cpu.dcache.demand_hits::cpu.data 77195831 +system.cpu.dcache.demand_hits::total 77195831 +system.cpu.dcache.overall_hits::cpu.data 77195831 +system.cpu.dcache.overall_hits::total 77195831 +system.cpu.dcache.ReadReq_misses::cpu.data 327 +system.cpu.dcache.ReadReq_misses::total 327 +system.cpu.dcache.WriteReq_misses::cpu.data 1578 +system.cpu.dcache.WriteReq_misses::total 1578 +system.cpu.dcache.demand_misses::cpu.data 1905 +system.cpu.dcache.demand_misses::total 1905 +system.cpu.dcache.overall_misses::cpu.data 1905 +system.cpu.dcache.overall_misses::total 1905 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20253500 +system.cpu.dcache.ReadReq_miss_latency::total 20253500 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 99266000 +system.cpu.dcache.WriteReq_miss_latency::total 99266000 +system.cpu.dcache.demand_miss_latency::cpu.data 119519500 +system.cpu.dcache.demand_miss_latency::total 119519500 +system.cpu.dcache.overall_miss_latency::cpu.data 119519500 +system.cpu.dcache.overall_miss_latency::total 119519500 +system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 +system.cpu.dcache.ReadReq_accesses::total 56682005 +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 +system.cpu.dcache.WriteReq_accesses::total 20515731 +system.cpu.dcache.demand_accesses::cpu.data 77197736 +system.cpu.dcache.demand_accesses::total 77197736 +system.cpu.dcache.overall_accesses::cpu.data 77197736 +system.cpu.dcache.overall_accesses::total 77197736 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 +system.cpu.dcache.ReadReq_miss_rate::total 0.000006 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 +system.cpu.dcache.WriteReq_miss_rate::total 0.000077 +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 +system.cpu.dcache.demand_miss_rate::total 0.000025 +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 +system.cpu.dcache.overall_miss_rate::total 0.000025 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.308869 +system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.308869 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62906.210393 +system.cpu.dcache.WriteReq_avg_miss_latency::total 62906.210393 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62739.895013 +system.cpu.dcache.demand_avg_miss_latency::total 62739.895013 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62739.895013 +system.cpu.dcache.overall_avg_miss_latency::total 62739.895013 +system.cpu.dcache.blocked_cycles::no_mshrs 0 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 0 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.writebacks::writebacks 7 +system.cpu.dcache.writebacks::total 7 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 +system.cpu.dcache.ReadReq_mshr_misses::total 327 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 +system.cpu.dcache.WriteReq_mshr_misses::total 1578 +system.cpu.dcache.demand_mshr_misses::cpu.data 1905 +system.cpu.dcache.demand_mshr_misses::total 1905 +system.cpu.dcache.overall_mshr_misses::cpu.data 1905 +system.cpu.dcache.overall_mshr_misses::total 1905 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19926500 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19926500 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97688000 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 97688000 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 117614500 +system.cpu.dcache.demand_mshr_miss_latency::total 117614500 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 117614500 +system.cpu.dcache.overall_mshr_miss_latency::total 117614500 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60937.308869 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60937.308869 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61906.210393 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61906.210393 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61739.895013 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61739.895013 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61739.895013 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61739.895013 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.cpu.icache.tags.replacements 2836 +system.cpu.icache.tags.tagsinuse 1455.237724 +system.cpu.icache.tags.total_refs 173489674 +system.cpu.icache.tags.sampled_refs 4694 +system.cpu.icache.tags.avg_refs 36959.879421 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.237724 +system.cpu.icache.tags.occ_percent::cpu.inst 0.710565 +system.cpu.icache.tags.occ_percent::total 0.710565 +system.cpu.icache.tags.occ_task_id_blocks::1024 1858 +system.cpu.icache.tags.age_task_id_blocks_1024::0 37 +system.cpu.icache.tags.age_task_id_blocks_1024::1 60 +system.cpu.icache.tags.age_task_id_blocks_1024::2 470 +system.cpu.icache.tags.age_task_id_blocks_1024::3 422 +system.cpu.icache.tags.age_task_id_blocks_1024::4 869 +system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 +system.cpu.icache.tags.tag_accesses 346993430 +system.cpu.icache.tags.data_accesses 346993430 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.cpu.icache.ReadReq_hits::cpu.inst 173489674 +system.cpu.icache.ReadReq_hits::total 173489674 +system.cpu.icache.demand_hits::cpu.inst 173489674 +system.cpu.icache.demand_hits::total 173489674 +system.cpu.icache.overall_hits::cpu.inst 173489674 +system.cpu.icache.overall_hits::total 173489674 +system.cpu.icache.ReadReq_misses::cpu.inst 4694 +system.cpu.icache.ReadReq_misses::total 4694 +system.cpu.icache.demand_misses::cpu.inst 4694 +system.cpu.icache.demand_misses::total 4694 +system.cpu.icache.overall_misses::cpu.inst 4694 +system.cpu.icache.overall_misses::total 4694 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 203072500 +system.cpu.icache.ReadReq_miss_latency::total 203072500 +system.cpu.icache.demand_miss_latency::cpu.inst 203072500 +system.cpu.icache.demand_miss_latency::total 203072500 +system.cpu.icache.overall_miss_latency::cpu.inst 203072500 +system.cpu.icache.overall_miss_latency::total 203072500 +system.cpu.icache.ReadReq_accesses::cpu.inst 173494368 +system.cpu.icache.ReadReq_accesses::total 173494368 +system.cpu.icache.demand_accesses::cpu.inst 173494368 +system.cpu.icache.demand_accesses::total 173494368 +system.cpu.icache.overall_accesses::cpu.inst 173494368 +system.cpu.icache.overall_accesses::total 173494368 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 +system.cpu.icache.ReadReq_miss_rate::total 0.000027 +system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 +system.cpu.icache.demand_miss_rate::total 0.000027 +system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 +system.cpu.icache.overall_miss_rate::total 0.000027 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43262.143161 +system.cpu.icache.ReadReq_avg_miss_latency::total 43262.143161 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43262.143161 +system.cpu.icache.demand_avg_miss_latency::total 43262.143161 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43262.143161 +system.cpu.icache.overall_avg_miss_latency::total 43262.143161 +system.cpu.icache.blocked_cycles::no_mshrs 0 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 0 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs nan +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 2836 +system.cpu.icache.writebacks::total 2836 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 +system.cpu.icache.ReadReq_mshr_misses::total 4694 +system.cpu.icache.demand_mshr_misses::cpu.inst 4694 +system.cpu.icache.demand_mshr_misses::total 4694 +system.cpu.icache.overall_mshr_misses::cpu.inst 4694 +system.cpu.icache.overall_mshr_misses::total 4694 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198378500 +system.cpu.icache.ReadReq_mshr_miss_latency::total 198378500 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198378500 +system.cpu.icache.demand_mshr_miss_latency::total 198378500 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198378500 +system.cpu.icache.overall_mshr_miss_latency::total 198378500 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 +system.cpu.icache.demand_mshr_miss_rate::total 0.000027 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 +system.cpu.icache.overall_mshr_miss_rate::total 0.000027 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42262.143161 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42262.143161 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42262.143161 +system.cpu.icache.demand_avg_mshr_miss_latency::total 42262.143161 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42262.143161 +system.cpu.icache.overall_avg_mshr_miss_latency::total 42262.143161 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.cpu.l2cache.tags.replacements 0 +system.cpu.l2cache.tags.tagsinuse 3195.628328 +system.cpu.l2cache.tags.total_refs 4741 +system.cpu.l2cache.tags.sampled_refs 4735 +system.cpu.l2cache.tags.avg_refs 1.001267 +system.cpu.l2cache.tags.warmup_cycle 0 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.901516 +system.cpu.l2cache.tags.occ_blocks::cpu.data 1365.726812 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.041679 +system.cpu.l2cache.tags.occ_percent::total 0.097523 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4735 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 512 +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 947 +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3200 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.144501 +system.cpu.l2cache.tags.tag_accesses 80543 +system.cpu.l2cache.tags.data_accesses 80543 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.cpu.l2cache.WritebackDirty_hits::writebacks 7 +system.cpu.l2cache.WritebackDirty_hits::total 7 +system.cpu.l2cache.WritebackClean_hits::writebacks 2836 +system.cpu.l2cache.WritebackClean_hits::total 2836 +system.cpu.l2cache.ReadExReq_hits::cpu.data 3 +system.cpu.l2cache.ReadExReq_hits::total 3 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 +system.cpu.l2cache.ReadCleanReq_hits::total 1854 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 +system.cpu.l2cache.ReadSharedReq_hits::total 7 +system.cpu.l2cache.demand_hits::cpu.inst 1854 +system.cpu.l2cache.demand_hits::cpu.data 10 +system.cpu.l2cache.demand_hits::total 1864 +system.cpu.l2cache.overall_hits::cpu.inst 1854 +system.cpu.l2cache.overall_hits::cpu.data 10 +system.cpu.l2cache.overall_hits::total 1864 +system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 +system.cpu.l2cache.ReadExReq_misses::total 1575 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 +system.cpu.l2cache.ReadCleanReq_misses::total 2840 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 +system.cpu.l2cache.ReadSharedReq_misses::total 320 +system.cpu.l2cache.demand_misses::cpu.inst 2840 +system.cpu.l2cache.demand_misses::cpu.data 1895 +system.cpu.l2cache.demand_misses::total 4735 +system.cpu.l2cache.overall_misses::cpu.inst 2840 +system.cpu.l2cache.overall_misses::cpu.data 1895 +system.cpu.l2cache.overall_misses::total 4735 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95288500 +system.cpu.l2cache.ReadExReq_miss_latency::total 95288500 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 171853000 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 171853000 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19362000 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 19362000 +system.cpu.l2cache.demand_miss_latency::cpu.inst 171853000 +system.cpu.l2cache.demand_miss_latency::cpu.data 114650500 +system.cpu.l2cache.demand_miss_latency::total 286503500 +system.cpu.l2cache.overall_miss_latency::cpu.inst 171853000 +system.cpu.l2cache.overall_miss_latency::cpu.data 114650500 +system.cpu.l2cache.overall_miss_latency::total 286503500 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 +system.cpu.l2cache.WritebackDirty_accesses::total 7 +system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 +system.cpu.l2cache.WritebackClean_accesses::total 2836 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 +system.cpu.l2cache.ReadExReq_accesses::total 1578 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 +system.cpu.l2cache.ReadCleanReq_accesses::total 4694 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 +system.cpu.l2cache.ReadSharedReq_accesses::total 327 +system.cpu.l2cache.demand_accesses::cpu.inst 4694 +system.cpu.l2cache.demand_accesses::cpu.data 1905 +system.cpu.l2cache.demand_accesses::total 6599 +system.cpu.l2cache.overall_accesses::cpu.inst 4694 +system.cpu.l2cache.overall_accesses::cpu.data 1905 +system.cpu.l2cache.overall_accesses::total 6599 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 +system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 +system.cpu.l2cache.demand_miss_rate::total 0.717533 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 +system.cpu.l2cache.overall_miss_rate::total 0.717533 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.634921 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.634921 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60511.619718 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60511.619718 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60506.250000 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60506.250000 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60511.619718 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.583113 +system.cpu.l2cache.demand_avg_miss_latency::total 60507.602957 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60511.619718 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.583113 +system.cpu.l2cache.overall_avg_miss_latency::total 60507.602957 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 +system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 +system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 +system.cpu.l2cache.demand_mshr_misses::total 4735 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 +system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 +system.cpu.l2cache.overall_mshr_misses::total 4735 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79538500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79538500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 143453000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 143453000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16162000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16162000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143453000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 95700500 +system.cpu.l2cache.demand_mshr_miss_latency::total 239153500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143453000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 95700500 +system.cpu.l2cache.overall_mshr_miss_latency::total 239153500 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.634921 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.634921 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50511.619718 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50511.619718 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50506.250000 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50506.250000 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50511.619718 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.583113 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50507.602957 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50511.619718 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.583113 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50507.602957 +system.cpu.toL2Bus.snoop_filter.tot_requests 9476 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.cpu.toL2Bus.trans_dist::ReadResp 5021 +system.cpu.toL2Bus.trans_dist::WritebackDirty 7 +system.cpu.toL2Bus.trans_dist::WritebackClean 2836 +system.cpu.toL2Bus.trans_dist::CleanEvict 34 +system.cpu.toL2Bus.trans_dist::ReadExReq 1578 +system.cpu.toL2Bus.trans_dist::ReadExResp 1578 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 +system.cpu.toL2Bus.pkt_count::total 16075 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 +system.cpu.toL2Bus.pkt_size::total 604288 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 6599 +system.cpu.toL2Bus.snoop_fanout::mean 0.000152 +system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% +system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 6599 +system.cpu.toL2Bus.reqLayer0.occupancy 7581000 +system.cpu.toL2Bus.reqLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer0.occupancy 7041000 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 2857500 +system.cpu.toL2Bus.respLayer1.utilization 0.0 +system.membus.snoop_filter.tot_requests 4735 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.membus.trans_dist::ReadResp 3160 +system.membus.trans_dist::ReadExReq 1575 +system.membus.trans_dist::ReadExResp 1575 +system.membus.trans_dist::ReadSharedReq 3160 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 +system.membus.pkt_count::total 9470 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 +system.membus.pkt_size::total 303040 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 4735 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 4735 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 4735 +system.membus.reqLayer0.occupancy 4771000 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 23675000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- |