diff options
Diffstat (limited to 'tests/quick/se/70.twolf/ref/x86/linux/simple-timing')
-rw-r--r-- | tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt | 210 |
1 files changed, 111 insertions, 99 deletions
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index af03b59c5..395ca7a25 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu sim_ticks 250953957500 # Number of ticks simulated final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 582427 # Simulator instruction rate (inst/s) -host_op_rate 976201 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1106694320 # Simulator tick rate (ticks/s) -host_mem_usage 282016 # Number of bytes of host memory used -host_seconds 226.76 # Real time elapsed on the host +host_inst_rate 750520 # Simulator instruction rate (inst/s) +host_op_rate 1257940 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1426094126 # Simulator tick rate (ticks/s) +host_mem_usage 340216 # Number of bytes of host memory used +host_seconds 175.97 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -93,12 +93,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.457564 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.457561 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457564 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457561 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id @@ -176,14 +176,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1905 system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17202000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17202000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84297000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84297000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 101499000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 101499000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 101499000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 101499000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17365500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17365500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 102451500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 102451500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 102451500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 102451500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses @@ -192,22 +192,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.504587 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.504587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53420.152091 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53420.152091 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53105.504587 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53105.504587 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.296636 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1455.296632 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296636 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296632 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id @@ -269,34 +269,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4694 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 173278500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 173278500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 173278500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 173278500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 173278500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 173278500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175625500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 175625500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175625500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 175625500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175625500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 175625500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36914.891351 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36914.891351 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.891351 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37414.891351 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2058.178675 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2058.178650 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978570 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178361 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978548 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178359 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy @@ -308,72 +308,78 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 516 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 57590 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 57590 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits system.cpu.l2cache.overall_hits::total 1864 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2840 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 320 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3160 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2840 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149117500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16801500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 165919000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82687500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 82687500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 149117500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 149117500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16801500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 16801500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 149117500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 99489000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 248606500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 149117500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 99489000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 248606500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 327 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.629357 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.687500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52506.012658 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52506.161972 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52504.687500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52504.687500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52504.012672 # average overall miss latency @@ -388,84 +394,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115020000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12960000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 127980000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63787500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63787500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115020000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76747500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 191767500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115020000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76747500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 191767500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 66937500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 66937500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 120717500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 120717500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13601500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13601500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120717500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 80539000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 201256500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120717500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 80539000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 201256500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42506.161972 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42506.161972 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42504.687500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42504.687500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 9476 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6606 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9476 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9476 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3160 # Transaction distribution system.membus.trans_dist::ReadResp 3160 # Transaction distribution system.membus.trans_dist::ReadExReq 1575 # Transaction distribution system.membus.trans_dist::ReadExResp 1575 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) |