diff options
Diffstat (limited to 'tests/quick/se/70.twolf/ref')
4 files changed, 665 insertions, 638 deletions
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 6c0305fad..eda01d75f 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.118729 # Number of seconds simulated -sim_ticks 118729316500 # Number of ticks simulated -final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.118763 # Number of seconds simulated +sim_ticks 118762761500 # Number of ticks simulated +final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1432938 # Simulator instruction rate (inst/s) -host_op_rate 1432938 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1851208744 # Simulator tick rate (ticks/s) -host_mem_usage 301400 # Number of bytes of host memory used -host_seconds 64.14 # Real time elapsed on the host +host_inst_rate 1561278 # Simulator instruction rate (inst/s) +host_op_rate 1561278 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2017578166 # Simulator tick rate (ticks/s) +host_mem_usage 301004 # Number of bytes of host memory used +host_seconds 58.86 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 167744 # Nu system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1412827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1155704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2568532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1412827 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1412827 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1412429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1155379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2567808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1412429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1412429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1412429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1155379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2567808 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237458633 # number of cpu cycles simulated +system.cpu.numCycles 237525523 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237458633 # Number of busy cycles +system.cpu.num_busy_cycles 237525523 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched @@ -122,19 +122,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1442.043368 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1441.946319 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043368 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.946319 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352038 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352038 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 491 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses @@ -155,14 +155,14 @@ system.cpu.dcache.demand_misses::cpu.data 2223 # n system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26856500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26856500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 107103000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 107103000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133959500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133959500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133959500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133959500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -179,14 +179,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56540 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56540 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61271.739130 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61271.739130 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60260.683761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60260.683761 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23424000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23424000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 93300000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 93300000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116724000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 116724000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116724000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 116724000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26381500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26381500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 105355000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 105355000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131736500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 131736500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 131736500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 131736500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -221,24 +221,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52507.422402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52507.422402 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55540 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55540 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60271.739130 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60271.739130 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 6681 # number of replacements -system.cpu.icache.tags.tagsinuse 1418.052751 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1417.953327 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052751 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1417.953327 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.692360 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.692360 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id @@ -260,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 220712500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 220712500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 220712500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 220712500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 220712500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 239145000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 239145000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 239145000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 239145000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 239145000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 239145000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -278,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.663925 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25935.663925 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25935.663925 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25935.663925 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28101.645123 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28101.645123 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28101.645123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28101.645123 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -292,55 +292,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 6681 # number of writebacks +system.cpu.icache.writebacks::total 6681 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 212202500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 212202500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 212202500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 212202500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 212202500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 212202500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 230635000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 230635000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 230635000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 230635000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 230635000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 230635000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24935.663925 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24935.663925 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24935.663925 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24935.663925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24935.663925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24935.663925 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27101.645123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27101.645123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2074.070486 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2073.923151 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.080733 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.795177 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.017940 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257369 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.795341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1704.894227 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.233582 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052029 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.063291 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 145425 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 145425 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6681 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5889 # number of ReadCleanReq hits @@ -365,20 +369,22 @@ system.cpu.l2cache.demand_misses::total 4765 # nu system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4765 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90405000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 90405000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137603000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 137603000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22155000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 22155000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 137603000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112560000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 250163000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 137603000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112560000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 250163000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 102460000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 102460000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155964000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 155964000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 25110500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 25110500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 155964000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 127570500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 283534500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 155964000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 127570500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 283534500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6681 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6681 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8510 # number of ReadCleanReq accesses(hits+misses) @@ -403,18 +409,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.443958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.190767 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.190767 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.104932 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.104932 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.580720 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.580720 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59505.532240 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59505.532240 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59503.554502 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59503.554502 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59503.567681 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59503.567681 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -435,18 +441,18 @@ system.cpu.l2cache.demand_mshr_misses::total 4765 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73185000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73185000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 111393000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 111393000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17935000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17935000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111393000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 202513000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111393000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 202513000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129754000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129754000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 20890500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 20890500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129754000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106130500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 235884500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129754000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106130500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 235884500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadCleanReq accesses @@ -459,18 +465,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.190767 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.190767 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.190767 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.104932 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.190767 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.104932 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.580720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.580720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49505.532240 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49505.532240 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49503.554502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49503.554502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -479,8 +485,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 8510 # Transaction distribution @@ -488,22 +495,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 475 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23701 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 28304 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 972224 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1121344 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 17571 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 10733 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 17571 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10733 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 17571 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8892500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 10733 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15573500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -528,9 +535,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 4765 # Request fanout histogram -system.membus.reqLayer0.occupancy 4765500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4782000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 23825500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 23825000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 879b8d2d0..0ec96492a 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.230174 # Number of seconds simulated -sim_ticks 230173520500 # Number of ticks simulated -final_tick 230173520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.230198 # Number of seconds simulated +sim_ticks 230197694500 # Number of ticks simulated +final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1035845 # Simulator instruction rate (inst/s) -host_op_rate 1092042 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1387457275 # Simulator tick rate (ticks/s) -host_mem_usage 319880 # Number of bytes of host memory used -host_seconds 165.90 # Real time elapsed on the host +host_inst_rate 1005681 # Simulator instruction rate (inst/s) +host_op_rate 1060242 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1347195966 # Simulator tick rate (ticks/s) +host_mem_usage 319496 # Number of bytes of host memory used +host_seconds 170.87 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 110656 # Nu system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 480750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 960110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 480750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 480750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 480750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 960110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 480700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 479310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 960010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 480700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 480700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 460347041 # number of cpu cycles simulated +system.cpu.numCycles 460395389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842484 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 40540779 # nu system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460347040.998000 # Number of busy cycles +system.cpu.num_busy_cycles 460395388.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 40300312 # Number of branches fetched @@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.619059 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619059 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.571253 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332903 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data 1788 # n system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35518000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35518000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95712500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95712500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95712500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95712500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39940000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39940000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 67838500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 67838500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 107778500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 107778500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 107778500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 107778500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51625 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51625 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53530.480984 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53530.480984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53500.558971 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53500.558971 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58052.325581 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58052.325581 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61671.363636 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61671.363636 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60278.803132 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60278.803132 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60245.108999 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,16 +309,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1788 system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34830000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34830000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59094500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 59094500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93924500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 93924500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93978500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 93978500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39252000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39252000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66738500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 66738500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105990500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 105990500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 106051500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 106051500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -329,26 +329,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50625 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50625 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52530.480984 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52530.480984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52531.302404 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52531.302404 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57052.325581 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57052.325581 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.992416 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992416 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.560526 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -370,12 +370,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 112484000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 112484000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 112484000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 112484000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 112484000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 112484000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 124592000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 124592000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 124592000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 124592000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 124592000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 124592000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses @@ -388,12 +388,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36867.912160 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36867.912160 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36867.912160 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36867.912160 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40836.447067 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40836.447067 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40836.447067 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40836.447067 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,44 +402,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1506 # number of writebacks +system.cpu.icache.writebacks::total 1506 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 109433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 109433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109433000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 109433000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121541000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 121541000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121541000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 121541000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121541000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 121541000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35867.912160 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35867.912160 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.663068 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036560 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588729 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.570775 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035675 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.051136 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id @@ -449,8 +451,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1448 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 # number of ReadCleanReq hits @@ -475,20 +479,22 @@ system.cpu.l2cache.demand_misses::total 3453 # nu system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses system.cpu.l2cache.overall_misses::total 3453 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57360500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 57360500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 90862500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 90862500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33203000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 33203000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 90862500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 90563500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 181426000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 90862500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 90563500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 181426000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65004500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 65004500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 102968000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 102968000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37629500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 37629500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 102968000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102634000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 205602000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 102968000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102634000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 205602000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1448 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1448 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3051 # number of ReadCleanReq accesses(hits+misses) @@ -513,18 +519,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.713430 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52552.053210 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52536.392405 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52536.392405 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52541.558065 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59553.499132 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59553.499132 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59540.348101 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59540.348101 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59543.006082 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,18 +551,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3453 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46440500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46440500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73572500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73572500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 26883000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 26883000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73572500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73323500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 146896000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73572500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73323500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 146896000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54084500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54084500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85678000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85678000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31309500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31309500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85678000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85394000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 171072000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85678000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85394000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 171072000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadCleanReq accesses @@ -569,18 +575,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42552.053210 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42552.053210 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42536.392405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42536.392405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42552.053210 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42552.053210 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49527.930403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49527.930403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49553.499132 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49553.499132 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -589,8 +595,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1466 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1448 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution @@ -598,22 +605,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7550 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3612 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 11162 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 287936 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 403456 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6386 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.035390 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.184778 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4840 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.033471 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.179882 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6160 96.46% 96.46% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 226 3.54% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4678 96.65% 96.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 162 3.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6386 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3209000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4840 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4715000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -638,9 +645,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3453 # Request fanout histogram -system.membus.reqLayer0.occupancy 3596500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3601500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 17408500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 17265000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index b410464ce..ab4d1300a 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.270563 # Number of seconds simulated -sim_ticks 270563083500 # Number of ticks simulated -final_tick 270563083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.270600 # Number of seconds simulated +sim_ticks 270599529500 # Number of ticks simulated +final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1207450 # Simulator instruction rate (inst/s) -host_op_rate 1207451 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1688810940 # Simulator tick rate (ticks/s) -host_mem_usage 300136 # Number of bytes of host memory used -host_seconds 160.21 # Real time elapsed on the host +host_inst_rate 1167307 # Simulator instruction rate (inst/s) +host_op_rate 1167308 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1632884817 # Simulator tick rate (ticks/s) +host_mem_usage 300512 # Number of bytes of host memory used +host_seconds 165.72 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 230208 # Nu system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 850848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 372793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 541126167 # number of cpu cycles simulated +system.cpu.numCycles 541199059 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 193444518 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 76733958 # nu system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 541126166.998000 # Number of busy cycles +system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 15132745 # Number of branches fetched @@ -90,14 +90,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.203935 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203935 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id @@ -127,16 +127,16 @@ system.cpu.dcache.demand_misses::cpu.data 1575 # n system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses system.cpu.dcache.overall_misses::total 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) @@ -157,16 +157,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,16 +187,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1575 system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26892000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26892000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58158000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 58158000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 54000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 54000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 85050000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 85050000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 85050000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 85050000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses @@ -207,26 +207,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 54000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 54000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.579162 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579162 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id @@ -248,12 +248,12 @@ system.cpu.icache.demand_misses::cpu.inst 12288 # n system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 310819500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 310819500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 310819500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 310819500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 310819500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 310819500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses @@ -266,12 +266,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.555664 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25294.555664 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.555664 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25294.555664 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.555664 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25294.555664 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -280,44 +280,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 10362 # number of writebacks +system.cpu.icache.writebacks::total 10362 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 298531500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 298531500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 298531500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 298531500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 298531500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 298531500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24294.555664 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24294.555664 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24294.555664 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24294.555664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24294.555664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24294.555664 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2678.340828 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282891 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057483 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id @@ -327,8 +329,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits @@ -347,20 +351,22 @@ system.cpu.l2cache.demand_misses::total 5173 # nu system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses system.cpu.l2cache.overall_misses::total 5173 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56595000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 56595000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 188843000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 188843000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 26145000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 26145000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 188843000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 82740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 271583000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 188843000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 82740000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 271583000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) @@ -385,18 +391,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.373125 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.139005 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.139005 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.096656 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.096656 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -417,18 +423,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5173 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45815000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45815000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 152873000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 152873000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 21165000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 21165000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 152873000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 66980000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 219853000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 152873000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 66980000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 219853000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses @@ -441,18 +447,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.139005 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.139005 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -461,8 +467,8 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 10362 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution @@ -470,22 +476,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 24228 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000041 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.006425 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 24227 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 24228 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12116000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -510,9 +516,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5173 # Request fanout histogram -system.membus.reqLayer0.occupancy 5173500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 25865500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 00e1fc087..d9abd5a16 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.250954 # Number of seconds simulated -sim_ticks 250953958500 # Number of ticks simulated -final_tick 250953958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.250987 # Number of seconds simulated +sim_ticks 250987138500 # Number of ticks simulated +final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 759533 # Simulator instruction rate (inst/s) -host_op_rate 1273047 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1443220819 # Simulator tick rate (ticks/s) -host_mem_usage 343748 # Number of bytes of host memory used -host_seconds 173.88 # Real time elapsed on the host +host_inst_rate 735776 # Simulator instruction rate (inst/s) +host_op_rate 1233228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1398263201 # Simulator tick rate (ticks/s) +host_mem_usage 343356 # Number of bytes of host memory used +host_seconds 179.50 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,18 +21,18 @@ system.physmem.bytes_inst_read::total 181760 # Nu system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 724276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 483276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1207552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501907917 # number of cpu cycles simulated +system.cpu.numCycles 501974277 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 77165304 # nu system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 501907916.998000 # Number of busy cycles +system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12326938 # Number of branches fetched @@ -93,19 +93,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.457562 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457562 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses @@ -126,14 +126,14 @@ system.cpu.dcache.demand_misses::cpu.data 1905 # n system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses system.cpu.dcache.overall_misses::total 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) @@ -150,14 +150,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -176,14 +176,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1905 system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17365500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17365500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85086000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85086000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 102451500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 102451500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 102451500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 102451500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19606500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19606500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96113000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 96113000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115719500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 115719500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115719500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses @@ -192,29 +192,29 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.296634 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296634 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses @@ -231,12 +231,12 @@ system.cpu.icache.demand_misses::cpu.inst 4694 # n system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 180320500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 180320500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 180320500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 180320500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 180320500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 180320500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 200232500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 200232500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 200232500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 200232500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 200232500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses @@ -249,12 +249,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38415.104389 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38415.104389 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38415.104389 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38415.104389 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42657.115467 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -263,55 +263,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 2836 # number of writebacks +system.cpu.icache.writebacks::total 2836 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175626500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 175626500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175626500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 175626500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175626500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 175626500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195538500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 195538500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195538500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 195538500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195538500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 195538500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.104389 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37415.104389 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2058.178654 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978552 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178359 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.172589 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.062808 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 516 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits @@ -336,20 +340,22 @@ system.cpu.l2cache.demand_misses::total 4735 # nu system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82687500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 82687500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 149117500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 149117500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16801500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 16801500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 149117500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 99489000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 248606500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 149117500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 99489000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 248606500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93713500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 93713500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 169013000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 169013000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19042000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 19042000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 169013000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112755500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 281768500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 169013000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112755500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 281768500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses) @@ -374,18 +380,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.717533 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52506.161972 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52504.687500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52504.687500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52504.012672 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52504.012672 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.634921 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.634921 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.619718 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.619718 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59506.250000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59506.250000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59507.602957 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -406,18 +412,18 @@ system.cpu.l2cache.demand_mshr_misses::total 4735 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 66937500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 66937500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 120717500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 120717500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13601500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13601500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120717500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 80539000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 201256500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120717500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 80539000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 201256500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140613000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140613000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15842000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15842000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140613000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93805500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 234418500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140613000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93805500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 234418500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses @@ -430,18 +436,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42506.161972 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42506.161972 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42504.687500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42504.687500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -450,8 +456,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2870 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution @@ -459,22 +466,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9476 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000106 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010273 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 9475 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9476 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -501,9 +508,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 4735 # Request fanout histogram -system.membus.reqLayer0.occupancy 4754000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4771000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 23694000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 23675000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |