diff options
Diffstat (limited to 'tests/quick/se')
46 files changed, 6928 insertions, 5056 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 0bab63428..a216e15cb 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000026 # Nu sim_ticks 25552000 # Number of ticks simulated final_tick 25552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78801 # Simulator instruction rate (inst/s) -host_op_rate 78787 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 314994021 # Simulator tick rate (ticks/s) -host_mem_usage 262608 # Number of bytes of host memory used +host_inst_rate 78387 # Simulator instruction rate (inst/s) +host_op_rate 78372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 313333088 # Simulator tick rate (ticks/s) +host_mem_usage 263656 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,27 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.629630 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 196.201768 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.982069 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16 29.63% 29.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 29.63% 59.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 12.96% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 7.41% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.85% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.85% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.70% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7 12.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54 # Bytes accessed per row activation -system.physmem.totQLat 2560250 # Total ticks spent queuing -system.physmem.totMemAccLat 12605250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 86 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.418605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 204.922237 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.300576 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27 31.40% 31.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21 24.42% 55.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10 11.63% 67.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 9.30% 76.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 1.16% 77.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.49% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 8.14% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.33% 91.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7 8.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86 # Bytes accessed per row activation +system.physmem.totQLat 3845750 # Total ticks spent queuing +system.physmem.totMemAccLat 12639500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers -system.physmem.totBankLat 7700000 # Total ticks spent accessing banks -system.physmem.avgQLat 5458.96 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16417.91 # Average bank access latency per DRAM burst +system.physmem.avgQLat 8199.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26876.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26949.89 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1174.70 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1174.70 # Average system read bandwidth in MiByte/s @@ -223,7 +222,11 @@ system.physmem.readRowHitRate 80.60 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 54450.96 # Average gap between requests system.physmem.pageHitRate 80.60 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.memoryStateTime::IDLE 13500 # Time in different power states +system.physmem.memoryStateTime::REF 780000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 22839000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.membus.throughput 1172197871 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 396 # Transaction distribution system.membus.trans_dist::ReadResp 395 # Transaction distribution @@ -237,7 +240,7 @@ system.membus.data_through_bus 29952 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 560000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4371250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4371000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 17.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1632 # Number of BP lookups @@ -304,9 +307,9 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11596 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11594 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 469 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 467 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 43730 # Number of cycles cpu's stages were not processed system.cpu.runCycles 7375 # Number of cycles cpu stages are processed. system.cpu.activity 14.431073 # Percentage of cycles cpu is active @@ -343,14 +346,14 @@ system.cpu.stage4.idleCycles 46641 # Nu system.cpu.stage4.runCycles 4464 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 8.734957 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.169993 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.073249 # Cycle average of tags in use system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.169993 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069419 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069419 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.073249 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069372 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069372 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id @@ -369,12 +372,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses system.cpu.icache.overall_misses::total 355 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25349750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25349750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25349750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25349750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25349750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25349750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24875750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24875750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24875750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24875750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24875750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24875750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses @@ -387,12 +390,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71407.746479 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71407.746479 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71407.746479 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71407.746479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71407.746479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71407.746479 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70072.535211 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70072.535211 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70072.535211 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70072.535211 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70072.535211 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70072.535211 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -413,24 +416,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21532500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21532500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21532500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21532500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21532500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21532500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21058500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21058500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21058500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21058500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21058500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21058500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71299.668874 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71299.668874 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71299.668874 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71299.668874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71299.668874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71299.668874 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69730.132450 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69730.132450 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69730.132450 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69730.132450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69730.132450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69730.132450 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 1174702567 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution @@ -449,19 +452,19 @@ system.cpu.toL2Bus.reqLayer0.occupancy 235000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 508000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 274750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 198.925679 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 198.803908 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.205920 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.719759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004340 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001731 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006071 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.109548 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.694360 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004337 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001730 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006067 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id @@ -485,17 +488,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21214000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6927250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28141250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4931500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4931500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21214000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11858750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33072750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21214000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11858750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33072750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20740000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7180750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27920750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5181250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5181250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20740000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12362000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33102000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20740000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12362000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33102000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -518,17 +521,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70478.405316 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72918.421053 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71063.762626 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67554.794521 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67554.794521 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70478.405316 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70587.797619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70517.590618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70478.405316 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70587.797619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70517.590618 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68903.654485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75586.842105 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70506.944444 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70976.027397 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70976.027397 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68903.654485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73583.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70579.957356 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68903.654485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73583.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70579.957356 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,17 +551,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17443000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5745750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23188750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4029500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4029500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17443000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9775250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27218250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17443000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9775250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27218250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16969500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5998750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22968250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4278250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4278250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16969500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10277000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27246500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16969500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10277000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27246500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -570,27 +573,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57950.166113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60481.578947 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58557.449495 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55198.630137 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55198.630137 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57950.166113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58186.011905 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58034.648188 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57950.166113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58186.011905 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58034.648188 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56377.076412 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63144.736842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58000.631313 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58606.164384 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58606.164384 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56377.076412 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.619048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58094.882729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56377.076412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.619048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58094.882729 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.450623 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.396801 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.450623 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025256 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025256 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.396801 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025243 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025243 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id @@ -613,14 +616,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7371250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7371250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21672250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21672250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29043500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29043500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29043500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29043500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7625750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7625750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22645250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22645250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30271000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30271000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30271000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30271000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -637,19 +640,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75992.268041 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75992.268041 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61920.714286 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61920.714286 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64974.272931 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64974.272931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64974.272931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64974.272931 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 487 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78615.979381 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78615.979381 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64700.714286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64700.714286 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67720.357942 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67720.357942 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67720.357942 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67720.357942 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.730769 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.307692 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -669,14 +672,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7028750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7028750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5009000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5009000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12037750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12037750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12037750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12037750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7282250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7282250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5258750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5258750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12541000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12541000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12541000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12541000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -685,14 +688,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73986.842105 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73986.842105 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68616.438356 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68616.438356 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71653.273810 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71653.273810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71653.273810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71653.273810 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76655.263158 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76655.263158 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72037.671233 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72037.671233 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74648.809524 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74648.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74648.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74648.809524 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 8bfd28333..33f9c5fe9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21078000 # Number of ticks simulated -final_tick 21078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21025000 # Number of ticks simulated +final_tick 21025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72140 # Simulator instruction rate (inst/s) -host_op_rate 72127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 238549554 # Simulator tick rate (ticks/s) -host_mem_usage 265696 # Number of bytes of host memory used +host_inst_rate 72274 # Simulator instruction rate (inst/s) +host_op_rate 72262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 238397605 # Simulator tick rate (ticks/s) +host_mem_usage 265716 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 950374798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 528323370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1478698169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 950374798 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 950374798 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 950374798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 528323370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1478698169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 952770511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 529655172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1482425684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 952770511 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 952770511 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 952770511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 529655172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1482425684 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 488 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21045000 # Total gap between requests +system.physmem.totGap 20992000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 328.393443 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.167058 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.898610 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21 34.43% 34.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 26.23% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 9.84% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 6.56% 77.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.92% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.64% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 16.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation -system.physmem.totQLat 3243750 # Total ticks spent queuing -system.physmem.totMemAccLat 13328750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.594937 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.218426 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.360278 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 24.05% 50.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11 13.92% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 10.13% 74.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 6.33% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.27% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.53% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.53% 87.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation +system.physmem.totQLat 4394750 # Total ticks spent queuing +system.physmem.totMemAccLat 13544750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers -system.physmem.totBankLat 7645000 # Total ticks spent accessing banks -system.physmem.avgQLat 6647.03 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15665.98 # Average bank access latency per DRAM burst +system.physmem.avgQLat 9005.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27313.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1481.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27755.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1485.47 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1481.73 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1485.47 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.58 # Data bus utilization in percentage -system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.61 # Data bus utilization in percentage +system.physmem.busUtilRead 11.61 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 394 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43125.00 # Average gap between requests +system.physmem.avgGap 43016.39 # Average gap between requests system.physmem.pageHitRate 80.74 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1478698169 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15304250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1482425684 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 415 # Transaction distribution system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -234,10 +238,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 31168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 618500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 4556750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2894 # Number of BP lookups system.cpu.branchPred.condPredicted 1702 # Number of conditional branches predicted @@ -252,22 +256,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2078 # DTB read hits +system.cpu.dtb.read_hits 2077 # DTB read hits system.cpu.dtb.read_misses 47 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2125 # DTB read accesses +system.cpu.dtb.read_accesses 2124 # DTB read accesses system.cpu.dtb.write_hits 1062 # DTB write hits system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 1093 # DTB write accesses -system.cpu.dtb.data_hits 3140 # DTB hits +system.cpu.dtb.data_hits 3139 # DTB hits system.cpu.dtb.data_misses 78 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3218 # DTB accesses -system.cpu.itb.fetch_hits 2388 # ITB hits +system.cpu.dtb.data_accesses 3217 # DTB accesses +system.cpu.itb.fetch_hits 2387 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2427 # ITB accesses +system.cpu.itb.fetch_accesses 2426 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -281,95 +285,95 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42157 # number of cpu cycles simulated +system.cpu.numCycles 42051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8510 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16605 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 8515 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16590 # Number of instructions fetch has processed system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2968 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1911 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1405 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 1438 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2388 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.109663 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.506678 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 384 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.106000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.503194 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11994 80.15% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 318 2.13% 82.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.56% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 214 1.43% 85.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 255 1.70% 86.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 241 1.61% 88.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.76% 90.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 184 1.23% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1260 8.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12032 80.21% 80.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 318 2.12% 82.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.56% 83.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 214 1.43% 85.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.70% 87.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 241 1.61% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.76% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 183 1.22% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1259 8.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.068648 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.393885 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9327 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1567 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2770 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 15000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.068821 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.394521 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9332 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1599 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2769 # Number of cycles decode is running system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1226 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 243 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15343 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15335 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1226 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9537 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 678 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2628 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 341 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14637 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 9542 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 708 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2627 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 344 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14630 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10979 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18262 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18253 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 301 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10973 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18255 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18246 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6409 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6403 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 843 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 874 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2768 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12974 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12973 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10780 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10779 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6201 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6200 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3613 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14964 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.720396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.363744 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15000 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.718600 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361398 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10463 69.92% 69.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1623 10.85% 80.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1158 7.74% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 756 5.05% 93.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 501 3.35% 96.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 270 1.80% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 146 0.98% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10485 69.90% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1646 10.97% 80.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1153 7.69% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 753 5.02% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 501 3.34% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 269 1.79% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15000 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available @@ -405,7 +409,7 @@ system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7243 67.19% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7243 67.20% 67.21% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued @@ -434,39 +438,39 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2399 22.25% 89.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2398 22.25% 89.49% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1133 10.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10780 # Type of FU issued -system.cpu.iq.rate 0.255711 # Inst issue rate +system.cpu.iq.FU_type_0::total 10779 # Type of FU issued +system.cpu.iq.rate 0.256332 # Inst issue rate system.cpu.iq.fu_busy_cnt 112 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010390 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36671 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19208 # Number of integer instruction queue writes +system.cpu.iq.fu_busy_rate 0.010391 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36705 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19206 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 9602 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10879 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10878 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1585 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 127 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 132 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1226 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 247 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13092 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 13091 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2768 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall @@ -475,43 +479,43 @@ system.cpu.iew.memOrderViolationEvents 16 # Nu system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 504 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10072 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 10071 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3231 # number of memory reference insts executed +system.cpu.iew.exec_refs 3230 # number of memory reference insts executed system.cpu.iew.exec_branches 1589 # Number of branches executed system.cpu.iew.exec_stores 1095 # Number of stores executed -system.cpu.iew.exec_rate 0.238916 # Inst execution rate +system.cpu.iew.exec_rate 0.239495 # Inst execution rate system.cpu.iew.wb_sent 9755 # cumulative count of insts sent to commit system.cpu.iew.wb_count 9612 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5080 # num instructions producing a value -system.cpu.iew.wb_consumers 6838 # num instructions consuming a value +system.cpu.iew.wb_producers 5069 # num instructions producing a value +system.cpu.iew.wb_consumers 6811 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.228005 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.228580 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.744237 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6701 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6700 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13738 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465060 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.277866 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13774 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.463845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.273398 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10960 79.78% 79.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1479 10.77% 90.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 519 3.78% 94.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 236 1.72% 96.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 157 1.14% 97.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 106 0.77% 97.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 104 0.76% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 34 0.25% 98.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10981 79.72% 79.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1489 10.81% 90.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 532 3.86% 94.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 235 1.71% 96.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 155 1.13% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 100 0.73% 97.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 106 0.77% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.24% 98.96% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 143 1.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13738 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13774 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -522,26 +526,61 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 6389 # Class of committed instruction system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 26334 # The number of ROB reads -system.cpu.rob.rob_writes 27415 # The number of ROB writes +system.cpu.rob.rob_reads 26369 # The number of ROB reads +system.cpu.rob.rob_writes 27413 # The number of ROB writes system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27193 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 27051 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 6.615976 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.615976 # CPI: Total CPI of All Threads -system.cpu.ipc 0.151149 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.151149 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12785 # number of integer regfile reads +system.cpu.cpi 6.599341 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.599341 # CPI: Total CPI of All Threads +system.cpu.ipc 0.151530 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.151530 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12784 # number of integer regfile reads system.cpu.int_regfile_writes 7268 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1481734510 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1485469679 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -556,61 +595,61 @@ system.cpu.toL2Bus.data_through_bus 31232 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 528000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 278250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 159.411930 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1899 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 159.423717 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.047771 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 159.411930 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077838 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077838 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 159.423717 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077844 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5090 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5090 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1899 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1899 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1899 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1899 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1899 # number of overall hits -system.cpu.icache.overall_hits::total 1899 # number of overall hits +system.cpu.icache.tags.tag_accesses 5088 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5088 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits +system.cpu.icache.overall_hits::total 1898 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses system.cpu.icache.overall_misses::total 489 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31431750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31431750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31431750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31431750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31431750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31431750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2388 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2388 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2388 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2388 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2388 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2388 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204774 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.204774 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.204774 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.204774 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.204774 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.204774 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64277.607362 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64277.607362 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64277.607362 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64277.607362 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31330250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31330250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31330250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31330250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31330250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31330250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64070.040900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64070.040900 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64070.040900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64070.040900 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,34 +670,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 315 system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22098000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22098000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22098000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22098000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22098000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22098000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131910 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.131910 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.131910 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70152.380952 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70152.380952 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22016000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22016000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22016000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22016000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22016000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22016000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69892.063492 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69892.063492 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 219.244506 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 219.258059 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.494883 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59.749622 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004867 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.507047 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59.751013 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004868 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001823 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006691 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id @@ -684,17 +723,17 @@ system.cpu.l2cache.demand_misses::total 488 # nu system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 488 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7725500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29497500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5467500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5467500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13193000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34965000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21772000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13193000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34965000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21690000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29408000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21690000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13435750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35125750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21690000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13435750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35125750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) @@ -717,17 +756,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997955 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69337.579618 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76490.099010 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.313253 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74897.260274 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74897.260274 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71649.590164 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71649.590164 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69076.433121 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76415.841584 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70862.650602 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78325.342466 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78325.342466 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71978.995902 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71978.995902 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -747,17 +786,17 @@ system.cpu.l2cache.demand_mshr_misses::total 488 system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17823000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6485500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4573000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4573000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17823000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11058500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28881500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17823000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11058500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28881500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17737500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6477000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24214500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4818250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4818250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11295250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29032750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17737500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11295250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29032750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses @@ -769,41 +808,41 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56761.146497 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64212.871287 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58574.698795 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56488.853503 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64128.712871 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58348.192771 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66003.424658 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66003.424658 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.267771 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.231811 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2229 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.810345 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.267771 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026188 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026188 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 107.231811 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026180 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026180 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5694 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5694 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5692 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5692 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits -system.cpu.dcache.overall_hits::total 2230 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2229 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2229 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2229 # number of overall hits +system.cpu.dcache.overall_hits::total 2229 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses @@ -812,43 +851,43 @@ system.cpu.dcache.demand_misses::cpu.data 530 # n system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses system.cpu.dcache.overall_misses::total 530 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11467500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11467500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23223733 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23223733 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34691233 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34691233 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34691233 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34691233 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11460500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11460500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25449978 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25449978 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36910478 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36910478 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36910478 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36910478 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2760 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2760 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2760 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2760 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090237 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.090237 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090285 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.090285 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.192029 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.192029 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.192029 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.192029 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67061.403509 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67061.403509 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64690.064067 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64690.064067 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65455.156604 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65455.156604 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1533 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.192099 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.192099 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.192099 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.192099 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67020.467836 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67020.467836 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70891.303621 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70891.303621 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69642.411321 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69642.411321 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1529 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.862069 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.970588 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -868,30 +907,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5462500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5462500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13377500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13377500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13377500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13377500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053826 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053826 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7907500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7907500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5712750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5712750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13620250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13620250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13620250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13620250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053854 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053854 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063043 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77598.039216 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77598.039216 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75868.055556 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75868.055556 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77524.509804 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77524.509804 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79343.750000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 53f3ae2a8..60119bd53 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 3208000 # Number of ticks simulated final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105446 # Simulator instruction rate (inst/s) -host_op_rate 105415 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52907298 # Simulator tick rate (ticks/s) -host_mem_usage 268408 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 172950 # Simulator instruction rate (inst/s) +host_op_rate 172880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 86758979 # Simulator tick rate (ticks/s) +host_mem_usage 253924 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 6417 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index 913b33750..351b1338b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000139 # Nu sim_ticks 138616 # Number of ticks simulated final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 14698 # Simulator instruction rate (inst/s) -host_op_rate 14697 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 318804 # Simulator tick rate (ticks/s) -host_mem_usage 174728 # Number of bytes of host memory used -host_seconds 0.43 # Real time elapsed on the host +host_inst_rate 36011 # Simulator instruction rate (inst/s) +host_op_rate 36008 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 781041 # Simulator tick rate (ticks/s) +host_mem_usage 161164 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -210,6 +210,41 @@ system.cpu.num_busy_cycles 138616 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.369871 system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 1041 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index f70111f0d..a76851914 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000118 # Nu sim_ticks 117611 # Number of ticks simulated final_tick 117611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 21881 # Simulator instruction rate (inst/s) -host_op_rate 21879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 402676 # Simulator tick rate (ticks/s) -host_mem_usage 177980 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 31716 # Simulator instruction rate (inst/s) +host_op_rate 31714 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 583663 # Simulator tick rate (ticks/s) +host_mem_usage 164416 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,6 +200,41 @@ system.cpu.num_busy_cycles 117611 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.786874 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1109 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 253 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index e6916bab3..706264b43 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000114 # Nu sim_ticks 113627 # Number of ticks simulated final_tick 113627 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 28822 # Simulator instruction rate (inst/s) -host_op_rate 28819 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 512426 # Simulator tick rate (ticks/s) -host_mem_usage 175880 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 50343 # Simulator instruction rate (inst/s) +host_op_rate 50337 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 894983 # Simulator tick rate (ticks/s) +host_mem_usage 161272 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -186,6 +186,41 @@ system.cpu.num_busy_cycles 113627 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.473611 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1178 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 204 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 66f09eeb4..29b31fb1d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000093 # Nu sim_ticks 93341 # Number of ticks simulated final_tick 93341 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 31508 # Simulator instruction rate (inst/s) -host_op_rate 31505 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 460155 # Simulator tick rate (ticks/s) -host_mem_usage 175808 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 52665 # Simulator instruction rate (inst/s) +host_op_rate 52659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 769125 # Simulator tick rate (ticks/s) +host_mem_usage 161200 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -185,6 +185,41 @@ system.cpu.num_busy_cycles 93341 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.199848 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index d0515d3c9..17ffa2150 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000144 # Nu sim_ticks 143853 # Number of ticks simulated final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 14935 # Simulator instruction rate (inst/s) -host_op_rate 14935 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 336198 # Simulator tick rate (ticks/s) -host_mem_usage 174340 # Number of bytes of host memory used -host_seconds 0.43 # Real time elapsed on the host +host_inst_rate 53676 # Simulator instruction rate (inst/s) +host_op_rate 53669 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1208067 # Simulator tick rate (ticks/s) +host_mem_usage 160752 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -160,6 +160,41 @@ system.cpu.num_busy_cycles 143853 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.011692 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 72bd7571c..e6ec389d1 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu sim_ticks 32544000 # Number of ticks simulated final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163681 # Simulator instruction rate (inst/s) -host_op_rate 163603 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 832819326 # Simulator tick rate (ticks/s) -host_mem_usage 277116 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 550056 # Simulator instruction rate (inst/s) +host_op_rate 549394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2794675827 # Simulator tick rate (ticks/s) +host_mem_usage 262632 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 65088 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 88231a1ee..5be5fa9ed 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12006500 # Number of ticks simulated -final_tick 12006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11975500 # Number of ticks simulated +final_tick 11975500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60243 # Simulator instruction rate (inst/s) -host_op_rate 60220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 302796832 # Simulator tick rate (ticks/s) -host_mem_usage 264400 # Number of bytes of host memory used +host_inst_rate 56599 # Simulator instruction rate (inst/s) +host_op_rate 56579 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 283759448 # Simulator tick rate (ticks/s) +host_mem_usage 265424 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1002123850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 453087911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1455211760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1002123850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1002123850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1002123850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 453087911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1455211760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1004717966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 454260782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1458978748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1004717966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1004717966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1004717966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 454260782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1458978748 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 273 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 273 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 11917000 # Total gap between requests +system.physmem.totGap 11886000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 84 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,33 +186,33 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 24 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 464 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 290.487911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.347726 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6 25.00% 25.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4 16.67% 41.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 12.50% 54.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1 4.17% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 8.33% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 8.33% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 25.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 24 # Bytes accessed per row activation -system.physmem.totQLat 1638000 # Total ticks spent queuing -system.physmem.totMemAccLat 7265500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 38 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.368421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.223359 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 366.580725 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14 36.84% 36.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5 13.16% 50.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4 10.53% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 5.26% 65.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 5.26% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 5.26% 76.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 5.26% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 2.63% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 15.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38 # Bytes accessed per row activation +system.physmem.totQLat 2067500 # Total ticks spent queuing +system.physmem.totMemAccLat 7186250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1365000 # Total ticks spent in databus transfers -system.physmem.totBankLat 4262500 # Total ticks spent accessing banks -system.physmem.avgQLat 6000.00 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15613.55 # Average bank access latency per DRAM burst +system.physmem.avgQLat 7573.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26613.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1455.21 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26323.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1458.98 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1455.21 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1458.98 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.37 # Data bus utilization in percentage -system.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.40 # Data bus utilization in percentage +system.physmem.busUtilRead 11.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,10 +220,14 @@ system.physmem.readRowHits 225 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43652.01 # Average gap between requests +system.physmem.avgGap 43538.46 # Average gap between requests system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.18 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1455211760 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem.memoryStateTime::REF 260000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 7796750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1458978748 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 249 # Transaction distribution system.membus.trans_dist::ReadResp 249 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution @@ -234,9 +238,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17472 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 344500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2552500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2556250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 21.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1176 # Number of BP lookups @@ -281,42 +285,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 24014 # number of cpu cycles simulated +system.cpu.numCycles 23952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 4342 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 7011 # Number of instructions fetch has processed system.cpu.fetch.Branches 1176 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 1209 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 541 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 531 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 1065 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.907925 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.314691 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 7705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.909929 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.316850 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6513 84.34% 84.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.69% 85.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 115 1.49% 86.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 95 1.23% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 176 2.28% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 76 0.98% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 64 0.83% 91.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 0.84% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 565 7.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6496 84.31% 84.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.69% 85.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 115 1.49% 86.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 95 1.23% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 176 2.28% 90.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 76 0.99% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.83% 91.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 0.84% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 565 7.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.048971 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.291955 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5487 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 579 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 7705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049098 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.292710 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5480 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 569 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1153 # Number of cycles decode is running system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing @@ -325,9 +329,9 @@ system.cpu.decode.BranchMispred 81 # Nu system.cpu.decode.DecodedInsts 6199 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5585 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 5578 # Number of cycles rename is idle system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 280 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1063 # Number of cycles rename is running system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 5900 # Number of instructions processed by rename @@ -354,23 +358,23 @@ system.cpu.iq.iqSquashedInstsIssued 54 # Nu system.cpu.iq.iqSquashedInstsExamined 2341 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 1389 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7722 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.523828 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.238657 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7705 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.524984 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.239779 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 6098 78.97% 78.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 565 7.32% 86.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 401 5.19% 91.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 263 3.41% 94.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 200 2.59% 97.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 120 1.55% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 6081 78.92% 78.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 565 7.33% 86.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 401 5.20% 91.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 263 3.41% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 200 2.60% 97.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 120 1.56% 99.03% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 47 0.61% 99.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7722 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7705 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available @@ -440,10 +444,10 @@ system.cpu.iq.FU_type_0::MemWrite 395 9.77% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 4045 # Type of FU issued -system.cpu.iq.rate 0.168443 # Inst issue rate +system.cpu.iq.rate 0.168879 # Inst issue rate system.cpu.iq.fu_busy_cnt 44 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010878 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15897 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 15880 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 7311 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 3652 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads @@ -484,26 +488,26 @@ system.cpu.iew.exec_nop 336 # nu system.cpu.iew.exec_refs 1130 # number of memory reference insts executed system.cpu.iew.exec_branches 644 # Number of branches executed system.cpu.iew.exec_stores 388 # Number of stores executed -system.cpu.iew.exec_rate 0.160531 # Inst execution rate +system.cpu.iew.exec_rate 0.160947 # Inst execution rate system.cpu.iew.wb_sent 3738 # cumulative count of insts sent to commit system.cpu.iew.wb_count 3658 # cumulative count of insts written-back system.cpu.iew.wb_producers 1710 # num instructions producing a value system.cpu.iew.wb_consumers 2211 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.152328 # insts written-back per cycle +system.cpu.iew.wb_rate 0.152722 # insts written-back per cycle system.cpu.iew.wb_fanout 0.773406 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 2726 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7228 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.356392 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.198445 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 7211 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.357232 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.199732 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6359 87.98% 87.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 204 2.82% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 308 4.26% 95.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 114 1.58% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6342 87.95% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204 2.83% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 308 4.27% 95.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 114 1.58% 96.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 72 1.00% 97.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 51 0.71% 98.34% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 32 0.44% 98.78% # Number of insts commited each cycle @@ -512,7 +516,7 @@ system.cpu.commit.committed_per_cycle::8 63 0.87% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7228 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7211 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -523,25 +527,60 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 189 7.34% 7.34% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1677 65.10% 72.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1 0.04% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 415 16.11% 88.59% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 2576 # Class of committed instruction system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12220 # The number of ROB reads +system.cpu.rob.rob_reads 12203 # The number of ROB reads system.cpu.rob.rob_writes 11111 # The number of ROB writes -system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16292 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16247 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 10.060327 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.060327 # CPI: Total CPI of All Threads -system.cpu.ipc 0.099400 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.099400 # IPC: Total IPC of All Threads +system.cpu.cpi 10.034353 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.034353 # CPI: Total CPI of All Threads +system.cpu.ipc 0.099658 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.099658 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 4672 # number of integer regfile reads system.cpu.int_regfile_writes 2825 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1455211760 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1458978748 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution @@ -556,19 +595,19 @@ system.cpu.toL2Bus.data_through_bus 17472 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 315500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 316750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 133000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 133500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 93.163170 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 93.052511 # Cycle average of tags in use system.cpu.icache.tags.total_refs 815 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4.335106 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 93.163170 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.045490 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.045490 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 93.052511 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.045436 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.045436 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id @@ -587,12 +626,12 @@ system.cpu.icache.demand_misses::cpu.inst 250 # n system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17591499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17591499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17591499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17591499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17591499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17591499 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17506249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17506249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17506249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17506249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17506249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17506249 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1065 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1065 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1065 # number of demand (read+write) accesses @@ -605,12 +644,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.234742 system.cpu.icache.demand_miss_rate::total 0.234742 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.234742 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.234742 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70365.996000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70365.996000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70365.996000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70365.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70365.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70365.996000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70024.996000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70024.996000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70024.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70024.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -631,36 +670,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 188 system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13162249 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13162249 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13162249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13162249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13162249 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13162249 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13110499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13110499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13110499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13110499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13110499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13110499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176526 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.176526 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.176526 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70011.962766 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70011.962766 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70011.962766 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70011.962766 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70011.962766 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70011.962766 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69736.696809 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69736.696809 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 122.028433 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 121.888429 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.360563 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.667870 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002849 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003724 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.250749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.637680 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002846 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000874 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003720 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 249 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -678,17 +717,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12973500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4680750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17654250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1693750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1693750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12973500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6374500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 19348000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12973500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6374500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 19348000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12921750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4652500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17574250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1688000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1688000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12921750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6340500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19262250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12921750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6340500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19262250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -711,17 +750,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69007.978723 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76733.606557 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70900.602410 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70572.916667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70572.916667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69007.978723 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74994.117647 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70871.794872 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69007.978723 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74994.117647 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70871.794872 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68732.712766 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76270.491803 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70579.317269 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70333.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70333.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70557.692308 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70557.692308 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,17 +780,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10603500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3934250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14537750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1399750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1399750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10603500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5334000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15937500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10603500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5334000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15937500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10547750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3905000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14452750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1393500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1393500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10547750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5298500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15846250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10547750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5298500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15846250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -763,30 +802,30 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56401.595745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64495.901639 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58384.538153 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58322.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58322.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56401.595745 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62752.941176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58379.120879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56401.595745 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62752.941176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58379.120879 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56105.053191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64016.393443 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58043.172691 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58062.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58062.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56105.053191 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62335.294118 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58044.871795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56105.053191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62335.294118 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58044.871795 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.630537 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 45.583444 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 759 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.929412 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.630537 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011140 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011140 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.583444 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011129 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011129 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1995 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1995 # Number of data accesses @@ -806,14 +845,14 @@ system.cpu.dcache.demand_misses::cpu.data 196 # n system.cpu.dcache.demand_misses::total 196 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 196 # number of overall misses system.cpu.dcache.overall_misses::total 196 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7964000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7964000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5323250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5323250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13287250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13287250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13287250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13287250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7876750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7876750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5302250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5302250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13179000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13179000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13179000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13179000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 661 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 661 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -830,14 +869,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.205236 system.cpu.dcache.demand_miss_rate::total 0.205236 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.205236 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.205236 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69252.173913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69252.173913 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65719.135802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65719.135802 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67792.091837 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67792.091837 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67792.091837 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67792.091837 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68493.478261 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68493.478261 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65459.876543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65459.876543 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67239.795918 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67239.795918 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67239.795918 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67239.795918 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -862,14 +901,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6461000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6461000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4713500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4713500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6427000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6427000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6427000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6427000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092284 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092284 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses @@ -878,14 +917,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089005 system.cpu.dcache.demand_mshr_miss_rate::total 0.089005 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089005 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.089005 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77733.606557 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77733.606557 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71635.416667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71635.416667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76011.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76011.764706 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77270.491803 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77270.491803 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 2cd66ec8a..6080ce665 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59390 # Simulator instruction rate (inst/s) -host_op_rate 59366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29878318 # Simulator tick rate (ticks/s) -host_mem_usage 267100 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 741583 # Simulator instruction rate (inst/s) +host_op_rate 738395 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 370291096 # Simulator tick rate (ticks/s) +host_mem_usage 253628 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 2596 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index 944c5b9f4..d01144a54 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000053 # Nu sim_ticks 52548 # Number of ticks simulated final_tick 52548 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 15623 # Simulator instruction rate (inst/s) -host_op_rate 15622 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 318507 # Simulator tick rate (ticks/s) -host_mem_usage 173288 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 36298 # Simulator instruction rate (inst/s) +host_op_rate 36291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 739863 # Simulator tick rate (ticks/s) +host_mem_usage 159844 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -209,6 +209,41 @@ system.cpu.num_busy_cycles 52548 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.426467 system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 431 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 215db9928..99c36fa52 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000045 # Nu sim_ticks 44968 # Number of ticks simulated final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 18935 # Simulator instruction rate (inst/s) -host_op_rate 18932 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 330302 # Simulator tick rate (ticks/s) -host_mem_usage 175652 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 32543 # Simulator instruction rate (inst/s) +host_op_rate 32537 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 567670 # Simulator tick rate (ticks/s) +host_mem_usage 162088 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,6 +200,41 @@ system.cpu.num_busy_cycles 44968 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.661804 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 423 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 87 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index eecde778c..c5b73657d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000043 # Nu sim_ticks 43073 # Number of ticks simulated final_tick 43073 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 22164 # Simulator instruction rate (inst/s) -host_op_rate 22160 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 370326 # Simulator tick rate (ticks/s) -host_mem_usage 173416 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 51660 # Simulator instruction rate (inst/s) +host_op_rate 51645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 862979 # Simulator tick rate (ticks/s) +host_mem_usage 159984 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -186,6 +186,41 @@ system.cpu.num_busy_cycles 43073 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.412904 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 293fb7685..3c031887e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000035 # Nu sim_ticks 35432 # Number of ticks simulated final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 22204 # Simulator instruction rate (inst/s) -host_op_rate 22201 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 305145 # Simulator tick rate (ticks/s) -host_mem_usage 174496 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 51262 # Simulator instruction rate (inst/s) +host_op_rate 51245 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 704386 # Simulator tick rate (ticks/s) +host_mem_usage 159904 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -184,6 +184,41 @@ system.cpu.num_busy_cycles 35432 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.200610 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 8be4f5dad..c9a4a26c5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000052 # Nu sim_ticks 52498 # Number of ticks simulated final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 10658 # Simulator instruction rate (inst/s) -host_op_rate 10657 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 217095 # Simulator tick rate (ticks/s) -host_mem_usage 172908 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 55191 # Simulator instruction rate (inst/s) +host_op_rate 55175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1123673 # Simulator tick rate (ticks/s) +host_mem_usage 158428 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -159,6 +159,41 @@ system.cpu.num_busy_cycles 52498 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.958322 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 4ab5ef724..3ccccfd43 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16524000 # Number of ticks simulated final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56666 # Simulator instruction rate (inst/s) -host_op_rate 56644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 363064230 # Simulator tick rate (ticks/s) -host_mem_usage 275808 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 366311 # Simulator instruction rate (inst/s) +host_op_rate 365532 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2339184598 # Simulator tick rate (ticks/s) +host_mem_usage 262348 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 33048 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 18325fbc5..06219c218 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17056000 # Number of ticks simulated -final_tick 17056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16955000 # Number of ticks simulated +final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29277 # Simulator instruction rate (inst/s) -host_op_rate 36530 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108745688 # Simulator tick rate (ticks/s) -host_mem_usage 308972 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 43189 # Simulator instruction rate (inst/s) +host_op_rate 53887 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 159459409 # Simulator tick rate (ticks/s) +host_mem_usage 309444 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17280 # Nu system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 392 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1013133208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 457786116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1470919325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1013133208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1013133208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1013133208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 457786116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1470919325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 392 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16998500 # Total gap between requests +system.physmem.totGap 16897500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 450 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 276.111928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.674706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7 21.88% 21.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8 25.00% 46.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 12.50% 59.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1 3.12% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 6.25% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 3.12% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 28.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32 # Bytes accessed per row activation -system.physmem.totQLat 4223500 # Total ticks spent queuing -system.physmem.totMemAccLat 11614750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation +system.physmem.totQLat 3795000 # Total ticks spent queuing +system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5431250 # Total ticks spent accessing banks -system.physmem.avgQLat 10774.23 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13855.23 # Average bank access latency per DRAM burst +system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29629.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1470.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1470.92 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.49 # Data bus utilization in percentage -system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.56 # Data bus utilization in percentage +system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 326 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43363.52 # Average gap between requests +system.physmem.avgGap 43105.87 # Average gap between requests system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1467166979 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15324750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1475906812 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution @@ -235,9 +239,9 @@ system.membus.tot_pkt_size::total 25024 # Cu system.membus.data_through_bus 25024 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3645250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.4 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2481 # Number of BP lookups system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted @@ -420,39 +424,39 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 34113 # number of cpu cycles simulated +system.cpu.numCycles 33911 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6922 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.138559 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.553229 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10602 80.14% 80.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.71% 81.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.71% 85.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.68% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.03% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.70% 89.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.072729 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.349515 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6934 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2426 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing @@ -461,9 +465,9 @@ system.cpu.decode.BranchMispred 159 # Nu system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7200 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2227 # Number of cycles rename is running system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename @@ -490,23 +494,23 @@ system.cpu.iq.iqSquashedInstsIssued 113 # Nu system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13229 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.674352 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.378841 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9649 72.94% 72.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1315 9.94% 82.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 815 6.16% 89.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 543 4.10% 93.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 260 1.97% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13229 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available @@ -576,10 +580,10 @@ system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8921 # Type of FU issued -system.cpu.iq.rate 0.261513 # Inst issue rate +system.cpu.iq.rate 0.263071 # Inst issue rate system.cpu.iq.fu_busy_cnt 224 # FU busy when requested system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31372 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads @@ -612,43 +616,43 @@ system.cpu.iew.memOrderViolationEvents 21 # Nu system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3299 # number of memory reference insts executed +system.cpu.iew.exec_refs 3300 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.249846 # Inst execution rate +system.cpu.iew.exec_rate 0.251364 # Inst execution rate system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8068 # cumulative count of insts written-back system.cpu.iew.wb_producers 3883 # num instructions producing a value -system.cpu.iew.wb_consumers 7788 # num instructions consuming a value +system.cpu.iew.wb_consumers 7789 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.236508 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back +system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12278 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.466607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.298423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9992 81.38% 81.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1070 8.71% 90.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 401 3.27% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 176 1.43% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 121 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12278 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -659,25 +663,60 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 5729 # Class of committed instruction system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23225 # The number of ROB reads +system.cpu.rob.rob_reads 23248 # The number of ROB reads system.cpu.rob.rob_writes 23415 # The number of ROB writes -system.cpu.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20884 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.430407 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.430407 # CPI: Total CPI of All Threads -system.cpu.ipc 0.134582 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.134582 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39210 # number of integer regfile reads +system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39214 # number of integer regfile reads system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 3239 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1636022514 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution @@ -692,22 +731,22 @@ system.cpu.toL2Bus.data_through_bus 27904 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228745 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 147.751269 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 147.751269 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072144 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses system.cpu.icache.tags.data_accesses 4184 # Number of data accesses @@ -723,12 +762,12 @@ system.cpu.icache.demand_misses::cpu.inst 363 # n system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.icache.overall_misses::total 363 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24948500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24948500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24948500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24948500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24948500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24948500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses @@ -741,12 +780,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68728.650138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68728.650138 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -767,39 +806,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 290 system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20177000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20177000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20177000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20177000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20177000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20177000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 186.152493 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.100090 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47.052403 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004245 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001436 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005681 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses @@ -823,17 +862,17 @@ system.cpu.l2cache.demand_misses::total 397 # nu system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 397 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19680500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6712250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26392750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19680500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9714250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29394750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19680500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9714250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29394750 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) @@ -856,17 +895,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.908467 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -892,17 +931,17 @@ system.cpu.l2cache.demand_mshr_misses::total 392 system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16292000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5423750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21715750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16292000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7922250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24214250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16292000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7922250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24214250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses @@ -914,39 +953,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.338696 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.338696 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021323 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021323 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits @@ -963,22 +1002,22 @@ system.cpu.dcache.demand_misses::cpu.data 496 # n system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses system.cpu.dcache.overall_misses::total 496 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11160743 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11160743 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31557743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31557743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31557743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31557743 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses @@ -989,22 +1028,22 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63624.481855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63624.481855 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -1031,14 +1070,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7022255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7022255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10066255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10066255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10066255 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10066255 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -1047,14 +1086,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index b2921c80f..41f6b039e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17056000 # Number of ticks simulated -final_tick 17056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16955000 # Number of ticks simulated +final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53685 # Simulator instruction rate (inst/s) -host_op_rate 66982 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 199380443 # Simulator tick rate (ticks/s) -host_mem_usage 308976 # Number of bytes of host memory used +host_inst_rate 52426 # Simulator instruction rate (inst/s) +host_op_rate 65410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 193552438 # Simulator tick rate (ticks/s) +host_mem_usage 308400 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17280 # Nu system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 392 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1013133208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 457786116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1470919325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1013133208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1013133208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1013133208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 457786116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1470919325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 392 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16998500 # Total gap between requests +system.physmem.totGap 16897500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 450 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 276.111928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.674706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7 21.88% 21.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8 25.00% 46.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 12.50% 59.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1 3.12% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 6.25% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 3.12% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 28.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32 # Bytes accessed per row activation -system.physmem.totQLat 4223500 # Total ticks spent queuing -system.physmem.totMemAccLat 11614750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation +system.physmem.totQLat 3795000 # Total ticks spent queuing +system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5431250 # Total ticks spent accessing banks -system.physmem.avgQLat 10774.23 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13855.23 # Average bank access latency per DRAM burst +system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29629.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1470.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1470.92 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.49 # Data bus utilization in percentage -system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.56 # Data bus utilization in percentage +system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 326 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43363.52 # Average gap between requests +system.physmem.avgGap 43105.87 # Average gap between requests system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1467166979 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15324750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1475906812 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution @@ -235,9 +239,9 @@ system.membus.tot_pkt_size::total 25024 # Cu system.membus.data_through_bus 25024 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3645250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.4 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2481 # Number of BP lookups system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted @@ -333,39 +337,39 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 34113 # number of cpu cycles simulated +system.cpu.numCycles 33911 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6922 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.138559 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.553229 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10602 80.14% 80.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.71% 81.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.71% 85.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.68% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.03% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.70% 89.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.072729 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.349515 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6934 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2426 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing @@ -374,9 +378,9 @@ system.cpu.decode.BranchMispred 159 # Nu system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7200 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2227 # Number of cycles rename is running system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename @@ -403,23 +407,23 @@ system.cpu.iq.iqSquashedInstsIssued 113 # Nu system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13229 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.674352 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.378841 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9649 72.94% 72.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1315 9.94% 82.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 815 6.16% 89.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 543 4.10% 93.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 260 1.97% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13229 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available @@ -489,10 +493,10 @@ system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8921 # Type of FU issued -system.cpu.iq.rate 0.261513 # Inst issue rate +system.cpu.iq.rate 0.263071 # Inst issue rate system.cpu.iq.fu_busy_cnt 224 # FU busy when requested system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31372 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads @@ -525,43 +529,43 @@ system.cpu.iew.memOrderViolationEvents 21 # Nu system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3299 # number of memory reference insts executed +system.cpu.iew.exec_refs 3300 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.249846 # Inst execution rate +system.cpu.iew.exec_rate 0.251364 # Inst execution rate system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8068 # cumulative count of insts written-back system.cpu.iew.wb_producers 3883 # num instructions producing a value -system.cpu.iew.wb_consumers 7788 # num instructions consuming a value +system.cpu.iew.wb_consumers 7789 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.236508 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back +system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12278 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.466607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.298423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9992 81.38% 81.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1070 8.71% 90.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 401 3.27% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 176 1.43% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 121 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12278 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -572,25 +576,60 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 5729 # Class of committed instruction system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23225 # The number of ROB reads +system.cpu.rob.rob_reads 23248 # The number of ROB reads system.cpu.rob.rob_writes 23415 # The number of ROB writes -system.cpu.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20884 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.430407 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.430407 # CPI: Total CPI of All Threads -system.cpu.ipc 0.134582 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.134582 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39210 # number of integer regfile reads +system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39214 # number of integer regfile reads system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 3239 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1636022514 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution @@ -605,22 +644,22 @@ system.cpu.toL2Bus.data_through_bus 27904 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228745 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 147.751269 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 147.751269 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072144 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses system.cpu.icache.tags.data_accesses 4184 # Number of data accesses @@ -636,12 +675,12 @@ system.cpu.icache.demand_misses::cpu.inst 363 # n system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.icache.overall_misses::total 363 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24948500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24948500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24948500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24948500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24948500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24948500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses @@ -654,12 +693,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68728.650138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68728.650138 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -680,39 +719,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 290 system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20177000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20177000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20177000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20177000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20177000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20177000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 186.152493 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.100090 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47.052403 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004245 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001436 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005681 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses @@ -736,17 +775,17 @@ system.cpu.l2cache.demand_misses::total 397 # nu system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 397 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19680500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6712250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26392750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19680500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9714250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29394750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19680500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9714250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29394750 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) @@ -769,17 +808,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.908467 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -805,17 +844,17 @@ system.cpu.l2cache.demand_mshr_misses::total 392 system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16292000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5423750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21715750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16292000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7922250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24214250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16292000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7922250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24214250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses @@ -827,39 +866,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.338696 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.338696 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021323 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021323 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits @@ -876,22 +915,22 @@ system.cpu.dcache.demand_misses::cpu.data 496 # n system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses system.cpu.dcache.overall_misses::total 496 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11160743 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11160743 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31557743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31557743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31557743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31557743 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses @@ -902,22 +941,22 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63624.481855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63624.481855 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -944,14 +983,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7022255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7022255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10066255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10066255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10066255 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10066255 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -960,14 +999,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index e746c690f..fe7b25846 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97101 # Simulator instruction rate (inst/s) -host_op_rate 121123 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60664840 # Simulator tick rate (ticks/s) -host_mem_usage 311632 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 790734 # Simulator instruction rate (inst/s) +host_op_rate 984195 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 492029482 # Simulator tick rate (ticks/s) +host_mem_usage 297624 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -234,5 +234,40 @@ system.cpu.num_busy_cycles 5742 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction +system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction +system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5742 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 584aefada..2a0a91e3f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82560 # Simulator instruction rate (inst/s) -host_op_rate 102991 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51587489 # Simulator tick rate (ticks/s) -host_mem_usage 311624 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 770690 # Simulator instruction rate (inst/s) +host_op_rate 959471 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 479615706 # Simulator tick rate (ticks/s) +host_mem_usage 296608 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,5 +147,40 @@ system.cpu.num_busy_cycles 5742 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction +system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction +system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5742 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 3e831f55e..ba11ac8e8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25969000 # Number of ticks simulated final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82063 # Simulator instruction rate (inst/s) -host_op_rate 101927 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 466514904 # Simulator tick rate (ticks/s) -host_mem_usage 320464 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 376681 # Simulator instruction rate (inst/s) +host_op_rate 467447 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2137718143 # Simulator tick rate (ticks/s) +host_mem_usage 306356 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -153,6 +153,41 @@ system.cpu.num_busy_cycles 51938 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction +system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction +system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5742 # Class of executed instruction system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 5e15549ca..12868f8fc 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24975000 # Number of ticks simulated -final_tick 24975000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24907000 # Number of ticks simulated +final_tick 24907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86020 # Simulator instruction rate (inst/s) -host_op_rate 86001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 369354314 # Simulator tick rate (ticks/s) -host_mem_usage 263428 # Number of bytes of host memory used +host_inst_rate 84163 # Simulator instruction rate (inst/s) +host_op_rate 84145 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 360406899 # Simulator tick rate (ticks/s) +host_mem_usage 264444 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 812332332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 353633634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1165965966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 812332332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 812332332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 812332332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 353633634 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1165965966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 814550126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 354599109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1169149235 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 814550126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 814550126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 814550126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 354599109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1169149235 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 455 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 455 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24894000 # Total gap between requests +system.physmem.totGap 24826000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,34 +186,32 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 267.093333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.339521 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.296765 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18 24.00% 24.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 29 38.67% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 12.00% 74.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 10.67% 85.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 5.33% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.33% 92.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.33% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 6.67% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation -system.physmem.totQLat 3086250 # Total ticks spent queuing -system.physmem.totMemAccLat 13542500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 106 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 268.075472 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.680617 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.800860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 25 23.58% 23.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40 37.74% 61.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14 13.21% 74.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 10 9.43% 83.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 6.60% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.89% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 2.83% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 4.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation +system.physmem.totQLat 4873000 # Total ticks spent queuing +system.physmem.totMemAccLat 13404250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8181250 # Total ticks spent accessing banks -system.physmem.avgQLat 6782.97 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 17980.77 # Average bank access latency per DRAM burst +system.physmem.avgQLat 10709.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29763.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1165.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29459.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1169.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1165.97 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1169.15 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.11 # Data bus utilization in percentage -system.physmem.busUtilRead 9.11 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.13 # Data bus utilization in percentage +system.physmem.busUtilRead 9.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.51 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -221,10 +219,14 @@ system.physmem.readRowHits 344 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.60 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54712.09 # Average gap between requests +system.physmem.avgGap 54562.64 # Average gap between requests system.physmem.pageHitRate 75.60 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.04 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1165965966 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 780000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 22841500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1169149235 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 404 # Transaction distribution system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -237,8 +239,8 @@ system.membus.data_through_bus 29120 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4258000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4259500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1156 # Number of BP lookups system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted @@ -268,7 +270,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 49951 # number of cpu cycles simulated +system.cpu.numCycles 49815 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). @@ -290,12 +292,12 @@ system.cpu.execution_unit.executions 3133 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9487 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 463 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 44568 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 44432 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. -system.cpu.activity 10.776561 # Percentage of cycles cpu is active +system.cpu.activity 10.805982 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -307,36 +309,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 8.591503 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.568111 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.591503 # CPI: Total CPI of All Threads -system.cpu.ipc 0.116394 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.568111 # CPI: Total CPI of All Threads +system.cpu.ipc 0.116712 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.116394 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 46303 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.116712 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 46167 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3648 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.303157 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 47138 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 7.323095 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 47002 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.631519 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 47184 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 5.646894 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 47048 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2767 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.539429 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 48713 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 5.554552 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 48577 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.478429 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 47063 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.485195 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46927 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2888 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.781666 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 5.797451 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 150.508435 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 150.585033 # Cycle average of tags in use system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.508435 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073490 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073490 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 150.585033 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073528 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073528 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 306 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id @@ -355,12 +357,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25364500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25364500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25364500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25364500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25364500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25364500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25291750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25291750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25291750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25291750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25291750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25291750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses @@ -373,12 +375,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72470 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72470 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72470 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72470 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72470 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72470 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72262.142857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72262.142857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72262.142857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72262.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72262.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72262.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,26 +401,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23031000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23031000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23031000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23031000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23031000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23031000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22956750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22956750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22956750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22956750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22956750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22956750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72197.492163 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72197.492163 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72197.492163 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72197.492163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72197.492163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72197.492163 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71964.733542 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71964.733542 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71964.733542 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71964.733542 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71964.733542 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71964.733542 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1171091091 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1174288353 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -433,21 +435,21 @@ system.cpu.toL2Bus.data_through_bus 29248 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 538000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 538750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 225500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 226250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 208.255183 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 208.347330 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.186433 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.068750 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004644 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.267110 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.080220 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001711 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006355 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006358 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id @@ -471,17 +473,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22685500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6903000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29588500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3846500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3846500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22685500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10749500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33435000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22685500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10749500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33435000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22611250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6877000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29488250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3810250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3810250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22611250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10687250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33298500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22611250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10687250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33298500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -504,17 +506,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71563.091483 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79344.827586 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73238.861386 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75421.568627 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75421.568627 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71563.091483 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77894.927536 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73483.516484 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71563.091483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77894.927536 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73483.516484 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71328.864353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79045.977011 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72990.717822 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74710.784314 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74710.784314 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71328.864353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77443.840580 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73183.516484 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71328.864353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77443.840580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73183.516484 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -534,17 +536,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18705000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5824500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24529500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3204500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3204500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18705000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9029000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27734000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18705000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9029000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27734000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18629250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5798500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24427750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3166750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3166750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18629250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8965250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27594500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18629250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8965250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27594500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -556,27 +558,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59006.309148 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66948.275862 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60716.584158 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59006.309148 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65427.536232 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60953.846154 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59006.309148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65427.536232 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60953.846154 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58767.350158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66649.425287 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60464.727723 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62093.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62093.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58767.350158 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64965.579710 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60647.252747 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58767.350158 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64965.579710 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60647.252747 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 90.278621 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 90.296415 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 90.278621 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022041 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022041 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 90.296415 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022045 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022045 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id @@ -599,14 +601,14 @@ system.cpu.dcache.demand_misses::cpu.data 450 # n system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses system.cpu.dcache.overall_misses::total 450 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7687000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7687000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21761250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21761250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29448250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29448250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29448250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29448250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7634750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7634750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21637250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21637250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29272000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29272000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29272000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29272000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -623,14 +625,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79247.422680 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 79247.422680 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61646.600567 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61646.600567 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65440.555556 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65440.555556 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65440.555556 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65440.555556 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78708.762887 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78708.762887 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61295.325779 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61295.325779 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65048.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65048.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65048.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65048.888889 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -655,14 +657,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6996500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6996500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3900500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3900500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10897000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10897000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10897000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10897000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6970500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6970500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3864250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3864250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10834750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10834750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10834750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10834750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -671,14 +673,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80419.540230 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80419.540230 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76480.392157 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76480.392157 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78963.768116 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78963.768116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78963.768116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78963.768116 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80120.689655 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80120.689655 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75769.607843 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75769.607843 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78512.681159 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78512.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78512.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78512.681159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index cbbbf2296..6e934b1b9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21918500 # Number of ticks simulated -final_tick 21918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21843500 # Number of ticks simulated +final_tick 21843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56826 # Simulator instruction rate (inst/s) -host_op_rate 56817 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 241494238 # Simulator tick rate (ticks/s) -host_mem_usage 266500 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 63396 # Simulator instruction rate (inst/s) +host_op_rate 63384 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 268482897 # Simulator tick rate (ticks/s) +host_mem_usage 267540 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory system.physmem.num_reads::total 477 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 978169127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 414626913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1392796040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 978169127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 978169127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 978169127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 414626913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1392796040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 981527686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 416050541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1397578227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 981527686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 981527686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 981527686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 416050541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1397578227 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 477 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21839000 # Total gap between requests +system.physmem.totGap 21764000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,34 +186,33 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.436782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.540369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 250.647056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 26 29.89% 29.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32 36.78% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 14.94% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 6.90% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 2.30% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.15% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.30% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 5.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation -system.physmem.totQLat 2715000 # Total ticks spent queuing -system.physmem.totMemAccLat 13776250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 254.238532 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.990405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 249.769927 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 31 28.44% 28.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40 36.70% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16 14.68% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 7.34% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 3.67% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 0.92% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 2.75% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.92% 95.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation +system.physmem.totQLat 4715500 # Total ticks spent queuing +system.physmem.totMemAccLat 13659250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8676250 # Total ticks spent accessing banks -system.physmem.avgQLat 5691.82 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 18189.20 # Average bank access latency per DRAM burst +system.physmem.avgQLat 9885.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28881.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1392.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28635.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1397.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1392.80 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1397.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.88 # Data bus utilization in percentage -system.physmem.busUtilRead 10.88 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.92 # Data bus utilization in percentage +system.physmem.busUtilRead 10.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -221,10 +220,14 @@ system.physmem.readRowHits 357 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 74.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45784.07 # Average gap between requests +system.physmem.avgGap 45626.83 # Average gap between requests system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1392796040 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15319000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1397578227 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 426 # Transaction distribution system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -235,10 +238,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 604500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4473250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4474250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2174 # Number of BP lookups system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted @@ -268,7 +271,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 43838 # number of cpu cycles simulated +system.cpu.numCycles 43688 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 8831 # Number of cycles fetch is stalled on an Icache miss @@ -277,18 +280,18 @@ system.cpu.fetch.Branches 2174 # Nu system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1408 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 1402 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.908859 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.220900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 14499 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.909235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221283 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11292 77.85% 77.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1317 9.08% 86.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 104 0.72% 87.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 131 0.90% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11286 77.84% 77.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1317 9.08% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 104 0.72% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 131 0.90% 88.54% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 305 2.10% 90.65% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 115 0.79% 91.44% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 150 1.03% 92.48% # Number of instructions fetched each cycle (Total) @@ -297,11 +300,11 @@ system.cpu.fetch.rateDist::8 933 6.43% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.049592 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.300721 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::total 14499 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049762 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.301753 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 8899 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1660 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 1654 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3025 # Number of cycles decode is running system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing @@ -311,8 +314,8 @@ system.cpu.decode.DecodedInsts 12292 # Nu system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 9081 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst +system.cpu.rename.BlockCycles 531 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2898 # Number of cycles rename is running system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename @@ -339,14 +342,14 @@ system.cpu.iq.iqSquashedInstsIssued 39 # Nu system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14505 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.571734 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.240341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.571970 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.240543 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10922 75.30% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1422 9.80% 85.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 891 6.14% 91.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 553 3.81% 95.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10916 75.29% 75.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1422 9.81% 85.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 891 6.15% 91.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 553 3.81% 95.05% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 355 2.45% 97.50% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 226 1.56% 99.06% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 89 0.61% 99.68% # Number of insts issued each cycle @@ -355,7 +358,7 @@ system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14499 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available @@ -425,10 +428,10 @@ system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8293 # Type of FU issued -system.cpu.iq.rate 0.189174 # Inst issue rate +system.cpu.iq.rate 0.189823 # Inst issue rate system.cpu.iq.fu_busy_cnt 160 # FU busy when requested system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31286 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 31280 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads @@ -469,23 +472,23 @@ system.cpu.iew.exec_nop 1512 # nu system.cpu.iew.exec_refs 3186 # number of memory reference insts executed system.cpu.iew.exec_branches 1344 # Number of branches executed system.cpu.iew.exec_stores 1079 # Number of stores executed -system.cpu.iew.exec_rate 0.180483 # Inst execution rate +system.cpu.iew.exec_rate 0.181102 # Inst execution rate system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit system.cpu.iew.wb_count 7455 # cumulative count of insts written-back system.cpu.iew.wb_producers 2921 # num instructions producing a value system.cpu.iew.wb_consumers 4197 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.170058 # insts written-back per cycle +system.cpu.iew.wb_rate 0.170642 # insts written-back per cycle system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13637 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.426267 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.206560 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13631 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.426454 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.206792 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11235 82.39% 82.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11229 82.38% 82.38% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 999 7.33% 89.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 630 4.62% 94.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 315 2.31% 96.64% # Number of insts commited each cycle @@ -497,7 +500,7 @@ system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13637 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13631 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -508,25 +511,60 @@ system.cpu.commit.branches 915 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5111 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 657 11.30% 11.30% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3062 52.68% 63.98% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 3 0.05% 64.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 1 0.02% 64.05% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.03% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1163 20.01% 84.09% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 5813 # Class of committed instruction system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24245 # The number of ROB reads +system.cpu.rob.rob_reads 24239 # The number of ROB reads system.cpu.rob.rob_writes 22333 # The number of ROB writes -system.cpu.timesIdled 286 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29333 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29189 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 8.502327 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.502327 # CPI: Total CPI of All Threads -system.cpu.ipc 0.117615 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.117615 # IPC: Total IPC of All Threads +system.cpu.cpi 8.473235 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.473235 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118019 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.118019 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 10743 # number of integer regfile reads system.cpu.int_regfile_writes 5234 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 148 # number of misc regfile reads -system.cpu.toL2Bus.throughput 1401555763 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1406368027 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -541,19 +579,19 @@ system.cpu.toL2Bus.data_through_bus 30720 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 571500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 161.390328 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 161.382673 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.390328 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078804 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078804 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.382673 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078800 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078800 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id @@ -572,12 +610,12 @@ system.cpu.icache.demand_misses::cpu.inst 451 # n system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses system.cpu.icache.overall_misses::total 451 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31256750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31256750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31256750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31256750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31256750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31256750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31159250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31159250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31159250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31159250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31159250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31159250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses @@ -590,12 +628,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69305.432373 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69305.432373 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69305.432373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69305.432373 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69089.246120 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69089.246120 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69089.246120 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69089.246120 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -616,36 +654,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 338 system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24262750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24262750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24262750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24262750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24262750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24262750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24154000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24154000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24154000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24154000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24154000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24154000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71783.284024 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71783.284024 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71461.538462 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71461.538462 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.496759 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.484913 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.678282 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.818477 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.674419 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810494 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006760 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006759 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id @@ -669,17 +707,17 @@ system.cpu.l2cache.demand_misses::total 477 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 477 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23894750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7065750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30960500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3800750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3800750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23894750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10866500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34761250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23894750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34761250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23786000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7056500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30842500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3776250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3776250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23786000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10832750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34618750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23786000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10832750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34618750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) @@ -702,17 +740,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993750 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71327.611940 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77645.604396 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72677.230047 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74524.509804 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74524.509804 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72874.737945 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72874.737945 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71002.985075 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77543.956044 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72400.234742 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72575.995807 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72575.995807 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -732,17 +770,17 @@ system.cpu.l2cache.demand_mshr_misses::total 477 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19660250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5948250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25608500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3170750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3170750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19660250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9119000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28779250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19660250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9119000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28779250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19551000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5938500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25489500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3144250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3144250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19551000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9082750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28633750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19551000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9082750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28633750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses @@ -754,27 +792,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58687.313433 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65365.384615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60113.849765 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62171.568627 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62171.568627 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58361.194030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65258.241758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59834.507042 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61651.960784 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61651.960784 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.623425 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 91.603992 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.623425 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022369 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022369 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.603992 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022364 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022364 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id @@ -797,14 +835,14 @@ system.cpu.dcache.demand_misses::cpu.data 510 # n system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10261250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22413999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22413999 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32675249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32675249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32675249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32675249 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10242750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22302249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22302249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32544999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32544999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32544999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32544999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -821,19 +859,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69332.770270 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69332.770270 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61917.124309 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61917.124309 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64069.115686 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64069.115686 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 605 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69207.770270 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69207.770270 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61608.422652 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61608.422652 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63813.723529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63813.723529 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -853,14 +891,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7160250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7160250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3852749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3852749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11012999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11012999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11012999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11012999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7151000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7151000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3828249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3828249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10979249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10979249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10979249 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10979249 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -869,14 +907,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78684.065934 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78684.065934 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75544.098039 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75544.098039 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78582.417582 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78582.417582 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index b2f335f88..c5418ef55 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2907000 # Number of ticks simulated final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99853 # Simulator instruction rate (inst/s) -host_op_rate 99820 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49894332 # Simulator tick rate (ticks/s) -host_mem_usage 269208 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 1298058 # Simulator instruction rate (inst/s) +host_op_rate 1293725 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 644853594 # Simulator tick rate (ticks/s) +host_mem_usage 255756 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -81,5 +81,40 @@ system.cpu.num_busy_cycles 5815 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 915 # Number of branches fetched +system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction +system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction +system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction +system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5815 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 24111f1bf..88e0b5c68 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000125 # Nu sim_ticks 125334 # Number of ticks simulated final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 32356 # Simulator instruction rate (inst/s) -host_op_rate 32352 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 697352 # Simulator tick rate (ticks/s) -host_mem_usage 176168 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 56489 # Simulator instruction rate (inst/s) +host_op_rate 56481 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1217426 # Simulator tick rate (ticks/s) +host_mem_usage 162604 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -146,6 +146,41 @@ system.cpu.num_busy_cycles 125334 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 915 # Number of branches fetched +system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction +system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction +system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction +system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5815 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.954490 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1493 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1489 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index d941cff49..ee2cc6627 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000032 # Nu sim_ticks 31633000 # Number of ticks simulated final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119247 # Simulator instruction rate (inst/s) -host_op_rate 119199 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 648290000 # Simulator tick rate (ticks/s) -host_mem_usage 277916 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 474922 # Simulator instruction rate (inst/s) +host_op_rate 474341 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2577866515 # Simulator tick rate (ticks/s) +host_mem_usage 263440 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -87,6 +87,41 @@ system.cpu.num_busy_cycles 63266 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 915 # Number of branches fetched +system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction +system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction +system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction +system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5815 # Class of executed instruction system.cpu.icache.tags.replacements 13 # number of replacements system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks. diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index d62c7aac6..810e47329 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19079500 # Number of ticks simulated -final_tick 19079500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19030500 # Number of ticks simulated +final_tick 19030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82615 # Simulator instruction rate (inst/s) -host_op_rate 82599 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 272039638 # Simulator tick rate (ticks/s) +host_inst_rate 79159 # Simulator instruction rate (inst/s) +host_op_rate 79144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 259986612 # Simulator tick rate (ticks/s) host_mem_usage 262500 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1157263031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 338792945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1496055976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1157263031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1157263031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1157263031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 338792945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1496055976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1160242768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 339665274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1499908042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1160242768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1160242768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1160242768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 339665274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1499908042 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 446 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18951000 # Total gap between requests +system.physmem.totGap 18902000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 143 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -186,45 +186,47 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.586207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.841802 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 367.136049 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 17 29.31% 29.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14 24.14% 53.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 10.34% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 5.17% 68.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 6.90% 75.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.45% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.72% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 18.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58 # Bytes accessed per row activation -system.physmem.totQLat 2851500 # Total ticks spent queuing -system.physmem.totMemAccLat 11984000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 77 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 342.441558 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 198.974683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 351.274465 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28 36.36% 36.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 22.08% 58.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6 7.79% 66.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 6.49% 72.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 6.49% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 2.60% 81.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 3.90% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 11 14.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 77 # Bytes accessed per row activation +system.physmem.totQLat 3599250 # Total ticks spent queuing +system.physmem.totMemAccLat 11961750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6902500 # Total ticks spent accessing banks -system.physmem.avgQLat 6393.50 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15476.46 # Average bank access latency per DRAM burst +system.physmem.avgQLat 8070.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26869.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1496.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26820.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1499.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1496.06 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1499.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.69 # Data bus utilization in percentage -system.physmem.busUtilRead 11.69 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.72 # Data bus utilization in percentage +system.physmem.busUtilRead 11.72 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 358 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42491.03 # Average gap between requests +system.physmem.avgGap 42381.17 # Average gap between requests system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1496055976 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1499908042 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -235,10 +237,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 567500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 565500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4177500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2235 # Number of BP lookups system.cpu.branchPred.condPredicted 1802 # Number of conditional branches predicted @@ -268,55 +270,55 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 38160 # number of cpu cycles simulated +system.cpu.numCycles 38062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7440 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13154 # Number of instructions fetch has processed system.cpu.fetch.Branches 2235 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2260 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 1309 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1810 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11787 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.115975 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.532873 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 11872 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.107985 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.525542 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9527 80.83% 80.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 176 1.49% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.49% 83.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 142 1.20% 85.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.93% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 132 1.12% 88.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.18% 90.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 110 0.93% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1040 8.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9612 80.96% 80.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 176 1.48% 82.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.48% 83.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 142 1.20% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.91% 87.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 132 1.11% 88.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.16% 90.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 110 0.93% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1040 8.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11787 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.058569 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.344706 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7519 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1384 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2094 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 11872 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.058720 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.345594 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7525 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1463 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2089 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 86 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 340 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 11724 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7704 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 677 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 7710 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 717 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 445 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1984 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 268 # Number of cycles rename is unblocking +system.cpu.rename.RunCycles 1980 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 311 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 11305 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 230 # Number of times rename has blocked due to LSQ full +system.cpu.rename.LSQFullEvents 264 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 18187 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 18161 # Number of integer rename lookups @@ -325,7 +327,7 @@ system.cpu.rename.CommittedMaps 4998 # Nu system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 582 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 615 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. @@ -337,23 +339,23 @@ system.cpu.iq.iqSquashedInstsIssued 241 # Nu system.cpu.iq.iqSquashedInstsExamined 4242 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11787 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.755154 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.486388 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11872 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.749747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.477871 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8427 71.49% 71.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 791 6.71% 87.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 500 4.24% 91.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 455 3.86% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 306 2.60% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8485 71.47% 71.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1128 9.50% 80.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 793 6.68% 87.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 504 4.25% 91.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.84% 95.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 296 2.49% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 132 1.11% 99.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11787 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11872 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available @@ -423,10 +425,10 @@ system.cpu.iq.FU_type_0::MemWrite 1627 18.28% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8901 # Type of FU issued -system.cpu.iq.rate 0.233255 # Inst issue rate +system.cpu.iq.rate 0.233855 # Inst issue rate system.cpu.iq.fu_busy_cnt 173 # FU busy when requested system.cpu.iq.fu_busy_rate 0.019436 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29941 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 30026 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 14573 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8128 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads @@ -467,35 +469,35 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3201 # number of memory reference insts executed system.cpu.iew.exec_branches 1350 # Number of branches executed system.cpu.iew.exec_stores 1523 # Number of stores executed -system.cpu.iew.exec_rate 0.222746 # Inst execution rate +system.cpu.iew.exec_rate 0.223320 # Inst execution rate system.cpu.iew.wb_sent 8270 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8155 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4217 # num instructions producing a value -system.cpu.iew.wb_consumers 6678 # num instructions consuming a value +system.cpu.iew.wb_producers 4187 # num instructions producing a value +system.cpu.iew.wb_consumers 6623 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.213705 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631476 # average fanout of values written-back +system.cpu.iew.wb_rate 0.214256 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.632191 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11078 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.522838 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.323591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11163 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.518857 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.312790 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8698 78.52% 78.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1008 9.10% 87.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 609 5.50% 93.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 270 2.44% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 70 0.63% 98.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 44 0.40% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8756 78.44% 78.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1031 9.24% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 625 5.60% 93.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.36% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 174 1.56% 97.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 104 0.93% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 65 0.58% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.39% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11078 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11163 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -506,24 +508,59 @@ system.cpu.commit.branches 1037 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 5792 # Class of committed instruction system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21343 # The number of ROB reads +system.cpu.rob.rob_reads 21428 # The number of ROB reads system.cpu.rob.rob_writes 21442 # The number of ROB writes -system.cpu.timesIdled 246 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26373 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26190 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 6.588398 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.588398 # CPI: Total CPI of All Threads -system.cpu.ipc 0.151782 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.151782 # IPC: Total IPC of All Threads +system.cpu.cpi 6.571478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.571478 # CPI: Total CPI of All Threads +system.cpu.ipc 0.152173 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.152173 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 13470 # number of integer regfile reads system.cpu.int_regfile_writes 7047 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.throughput 1519536675 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1523449200 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution @@ -538,19 +575,19 @@ system.cpu.toL2Bus.data_through_bus 28992 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 585250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 161250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.852168 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 168.931685 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1369 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.900285 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.852168 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082447 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082447 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 168.931685 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082486 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id @@ -569,12 +606,12 @@ system.cpu.icache.demand_misses::cpu.inst 441 # n system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses system.cpu.icache.overall_misses::total 441 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30135000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30135000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30135000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30135000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30135000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30135000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30033500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30033500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30033500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30033500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30033500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30033500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1810 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1810 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1810 # number of demand (read+write) accesses @@ -587,12 +624,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.243646 system.cpu.icache.demand_miss_rate::total 0.243646 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.243646 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.243646 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68333.333333 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68333.333333 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68333.333333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68333.333333 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68103.174603 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68103.174603 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68103.174603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68103.174603 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -613,36 +650,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 351 system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24444750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24444750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24444750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24444750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24444750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24444750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24362250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24362250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24362250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24362250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24362250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24362250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193923 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69643.162393 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69643.162393 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69408.119658 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69408.119658 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.197303 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.280245 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.717049 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.480255 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.794904 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.485341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005121 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006079 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006082 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id @@ -669,17 +706,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24033250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4074500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28107750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3621750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3621750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24033250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7696250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31729500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24033250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7696250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31729500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23950750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4072250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28023000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3614250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3614250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23950750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7686500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31637250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23950750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7686500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31637250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -702,17 +739,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69661.594203 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70445.488722 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77058.510638 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77058.510638 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71142.376682 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71142.376682 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69422.463768 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75412.037037 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70233.082707 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76898.936170 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76898.936170 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70935.538117 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70935.538117 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -732,17 +769,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19691750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3410500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23102250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3044750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3044750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19691750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6455250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26147000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19691750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6455250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26147000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19603250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3407750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3033250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3033250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19603250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6441000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26044250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19603250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6441000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26044250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -754,25 +791,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57077.536232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.375940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56821.014493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63106.481481 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57671.679198 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64537.234043 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64537.234043 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.689105 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 63.690367 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.689105 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 63.690367 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.015549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.015549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id @@ -797,14 +834,14 @@ system.cpu.dcache.demand_misses::cpu.data 435 # n system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses system.cpu.dcache.overall_misses::total 435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7364750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7364750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20363246 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20363246 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27727996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27727996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27727996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27727996 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7366750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7366750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20319996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20319996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27686746 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27686746 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27686746 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27686746 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -821,19 +858,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70814.903846 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70814.903846 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61520.380665 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61520.380665 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63742.519540 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63742.519540 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70834.134615 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70834.134615 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61389.716012 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61389.716012 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63647.691954 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63647.691954 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 98.400000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -853,14 +890,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4140000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4140000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3671748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3671748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7811748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7811748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7811748 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7811748 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4137750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4137750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3664248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3664248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7801998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7801998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7801998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7801998 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -869,14 +906,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78122.297872 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78122.297872 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75231.818182 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75231.818182 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77962.723404 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77962.723404 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index 96c448d8d..bcfd2d5d0 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139089 # Simulator instruction rate (inst/s) -host_op_rate 138996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69453756 # Simulator tick rate (ticks/s) -host_mem_usage 265200 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 1148266 # Simulator instruction rate (inst/s) +host_op_rate 1144862 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 570752858 # Simulator tick rate (ticks/s) +host_mem_usage 250716 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -81,5 +81,40 @@ system.cpu.num_busy_cycles 5793 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1037 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3784 65.32% 65.32% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 65.32% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 65.32% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 65.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::MemRead 961 16.59% 81.94% # Class of executed instruction +system.cpu.op_class::MemWrite 1046 18.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5793 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index ca26bca81..90109d140 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20970500 # Number of ticks simulated -final_tick 20970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20918500 # Number of ticks simulated +final_tick 20918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71497 # Simulator instruction rate (inst/s) -host_op_rate 71482 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 281347268 # Simulator tick rate (ticks/s) -host_mem_usage 269780 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 69876 # Simulator instruction rate (inst/s) +host_op_rate 69862 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 274294219 # Simulator tick rate (ticks/s) +host_mem_usage 270808 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 882000906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 408955437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1290956343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 882000906 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 882000906 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 882000906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 408955437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1290956343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 884193417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 409972034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1294165452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 884193417 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 884193417 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 884193417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 409972034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1294165452 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20901000 # Total gap between requests +system.physmem.totGap 20849000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,33 +186,31 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 337.333333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 221.579222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 300.401245 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 27.08% 27.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9 18.75% 45.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 12.50% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 14.58% 72.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 12.50% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 4.17% 89.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 10.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48 # Bytes accessed per row activation -system.physmem.totQLat 3113750 # Total ticks spent queuing -system.physmem.totMemAccLat 11732500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 74 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.459459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 226.188766 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 265.234411 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 17 22.97% 22.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 21.62% 44.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11 14.86% 59.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 13 17.57% 77.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8 10.81% 87.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 5.41% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 6.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 74 # Bytes accessed per row activation +system.physmem.totQLat 3773250 # Total ticks spent queuing +system.physmem.totMemAccLat 11704500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6503750 # Total ticks spent accessing banks -system.physmem.avgQLat 7361.11 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15375.30 # Average bank access latency per DRAM burst +system.physmem.avgQLat 8920.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27736.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1290.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27670.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1294.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1290.96 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1294.17 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.09 # Data bus utilization in percentage -system.physmem.busUtilRead 10.09 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.11 # Data bus utilization in percentage +system.physmem.busUtilRead 10.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,10 +218,14 @@ system.physmem.readRowHits 339 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49411.35 # Average gap between requests +system.physmem.avgGap 49288.42 # Average gap between requests system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1290956343 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 13500 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15312750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1294165452 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 342 # Transaction distribution system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution @@ -236,8 +238,8 @@ system.membus.data_through_bus 27072 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3929500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 18.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted @@ -249,7 +251,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41942 # number of cpu cycles simulated +system.cpu.numCycles 41838 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). @@ -271,12 +273,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9659 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9657 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 424 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35694 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 422 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35590 # Number of cycles cpu's stages were not processed system.cpu.runCycles 6248 # Number of cycles cpu stages are processed. -system.cpu.activity 14.896762 # Percentage of cycles cpu is active +system.cpu.activity 14.933792 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -288,36 +290,36 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.873475 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.853952 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.873475 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127009 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.853952 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127324 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.127009 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 37302 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.127324 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37198 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.062896 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38748 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.090396 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38644 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3194 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.615278 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38908 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.634208 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38804 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.233799 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 40966 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.251781 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40862 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 976 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.327023 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38785 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.332807 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38681 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.527061 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.545772 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.644710 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.676310 # Cycle average of tags in use system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.644710 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069651 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069651 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.676310 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069666 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069666 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id @@ -336,12 +338,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25482750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25482750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25482750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25482750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25482750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25482750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25425250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25425250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25425250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25425250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25425250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25425250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses @@ -354,12 +356,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69625 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69625 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69625 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69625 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69625 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69625 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69467.896175 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69467.896175 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69467.896175 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69467.896175 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69467.896175 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69467.896175 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,26 +382,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20711750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20711750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20711750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20711750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20711750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20711750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20653250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20653250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20653250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20653250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20653250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20653250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71174.398625 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71174.398625 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71174.398625 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71174.398625 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71174.398625 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71174.398625 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70973.367698 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70973.367698 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70973.367698 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70973.367698 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70973.367698 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70973.367698 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1300112062 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1303343930 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -414,24 +416,24 @@ system.cpu.toL2Bus.data_through_bus 27264 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 486250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 216250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 217000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 169.087834 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 169.122448 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.075458 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.012376 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004336 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.106217 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.016231 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004337 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005160 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005161 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010437 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3831 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3831 # Number of data accesses @@ -455,17 +457,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20393250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4031000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24424250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6031750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6031750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20393250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10062750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30456000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20393250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10062750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30456000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20334750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4016000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24350750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5999500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5999500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20334750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10015500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30350250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20334750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10015500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30350250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -488,17 +490,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70564.878893 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76056.603774 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71415.935673 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74466.049383 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74466.049383 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70564.878893 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75095.149254 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70564.878893 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75095.149254 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70362.456747 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75773.584906 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71201.023392 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74067.901235 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74067.901235 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70362.456747 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74742.537313 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71750 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70362.456747 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74742.537313 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71750 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,17 +520,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16781250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3376000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20157250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5037250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5037250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16781250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8413250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25194500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16781250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8413250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25194500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16720750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3361000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20081750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5004000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5004000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16720750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8365000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25085750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16720750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8365000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25085750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -540,27 +542,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58066.608997 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63698.113208 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58939.327485 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62188.271605 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62188.271605 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58066.608997 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62785.447761 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59561.465721 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58066.608997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62785.447761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59561.465721 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57857.266436 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63415.094340 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58718.567251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61777.777778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61777.777778 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57857.266436 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62425.373134 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59304.373522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57857.266436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62425.373134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59304.373522 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.369033 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 85.354091 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.369033 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 85.354091 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020838 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020838 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id @@ -583,14 +585,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4594750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4594750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29091500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29091500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33686250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33686250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33686250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33686250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4579750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4579750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28882250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28882250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33462000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33462000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33462000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33462000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -607,14 +609,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75323.770492 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75323.770492 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70439.467312 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70439.467312 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71068.037975 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71068.037975 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71068.037975 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71068.037975 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75077.868852 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75077.868852 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69932.808717 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69932.808717 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70594.936709 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70594.936709 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70594.936709 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70594.936709 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked @@ -639,14 +641,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4097500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4097500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6115250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6115250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10212750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10212750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10212750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10212750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4082500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4082500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6083000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6083000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10165500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10165500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10165500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10165500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -655,14 +657,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75879.629630 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75879.629630 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75496.913580 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75496.913580 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75650 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75650 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75650 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75650 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75601.851852 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75601.851852 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75098.765432 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75098.765432 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75300 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75300 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75300 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75300 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index fd2ae491a..0e41891dc 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97647 # Simulator instruction rate (inst/s) -host_op_rate 97614 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49358124 # Simulator tick rate (ticks/s) -host_mem_usage 275540 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 1015247 # Simulator instruction rate (inst/s) +host_op_rate 1012545 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 510902541 # Simulator tick rate (ticks/s) +host_mem_usage 261064 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -63,5 +63,40 @@ system.cpu.num_busy_cycles 5390 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched +system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction +system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction +system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5370 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 97d6558cc..0f04f9760 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000108 # Nu sim_ticks 107952 # Number of ticks simulated final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 1705 # Simulator instruction rate (inst/s) -host_op_rate 1705 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34543 # Simulator tick rate (ticks/s) -host_mem_usage 182496 # Number of bytes of host memory used -host_seconds 3.13 # Real time elapsed on the host +host_inst_rate 57135 # Simulator instruction rate (inst/s) +host_op_rate 57126 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1157488 # Simulator tick rate (ticks/s) +host_mem_usage 168948 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -128,6 +128,41 @@ system.cpu.num_busy_cycles 107952 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched +system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction +system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction +system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5370 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.968393 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 9e27f540c..f251b736b 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27800000 # Number of ticks simulated final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49661 # Simulator instruction rate (inst/s) -host_op_rate 49653 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 259077754 # Simulator tick rate (ticks/s) -host_mem_usage 284248 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 487107 # Simulator instruction rate (inst/s) +host_op_rate 486440 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2535570960 # Simulator tick rate (ticks/s) +host_mem_usage 269788 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -69,6 +69,41 @@ system.cpu.num_busy_cycles 55600 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched +system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction +system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction +system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5370 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 33851c6e5..32cefdc54 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20069500 # Number of ticks simulated -final_tick 20069500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20011500 # Number of ticks simulated +final_tick 20011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42536 # Simulator instruction rate (inst/s) -host_op_rate 77054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158640887 # Simulator tick rate (ticks/s) -host_mem_usage 283320 # Number of bytes of host memory used +host_inst_rate 41048 # Simulator instruction rate (inst/s) +host_op_rate 74359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152650007 # Simulator tick rate (ticks/s) +host_mem_usage 284392 # Number of bytes of host memory used host_seconds 0.13 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17472 # Nu system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 414 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 870574753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 449637510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1320212262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 870574753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 870574753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 870574753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 449637510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1320212262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 873097969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 450940709 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1324038678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 873097969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 873097969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 873097969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 450940709 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1324038678 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 415 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20021000 # Total gap between requests +system.physmem.totGap 19963000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,33 +186,31 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 240.676056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.837127 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 281.987222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 26 36.62% 36.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 26 36.62% 73.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 11.27% 84.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 2.82% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.82% 90.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.82% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 7.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation -system.physmem.totQLat 2360500 # Total ticks spent queuing -system.physmem.totMemAccLat 12135500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.697208 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 270.249471 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 33 34.02% 34.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 34 35.05% 69.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13 13.40% 82.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 6.19% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 3.09% 94.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation +system.physmem.totQLat 4234000 # Total ticks spent queuing +system.physmem.totMemAccLat 12015250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers -system.physmem.totBankLat 7700000 # Total ticks spent accessing banks -system.physmem.avgQLat 5687.95 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 18554.22 # Average bank access latency per DRAM burst +system.physmem.avgQLat 10202.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29242.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1323.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28952.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1327.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1323.40 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1327.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.34 # Data bus utilization in percentage -system.physmem.busUtilRead 10.34 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.37 # Data bus utilization in percentage +system.physmem.busUtilRead 10.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,10 +218,14 @@ system.physmem.readRowHits 307 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 73.98 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48243.37 # Average gap between requests +system.physmem.avgGap 48103.61 # Average gap between requests system.physmem.pageHitRate 73.98 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1320212262 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15333750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1324038678 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 338 # Transaction distribution system.membus.trans_dist::ReadResp 337 # Transaction distribution system.membus.trans_dist::ReadExReq 77 # Transaction distribution @@ -236,109 +238,109 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26496 system.membus.tot_pkt_size::total 26496 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 26496 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 500500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 501000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 3871750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 3873250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 3084 # Number of BP lookups -system.cpu.branchPred.condPredicted 3084 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 542 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2283 # Number of BTB lookups -system.cpu.branchPred.BTBHits 726 # Number of BTB hits +system.cpu.branchPred.lookups 3083 # Number of BP lookups +system.cpu.branchPred.condPredicted 3083 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2281 # Number of BTB lookups +system.cpu.branchPred.BTBHits 725 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.800263 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 31.784305 # BTB Hit Percentage system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 40140 # number of cpu cycles simulated +system.cpu.numCycles 40024 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10289 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14134 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3084 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3940 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5352 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 10292 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14141 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3083 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3942 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2472 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5349 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1980 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21899 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.150509 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.666400 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.150913 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.666787 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18060 82.47% 82.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 216 0.99% 83.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18059 82.46% 82.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 217 0.99% 83.45% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 142 0.65% 84.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.02% 85.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 181 0.83% 85.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 200 0.91% 86.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.02% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 180 0.82% 85.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 201 0.92% 86.86% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 275 1.26% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 159 0.73% 88.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2442 11.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 159 0.73% 88.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2443 11.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21899 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.076831 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.352118 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11081 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5247 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 21900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077029 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.353313 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11088 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5242 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3583 # Number of cycles decode is running system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24173 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11446 # Number of cycles rename is idle +system.cpu.decode.SquashCycles 1856 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24179 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1856 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11454 # Number of cycles rename is idle system.cpu.rename.BlockCycles 3886 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 603 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3331 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 776 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22661 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 592 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3330 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 782 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22657 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 663 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25256 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 55040 # Number of register rename lookups that rename has made +system.cpu.rename.IQFullEvents 37 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 664 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 25254 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 55037 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 31380 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14193 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 14191 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2047 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 2053 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2285 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1565 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20236 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 20246 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17027 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9729 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13960 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17025 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 298 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9739 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13977 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21899 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.652832 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 21900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.777397 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.653011 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16413 74.95% 74.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1539 7.03% 81.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1092 4.99% 86.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 724 3.31% 90.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 698 3.19% 93.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 576 2.63% 96.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 581 2.65% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16414 74.95% 74.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1544 7.05% 82.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1087 4.96% 86.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 722 3.30% 90.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 701 3.20% 93.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 573 2.62% 96.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 583 2.66% 98.74% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21899 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21900 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available @@ -374,7 +376,7 @@ system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13667 80.27% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13665 80.26% 80.28% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued @@ -407,17 +409,17 @@ system.cpu.iq.FU_type_0::MemRead 1973 11.59% 91.94% # Ty system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17027 # Type of FU issued -system.cpu.iq.rate 0.424190 # Inst issue rate +system.cpu.iq.FU_type_0::total 17025 # Type of FU issued +system.cpu.iq.rate 0.425370 # Inst issue rate system.cpu.iq.fu_busy_cnt 181 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010630 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 56416 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 29998 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15642 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.010631 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 56421 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30018 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15641 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17201 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17199 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 168 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -430,10 +432,10 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3086 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1856 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3085 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20262 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 20272 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2285 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1565 # Number of dispatched store instructions @@ -442,33 +444,33 @@ system.cpu.iew.iewIQFullEvents 4 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 686 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16124 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1854 # Number of load instructions executed +system.cpu.iew.predictedNotTakenIncorrect 571 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 687 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16122 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1853 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3127 # number of memory reference insts executed +system.cpu.iew.exec_refs 3126 # number of memory reference insts executed system.cpu.iew.exec_branches 1623 # Number of branches executed system.cpu.iew.exec_stores 1273 # Number of stores executed -system.cpu.iew.exec_rate 0.401694 # Inst execution rate -system.cpu.iew.wb_sent 15865 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15646 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.402808 # Inst execution rate +system.cpu.iew.wb_sent 15864 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15645 # cumulative count of insts written-back system.cpu.iew.wb_producers 10128 # num instructions producing a value -system.cpu.iew.wb_consumers 15579 # num instructions consuming a value +system.cpu.iew.wb_consumers 15590 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.389786 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.650106 # average fanout of values written-back +system.cpu.iew.wb_rate 0.390890 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.649647 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10526 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10536 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20042 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.486329 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.342699 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 592 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 20044 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.486280 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.342641 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16474 82.20% 82.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16476 82.20% 82.20% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1360 6.79% 88.98% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 589 2.94% 91.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 713 3.56% 95.48% # Number of insts commited each cycle @@ -480,7 +482,7 @@ system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 20044 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -491,27 +493,62 @@ system.cpu.commit.branches 1208 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9653 # Number of committed integer instructions. system.cpu.commit.function_calls 106 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 9747 # Class of committed instruction system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 40103 # The number of ROB reads -system.cpu.rob.rob_writes 42426 # The number of ROB writes -system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18241 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 40115 # The number of ROB reads +system.cpu.rob.rob_writes 42444 # The number of ROB writes +system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18124 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 7.460967 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.460967 # CPI: Total CPI of All Threads -system.cpu.ipc 0.134031 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.134031 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 20727 # number of integer regfile reads -system.cpu.int_regfile_writes 12358 # number of integer regfile writes +system.cpu.cpi 7.439405 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.439405 # CPI: Total CPI of All Threads +system.cpu.ipc 0.134419 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.134419 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 20731 # number of integer regfile reads +system.cpu.int_regfile_writes 12356 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8004 # number of cc regfile reads -system.cpu.cc_regfile_writes 4850 # number of cc regfile writes -system.cpu.misc_regfile_reads 7135 # number of misc regfile reads +system.cpu.cc_regfile_reads 8007 # number of cc regfile reads +system.cpu.cc_regfile_writes 4854 # number of cc regfile writes +system.cpu.misc_regfile_reads 7133 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1326590099 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1330435000 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution @@ -526,61 +563,61 @@ system.cpu.toL2Bus.data_through_bus 26624 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 458250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 459500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 236250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.897576 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 130.942440 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.872263 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.875912 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.897576 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063915 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063915 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 130.942440 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063937 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063937 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 274 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4234 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4234 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits -system.cpu.icache.overall_hits::total 1609 # number of overall hits +system.cpu.icache.tags.tag_accesses 4236 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4236 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits +system.cpu.icache.overall_hits::total 1610 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses system.cpu.icache.overall_misses::total 371 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25180750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25180750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25180750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25180750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25180750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25180750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1980 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1980 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1980 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1980 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1980 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187374 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.187374 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.187374 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.187374 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.187374 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.187374 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67872.641509 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67872.641509 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67872.641509 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67872.641509 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67872.641509 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67872.641509 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25106250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25106250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25106250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25106250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25106250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25106250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187279 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.187279 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.187279 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.187279 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.187279 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.187279 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67671.832884 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67671.832884 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67671.832884 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67671.832884 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -601,39 +638,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 274 system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19745750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19745750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19745750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19745750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19745750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19745750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138384 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138384 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138384 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72064.781022 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72064.781022 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72064.781022 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72064.781022 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72064.781022 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72064.781022 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19660000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19660000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138314 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138314 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138314 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71751.824818 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71751.824818 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.708534 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 163.759335 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 337 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005935 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.966386 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32.742148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003997 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.011600 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32.747734 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003998 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004996 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010284 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3750 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3750 # Number of data accesses @@ -657,17 +694,17 @@ system.cpu.l2cache.demand_misses::total 415 # nu system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 415 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19460250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5265000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24725250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5444500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5444500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19460250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10709500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30169750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19460250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10709500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30169750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19374500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5212250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24586750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5445500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5445500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19374500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10657750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30032250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19374500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10657750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30032250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 274 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 66 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) @@ -690,17 +727,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995204 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.993007 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995204 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71282.967033 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73151.627219 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70707.792208 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70707.792208 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71282.967033 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75419.014085 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72698.192771 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71282.967033 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75419.014085 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72698.192771 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70968.864469 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80188.461538 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72741.863905 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70720.779221 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70720.779221 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72366.867470 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72366.867470 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -720,17 +757,17 @@ system.cpu.l2cache.demand_mshr_misses::total 415 system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16034750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4466500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20501250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4485000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4485000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16034750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8951500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24986250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16034750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8951500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24986250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15946000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4413250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20359250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4486000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4486000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15946000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8899250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24845250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15946000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8899250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24845250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.984848 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994118 # mshr miss rate for ReadReq accesses @@ -742,81 +779,81 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58735.347985 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68715.384615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60654.585799 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58246.753247 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58246.753247 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58735.347985 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63038.732394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60207.831325 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58735.347985 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63038.732394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60207.831325 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58410.256410 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67896.153846 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60234.467456 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58259.740260 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58259.740260 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.267922 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2337 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 83.261165 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2335 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.457746 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.443662 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.267922 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020329 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020329 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 83.261165 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020327 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020327 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5234 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5234 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5232 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5232 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2337 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2337 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2337 # number of overall hits -system.cpu.dcache.overall_hits::total 2337 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2335 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2335 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2335 # number of overall hits +system.cpu.dcache.overall_hits::total 2335 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 209 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses -system.cpu.dcache.overall_misses::total 209 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9669000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9669000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5702500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5702500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15371500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15371500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15371500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15371500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1611 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 210 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses +system.cpu.dcache.overall_misses::total 210 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9645750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9645750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5703500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5703500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15349250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15349250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15349250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15349250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1610 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1610 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2546 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2546 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2546 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2546 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081937 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081937 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2545 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2545 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2545 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2545 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082609 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.082609 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082090 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082090 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.082090 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.082090 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73250 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73250 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74058.441558 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74058.441558 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73547.846890 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73547.846890 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73547.846890 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73547.846890 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.082515 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082515 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082515 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082515 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72524.436090 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72524.436090 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74071.428571 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74071.428571 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73091.666667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73091.666667 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -825,12 +862,12 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.750000 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 67 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 66 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses @@ -839,30 +876,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5340000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5340000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5521500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5521500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10861500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10861500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10861500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10861500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040968 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040968 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5522500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5522500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10809750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10809750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10809750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10809750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040994 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040994 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.056167 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.056167 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80909.090909 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80909.090909 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71707.792208 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71707.792208 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75954.545455 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75954.545455 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75954.545455 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75954.545455 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.056189 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.056189 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80109.848485 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80109.848485 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71720.779221 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71720.779221 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 95eaee017..0a6735ef0 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57597 # Simulator instruction rate (inst/s) -host_op_rate 104318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60076981 # Simulator tick rate (ticks/s) -host_mem_usage 286548 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 478524 # Simulator instruction rate (inst/s) +host_op_rate 865796 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 498092788 # Simulator tick rate (ticks/s) +host_mem_usage 271572 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -66,5 +66,40 @@ system.cpu.num_busy_cycles 11231 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction +system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 9748 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index f68024429..be3906efe 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000122 # Nu sim_ticks 121759 # Number of ticks simulated final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 27489 # Simulator instruction rate (inst/s) -host_op_rate 49793 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 621883 # Simulator tick rate (ticks/s) -host_mem_usage 193512 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 47256 # Simulator instruction rate (inst/s) +host_op_rate 85597 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1069027 # Simulator tick rate (ticks/s) +host_mem_usage 179456 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -131,6 +131,41 @@ system.cpu.num_busy_cycles 121759 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction +system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.652970 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 35c0c845e..bc4d8d180 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28358000 # Number of ticks simulated final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50744 # Simulator instruction rate (inst/s) -host_op_rate 91910 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 267330545 # Simulator tick rate (ticks/s) -host_mem_usage 295388 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 260669 # Simulator instruction rate (inst/s) +host_op_rate 471875 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1371807276 # Simulator tick rate (ticks/s) +host_mem_usage 281320 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -74,6 +74,41 @@ system.cpu.num_busy_cycles 56716 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction +system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 9748 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks. diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 463d0c1e4..343b8a125 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24279500 # Number of ticks simulated -final_tick 24279500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 24520500 # Number of ticks simulated +final_tick 24520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38690 # Simulator instruction rate (inst/s) -host_op_rate 38688 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73697435 # Simulator tick rate (ticks/s) -host_mem_usage 279072 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host +host_inst_rate 60032 # Simulator instruction rate (inst/s) +host_op_rate 60027 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115480799 # Simulator tick rate (ticks/s) +host_mem_usage 266308 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 39872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22464 # Number of bytes read from this memory -system.physmem.bytes_read::total 62336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39872 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 623 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 351 # Number of read requests responded to by this memory -system.physmem.num_reads::total 974 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1642208447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 925224984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2567433431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1642208447 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1642208447 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1642208447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 925224984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2567433431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 974 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 40128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22656 # Number of bytes read from this memory +system.physmem.bytes_read::total 62784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40128 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 627 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 354 # Number of read requests responded to by this memory +system.physmem.num_reads::total 981 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1636508228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 923961583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2560469811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1636508228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1636508228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1636508228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 923961583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2560469811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 981 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 974 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 981 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62336 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 62784 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62336 # Total read bytes from the system interface side +system.physmem.bytesReadSys 62784 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 83 # Per bank write bursts -system.physmem.perBankRdBursts::1 153 # Per bank write bursts +system.physmem.perBankRdBursts::1 156 # Per bank write bursts system.physmem.perBankRdBursts::2 77 # Per bank write bursts -system.physmem.perBankRdBursts::3 58 # Per bank write bursts +system.physmem.perBankRdBursts::3 59 # Per bank write bursts system.physmem.perBankRdBursts::4 87 # Per bank write bursts -system.physmem.perBankRdBursts::5 48 # Per bank write bursts +system.physmem.perBankRdBursts::5 49 # Per bank write bursts system.physmem.perBankRdBursts::6 32 # Per bank write bursts -system.physmem.perBankRdBursts::7 50 # Per bank write bursts +system.physmem.perBankRdBursts::7 51 # Per bank write bursts system.physmem.perBankRdBursts::8 42 # Per bank write bursts -system.physmem.perBankRdBursts::9 39 # Per bank write bursts -system.physmem.perBankRdBursts::10 30 # Per bank write bursts +system.physmem.perBankRdBursts::9 38 # Per bank write bursts +system.physmem.perBankRdBursts::10 31 # Per bank write bursts system.physmem.perBankRdBursts::11 33 # Per bank write bursts system.physmem.perBankRdBursts::12 15 # Per bank write bursts -system.physmem.perBankRdBursts::13 121 # Per bank write bursts -system.physmem.perBankRdBursts::14 70 # Per bank write bursts +system.physmem.perBankRdBursts::13 123 # Per bank write bursts +system.physmem.perBankRdBursts::14 69 # Per bank write bursts system.physmem.perBankRdBursts::15 36 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24131500 # Total gap between requests +system.physmem.totGap 24372500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 974 # Read request sizes (log2) +system.physmem.readPktSize::6 981 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,13 +90,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -186,90 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 172 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 270.511628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.030710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 293.903144 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 69 40.12% 40.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42 24.42% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 21 12.21% 76.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 4.07% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 7 4.07% 84.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5 2.91% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7 4.07% 91.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.16% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 12 6.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 172 # Bytes accessed per row activation -system.physmem.totQLat 8865250 # Total ticks spent queuing -system.physmem.totMemAccLat 30510250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4870000 # Total ticks spent in databus transfers -system.physmem.totBankLat 16775000 # Total ticks spent accessing banks -system.physmem.avgQLat 9101.90 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 17222.79 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 218 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 281.541284 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 177.445911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 284.903946 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 77 35.32% 35.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 55 25.23% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 27 12.39% 72.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 16 7.34% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 3.21% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13 5.96% 89.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 3.21% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 1.83% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 12 5.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 218 # Bytes accessed per row activation +system.physmem.totQLat 12385000 # Total ticks spent queuing +system.physmem.totMemAccLat 30778750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4905000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12624.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31324.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2567.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31374.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2560.47 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2567.43 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2560.47 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 20.06 # Data bus utilization in percentage -system.physmem.busUtilRead 20.06 # Data bus utilization in percentage for reads +system.physmem.busUtil 20.00 # Data bus utilization in percentage +system.physmem.busUtilRead 20.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.36 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.35 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 754 # Number of row buffer hits during reads +system.physmem.readRowHits 755 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.41 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.96 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 24775.67 # Average gap between requests -system.physmem.pageHitRate 77.41 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.13 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 2567433431 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 828 # Transaction distribution -system.membus.trans_dist::ReadResp 828 # Transaction distribution +system.physmem.avgGap 24844.55 # Average gap between requests +system.physmem.pageHitRate 76.96 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem.memoryStateTime::REF 780000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 22830500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 2560469811 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 835 # Transaction distribution +system.membus.trans_dist::ReadResp 835 # Transaction distribution system.membus.trans_dist::ReadExReq 146 # Transaction distribution system.membus.trans_dist::ReadExResp 146 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1948 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62336 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 62336 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 62336 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1962 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1962 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62784 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 62784 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 62784 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1237000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1242500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9036000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9118000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 37.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 6878 # Number of BP lookups -system.cpu.branchPred.condPredicted 3868 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1521 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4939 # Number of BTB lookups -system.cpu.branchPred.BTBHits 851 # Number of BTB hits +system.cpu.branchPred.lookups 6989 # Number of BP lookups +system.cpu.branchPred.condPredicted 3925 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1533 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5035 # Number of BTB lookups +system.cpu.branchPred.BTBHits 984 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 17.230209 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 911 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 184 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 19.543198 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 915 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 192 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4650 # DTB read hits -system.cpu.dtb.read_misses 105 # DTB read misses +system.cpu.dtb.read_hits 4762 # DTB read hits +system.cpu.dtb.read_misses 100 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4755 # DTB read accesses -system.cpu.dtb.write_hits 2025 # DTB write hits -system.cpu.dtb.write_misses 86 # DTB write misses +system.cpu.dtb.read_accesses 4862 # DTB read accesses +system.cpu.dtb.write_hits 2071 # DTB write hits +system.cpu.dtb.write_misses 87 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2111 # DTB write accesses -system.cpu.dtb.data_hits 6675 # DTB hits -system.cpu.dtb.data_misses 191 # DTB misses +system.cpu.dtb.write_accesses 2158 # DTB write accesses +system.cpu.dtb.data_hits 6833 # DTB hits +system.cpu.dtb.data_misses 187 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6866 # DTB accesses -system.cpu.itb.fetch_hits 5377 # ITB hits -system.cpu.itb.fetch_misses 57 # ITB misses +system.cpu.dtb.data_accesses 7020 # DTB accesses +system.cpu.itb.fetch_hits 5544 # ITB hits +system.cpu.itb.fetch_misses 61 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5434 # ITB accesses +system.cpu.itb.fetch_accesses 5605 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -284,322 +286,322 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 48560 # number of cpu cycles simulated +system.cpu.numCycles 49042 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1593 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 37812 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6878 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1762 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 6306 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1885 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 390 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5377 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 876 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.326690 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.748404 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1654 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 38433 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6989 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1899 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 6450 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1925 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 460 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5544 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 915 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 29475 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.303919 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.725203 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22195 77.87% 77.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 545 1.91% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 361 1.27% 81.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 442 1.55% 82.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 446 1.56% 84.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 426 1.49% 85.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 467 1.64% 87.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 449 1.58% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3170 11.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23025 78.12% 78.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 583 1.98% 80.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 359 1.22% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 471 1.60% 82.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 462 1.57% 84.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 415 1.41% 85.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 502 1.70% 87.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 480 1.63% 89.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3178 10.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.141639 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.778666 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 39333 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8850 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5436 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 479 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2774 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 616 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 400 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 33055 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 811 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2774 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 40067 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5599 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1111 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5029 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2292 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 30468 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 68 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 66 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2187 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 22824 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 37480 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 37462 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 29475 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.142511 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.783675 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40916 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9080 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5548 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 476 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2800 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 645 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 409 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 33474 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 772 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2800 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 41622 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5416 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1578 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5169 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2235 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30891 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 39 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 88 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2140 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 23128 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 38063 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 38045 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13684 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6207 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2994 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1412 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 13988 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 50 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5886 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3185 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 3053 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1420 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 2 # Number of conflicting loads. +system.cpu.memDep1.insertedLoads 2945 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1353 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 17 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 26659 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 26844 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 79 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21903 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 125 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12970 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8208 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 22133 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 13088 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8205 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28501 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.768499 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.351420 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 29475 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.750908 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.340856 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19061 66.88% 66.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3422 12.01% 78.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2553 8.96% 87.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1621 5.69% 93.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1071 3.76% 97.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 496 1.74% 99.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 208 0.73% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 52 0.18% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 17 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19871 67.42% 67.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3550 12.04% 79.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2637 8.95% 88.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1555 5.28% 93.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1051 3.57% 97.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 510 1.73% 98.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 229 0.78% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 60 0.20% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 29475 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 0.63% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 93 58.86% 59.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 64 40.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7 3.80% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 112 60.87% 64.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 65 35.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7187 65.71% 65.72% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2598 23.75% 89.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1148 10.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7355 65.30% 65.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2746 24.38% 89.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1157 10.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10938 # Type of FU issued +system.cpu.iq.FU_type_0::total 11263 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7209 65.75% 65.76% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.77% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.77% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2626 23.95% 89.74% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1125 10.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7126 65.56% 65.57% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.58% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.58% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.60% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2577 23.71% 89.31% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1162 10.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10965 # Type of FU issued -system.cpu.iq.FU_type::total 21903 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.451050 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 75 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 83 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 158 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.003424 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.003789 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.007214 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 72548 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 39716 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 18903 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 10870 # Type of FU issued +system.cpu.iq.FU_type::total 22133 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.451307 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 83 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 101 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 184 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.003750 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004563 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008313 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 74007 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 40020 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19098 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22035 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22291 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 72 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 89 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1811 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 547 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2002 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 585 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 298 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 59 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 438 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1870 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 555 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1762 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 488 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 395 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 324 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2774 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2285 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 26933 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 586 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 6047 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2832 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 2800 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2321 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 27123 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 657 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 6130 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2803 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 242 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1098 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1340 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20369 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2363 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2406 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4769 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1534 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 244 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1350 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20610 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2500 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2378 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4878 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1523 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 106 # number of nop insts executed +system.cpu.iew.exec_nop::0 111 # number of nop insts executed system.cpu.iew.exec_nop::1 89 # number of nop insts executed -system.cpu.iew.exec_nop::total 195 # number of nop insts executed -system.cpu.iew.exec_refs::0 3425 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3474 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6899 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1614 # Number of branches executed -system.cpu.iew.exec_branches::1 1639 # Number of branches executed -system.cpu.iew.exec_branches::total 3253 # Number of branches executed -system.cpu.iew.exec_stores::0 1062 # Number of stores executed -system.cpu.iew.exec_stores::1 1068 # Number of stores executed -system.cpu.iew.exec_stores::total 2130 # Number of stores executed -system.cpu.iew.exec_rate 0.419460 # Inst execution rate -system.cpu.iew.wb_sent::0 9620 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9621 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19241 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9442 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9481 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 18923 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4820 # num instructions producing a value -system.cpu.iew.wb_producers::1 4844 # num instructions producing a value -system.cpu.iew.wb_producers::total 9664 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6291 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6358 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12649 # num instructions consuming a value +system.cpu.iew.exec_nop::total 200 # number of nop insts executed +system.cpu.iew.exec_refs::0 3609 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3448 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 7057 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1643 # Number of branches executed +system.cpu.iew.exec_branches::1 1628 # Number of branches executed +system.cpu.iew.exec_branches::total 3271 # Number of branches executed +system.cpu.iew.exec_stores::0 1109 # Number of stores executed +system.cpu.iew.exec_stores::1 1070 # Number of stores executed +system.cpu.iew.exec_stores::total 2179 # Number of stores executed +system.cpu.iew.exec_rate 0.420252 # Inst execution rate +system.cpu.iew.wb_sent::0 9814 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9602 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19416 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9666 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9452 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19118 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4886 # num instructions producing a value +system.cpu.iew.wb_producers::1 4825 # num instructions producing a value +system.cpu.iew.wb_producers::total 9711 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6421 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6315 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12736 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.194440 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.195243 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.389683 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.766174 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.761875 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.764013 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.197096 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.192733 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.389829 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.760941 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.764054 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.762484 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 14135 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 14324 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1145 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 28452 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.449142 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.218832 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1153 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29419 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.434379 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.208273 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22772 80.04% 80.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2961 10.41% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1118 3.93% 94.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 506 1.78% 96.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 376 1.32% 97.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 249 0.88% 98.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 186 0.65% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.26% 99.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 211 0.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23668 80.45% 80.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3132 10.65% 91.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1070 3.64% 94.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 465 1.58% 96.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 341 1.16% 97.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 243 0.83% 98.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 188 0.64% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 91 0.31% 99.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 221 0.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 28452 # Number of insts commited each cycle -system.cpu.commit.committedInsts::0 6390 # Number of instructions committed -system.cpu.commit.committedInsts::1 6389 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 29419 # Number of insts commited each cycle +system.cpu.commit.committedInsts::0 6389 # Number of instructions committed +system.cpu.commit.committedInsts::1 6390 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed -system.cpu.commit.committedOps::0 6390 # Number of ops (including micro ops) committed -system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::1 6390 # Number of ops (including micro ops) committed system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed @@ -625,222 +627,293 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 211 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 6389 # Class of committed instruction +system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction +system.cpu.commit.op_class_1::IntAlu 4320 67.61% 67.90% # Class of committed instruction +system.cpu.commit.op_class_1::IntMult 1 0.02% 67.92% # Class of committed instruction +system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.92% # Class of committed instruction +system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::MemRead 1183 18.51% 86.46% # Class of committed instruction +system.cpu.commit.op_class_1::MemWrite 865 13.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_1::total 6390 # Class of committed instruction +system.cpu.commit.op_class::total 12779 0.00% 0.00% # Class of committed instruction +system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 131641 # The number of ROB reads -system.cpu.rob.rob_writes 56622 # The number of ROB writes -system.cpu.timesIdled 379 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20059 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts::0 6373 # Number of Instructions Simulated -system.cpu.committedInsts::1 6372 # Number of Instructions Simulated -system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated -system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated +system.cpu.rob.rob_reads 133441 # The number of ROB reads +system.cpu.rob.rob_writes 57026 # The number of ROB writes +system.cpu.timesIdled 384 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19567 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts::0 6372 # Number of Instructions Simulated +system.cpu.committedInsts::1 6373 # Number of Instructions Simulated +system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 7.619645 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.620841 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.810122 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.131240 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.131219 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.262459 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25548 # number of integer regfile reads -system.cpu.int_regfile_writes 14297 # number of integer regfile writes +system.cpu.cpi::0 7.696485 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.695277 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.847940 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.129929 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.129950 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.259879 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25834 # number of integer regfile reads +system.cpu.int_regfile_writes 14427 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.toL2Bus.throughput 2572705369 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 830 # Transaction distribution +system.cpu.toL2Bus.throughput 2565689933 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 837 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 837 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1250 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1952 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 62464 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1258 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 708 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1966 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 62912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 62912 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 491500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1024500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1033500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 562000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 567500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.cpu.icache.tags.replacements::0 6 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 6 # number of replacements -system.cpu.icache.tags.tagsinuse 311.393112 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4352 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 625 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.963200 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 315.418856 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4518 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 629 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.182830 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 311.393112 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.152047 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.152047 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 619 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.302246 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11367 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11367 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4352 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4352 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4352 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4352 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4352 # number of overall hits -system.cpu.icache.overall_hits::total 4352 # number of overall hits +system.cpu.icache.tags.occ_blocks::cpu.inst 315.418856 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.154013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.154013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 623 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.304199 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11703 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11703 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4518 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4518 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4518 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4518 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4518 # number of overall hits +system.cpu.icache.overall_hits::total 4518 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1019 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1019 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1019 # number of overall misses system.cpu.icache.overall_misses::total 1019 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 67780746 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 67780746 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 67780746 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 67780746 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 67780746 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 67780746 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.189723 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.189723 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.189723 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.189723 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.189723 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.189723 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66516.924436 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66516.924436 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66516.924436 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66516.924436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66516.924436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66516.924436 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2455 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 68389495 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 68389495 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 68389495 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 68389495 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 68389495 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 68389495 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5537 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5537 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5537 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5537 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5537 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5537 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184035 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.184035 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.184035 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.184035 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.184035 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.184035 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67114.322866 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67114.322866 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67114.322866 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67114.322866 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67114.322866 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67114.322866 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2439 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 61 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.245902 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42.051724 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 394 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 394 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 394 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 394 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 394 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 394 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 625 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 625 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 625 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46793246 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46793246 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46793246 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46793246 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46793246 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46793246 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116366 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116366 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116366 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116366 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116366 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116366 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74869.193600 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74869.193600 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74869.193600 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74869.193600 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74869.193600 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74869.193600 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 390 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 390 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 390 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 390 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 390 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 390 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 629 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 629 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 629 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 629 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 629 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 629 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46962248 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46962248 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46962248 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46962248 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46962248 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46962248 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113599 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113599 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113599 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.113599 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113599 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.113599 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74661.761526 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74661.761526 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74661.761526 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74661.761526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74661.761526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74661.761526 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements system.cpu.l2cache.tags.replacements::total 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 432.103746 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 437.810879 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 828 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002415 # 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Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025269 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 8782 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 8782 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::cpu.inst 315.920365 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 121.890513 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009641 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003720 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.013361 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 835 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 328 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 507 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025482 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 8845 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 8845 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 623 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 205 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 828 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 627 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 208 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 835 # 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miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997611 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996800 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996820 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996800 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997965 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996820 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74068.218299 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78821.951220 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75245.169082 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82171.232877 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82171.232877 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74068.218299 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80215.099715 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76283.367556 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74068.218299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80215.099715 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76283.367556 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997965 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73859.649123 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81989.182692 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75884.730539 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78717.465753 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78717.465753 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73859.649123 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80639.830508 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76306.320082 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73859.649123 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80639.830508 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76306.320082 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -849,164 +922,164 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 623 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 828 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 208 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 835 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 623 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 974 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 623 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 974 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38385500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13633000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52018500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10201000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10201000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38385500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23834000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 62219500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38385500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23834000 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9689750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9689750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38486500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24182500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 62669000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38486500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24182500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 62669000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996820 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997611 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996820 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997965 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996820 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61613.964687 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66502.439024 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62824.275362 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69869.863014 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69869.863014 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61613.964687 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67903.133903 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63880.390144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61613.964687 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67903.133903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63880.390144 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997965 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61381.977671 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69676.682692 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63448.203593 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66368.150685 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66368.150685 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61381.977671 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68312.146893 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63882.772681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61381.977671 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68312.146893 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63882.772681 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 213.465522 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4559 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.988604 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 215.425119 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4587 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 354 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.957627 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 213.465522 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052116 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052116 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 215.425119 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052594 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052594 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 11545 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 11545 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 3545 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3545 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1014 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1014 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4559 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4559 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4559 # number of overall hits -system.cpu.dcache.overall_hits::total 4559 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 322 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 322 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 716 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 716 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1038 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1038 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1038 # number of overall misses -system.cpu.dcache.overall_misses::total 1038 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22755500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22755500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 51611211 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 51611211 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 74366711 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 74366711 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 74366711 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 74366711 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3867 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3867 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.086426 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 11596 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 11596 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 3561 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3561 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1026 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1026 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4587 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4587 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4587 # number of overall hits +system.cpu.dcache.overall_hits::total 4587 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 330 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 330 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 704 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 704 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1034 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1034 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1034 # number of overall misses +system.cpu.dcache.overall_misses::total 1034 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24450500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24450500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 50450459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 50450459 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 74900959 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 74900959 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 74900959 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 74900959 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3891 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3891 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5597 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5597 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5597 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5597 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083269 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.083269 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.413873 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.413873 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.185456 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.185456 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.185456 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.185456 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70669.254658 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70669.254658 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72082.696927 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72082.696927 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71644.230250 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71644.230250 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71644.230250 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71644.230250 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4526 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5621 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5621 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5621 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5621 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084811 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.084811 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.406936 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.406936 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.183953 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.183953 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.183953 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.183953 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74092.424242 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74092.424242 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71662.583807 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71662.583807 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72438.064797 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72438.064797 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72438.064797 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72438.064797 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4010 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 103 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 101 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.941748 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.702970 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 117 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 117 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 570 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 570 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 687 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 687 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 687 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 687 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 122 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 122 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 558 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 558 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 208 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 208 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16372000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16372000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12145496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12145496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28517496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28517496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28517496 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28517496 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053013 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053013 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 354 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 354 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 354 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 354 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17272750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17272750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11640746 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11640746 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28913496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28913496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28913496 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28913496 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053457 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053457 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062712 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062712 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062712 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062712 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79863.414634 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79863.414634 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83188.328767 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83188.328767 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81246.427350 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81246.427350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81246.427350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81246.427350 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062978 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062978 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062978 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062978 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83042.067308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83042.067308 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79731.136986 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79731.136986 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81676.542373 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81676.542373 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81676.542373 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81676.542373 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 260a10b90..2ad955d95 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27725000 # Number of ticks simulated -final_tick 27725000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27662000 # Number of ticks simulated +final_tick 27662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72342 # Simulator instruction rate (inst/s) -host_op_rate 72337 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132265036 # Simulator tick rate (ticks/s) -host_mem_usage 269700 # Number of bytes of host memory used +host_inst_rate 71683 # Simulator instruction rate (inst/s) +host_op_rate 71677 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 130761776 # Simulator tick rate (ticks/s) +host_mem_usage 270740 # Number of bytes of host memory used host_seconds 0.21 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19008 # Nu system.physmem.num_reads::cpu.inst 297 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 435 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 685590622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 318557259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1004147881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 685590622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 685590622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 685590622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 318557259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1004147881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 687152050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 319282771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1006434820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 687152050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 687152050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 687152050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 319282771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1006434820 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 436 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 27691500 # Total gap between requests +system.physmem.totGap 27628500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,44 +186,47 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 487.111111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 330.231493 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 390.430808 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3 8.33% 8.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9 25.00% 33.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 22.22% 55.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 5.56% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 5.56% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 2.78% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 30.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 2136500 # Total ticks spent queuing -system.physmem.totMemAccLat 10682750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 66 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 390.787879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 254.304435 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.314954 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 18.18% 18.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 28.79% 46.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10 15.15% 62.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 6.06% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 6.06% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.55% 78.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.55% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 11 16.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation +system.physmem.totQLat 2526750 # Total ticks spent queuing +system.physmem.totMemAccLat 10701750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2180000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6366250 # Total ticks spent accessing banks -system.physmem.avgQLat 4900.23 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14601.49 # Average bank access latency per DRAM burst +system.physmem.avgQLat 5795.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24501.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1006.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24545.30 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1008.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1006.46 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1008.75 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.86 # Data bus utilization in percentage -system.physmem.busUtilRead 7.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.88 # Data bus utilization in percentage +system.physmem.busUtilRead 7.88 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 362 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.03 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 63512.61 # Average gap between requests +system.physmem.avgGap 63368.12 # Average gap between requests system.physmem.pageHitRate 83.03 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.51 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1004147881 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 1258750 # Time in different power states +system.physmem.memoryStateTime::REF 780000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 21617500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1006434820 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution @@ -236,7 +239,7 @@ system.membus.data_through_bus 27840 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 519500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4047500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4048500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 14.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 5146 # Number of BP lookups @@ -249,7 +252,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 55451 # number of cpu cycles simulated +system.cpu.numCycles 55325 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). @@ -271,12 +274,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21862 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21861 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 439 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 37883 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 438 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 37757 # Number of cycles cpu's stages were not processed system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. -system.cpu.activity 31.682026 # Percentage of cycles cpu is active +system.cpu.activity 31.754180 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -288,36 +291,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.657235 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.648925 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.657235 # CPI: Total CPI of All Threads -system.cpu.ipc 0.273431 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.648925 # CPI: Total CPI of All Threads +system.cpu.ipc 0.274053 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.273431 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 42025 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.274053 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 41899 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 24.212368 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46098 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 24.267510 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 45972 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 16.867144 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46648 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 16.905558 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46522 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 15.875277 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 52573 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 15.911432 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 52447 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.190168 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46142 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 5.201988 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46016 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 16.787795 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 16.826028 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.846335 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 168.857752 # Cycle average of tags in use system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.846335 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082444 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082444 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 168.857752 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082450 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082450 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 299 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id @@ -336,12 +339,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25942000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25942000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25942000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25942000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25942000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25942000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25881500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25881500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25881500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25881500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25881500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25881500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -354,12 +357,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68089.238845 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68089.238845 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68089.238845 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68089.238845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68089.238845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68089.238845 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67930.446194 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67930.446194 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67930.446194 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67930.446194 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67930.446194 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67930.446194 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,26 +383,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20512000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20512000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20512000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20512000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20512000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20512000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20450500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20450500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20450500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20450500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20450500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20450500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68146.179402 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68146.179402 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68146.179402 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68146.179402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68146.179402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68146.179402 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67941.860465 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67941.860465 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67941.860465 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67941.860465 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67941.860465 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67941.860465 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1008764653 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1011062107 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -414,24 +417,24 @@ system.cpu.toL2Bus.data_through_bus 27968 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 499500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 500000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 221500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 222000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.869816 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.884332 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.179067 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.690749 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005132 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.191422 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.692910 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005133 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000967 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006100 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3947 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3947 # Number of data accesses @@ -452,17 +455,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20188500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3701000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23889500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6006500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6006500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20188500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9707500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29896000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20188500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9707500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29896000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20127000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3695250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 23822250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6008750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6008750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20127000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9704000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29831000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20127000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9704000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29831000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -485,17 +488,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67520.066890 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69830.188679 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67867.897727 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70664.705882 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70664.705882 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67520.066890 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70344.202899 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68411.899314 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67520.066890 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70344.202899 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68411.899314 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67314.381271 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69721.698113 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67676.846591 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70691.176471 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70691.176471 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67314.381271 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70318.840580 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68263.157895 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67314.381271 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70318.840580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68263.157895 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -515,17 +518,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16473000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3042500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19515500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4962500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4962500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16473000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8005000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24478000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16473000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8005000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24478000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16410500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3036250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19446750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4964250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4964250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16410500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8000500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24411000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16410500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8000500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24411000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -537,27 +540,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55093.645485 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57405.660377 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55441.761364 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58382.352941 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58382.352941 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55093.645485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58007.246377 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56013.729977 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55093.645485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58007.246377 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56013.729977 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54884.615385 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57287.735849 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55246.448864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58402.941176 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58402.941176 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54884.615385 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57974.637681 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55860.411899 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54884.615385 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57974.637681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55860.411899 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.543212 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 98.520897 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.543212 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024058 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024058 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.520897 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024053 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024053 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id @@ -582,14 +585,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4273500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4273500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25910250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25910250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30183750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30183750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30183750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30183750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4268250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4268250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25916250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25916250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30184500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30184500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30184500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30184500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -608,19 +611,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73681.034483 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73681.034483 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61398.696682 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61398.696682 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62882.812500 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62882.812500 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62882.812500 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62882.812500 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1097 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73590.517241 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73590.517241 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61412.914692 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61412.914692 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62884.375000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62884.375000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62884.375000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62884.375000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1102 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.242424 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.393939 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -640,14 +643,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3755500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3755500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6094500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6094500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9850000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9850000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9850000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9850000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3749750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3749750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6096750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6096750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9846500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9846500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9846500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9846500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -656,14 +659,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70858.490566 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70858.490566 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71700 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71700 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71376.811594 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71376.811594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71376.811594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71376.811594 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70750 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71726.470588 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71726.470588 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71351.449275 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71351.449275 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71351.449275 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71351.449275 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 48a264b11..a29a98d10 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 26743500 # Number of ticks simulated -final_tick 26743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 26706500 # Number of ticks simulated +final_tick 26706500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53060 # Simulator instruction rate (inst/s) -host_op_rate 53057 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 98286640 # Simulator tick rate (ticks/s) -host_mem_usage 272776 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 64712 # Simulator instruction rate (inst/s) +host_op_rate 64708 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119701044 # Simulator tick rate (ticks/s) +host_mem_usage 272800 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 482 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 801690130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 351786415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1153476546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 801690130 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 801690130 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 801690130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 351786415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1153476546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 802800816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 352273791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1155074607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 802800816 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 802800816 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 802800816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 352273791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1155074607 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 482 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26582500 # Total gap between requests +system.physmem.totGap 26545500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -186,34 +186,33 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 298.774659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 377.002918 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5 12.20% 12.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12 29.27% 41.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 17.07% 58.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 4.88% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 4.88% 68.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 2.44% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 4.88% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 24.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation -system.physmem.totQLat 2269000 # Total ticks spent queuing -system.physmem.totMemAccLat 11609000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 403.200000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 265.551535 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.027861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22 31.43% 48.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 12.86% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 4.29% 65.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 5.71% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.29% 75.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 8.57% 84.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.43% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 14.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation +system.physmem.totQLat 2602000 # Total ticks spent queuing +system.physmem.totMemAccLat 11639500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6930000 # Total ticks spent accessing banks -system.physmem.avgQLat 4707.47 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14377.59 # Average bank access latency per DRAM burst +system.physmem.avgQLat 5398.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24085.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1153.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24148.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1155.07 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1153.48 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1155.07 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.01 # Data bus utilization in percentage -system.physmem.busUtilRead 9.01 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.02 # Data bus utilization in percentage +system.physmem.busUtilRead 9.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.51 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -221,10 +220,14 @@ system.physmem.readRowHits 403 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 55150.41 # Average gap between requests +system.physmem.avgGap 55073.65 # Average gap between requests system.physmem.pageHitRate 83.61 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 5.72 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1153476546 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 1553250 # Time in different power states +system.physmem.memoryStateTime::REF 780000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 21299250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1155074607 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution @@ -235,105 +238,105 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 606500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 4495000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4499500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 16.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 6710 # Number of BP lookups -system.cpu.branchPred.condPredicted 4453 # Number of conditional branches predicted +system.cpu.branchPred.lookups 6716 # Number of BP lookups +system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5017 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups system.cpu.branchPred.BTBHits 2432 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.475184 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 53488 # number of cpu cycles simulated +system.cpu.numCycles 53414 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12425 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31097 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6710 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 12411 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31121 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9129 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3043 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 9229 # Number of cycles fetch has spent blocked +system.cpu.fetch.Cycles 9132 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 9191 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5378 # Number of cache lines fetched +system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 33579 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.926085 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.119056 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 33531 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.928126 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.121319 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24450 72.81% 72.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4510 13.43% 86.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 474 1.41% 87.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 392 1.17% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 680 2.03% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 706 2.10% 92.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 235 0.70% 93.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 253 0.75% 94.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1879 5.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24399 72.77% 72.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4510 13.45% 86.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 474 1.41% 87.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 392 1.17% 88.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 680 2.03% 90.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 706 2.11% 92.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.70% 93.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 253 0.75% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1882 5.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 33579 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.125449 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.581383 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12934 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 10235 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8342 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1871 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 28992 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1871 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13577 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 435 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9274 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7946 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 476 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 26641 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 33531 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.125735 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.582638 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12927 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 10191 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8340 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 201 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13569 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 456 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9204 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7948 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 482 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 148 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 23939 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 49429 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 40899 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 152 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 40918 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10120 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 10132 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 691 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2745 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3528 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2282 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2747 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3529 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2285 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22511 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 22517 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21117 # Number of instructions issued +system.cpu.iq.iqInstsIssued 21121 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7892 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5484 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 7903 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 33579 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.628875 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.255627 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 33531 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.629895 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.256216 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24339 72.48% 72.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3553 10.58% 83.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2322 6.92% 89.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1704 5.07% 95.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 887 2.64% 97.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 469 1.40% 99.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 240 0.71% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24281 72.41% 72.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3570 10.65% 83.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2315 6.90% 89.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1704 5.08% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 886 2.64% 97.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 470 1.40% 99.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 240 0.72% 99.81% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.13% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 33579 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 33531 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available @@ -369,7 +372,7 @@ system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 15648 74.10% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15650 74.10% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued @@ -398,40 +401,40 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2107 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2109 9.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21117 # Type of FU issued -system.cpu.iq.rate 0.394799 # Inst issue rate +system.cpu.iq.FU_type_0::total 21121 # Type of FU issued +system.cpu.iq.rate 0.395421 # Inst issue rate system.cpu.iq.fu_busy_cnt 147 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006961 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 76057 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31084 # Number of integer instruction queue writes +system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 76017 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31101 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21264 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21268 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1303 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1304 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 834 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 837 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1871 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 286 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24299 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 399 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3528 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2282 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 1872 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 300 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24306 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 403 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2285 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -441,32 +444,32 @@ system.cpu.iew.predictedNotTakenIncorrect 946 # N system.cpu.iew.branchMispredicts 1210 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1043 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1047 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1133 # number of nop insts executed +system.cpu.iew.exec_nop 1134 # number of nop insts executed system.cpu.iew.exec_refs 5224 # number of memory reference insts executed system.cpu.iew.exec_branches 4239 # Number of branches executed system.cpu.iew.exec_stores 2022 # Number of stores executed -system.cpu.iew.exec_rate 0.375299 # Inst execution rate +system.cpu.iew.exec_rate 0.375819 # Inst execution rate system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit system.cpu.iew.wb_count 19522 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9122 # num instructions producing a value -system.cpu.iew.wb_consumers 11233 # num instructions consuming a value +system.cpu.iew.wb_producers 9116 # num instructions producing a value +system.cpu.iew.wb_consumers 11226 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.364979 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.812072 # average fanout of values written-back +system.cpu.iew.wb_rate 0.365485 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.812043 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9039 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9046 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 31708 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.478176 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.176132 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 31659 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.478916 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.176623 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 24394 76.93% 76.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4067 12.83% 89.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1357 4.28% 94.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 765 2.41% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 24337 76.87% 76.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4081 12.89% 89.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1353 4.27% 94.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 763 2.41% 96.45% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 348 1.10% 97.55% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 270 0.85% 98.40% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 322 1.02% 99.42% # Number of insts commited each cycle @@ -475,7 +478,7 @@ system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 31708 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 31659 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -486,24 +489,59 @@ system.cpu.commit.branches 3358 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12174 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 15162 # Class of committed instruction system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54969 # The number of ROB reads -system.cpu.rob.rob_writes 50281 # The number of ROB writes +system.cpu.rob.rob_reads 54927 # The number of ROB reads +system.cpu.rob.rob_writes 50296 # The number of ROB writes system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19909 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19883 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.705181 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.705181 # CPI: Total CPI of All Threads -system.cpu.ipc 0.269892 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.269892 # IPC: Total IPC of All Threads +system.cpu.cpi 3.700055 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.700055 # CPI: Total CPI of All Threads +system.cpu.ipc 0.270266 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.270266 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 32043 # number of integer regfile reads system.cpu.int_regfile_writes 17841 # number of integer regfile writes system.cpu.misc_regfile_reads 6919 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1158262755 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1159867448 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution @@ -518,61 +556,61 @@ system.cpu.toL2Bus.data_through_bus 30976 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 562250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 564000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 233750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 235000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 187.339200 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4870 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 187.422918 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.451039 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 187.339200 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.091474 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.091474 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 187.422918 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.091515 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.091515 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.164551 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11093 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11093 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4870 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4870 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4870 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4870 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4870 # number of overall hits -system.cpu.icache.overall_hits::total 4870 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 508 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 508 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 508 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 508 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 508 # number of overall misses -system.cpu.icache.overall_misses::total 508 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31654500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31654500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31654500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31654500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31654500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31654500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5378 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5378 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5378 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5378 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5378 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5378 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094459 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094459 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094459 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094459 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094459 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094459 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62312.007874 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62312.007874 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62312.007874 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62312.007874 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62312.007874 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62312.007874 # average overall miss latency +system.cpu.icache.tags.tag_accesses 11095 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11095 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits +system.cpu.icache.overall_hits::total 4872 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses +system.cpu.icache.overall_misses::total 507 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31638750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31638750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31638750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31638750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31638750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31638750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62403.846154 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62403.846154 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62403.846154 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62403.846154 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62403.846154 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62403.846154 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -581,48 +619,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 171 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 171 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 171 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 171 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 171 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 171 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 170 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 170 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 170 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 170 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 170 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 170 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22543250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22543250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22543250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22543250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22543250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22543250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062663 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062663 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062663 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.062663 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062663 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.062663 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66893.916914 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66893.916914 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66893.916914 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66893.916914 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66893.916914 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66893.916914 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22516000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22516000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66813.056380 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66813.056380 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66813.056380 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66813.056380 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66813.056380 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66813.056380 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.171170 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.271055 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.732473 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.438696 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005699 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001051 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.815406 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.455649 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005701 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006753 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id @@ -646,17 +684,17 @@ system.cpu.l2cache.demand_misses::total 482 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses system.cpu.l2cache.overall_misses::total 482 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22186250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4642250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26828500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6101000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6101000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22186250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10743250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32929500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22186250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10743250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32929500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22159000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4637250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 26796250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6037250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6037250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22159000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10674500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32833500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22159000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10674500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32833500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) @@ -679,17 +717,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995868 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66227.611940 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72535.156250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67239.348371 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73506.024096 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73506.024096 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66227.611940 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73083.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68318.464730 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66227.611940 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73083.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68318.464730 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66146.268657 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72457.031250 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67158.521303 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72737.951807 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72737.951807 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66146.268657 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72615.646259 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68119.294606 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66146.268657 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72615.646259 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68119.294606 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -709,17 +747,17 @@ system.cpu.l2cache.demand_mshr_misses::total 482 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17979250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3856250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21835500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5083000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5083000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17979250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8939250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26918500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17979250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8939250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26918500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17946500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3851750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21798250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5016750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5016750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17946500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8868500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26815000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17946500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8868500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26815000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses @@ -731,27 +769,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53669.402985 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60253.906250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54725.563910 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61240.963855 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61240.963855 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53669.402985 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60811.224490 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55847.510373 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53669.402985 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60811.224490 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55847.510373 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53571.641791 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60183.593750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54632.205514 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60442.771084 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60442.771084 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53571.641791 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60329.931973 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55632.780083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53571.641791 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60329.931973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55632.780083 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 99.038544 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 99.054052 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 99.038544 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024179 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024179 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 99.054052 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024183 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024183 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id @@ -776,14 +814,14 @@ system.cpu.dcache.demand_misses::cpu.data 535 # n system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses system.cpu.dcache.overall_misses::total 535 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7972250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7972250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25777976 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25777976 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33750226 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33750226 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33750226 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33750226 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7967250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7967250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25697977 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25697977 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33665227 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33665227 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33665227 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33665227 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -802,19 +840,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63271.825397 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63271.825397 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63026.836186 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63026.836186 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63084.534579 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63084.534579 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63084.534579 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63084.534579 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63232.142857 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63232.142857 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62831.239609 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62831.239609 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62925.657944 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62925.657944 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62925.657944 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62925.657944 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 776 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 25 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.461538 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.040000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -834,14 +872,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4706750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4706750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6185000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6185000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10891750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10891750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10891750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10891750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4701750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4701750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6121250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6121250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10823000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10823000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10823000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10823000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses @@ -850,14 +888,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73542.968750 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73542.968750 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74518.072289 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74518.072289 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74093.537415 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74093.537415 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74093.537415 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74093.537415 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73464.843750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73464.843750 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73750 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73625.850340 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73625.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73625.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73625.850340 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index fd07afc4b..33f452573 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000008 # Nu sim_ticks 7612000 # Number of ticks simulated final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30038 # Simulator instruction rate (inst/s) -host_op_rate 30037 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15079139 # Simulator tick rate (ticks/s) -host_mem_usage 275464 # Number of bytes of host memory used -host_seconds 0.51 # Real time elapsed on the host +host_inst_rate 945144 # Simulator instruction rate (inst/s) +host_op_rate 944261 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 473677660 # Simulator tick rate (ticks/s) +host_mem_usage 260980 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -65,5 +65,40 @@ system.cpu.num_busy_cycles 15225 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 3363 # Number of branches fetched +system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction +system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction +system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 15207 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 2ac6dbc74..853f97527 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu sim_ticks 41368000 # Number of ticks simulated final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29571 # Simulator instruction rate (inst/s) -host_op_rate 29570 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 80676332 # Simulator tick rate (ticks/s) -host_mem_usage 284172 # Number of bytes of host memory used -host_seconds 0.51 # Real time elapsed on the host +host_inst_rate 324057 # Simulator instruction rate (inst/s) +host_op_rate 323947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 883591781 # Simulator tick rate (ticks/s) +host_mem_usage 269720 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -69,6 +69,41 @@ system.cpu.num_busy_cycles 82736 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 3363 # Number of branches fetched +system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction +system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction +system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 15207 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 7012b3f19..8ec8c1281 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000111 # Number of seconds simulated -sim_ticks 110955500 # Number of ticks simulated -final_tick 110955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 110872500 # Number of ticks simulated +final_tick 110872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120250 # Simulator instruction rate (inst/s) -host_op_rate 120250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12800201 # Simulator tick rate (ticks/s) -host_mem_usage 288992 # Number of bytes of host memory used -host_seconds 8.67 # Real time elapsed on the host -sim_insts 1042358 # Number of instructions simulated -sim_ops 1042358 # Number of ops (including micro ops) simulated +host_inst_rate 118027 # Simulator instruction rate (inst/s) +host_op_rate 118027 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12557410 # Simulator tick rate (ticks/s) +host_mem_usage 289008 # Number of bytes of host memory used +host_seconds 8.83 # Real time elapsed on the host +sim_insts 1042088 # Number of instructions simulated +sim_ops 1042088 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory @@ -36,29 +36,29 @@ system.physmem.num_reads::cpu2.data 20 # Nu system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 659 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 205343584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 96903714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 5768078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7498502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 41530163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 11536156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 4037655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7498502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380116353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205343584 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 5768078 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 41530163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 4037655 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 256679480 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205343584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 96903714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 5768078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7498502 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 41530163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 11536156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 4037655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7498502 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 380116353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 205497305 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 96976257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 5772396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7504115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 41561253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 11544792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 4040677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7504115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 380400911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205497305 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 5772396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 41561253 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 4040677 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 256871632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205497305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 96976257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 5772396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7504115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 41561253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 11544792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 4040677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7504115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 380400911 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 660 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue @@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 110927500 # Total gap between requests +system.physmem.totGap 110844500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -120,8 +120,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see @@ -216,35 +216,33 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 285.483146 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.878201 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 280.642368 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28 31.46% 31.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 26 29.21% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 14.61% 75.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 5 5.62% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 5.62% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.37% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.25% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.12% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 6.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation -system.physmem.totQLat 3793500 # Total ticks spent queuing -system.physmem.totMemAccLat 17983500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 275.027027 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 186.656156 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 254.302887 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45 30.41% 30.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43 29.05% 59.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 21 14.19% 73.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 8.11% 81.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 10 6.76% 88.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5 3.38% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 3.38% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.68% 95.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 4.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation +system.physmem.totQLat 5597750 # Total ticks spent queuing +system.physmem.totMemAccLat 17972750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers -system.physmem.totBankLat 10890000 # Total ticks spent accessing banks -system.physmem.avgQLat 5747.73 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16500.00 # Average bank access latency per DRAM burst +system.physmem.avgQLat 8481.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27247.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.69 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27231.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.98 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 380.69 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 380.98 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.97 # Data bus utilization in percentage -system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.98 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -252,10 +250,14 @@ system.physmem.readRowHits 505 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 168071.97 # Average gap between requests +system.physmem.avgGap 167946.21 # Average gap between requests system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 9.12 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 380116353 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 48028250 # Time in different power states +system.physmem.memoryStateTime::REF 3640000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 57613000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 380400911 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 529 # Transaction distribution system.membus.trans_dist::ReadResp 528 # Transaction distribution system.membus.trans_dist::UpgradeReq 287 # Transaction distribution @@ -268,26 +270,26 @@ system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 925000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 925500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 6291924 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 6302174 # Layer occupancy (ticks) system.membus.respLayer1.utilization 5.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 417.123879 # Cycle average of tags in use +system.l2c.tags.tagsinuse 417.213115 # Cycle average of tags in use system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.799384 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 285.051208 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.412458 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 7.037952 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.694517 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 55.368542 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.407900 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 3.619836 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.732082 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.799585 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 285.091922 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.421534 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 7.040102 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.695019 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 55.399606 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5.410902 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 3.621924 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.732522 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy @@ -297,11 +299,11 @@ system.l2c.tags.occ_percent::cpu2.inst 0.000845 # Av system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.000055 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006365 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006366 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 526 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 179 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.008026 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 18244 # Number of tag accesses system.l2c.tags.data_accesses 18244 # Number of data accesses @@ -373,38 +375,38 @@ system.l2c.overall_misses::cpu2.data 20 # nu system.l2c.overall_misses::cpu3.inst 10 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 674 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 24538000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 5612000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 1134000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 24533250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 5569000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 1122250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 5318500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 5286500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 495250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.inst 658250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 37905000 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6786000 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::total 37813500 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6780000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 852250 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2.data 1087000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 978750 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9704000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 24538000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 12398000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1134000 # number of demand (read+write) miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 943000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9662250 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 24533250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 12349000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 1122250 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 926750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 5318500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 5286500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.data 1582250 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.inst 658250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 1053250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 47609000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 24538000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 12398000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1134000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu3.data 1017500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 47475750 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 24533250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 12349000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 1122250 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 926750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 5318500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 5286500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.data 1582250 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.inst 658250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 1053250 # number of overall miss cycles -system.l2c.overall_miss_latency::total 47609000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1017500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 47475750 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) @@ -481,38 +483,38 @@ system.l2c.overall_miss_rate::cpu2.data 0.800000 # mi system.l2c.overall_miss_rate::cpu3.inst 0.023256 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68350.974930 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 75837.837838 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75600 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68337.743733 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 75256.756757 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74816.666667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69980.263158 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69559.210526 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 70750 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.inst 65825 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 69806.629834 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 72191.489362 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 69638.121547 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 72127.659574 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 81562.500000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 74076.335878 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 68350.974930 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 73797.619048 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75600 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 78583.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 73757.633588 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 68337.743733 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 73505.952381 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 74816.666667 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 69980.263158 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 69559.210526 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.inst 65825 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 81019.230769 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 70636.498516 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 68350.974930 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 73797.619048 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75600 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 78269.230769 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 70438.798220 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 68337.743733 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 73505.952381 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 74816.666667 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 69980.263158 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 69559.210526 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.inst 65825 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 81019.230769 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 70636.498516 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 78269.230769 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 70438.798220 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,43 +575,43 @@ system.l2c.overall_mshr_misses::cpu2.data 20 # n system.l2c.overall_mshr_misses::cpu3.inst 7 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19975750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4701500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 711000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19962500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4657000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 698750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4193250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4160750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.data 408750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 431250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 30546500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 30444000 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 199518 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 160016 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 779576 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5616500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5606500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 701750 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 928000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 828750 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8075000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 19975750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 10318000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 711000 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 792500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8028750 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 19962500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 10263500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 698750 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 764250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 4193250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 4160750 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.data 1336750 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.inst 431250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 891250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 38621500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 19975750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 10318000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 711000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 855000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 38472750 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 19962500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 10263500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 698750 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 764250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 4193250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 4160750 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.data 1336750 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.inst 431250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 891250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 38621500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 855000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 38472750 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses @@ -647,45 +649,45 @@ system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.016279 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55954.481793 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63533.783784 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71100 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62932.432432 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69875 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58239.583333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 57743.856333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 57550.094518 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10500.947368 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10124.363636 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59750 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59643.617021 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 69062.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61641.221374 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55954.481793 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61416.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71100 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 66041.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61288.167939 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58239.583333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 68557.692308 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58517.424242 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55954.481793 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61416.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71100 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58239.583333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 68557.692308 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58517.424242 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.throughput 1688893295 # Throughput (bytes/s) +system.toL2Bus.throughput 1690157613 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution @@ -713,153 +715,153 @@ system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 135488 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 51904 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1624976 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.occupancy 1624477 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2704748 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2708498 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1464514 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1467012 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1928496 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1928746 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) system.toL2Bus.respLayer3.occupancy 1148249 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) system.toL2Bus.respLayer4.occupancy 1927493 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1209236 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 1209237 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) system.toL2Bus.respLayer6.occupancy 1936745 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1133252 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 1133003 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 83023 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80825 # Number of conditional branches predicted +system.cpu0.branchPred.lookups 82981 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80783 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 80352 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 78307 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 80310 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 78265 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.454948 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 97.453617 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 221912 # number of cpu cycles simulated +system.cpu0.numCycles 221746 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17233 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 492726 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 83023 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 78819 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 161746 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.icacheStallCycles 17234 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 492474 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 82981 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 78777 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 161662 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 3811 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13929 # Number of cycles fetch has spent blocked +system.cpu0.fetch.BlockedCycles 13862 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 196870 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.502799 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.215097 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.IcacheSquashes 492 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 196720 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.503426 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.215057 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35124 17.84% 17.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 80120 40.70% 58.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 973 0.49% 59.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 477 0.24% 59.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 76224 38.72% 98.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 570 0.29% 98.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35058 17.82% 17.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 80078 40.71% 58.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 578 0.29% 58.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 76182 38.73% 98.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 570 0.29% 98.57% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::8 2455 1.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 196870 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.374126 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.220367 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17821 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 15547 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 160777 # Number of cycles decode is running +system.cpu0.fetch.rateDist::total 196720 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.374216 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.220892 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17819 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15483 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 160693 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 280 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 2445 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 489900 # Number of instructions handled by decode +system.cpu0.decode.DecodedInsts 489648 # Number of instructions handled by decode system.cpu0.rename.SquashCycles 2445 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18476 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 865 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14063 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 160426 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 595 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 487057 # Number of instructions processed by rename +system.cpu0.rename.IdleCycles 18474 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 866 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14003 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 160341 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 591 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 486805 # Number of instructions processed by rename system.cpu0.rename.LSQFullEvents 216 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 333048 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 971305 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 733660 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 320079 # Number of HB maps that are committed +system.cpu0.rename.RenamedOperands 332880 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 970801 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 733282 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 319911 # Number of HB maps that are committed system.cpu0.rename.UndoneMaps 12969 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 866 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 886 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3628 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 155827 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 78749 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 76001 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 75817 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 407304 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.skidInsts 3624 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 155743 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 78707 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 75959 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 75775 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 407094 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 910 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 404579 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued +system.cpu0.iq.iqInstsIssued 404367 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued system.cpu0.iq.iqSquashedInstsExamined 10771 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9747 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedOperandsExamined 9755 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 351 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 196870 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.055057 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097769 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 196720 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.055546 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097437 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 34107 17.32% 17.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4943 2.51% 19.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 77928 39.58% 59.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 77295 39.26% 98.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1579 0.80% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 650 0.33% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34036 17.30% 17.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4955 2.52% 19.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 77877 39.59% 59.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 77259 39.27% 98.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1573 0.80% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 652 0.33% 99.81% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 196870 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 196720 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 57 25.68% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 53 23.87% 49.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 50.45% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 57 25.79% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 52 23.53% 49.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 50.68% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 171055 42.28% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 170970 42.28% 42.28% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued @@ -888,23 +890,23 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 155363 38.40% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 78161 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 155279 38.40% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 78118 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 404579 # Type of FU issued -system.cpu0.iq.rate 1.823151 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 222 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000549 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1006383 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 419039 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 402754 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 404367 # Type of FU issued +system.cpu0.iq.rate 1.823559 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 221 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000547 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1005807 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 418829 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 402541 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 404801 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 404588 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 75529 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 75486 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread0.squashedLoads 2198 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed @@ -913,15 +915,15 @@ system.cpu0.iew.lsq.thread0.squashedStores 1428 # system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 2445 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 405 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 484766 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 308 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 155827 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 78749 # Number of dispatched store instructions +system.cpu0.iew.iewBlockCycles 400 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 484514 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 155743 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 78707 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -929,80 +931,115 @@ system.cpu0.iew.memOrderViolationEvents 54 # Nu system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 403510 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 155033 # Number of load instructions executed +system.cpu0.iew.iewExecutedInsts 403298 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 154949 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1069 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 76552 # number of nop insts executed -system.cpu0.iew.exec_refs 233092 # number of memory reference insts executed -system.cpu0.iew.exec_branches 80162 # Number of branches executed -system.cpu0.iew.exec_stores 78059 # Number of stores executed -system.cpu0.iew.exec_rate 1.818333 # Inst execution rate -system.cpu0.iew.wb_sent 403084 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 402754 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 238663 # num instructions producing a value -system.cpu0.iew.wb_consumers 241120 # num instructions consuming a value +system.cpu0.iew.exec_nop 76510 # number of nop insts executed +system.cpu0.iew.exec_refs 232965 # number of memory reference insts executed +system.cpu0.iew.exec_branches 80120 # Number of branches executed +system.cpu0.iew.exec_stores 78016 # Number of stores executed +system.cpu0.iew.exec_rate 1.818739 # Inst execution rate +system.cpu0.iew.wb_sent 402871 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 402541 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 238524 # num instructions producing a value +system.cpu0.iew.wb_consumers 240975 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.814927 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989810 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.815325 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989829 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.commit.commitSquashedInsts 12269 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 194425 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430089 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136483 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 194275 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430668 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136401 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34537 17.76% 17.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 79950 41.12% 58.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2378 1.22% 60.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 690 0.35% 60.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 75328 38.74% 99.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 457 0.24% 99.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 248 0.13% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34469 17.74% 17.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 79913 41.13% 58.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2377 1.22% 60.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 686 0.35% 60.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 75283 38.75% 99.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 305 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 194425 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 472470 # Number of instructions committed -system.cpu0.commit.committedOps 472470 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 194275 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 472218 # Number of instructions committed +system.cpu0.commit.committedOps 472218 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 230950 # Number of memory references committed -system.cpu0.commit.loads 153629 # Number of loads committed +system.cpu0.commit.refs 230824 # Number of memory references committed +system.cpu0.commit.loads 153545 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 79208 # Number of branches committed +system.cpu0.commit.branches 79166 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 318410 # Number of committed integer instructions. +system.cpu0.commit.int_insts 318242 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::No_OpClass 75898 16.07% 16.07% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 165412 35.03% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 153629 32.53% 83.63% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77279 16.37% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::total 472218 # Class of committed instruction +system.cpu0.commit.bw_lim_events 305 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 677696 # The number of ROB reads -system.cpu0.rob.rob_writes 971940 # The number of ROB writes +system.cpu0.rob.rob_reads 677296 # The number of ROB reads +system.cpu0.rob.rob_writes 971436 # The number of ROB writes system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25042 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 396446 # Number of Instructions Simulated -system.cpu0.committedOps 396446 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 396446 # Number of Instructions Simulated -system.cpu0.cpi 0.559753 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.559753 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.786501 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.786501 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 721878 # number of integer regfile reads -system.cpu0.int_regfile_writes 325337 # number of integer regfile writes +system.cpu0.idleCycles 25026 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 396236 # Number of Instructions Simulated +system.cpu0.committedOps 396236 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 396236 # Number of Instructions Simulated +system.cpu0.cpi 0.559631 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.559631 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.786891 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.786891 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 721496 # number of integer regfile reads +system.cpu0.int_regfile_writes 325166 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 234915 # number of misc regfile reads +system.cpu0.misc_regfile_reads 234788 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.tags.replacements 297 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.280038 # Cycle average of tags in use +system.cpu0.icache.tags.tagsinuse 241.323737 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.280038 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471250 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.471250 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.323737 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471335 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471335 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id @@ -1022,12 +1059,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 756 # system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses system.cpu0.icache.overall_misses::total 756 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35676245 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 35676245 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 35676245 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 35676245 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 35676245 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 35676245 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35655495 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 35655495 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 35655495 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 35655495 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 35655495 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 35655495 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses @@ -1040,12 +1077,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47190.800265 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 47190.800265 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47190.800265 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 47190.800265 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47190.800265 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 47190.800265 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47163.353175 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 47163.353175 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 47163.353175 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 47163.353175 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1066,119 +1103,119 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27430752 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 27430752 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27430752 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 27430752 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27430752 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 27430752 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27420002 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 27420002 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27420002 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27420002 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27420002 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27420002 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46650.938776 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46650.938776 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46650.938776 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 46650.938776 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46650.938776 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 46650.938776 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46632.656463 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 142.009454 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155675 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 142.026535 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155594 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 915.735294 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 915.258824 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.009454 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277362 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277362 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026535 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 627368 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 627368 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79025 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 79025 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 76734 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 76734 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 627036 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 627036 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 78986 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 78986 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 76692 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 76692 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 155759 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 155759 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 155759 # number of overall hits -system.cpu0.dcache.overall_hits::total 155759 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 418 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 418 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 155678 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 155678 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 155678 # number of overall hits +system.cpu0.dcache.overall_hits::total 155678 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 416 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 416 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 963 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 963 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 963 # number of overall misses -system.cpu0.dcache.overall_misses::total 963 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13454697 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13454697 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32621759 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32621759 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 961 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 961 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 961 # number of overall misses +system.cpu0.dcache.overall_misses::total 961 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13375931 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13375931 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32683256 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 32683256 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 46076456 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 46076456 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 46076456 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 46076456 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 79443 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 79443 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77279 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77279 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 46059187 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 46059187 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 46059187 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 46059187 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 79402 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 79402 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77237 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77237 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 156722 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 156722 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 156722 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 156722 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005262 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005262 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007052 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007052 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 156639 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 156639 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 156639 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 156639 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005239 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005239 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007056 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007056 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006145 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006145 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006145 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006145 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32188.270335 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 32188.270335 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59856.438532 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 59856.438532 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006135 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006135 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006135 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006135 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32153.680288 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 32153.680288 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59969.277064 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 59969.277064 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47846.787124 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 47846.787124 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47846.787124 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 47846.787124 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 524 # number of cycles access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 47928.394381 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 47928.394381 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 512 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.200000 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.380952 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 230 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 230 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 228 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 228 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 600 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 600 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 600 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 600 # number of overall MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 598 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 598 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 598 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses @@ -1189,122 +1226,122 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 363 system.cpu0.dcache.demand_mshr_misses::total 363 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 363 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 363 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6237508 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6237508 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7264228 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7264228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6192510 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6192510 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7258228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7258228 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13501736 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13501736 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13501736 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13501736 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002366 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002366 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13450738 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13450738 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13450738 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13450738 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002368 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002368 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002266 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002266 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002316 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002316 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002316 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002316 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33178.234043 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33178.234043 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41509.874286 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41509.874286 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002317 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002317 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32938.882979 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32938.882979 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41475.588571 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41475.588571 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37194.865014 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37194.865014 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37194.865014 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37194.865014 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 49230 # Number of BP lookups -system.cpu1.branchPred.condPredicted 46482 # Number of conditional branches predicted +system.cpu1.branchPred.lookups 49222 # Number of BP lookups +system.cpu1.branchPred.condPredicted 46474 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 1275 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 43125 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 42318 # Number of BTB hits +system.cpu1.branchPred.BTBLookups 43117 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 42310 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.128696 # BTB Hit Percentage +system.cpu1.branchPred.BTBHitPct 98.128348 # BTB Hit Percentage system.cpu1.branchPred.usedRAS 644 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 177729 # number of cpu cycles simulated +system.cpu1.numCycles 177641 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 30707 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 271510 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 49230 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 42962 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 98061 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.icacheStallCycles 30689 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 271480 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 49222 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 42954 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 98036 # Number of cycles fetch has run and was not squashing or blocked system.cpu1.fetch.SquashCycles 3712 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 35852 # Number of cycles fetch has spent blocked +system.cpu1.fetch.BlockedCycles 35816 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 7757 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.NoActiveThreadStallCycles 7751 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 22354 # Number of cache lines fetched +system.cpu1.fetch.CacheLines 22336 # Number of cache lines fetched system.cpu1.fetch.IcacheSquashes 259 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 175517 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.546916 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.089154 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::samples 175432 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.547494 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.089471 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 77456 44.13% 44.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 50516 28.78% 72.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7423 4.23% 77.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3189 1.82% 78.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 704 0.40% 79.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 30974 17.65% 97.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1193 0.68% 97.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 77396 44.12% 44.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 50499 28.79% 72.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7414 4.23% 77.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3189 1.82% 78.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 704 0.40% 79.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 30975 17.66% 97.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1193 0.68% 97.68% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::7 759 0.43% 98.12% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::8 3303 1.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 175517 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.276995 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.527663 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 37188 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 31008 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 90874 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 6330 # Number of cycles decode is unblocking +system.cpu1.fetch.rateDist::total 175432 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.277087 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.528251 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 37161 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 30981 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 90858 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 6321 # Number of cycles decode is unblocking system.cpu1.decode.SquashCycles 2360 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 267842 # Number of instructions handled by decode +system.cpu1.decode.DecodedInsts 267812 # Number of instructions handled by decode system.cpu1.rename.SquashCycles 2360 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 37871 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18552 # Number of cycles rename is blocking +system.cpu1.rename.IdleCycles 37844 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18525 # Number of cycles rename is blocking system.cpu1.rename.serializeStallCycles 11702 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 84813 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 12462 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 265527 # Number of instructions processed by rename +system.cpu1.rename.RunCycles 84806 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 12444 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 265497 # Number of instructions processed by rename system.cpu1.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu1.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 184379 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 502490 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 391665 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 171551 # Number of HB maps that are committed +system.cpu1.rename.RenamedOperands 184374 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 502466 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 391647 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 171546 # Number of HB maps that are committed system.cpu1.rename.UndoneMaps 12828 # Number of HB maps that are undone due to squashing system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed system.cpu1.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 15186 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 73774 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 34232 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 35732 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 29187 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 218298 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7639 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 221677 # Number of instructions issued +system.cpu1.rename.skidInsts 15168 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 73767 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 34233 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 35724 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 29188 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 218285 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 7630 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 221655 # Number of instructions issued system.cpu1.iq.iqSquashedInstsIssued 99 # Number of squashed instructions issued system.cpu1.iq.iqSquashedInstsExamined 10737 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu1.iq.iqSquashedOperandsExamined 10712 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.iq.iqSquashedNonSpecRemoved 591 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 175517 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.262994 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.299330 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::samples 175432 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.263481 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.299438 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 74868 42.66% 42.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 26303 14.99% 57.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 34475 19.64% 77.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 35103 20.00% 97.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 74808 42.64% 42.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 26276 14.98% 57.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 34476 19.65% 77.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 35104 20.01% 97.28% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::4 3248 1.85% 99.13% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 1161 0.66% 99.80% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 252 0.14% 99.94% # Number of insts issued each cycle @@ -1313,7 +1350,7 @@ system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Nu system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 175517 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 175432 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IntAlu 12 4.51% 4.51% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available @@ -1349,7 +1386,7 @@ system.cpu1.iq.fu_full::MemWrite 210 78.95% 100.00% # at system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 108767 49.07% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 108760 49.07% 49.07% # Type of FU issued system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.07% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.07% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.07% # Type of FU issued @@ -1378,23 +1415,23 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.07% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.07% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.07% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 79372 35.81% 84.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 33538 15.13% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 79356 35.80% 84.87% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 33539 15.13% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 221677 # Type of FU issued -system.cpu1.iq.rate 1.247275 # Inst issue rate +system.cpu1.iq.FU_type_0::total 221655 # Type of FU issued +system.cpu1.iq.rate 1.247769 # Inst issue rate system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested system.cpu1.iq.fu_busy_rate 0.001200 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 619236 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 236717 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 219849 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.int_inst_queue_reads 619107 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 236695 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 219827 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 221943 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 221921 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 28929 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 28930 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed @@ -1408,10 +1445,10 @@ system.cpu1.iew.iewIdleCycles 0 # Nu system.cpu1.iew.iewSquashCycles 2360 # Number of cycles IEW is squashing system.cpu1.iew.iewBlockCycles 686 # Number of cycles IEW is blocking system.cpu1.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 262595 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispatchedInsts 262565 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 349 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 73774 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 34232 # Number of dispatched store instructions +system.cpu1.iew.iewDispLoadInsts 73767 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 34233 # Number of dispatched store instructions system.cpu1.iew.iewDispNonSpecInsts 1056 # Number of dispatched non-speculative instructions system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -1419,123 +1456,158 @@ system.cpu1.iew.memOrderViolationEvents 43 # Nu system.cpu1.iew.predictedTakenIncorrect 467 # Number of branches that were predicted taken incorrectly system.cpu1.iew.predictedNotTakenIncorrect 918 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 220501 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 72766 # Number of load instructions executed +system.cpu1.iew.iewExecutedInsts 220479 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 72759 # Number of load instructions executed system.cpu1.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 36658 # number of nop insts executed -system.cpu1.iew.exec_refs 106223 # number of memory reference insts executed -system.cpu1.iew.exec_branches 45902 # Number of branches executed -system.cpu1.iew.exec_stores 33457 # Number of stores executed -system.cpu1.iew.exec_rate 1.240659 # Inst execution rate -system.cpu1.iew.wb_sent 220134 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 219849 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 122957 # num instructions producing a value -system.cpu1.iew.wb_consumers 127616 # num instructions consuming a value +system.cpu1.iew.exec_nop 36650 # number of nop insts executed +system.cpu1.iew.exec_refs 106217 # number of memory reference insts executed +system.cpu1.iew.exec_branches 45894 # Number of branches executed +system.cpu1.iew.exec_stores 33458 # Number of stores executed +system.cpu1.iew.exec_rate 1.241149 # Inst execution rate +system.cpu1.iew.wb_sent 220112 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 219827 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 122951 # num instructions producing a value +system.cpu1.iew.wb_consumers 127610 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.236990 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.963492 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.237479 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.963490 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu1.commit.commitSquashedInsts 12326 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 7048 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitNonSpecStalls 7039 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 1275 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 165400 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.513005 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.970213 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::samples 165321 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.513546 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.970448 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 73929 44.70% 44.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 44053 26.63% 71.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6103 3.69% 75.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 7962 4.81% 79.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1564 0.95% 80.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 29500 17.84% 98.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 73866 44.68% 44.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 44045 26.64% 71.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6103 3.69% 75.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 7953 4.81% 79.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1564 0.95% 80.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 29501 17.84% 98.62% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::6 477 0.29% 98.90% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::7 1008 0.61% 99.51% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::8 804 0.49% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 165400 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 250251 # Number of instructions committed -system.cpu1.commit.committedOps 250251 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 165321 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 250221 # Number of instructions committed +system.cpu1.commit.committedOps 250221 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 104168 # Number of memory references committed -system.cpu1.commit.loads 71380 # Number of loads committed -system.cpu1.commit.membars 6331 # Number of memory barriers committed -system.cpu1.commit.branches 45080 # Number of branches committed +system.cpu1.commit.refs 104162 # Number of memory references committed +system.cpu1.commit.loads 71373 # Number of loads committed +system.cpu1.commit.membars 6322 # Number of memory barriers committed +system.cpu1.commit.branches 45072 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 171367 # Number of committed integer instructions. +system.cpu1.commit.int_insts 171353 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 35859 14.33% 14.33% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 103878 41.51% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.85% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 77695 31.05% 86.90% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 32789 13.10% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::total 250221 # Class of committed instruction system.cpu1.commit.bw_lim_events 804 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 426586 # The number of ROB reads -system.cpu1.rob.rob_writes 527520 # The number of ROB writes +system.cpu1.rob.rob_reads 426477 # The number of ROB reads +system.cpu1.rob.rob_writes 527460 # The number of ROB writes system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2212 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 44181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 208053 # Number of Instructions Simulated -system.cpu1.committedOps 208053 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 208053 # Number of Instructions Simulated -system.cpu1.cpi 0.854249 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.854249 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.170619 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.170619 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 377223 # number of integer regfile reads -system.cpu1.int_regfile_writes 176309 # number of integer regfile writes +system.cpu1.idleCycles 2209 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 44103 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 208040 # Number of Instructions Simulated +system.cpu1.committedOps 208040 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 208040 # Number of Instructions Simulated +system.cpu1.cpi 0.853879 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.853879 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.171126 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.171126 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 377205 # number of integer regfile reads +system.cpu1.int_regfile_writes 176304 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 107781 # number of misc regfile reads +system.cpu1.misc_regfile_reads 107775 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.tags.replacements 318 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.722565 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 21879 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 76.769709 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 21861 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 51.119159 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 51.077103 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.722565 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149849 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.149849 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.769709 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149941 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149941 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 22782 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 22782 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 21879 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21879 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21879 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21879 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21879 # number of overall hits -system.cpu1.icache.overall_hits::total 21879 # number of overall hits +system.cpu1.icache.tags.tag_accesses 22764 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 22764 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 21861 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 21861 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 21861 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 21861 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 21861 # number of overall hits +system.cpu1.icache.overall_hits::total 21861 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 475 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 475 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 475 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 475 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 475 # number of overall misses system.cpu1.icache.overall_misses::total 475 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7157495 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7157495 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7157495 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7157495 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7157495 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7157495 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 22354 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 22354 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 22354 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 22354 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 22354 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 22354 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021249 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.021249 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021249 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.021249 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021249 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.021249 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15068.410526 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15068.410526 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15068.410526 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15068.410526 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15068.410526 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15068.410526 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7146245 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7146245 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7146245 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7146245 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7146245 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7146245 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 22336 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 22336 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 22336 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 22336 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 22336 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 22336 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021266 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.021266 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021266 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.021266 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021266 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.021266 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15044.726316 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15044.726316 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15044.726316 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15044.726316 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1556,49 +1628,49 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5706004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5706004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5706004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5706004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5706004 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5706004 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019146 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019146 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019146 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019146 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019146 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019146 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13331.785047 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13331.785047 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13331.785047 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13331.785047 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13331.785047 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13331.785047 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5694254 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5694254 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5694254 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5694254 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5694254 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5694254 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019162 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.019162 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.019162 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13304.331776 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 23.630187 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 38790 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 23.645460 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 38791 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1385.357143 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1385.392857 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.630187 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046153 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.046153 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.645460 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046183 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.046183 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 306681 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 306681 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 43485 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 43485 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 32585 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 32585 # number of WriteReq hits +system.cpu1.dcache.tags.tag_accesses 306653 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 306653 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 43477 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 43477 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 32586 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 32586 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 76070 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 76070 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 76070 # number of overall hits -system.cpu1.dcache.overall_hits::total 76070 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 76063 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 76063 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 76063 # number of overall hits +system.cpu1.dcache.overall_hits::total 76063 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 336 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 336 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses @@ -1609,46 +1681,46 @@ system.cpu1.dcache.demand_misses::cpu1.data 468 # system.cpu1.dcache.demand_misses::total 468 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 468 # number of overall misses system.cpu1.dcache.overall_misses::total 468 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4179135 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4179135 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4177635 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4177635 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2763761 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 2763761 # number of WriteReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 521507 # number of SwapReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::total 521507 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6942896 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6942896 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6942896 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6942896 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 43821 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 43821 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 32717 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 32717 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.demand_miss_latency::cpu1.data 6941396 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6941396 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6941396 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6941396 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 43813 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 43813 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 32718 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 32718 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 76538 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 76538 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 76538 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 76538 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007668 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.007668 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004035 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004035 # miss rate for WriteReq accesses +system.cpu1.dcache.demand_accesses::cpu1.data 76531 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 76531 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 76531 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 76531 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007669 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.007669 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004034 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004034 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006115 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.006115 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006115 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.006115 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12437.901786 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12437.901786 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12433.437500 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12433.437500 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20937.583333 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 20937.583333 # average WriteReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9149.245614 # average SwapReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::total 9149.245614 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14835.247863 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14835.247863 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14835.247863 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14835.247863 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14832.042735 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14832.042735 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1675,16 +1747,16 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1078019 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1078019 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1076519 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1076519 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1313739 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1313739 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 407493 # number of SwapReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::total 407493 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2391758 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2391758 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2391758 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2391758 # number of overall MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2390258 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2390258 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2390258 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2390258 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003606 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003606 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003118 # mshr miss rate for WriteReq accesses @@ -1695,110 +1767,110 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003397 system.cpu1.dcache.demand_mshr_miss_rate::total 0.003397 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.003397 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6822.905063 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6822.905063 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6813.411392 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6813.411392 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12879.794118 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12879.794118 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7149 # average SwapReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7149 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9199.069231 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9199.069231 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9199.069231 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9199.069231 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 47736 # Number of BP lookups -system.cpu2.branchPred.condPredicted 45029 # Number of conditional branches predicted +system.cpu2.branchPred.lookups 47728 # Number of BP lookups +system.cpu2.branchPred.condPredicted 45021 # Number of conditional branches predicted system.cpu2.branchPred.condIncorrect 1300 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 41576 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 40869 # Number of BTB hits +system.cpu2.branchPred.BTBLookups 41568 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 40861 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.299500 # BTB Hit Percentage +system.cpu2.branchPred.BTBHitPct 98.299172 # BTB Hit Percentage system.cpu2.branchPred.usedRAS 682 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 177364 # number of cpu cycles simulated +system.cpu2.numCycles 177276 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.fetch.icacheStallCycles 30843 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 263253 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 47736 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 41551 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 94921 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.Insts 263204 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 47728 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 41543 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 94904 # Number of cycles fetch has run and was not squashing or blocked system.cpu2.fetch.SquashCycles 3824 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 35042 # Number of cycles fetch has spent blocked +system.cpu2.fetch.BlockedCycles 35041 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 7755 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from system.cpu2.fetch.PendingTrapStallCycles 807 # Number of stall cycles due to pending traps system.cpu2.fetch.CacheLines 21784 # Number of cache lines fetched system.cpu2.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 171818 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.532162 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.088026 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::samples 171794 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.532091 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.088011 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 76897 44.75% 44.75% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 48842 28.43% 73.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 76890 44.76% 44.76% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 48833 28.43% 73.18% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::2 7151 4.16% 77.34% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::3 3183 1.85% 79.20% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::4 686 0.40% 79.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 29853 17.37% 96.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1160 0.68% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 29845 17.37% 96.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1160 0.68% 97.64% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::7 777 0.45% 98.10% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::8 3269 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 171818 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.269141 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.484253 # Number of inst fetches per cycle +system.cpu2.fetch.rateDist::total 171794 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.269230 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.484713 # Number of inst fetches per cycle system.cpu2.decode.IdleCycles 36742 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 30807 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 88098 # Number of cycles decode is running +system.cpu2.decode.BlockedCycles 30806 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 88081 # Number of cycles decode is running system.cpu2.decode.UnblockCycles 5970 # Number of cycles decode is unblocking system.cpu2.decode.SquashCycles 2446 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 259780 # Number of instructions handled by decode +system.cpu2.decode.DecodedInsts 259729 # Number of instructions handled by decode system.cpu2.rename.SquashCycles 2446 # Number of cycles rename is squashing system.cpu2.rename.IdleCycles 37466 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 17719 # Number of cycles rename is blocking +system.cpu2.rename.BlockCycles 17718 # Number of cycles rename is blocking system.cpu2.rename.serializeStallCycles 12322 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 82368 # Number of cycles rename is running +system.cpu2.rename.RunCycles 82351 # Number of cycles rename is running system.cpu2.rename.UnblockCycles 11742 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 257506 # Number of instructions processed by rename +system.cpu2.rename.RenamedInsts 257457 # Number of instructions processed by rename system.cpu2.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 179566 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 487666 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 380584 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 166435 # Number of HB maps that are committed +system.cpu2.rename.RenamedOperands 179534 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 487570 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 380512 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 166403 # Number of HB maps that are committed system.cpu2.rename.UndoneMaps 13131 # Number of HB maps that are undone due to squashing system.cpu2.rename.serializingInsts 1114 # count of serializing insts renamed system.cpu2.rename.tempSerializingInsts 1238 # count of temporary serializing insts renamed system.cpu2.rename.skidInsts 14439 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 71199 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 33061 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 34327 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 28016 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 212074 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.memDep0.insertedLoads 71183 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 33053 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 34319 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 28008 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 212034 # Number of instructions added to the IQ (excludes non-spec) system.cpu2.iq.iqNonSpecInstsAdded 7370 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 214906 # Number of instructions issued +system.cpu2.iq.iqInstsIssued 214866 # Number of instructions issued system.cpu2.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued system.cpu2.iq.iqSquashedInstsExamined 11214 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu2.iq.iqSquashedOperandsExamined 11199 # Number of squashed operands that are examined and possibly removed from graph system.cpu2.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 171818 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.250777 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.303706 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::samples 171794 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.250719 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.303691 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 74494 43.36% 43.36% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 25338 14.75% 58.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 33284 19.37% 77.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 33913 19.74% 97.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3241 1.89% 99.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1161 0.68% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 74486 43.36% 43.36% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 25336 14.75% 58.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 33280 19.37% 77.48% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 33902 19.73% 97.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3243 1.89% 99.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1160 0.68% 99.77% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::6 274 0.16% 99.93% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 171818 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 171794 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IntAlu 17 6.18% 6.18% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 0 0.00% 6.18% # attempts to use FU when none available @@ -1834,7 +1906,7 @@ system.cpu2.iq.fu_full::MemWrite 210 76.36% 100.00% # at system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 106166 49.40% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 106150 49.40% 49.40% # Type of FU issued system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.40% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.40% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.40% # Type of FU issued @@ -1863,23 +1935,23 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.40% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.40% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.40% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 76377 35.54% 84.94% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 32363 15.06% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 76361 35.54% 84.94% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 32355 15.06% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 214906 # Type of FU issued -system.cpu2.iq.rate 1.211666 # Inst issue rate +system.cpu2.iq.FU_type_0::total 214866 # Type of FU issued +system.cpu2.iq.rate 1.212042 # Inst issue rate system.cpu2.iq.fu_busy_cnt 275 # FU busy when requested system.cpu2.iq.fu_busy_rate 0.001280 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 602011 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 230706 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 213087 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.int_inst_queue_reads 601907 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 230666 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 213047 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 215181 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 215141 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 27728 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 27720 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu2.iew.lsq.thread0.squashedLoads 2543 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed @@ -1891,12 +1963,12 @@ system.cpu2.iew.lsq.thread0.rescheduledLoads 0 system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu2.iew.iewSquashCycles 2446 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 917 # Number of cycles IEW is blocking +system.cpu2.iew.iewBlockCycles 916 # Number of cycles IEW is blocking system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 254656 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispatchedInsts 254607 # Number of instructions dispatched to IQ system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 71199 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 33061 # Number of dispatched store instructions +system.cpu2.iew.iewDispLoadInsts 71183 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 33053 # Number of dispatched store instructions system.cpu2.iew.iewDispNonSpecInsts 1074 # Number of dispatched non-speculative instructions system.cpu2.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -1904,81 +1976,116 @@ system.cpu2.iew.memOrderViolationEvents 48 # Nu system.cpu2.iew.predictedTakenIncorrect 458 # Number of branches that were predicted taken incorrectly system.cpu2.iew.predictedNotTakenIncorrect 967 # Number of branches that were predicted not taken incorrectly system.cpu2.iew.branchMispredicts 1425 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 213756 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 70098 # Number of load instructions executed +system.cpu2.iew.iewExecutedInsts 213716 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 70082 # Number of load instructions executed system.cpu2.iew.iewExecSquashedInsts 1150 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 35212 # number of nop insts executed -system.cpu2.iew.exec_refs 102378 # number of memory reference insts executed -system.cpu2.iew.exec_branches 44395 # Number of branches executed -system.cpu2.iew.exec_stores 32280 # Number of stores executed -system.cpu2.iew.exec_rate 1.205183 # Inst execution rate -system.cpu2.iew.wb_sent 213374 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 213087 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 119148 # num instructions producing a value -system.cpu2.iew.wb_consumers 123853 # num instructions consuming a value +system.cpu2.iew.exec_nop 35203 # number of nop insts executed +system.cpu2.iew.exec_refs 102354 # number of memory reference insts executed +system.cpu2.iew.exec_branches 44387 # Number of branches executed +system.cpu2.iew.exec_stores 32272 # Number of stores executed +system.cpu2.iew.exec_rate 1.205555 # Inst execution rate +system.cpu2.iew.wb_sent 213334 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 213047 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 119124 # num instructions producing a value +system.cpu2.iew.wb_consumers 123829 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.201411 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.962011 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.201781 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.962004 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12898 # The number of squashed insts skipped by commit +system.cpu2.commit.commitSquashedInsts 12897 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 6722 # The number of times commit has been forced to stall to communicate backwards system.cpu2.commit.branchMispredicts 1300 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 161617 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.495857 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.966536 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::samples 161599 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.495727 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.966465 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 73208 45.30% 45.30% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 42532 26.32% 71.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 73205 45.30% 45.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 42525 26.32% 71.62% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::2 6095 3.77% 75.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 7628 4.72% 80.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7628 4.72% 80.11% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::4 1558 0.96% 81.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 28303 17.51% 98.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 470 0.29% 98.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 28296 17.51% 98.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 469 0.29% 98.87% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 161617 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 241756 # Number of instructions committed -system.cpu2.commit.committedOps 241756 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 161599 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 241708 # Number of instructions committed +system.cpu2.commit.committedOps 241708 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 100248 # Number of memory references committed -system.cpu2.commit.loads 68656 # Number of loads committed +system.cpu2.commit.refs 100224 # Number of memory references committed +system.cpu2.commit.loads 68640 # Number of loads committed system.cpu2.commit.membars 6003 # Number of memory barriers committed -system.cpu2.commit.branches 43556 # Number of branches committed +system.cpu2.commit.branches 43548 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 165922 # Number of committed integer instructions. +system.cpu2.commit.int_insts 165890 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 34333 14.20% 14.20% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 101148 41.85% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 74643 30.88% 86.93% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 31584 13.07% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::total 241708 # Class of committed instruction system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 414862 # The number of ROB reads -system.cpu2.rob.rob_writes 511759 # The number of ROB writes +system.cpu2.rob.rob_reads 414795 # The number of ROB reads +system.cpu2.rob.rob_writes 511661 # The number of ROB writes system.cpu2.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5546 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 44546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 201412 # Number of Instructions Simulated -system.cpu2.committedOps 201412 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 201412 # Number of Instructions Simulated -system.cpu2.cpi 0.880603 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.880603 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.135586 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.135586 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 365854 # number of integer regfile reads -system.cpu2.int_regfile_writes 171387 # number of integer regfile writes +system.cpu2.idleCycles 5482 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 44468 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 201372 # Number of Instructions Simulated +system.cpu2.committedOps 201372 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 201372 # Number of Instructions Simulated +system.cpu2.cpi 0.880341 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.880341 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.135924 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.135924 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 365782 # number of integer regfile reads +system.cpu2.int_regfile_writes 171355 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 103940 # number of misc regfile reads +system.cpu2.misc_regfile_reads 103916 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.tags.replacements 317 # number of replacements -system.cpu2.icache.tags.tagsinuse 82.194037 # Cycle average of tags in use +system.cpu2.icache.tags.tagsinuse 82.236907 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 21297 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. system.cpu2.icache.tags.avg_refs 50.110588 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.194037 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160535 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.160535 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236907 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160619 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.160619 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 108 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id @@ -1997,12 +2104,12 @@ system.cpu2.icache.demand_misses::cpu2.inst 487 # system.cpu2.icache.demand_misses::total 487 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 487 # number of overall misses system.cpu2.icache.overall_misses::total 487 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11553239 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 11553239 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 11553239 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 11553239 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 11553239 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 11553239 # number of overall miss cycles +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521239 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 11521239 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 11521239 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 11521239 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 11521239 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 11521239 # number of overall miss cycles system.cpu2.icache.ReadReq_accesses::cpu2.inst 21784 # number of ReadReq accesses(hits+misses) system.cpu2.icache.ReadReq_accesses::total 21784 # number of ReadReq accesses(hits+misses) system.cpu2.icache.demand_accesses::cpu2.inst 21784 # number of demand (read+write) accesses @@ -2015,12 +2122,12 @@ system.cpu2.icache.demand_miss_rate::cpu2.inst 0.022356 system.cpu2.icache.demand_miss_rate::total 0.022356 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.022356 # miss rate for overall accesses system.cpu2.icache.overall_miss_rate::total 0.022356 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23723.283368 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 23723.283368 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23723.283368 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 23723.283368 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23723.283368 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 23723.283368 # average overall miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23657.574949 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23657.574949 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23657.574949 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 23657.574949 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -2041,50 +2148,50 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9258007 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 9258007 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9258007 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 9258007 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9258007 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 9258007 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9226007 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 9226007 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9226007 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 9226007 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9226007 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 9226007 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019510 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_miss_rate::total 0.019510 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_miss_rate::total 0.019510 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21783.545882 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21783.545882 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21783.545882 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21783.545882 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21783.545882 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21783.545882 # average overall mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21708.251765 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.156826 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 37738 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 26.169210 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 37730 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1301.310345 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1301.034483 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.156826 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051088 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.051088 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.169210 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051112 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.051112 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 296038 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 296038 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 31379 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 31379 # number of WriteReq hits +system.cpu2.dcache.tags.tag_accesses 295974 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 295974 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 42003 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42003 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 31371 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 31371 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 73390 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 73390 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 73390 # number of overall hits -system.cpu2.dcache.overall_hits::total 73390 # number of overall hits +system.cpu2.dcache.demand_hits::cpu2.data 73374 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 73374 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 73374 # number of overall hits +system.cpu2.dcache.overall_hits::total 73374 # number of overall hits system.cpu2.dcache.ReadReq_misses::cpu2.data 342 # number of ReadReq misses system.cpu2.dcache.ReadReq_misses::total 342 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 140 # number of WriteReq misses @@ -2095,46 +2202,46 @@ system.cpu2.dcache.demand_misses::cpu2.data 482 # system.cpu2.dcache.demand_misses::total 482 # number of demand (read+write) misses system.cpu2.dcache.overall_misses::cpu2.data 482 # number of overall misses system.cpu2.dcache.overall_misses::total 482 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5441573 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5441573 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5435581 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5435581 # number of ReadReq miss cycles system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3139010 # number of WriteReq miss cycles system.cpu2.dcache.WriteReq_miss_latency::total 3139010 # number of WriteReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 574505 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::total 574505 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 8580583 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 8580583 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 8580583 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 8580583 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 42353 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 42353 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 31519 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 31519 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.demand_miss_latency::cpu2.data 8574591 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 8574591 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 8574591 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 8574591 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42345 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42345 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 31511 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 31511 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 73872 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 73872 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 73872 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 73872 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008075 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.008075 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004442 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004442 # miss rate for WriteReq accesses +system.cpu2.dcache.demand_accesses::cpu2.data 73856 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 73856 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 73856 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 73856 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008077 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004443 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004443 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.808219 # miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_miss_rate::total 0.808219 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006525 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.006525 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006525 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.006525 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15911.032164 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 15911.032164 # average ReadReq miss latency +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006526 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.006526 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006526 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.006526 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15893.511696 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 15893.511696 # average ReadReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22421.500000 # average WriteReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::total 22421.500000 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9737.372881 # average SwapReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::total 9737.372881 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17802.039419 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17802.039419 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17802.039419 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17802.039419 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17789.607884 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17789.607884 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17789.607884 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17789.607884 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2161,123 +2268,123 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1516779 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1516779 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1515278 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1515278 # number of ReadReq MSHR miss cycles system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1527990 # number of WriteReq MSHR miss cycles system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1527990 # number of WriteReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456495 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456495 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3044769 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3044769 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3044769 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3044769 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003896 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003896 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003363 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003363 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3043268 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3043268 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3043268 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3043268 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003897 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003897 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003364 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003364 # mshr miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.808219 # mshr miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.808219 # mshr miss rate for SwapReq accesses system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for demand accesses system.cpu2.dcache.demand_mshr_miss_rate::total 0.003669 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for overall accesses system.cpu2.dcache.overall_mshr_miss_rate::total 0.003669 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9192.600000 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9192.600000 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9183.503030 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9183.503030 # average ReadReq mshr miss latency system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14415 # average WriteReq mshr miss latency system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14415 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7737.203390 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7737.203390 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11235.309963 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11235.309963 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11235.309963 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11235.309963 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 53969 # Number of BP lookups -system.cpu3.branchPred.condPredicted 51237 # Number of conditional branches predicted +system.cpu3.branchPred.lookups 53964 # Number of BP lookups +system.cpu3.branchPred.condPredicted 51232 # Number of conditional branches predicted system.cpu3.branchPred.condIncorrect 1265 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 47879 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 47122 # Number of BTB hits +system.cpu3.branchPred.BTBLookups 47874 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 47117 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.418931 # BTB Hit Percentage +system.cpu3.branchPred.BTBHitPct 98.418766 # BTB Hit Percentage system.cpu3.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 177018 # number of cpu cycles simulated +system.cpu3.numCycles 176930 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 27849 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 302683 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 53969 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 47767 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 106238 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.icacheStallCycles 27837 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 302665 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 53964 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 47762 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 106222 # Number of cycles fetch has run and was not squashing or blocked system.cpu3.fetch.SquashCycles 3643 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 30687 # Number of cycles fetch has spent blocked +system.cpu3.fetch.BlockedCycles 30631 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 7755 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 19589 # Number of cache lines fetched +system.cpu3.fetch.CacheLines 19577 # Number of cache lines fetched system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 175633 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.723383 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.153093 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::samples 175543 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.724164 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.153360 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 69395 39.51% 39.51% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 53961 30.72% 70.24% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 6037 3.44% 73.67% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3206 1.83% 75.50% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 696 0.40% 75.89% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 37090 21.12% 97.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 69321 39.49% 39.49% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 53950 30.73% 70.22% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 6031 3.44% 73.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3206 1.83% 75.48% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 696 0.40% 75.88% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 37091 21.13% 97.01% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::6 1217 0.69% 97.70% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::7 754 0.43% 98.13% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::8 3277 1.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 175633 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.304879 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.709900 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 32991 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 27180 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 100358 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 5049 # Number of cycles decode is unblocking +system.cpu3.fetch.rateDist::total 175543 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.305002 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.710648 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 32973 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 27130 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 100348 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5043 # Number of cycles decode is unblocking system.cpu3.decode.SquashCycles 2300 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 299127 # Number of instructions handled by decode +system.cpu3.decode.DecodedInsts 299109 # Number of instructions handled by decode system.cpu3.rename.SquashCycles 2300 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 33666 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 14636 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11796 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 95593 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 9887 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 297010 # Number of instructions processed by rename +system.cpu3.rename.IdleCycles 33648 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 14616 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 11766 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 95589 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 9875 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 296992 # Number of instructions processed by rename system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full system.cpu3.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 207704 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 570857 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 442944 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 195081 # Number of HB maps that are committed +system.cpu3.rename.RenamedOperands 207702 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 570845 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 442935 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 195079 # Number of HB maps that are committed system.cpu3.rename.UndoneMaps 12623 # Number of HB maps that are undone due to squashing system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed system.cpu3.rename.tempSerializingInsts 1224 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 12502 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 84726 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 40382 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 40460 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 35337 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 246420 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6261 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 248749 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued +system.cpu3.rename.skidInsts 12490 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 84722 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 40383 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 40455 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 35338 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 246413 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6255 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 248738 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 58 # Number of squashed instructions issued system.cpu3.iq.iqSquashedInstsExamined 10413 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 9956 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedOperandsExamined 9948 # Number of squashed operands that are examined and possibly removed from graph system.cpu3.iq.iqSquashedNonSpecRemoved 566 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 175633 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.416300 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.309117 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::samples 175543 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.416963 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.309147 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 66575 37.91% 37.91% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 22292 12.69% 50.60% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 40685 23.16% 73.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 41298 23.51% 97.28% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3252 1.85% 99.13% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 66501 37.88% 37.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 22275 12.69% 50.57% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 40683 23.18% 73.75% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 41300 23.53% 97.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3253 1.85% 99.13% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::5 1166 0.66% 99.79% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::7 47 0.03% 99.97% # Number of insts issued each cycle @@ -2285,43 +2392,43 @@ system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Nu system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 175633 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 175543 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 17 6.46% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 36 13.69% 20.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 79.85% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 17 6.44% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 37 14.02% 20.45% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 119915 48.21% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 119912 48.21% 48.21% # Type of FU issued system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.21% # Type of FU issued system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.21% # Type of FU issued system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.21% # Type of FU issued @@ -2350,23 +2457,23 @@ system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.21% # Ty system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.21% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.21% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 89111 35.82% 84.03% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 39723 15.97% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 89101 35.82% 84.03% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 39725 15.97% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 248749 # Type of FU issued -system.cpu3.iq.rate 1.405219 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 263 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001057 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 673451 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 263132 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 246950 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 248738 # Type of FU issued +system.cpu3.iq.rate 1.405855 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 264 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001061 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 673341 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 263119 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 246940 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 249012 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 249002 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 35153 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 35155 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu3.iew.lsq.thread0.squashedLoads 2247 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed @@ -2378,12 +2485,12 @@ system.cpu3.iew.lsq.thread0.rescheduledLoads 0 system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu3.iew.iewSquashCycles 2300 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 645 # Number of cycles IEW is blocking +system.cpu3.iew.iewBlockCycles 643 # Number of cycles IEW is blocking system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 294144 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispatchedInsts 294126 # Number of instructions dispatched to IQ system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 84726 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 40382 # Number of dispatched store instructions +system.cpu3.iew.iewDispLoadInsts 84722 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 40383 # Number of dispatched store instructions system.cpu3.iew.iewDispNonSpecInsts 1060 # Number of dispatched non-speculative instructions system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -2391,93 +2498,128 @@ system.cpu3.iew.memOrderViolationEvents 38 # Nu system.cpu3.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly system.cpu3.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly system.cpu3.iew.branchMispredicts 1378 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 247595 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 83855 # Number of load instructions executed +system.cpu3.iew.iewExecutedInsts 247584 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 83851 # Number of load instructions executed system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 41463 # number of nop insts executed -system.cpu3.iew.exec_refs 123509 # number of memory reference insts executed -system.cpu3.iew.exec_branches 50804 # Number of branches executed -system.cpu3.iew.exec_stores 39654 # Number of stores executed -system.cpu3.iew.exec_rate 1.398700 # Inst execution rate -system.cpu3.iew.wb_sent 247239 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 246950 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 140249 # num instructions producing a value -system.cpu3.iew.wb_consumers 144916 # num instructions consuming a value +system.cpu3.iew.exec_nop 41458 # number of nop insts executed +system.cpu3.iew.exec_refs 123507 # number of memory reference insts executed +system.cpu3.iew.exec_branches 50799 # Number of branches executed +system.cpu3.iew.exec_stores 39656 # Number of stores executed +system.cpu3.iew.exec_rate 1.399333 # Inst execution rate +system.cpu3.iew.wb_sent 247229 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 246940 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 140247 # num instructions producing a value +system.cpu3.iew.wb_consumers 144914 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.395056 # insts written-back per cycle +system.cpu3.iew.wb_rate 1.395693 # insts written-back per cycle system.cpu3.iew.wb_fanout 0.967795 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu3.commit.commitSquashedInsts 11951 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 5695 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.commitNonSpecStalls 5689 # The number of times commit has been forced to stall to communicate backwards system.cpu3.commit.branchMispredicts 1265 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 165578 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.704170 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.038930 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::samples 165494 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.704926 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.039126 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 64386 38.89% 38.89% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 48906 29.54% 68.42% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6087 3.68% 72.10% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 6642 4.01% 76.11% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1574 0.95% 77.06% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 35662 21.54% 98.60% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 64312 38.86% 38.86% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 48901 29.55% 68.41% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6087 3.68% 72.09% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 6636 4.01% 76.10% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1574 0.95% 77.05% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 35663 21.55% 98.60% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::6 504 0.30% 98.90% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::7 999 0.60% 99.51% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::8 818 0.49% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 165578 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 282173 # Number of instructions committed -system.cpu3.commit.committedOps 282173 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 165494 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 282155 # Number of instructions committed +system.cpu3.commit.committedOps 282155 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 121476 # Number of memory references committed -system.cpu3.commit.loads 82479 # Number of loads committed -system.cpu3.commit.membars 4985 # Number of memory barriers committed -system.cpu3.commit.branches 49947 # Number of branches committed +system.cpu3.commit.refs 121473 # Number of memory references committed +system.cpu3.commit.loads 82475 # Number of loads committed +system.cpu3.commit.membars 4979 # Number of memory barriers committed +system.cpu3.commit.branches 49942 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 193548 # Number of committed integer instructions. +system.cpu3.commit.int_insts 193540 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. +system.cpu3.commit.op_class_0::No_OpClass 40736 14.44% 14.44% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 114967 40.75% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.18% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 87454 31.00% 86.18% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 38998 13.82% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::total 282155 # Class of committed instruction system.cpu3.commit.bw_lim_events 818 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 458297 # The number of ROB reads -system.cpu3.rob.rob_writes 590554 # The number of ROB writes +system.cpu3.rob.rob_reads 458195 # The number of ROB reads +system.cpu3.rob.rob_writes 590518 # The number of ROB writes system.cpu3.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1385 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44892 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 236447 # Number of Instructions Simulated -system.cpu3.committedOps 236447 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 236447 # Number of Instructions Simulated -system.cpu3.cpi 0.748658 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.748658 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.335723 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.335723 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 429146 # number of integer regfile reads -system.cpu3.int_regfile_writes 199911 # number of integer regfile writes +system.cpu3.idleCycles 1387 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 44814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 236440 # Number of Instructions Simulated +system.cpu3.committedOps 236440 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 236440 # Number of Instructions Simulated +system.cpu3.cpi 0.748308 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.748308 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.336348 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.336348 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 429141 # number of integer regfile reads +system.cpu3.int_regfile_writes 199912 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 125103 # number of misc regfile reads +system.cpu3.misc_regfile_reads 125101 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.tags.replacements 319 # number of replacements -system.cpu3.icache.tags.tagsinuse 80.480006 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 19114 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 80.524551 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 19102 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 44.451163 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 44.423256 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.480006 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157188 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.157188 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.524551 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157275 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.157275 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 20019 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 20019 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 19114 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 19114 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 19114 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 19114 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 19114 # number of overall hits -system.cpu3.icache.overall_hits::total 19114 # number of overall hits +system.cpu3.icache.tags.tag_accesses 20007 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 20007 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 19102 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 19102 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 19102 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 19102 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 19102 # number of overall hits +system.cpu3.icache.overall_hits::total 19102 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses @@ -2490,18 +2632,18 @@ system.cpu3.icache.demand_miss_latency::cpu3.inst 6525745 system.cpu3.icache.demand_miss_latency::total 6525745 # number of demand (read+write) miss cycles system.cpu3.icache.overall_miss_latency::cpu3.inst 6525745 # number of overall miss cycles system.cpu3.icache.overall_miss_latency::total 6525745 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 19589 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 19589 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 19589 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 19589 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 19589 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 19589 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024248 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.024248 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024248 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.024248 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024248 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.024248 # miss rate for overall accesses +system.cpu3.icache.ReadReq_accesses::cpu3.inst 19577 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 19577 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 19577 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 19577 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 19577 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 19577 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024263 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.024263 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024263 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.024263 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024263 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.024263 # miss rate for overall accesses system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13738.410526 # average ReadReq miss latency system.cpu3.icache.ReadReq_avg_miss_latency::total 13738.410526 # average ReadReq miss latency system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency @@ -2534,12 +2676,12 @@ system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5298255 system.cpu3.icache.demand_mshr_miss_latency::total 5298255 # number of demand (read+write) MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5298255 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::total 5298255 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021951 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021951 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021951 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.021951 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021951 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.021951 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021965 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.021965 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.021965 # mshr miss rate for overall accesses system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average ReadReq mshr miss latency system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12321.523256 # average ReadReq mshr miss latency system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency @@ -2548,29 +2690,29 @@ system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12321.523256 system.cpu3.icache.overall_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.751493 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 44991 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.706550 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 44992 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1606.821429 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1606.857143 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.751493 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048343 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.048343 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.706550 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048255 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.048255 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 350966 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 350966 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 48333 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 48333 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 38794 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 38794 # number of WriteReq hits +system.cpu3.dcache.tags.tag_accesses 350946 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 350946 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 48327 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 48327 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 38795 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 38795 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 87127 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 87127 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 87127 # number of overall hits -system.cpu3.dcache.overall_hits::total 87127 # number of overall hits +system.cpu3.dcache.demand_hits::cpu3.data 87122 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 87122 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 87122 # number of overall hits +system.cpu3.dcache.overall_hits::total 87122 # number of overall hits system.cpu3.dcache.ReadReq_misses::cpu3.data 351 # number of ReadReq misses system.cpu3.dcache.ReadReq_misses::total 351 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses @@ -2581,28 +2723,28 @@ system.cpu3.dcache.demand_misses::cpu3.data 490 # system.cpu3.dcache.demand_misses::total 490 # number of demand (read+write) misses system.cpu3.dcache.overall_misses::cpu3.data 490 # number of overall misses system.cpu3.dcache.overall_misses::total 490 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4639136 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 4639136 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3479012 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3479012 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 512008 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 512008 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 8118148 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 8118148 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 8118148 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 8118148 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 48684 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 48684 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 38933 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 38933 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4621144 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 4621144 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3311512 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3311512 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 513008 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 513008 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 7932656 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7932656 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7932656 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7932656 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 48678 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 48678 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 38934 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 38934 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 87617 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 87617 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 87617 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 87617 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007210 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.007210 # miss rate for ReadReq accesses +system.cpu3.dcache.demand_accesses::cpu3.data 87612 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 87612 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 87612 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 87612 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007211 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.007211 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003570 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_miss_rate::total 0.003570 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses @@ -2611,16 +2753,16 @@ system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005593 system.cpu3.dcache.demand_miss_rate::total 0.005593 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005593 # miss rate for overall accesses system.cpu3.dcache.overall_miss_rate::total 0.005593 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13216.911681 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 13216.911681 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25028.863309 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 25028.863309 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9846.307692 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 9846.307692 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16567.648980 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 16567.648980 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16567.648980 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 16567.648980 # average overall miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13165.652422 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 13165.652422 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23823.827338 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 23823.827338 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9865.538462 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9865.538462 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16189.093878 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16189.093878 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2647,36 +2789,36 @@ system.cpu3.dcache.demand_mshr_misses::cpu3.data 260 system.cpu3.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses system.cpu3.dcache.overall_mshr_misses::cpu3.data 260 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1051018 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1051018 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1439238 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1439238 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 407992 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 407992 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2490256 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2490256 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2490256 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2490256 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003163 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003163 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1052517 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1052517 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1403488 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1403488 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 408992 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 408992 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2456005 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2456005 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2456005 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2456005 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003164 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003164 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002723 # mshr miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002723 # mshr miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.812500 # mshr miss rate for SwapReq accesses system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.812500 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002967 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.002967 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002967 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.002967 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6824.792208 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6824.792208 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13577.716981 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13577.716981 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7846 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7846 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9577.907692 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9577.907692 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9577.907692 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9577.907692 # average overall mshr miss latency +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.002968 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.002968 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6834.525974 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6834.525974 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13240.452830 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13240.452830 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7865.230769 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7865.230769 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 728e876c6..3bc9d35ce 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 202617 # Simulator instruction rate (inst/s) -host_op_rate 202616 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26236566 # Simulator tick rate (ticks/s) -host_mem_usage 297428 # Number of bytes of host memory used -host_seconds 3.34 # Real time elapsed on the host +host_inst_rate 1618143 # Simulator instruction rate (inst/s) +host_op_rate 1618081 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 209518099 # Simulator tick rate (ticks/s) +host_mem_usage 283888 # Number of bytes of host memory used +host_seconds 0.42 # Real time elapsed on the host sim_insts 677327 # Number of instructions simulated sim_ops 677327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -274,6 +274,41 @@ system.cpu0.num_busy_cycles 175415 # Nu system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.Branches 29689 # Number of branches fetched +system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction +system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction +system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 175388 # Class of executed instruction system.cpu0.icache.tags.replacements 215 # number of replacements system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. @@ -411,6 +446,41 @@ system.cpu1.num_busy_cycles 165421.275663 # N system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles system.cpu1.Branches 34390 # Number of branches fetched +system.cpu1.op_class::No_OpClass 25177 15.04% 15.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 73170 43.70% 58.74% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::MemRead 56341 33.65% 92.39% # Class of executed instruction +system.cpu1.op_class::MemWrite 12742 7.61% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 167430 # Class of executed instruction system.cpu1.icache.tags.replacements 278 # number of replacements system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. @@ -545,6 +615,41 @@ system.cpu2.num_busy_cycles 165358.048783 # N system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles system.cpu2.Branches 32652 # Number of branches fetched +system.cpu2.op_class::No_OpClass 23444 14.01% 14.01% # Class of executed instruction +system.cpu2.op_class::IntAlu 74873 44.74% 58.74% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::MemRead 52874 31.59% 90.34% # Class of executed instruction +system.cpu2.op_class::MemWrite 16175 9.66% 100.00% # Class of executed instruction +system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::total 167366 # Class of executed instruction system.cpu2.icache.tags.replacements 278 # number of replacements system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. @@ -679,6 +784,41 @@ system.cpu3.num_busy_cycles 165292.880154 # N system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles system.cpu3.Branches 33511 # Number of branches fetched +system.cpu3.op_class::No_OpClass 24299 14.52% 14.52% # Class of executed instruction +system.cpu3.op_class::IntAlu 73982 44.22% 58.75% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::MemRead 54586 32.63% 91.37% # Class of executed instruction +system.cpu3.op_class::MemWrite 14434 8.63% 100.00% # Class of executed instruction +system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::total 167301 # Class of executed instruction system.cpu3.icache.tags.replacements 279 # number of replacements system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 036213a3d..704fea740 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000263 # Nu sim_ticks 262794500 # Number of ticks simulated final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160692 # Simulator instruction rate (inst/s) -host_op_rate 160691 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63638702 # Simulator tick rate (ticks/s) -host_mem_usage 297424 # Number of bytes of host memory used -host_seconds 4.13 # Real time elapsed on the host +host_inst_rate 985745 # Simulator instruction rate (inst/s) +host_op_rate 985721 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 390370221 # Simulator tick rate (ticks/s) +host_mem_usage 283880 # Number of bytes of host memory used +host_seconds 0.67 # Real time elapsed on the host sim_insts 663567 # Number of instructions simulated sim_ops 663567 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -561,6 +561,41 @@ system.cpu0.num_busy_cycles 525589 # Nu system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.Branches 26897 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23624 14.89% 14.89% # Class of executed instruction +system.cpu0.op_class::IntAlu 60907 38.39% 53.29% # Class of executed instruction +system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::MemRead 49091 30.95% 84.23% # Class of executed instruction +system.cpu0.op_class::MemWrite 25014 15.77% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 158636 # Class of executed instruction system.cpu0.icache.tags.replacements 215 # number of replacements system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. @@ -794,6 +829,41 @@ system.cpu1.num_busy_cycles 456241.130205 # N system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles system.cpu1.Branches 31528 # Number of branches fetched +system.cpu1.op_class::No_OpClass 22316 13.65% 13.65% # Class of executed instruction +system.cpu1.op_class::IntAlu 75095 45.93% 59.58% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.58% # Class of executed instruction +system.cpu1.op_class::MemRead 49612 30.34% 89.92% # Class of executed instruction +system.cpu1.op_class::MemWrite 16480 10.08% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 163503 # Class of executed instruction system.cpu1.icache.tags.replacements 280 # number of replacements system.cpu1.icache.tags.tagsinuse 70.017504 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. @@ -1026,6 +1096,41 @@ system.cpu2.num_busy_cycles 455984.130695 # N system.cpu2.not_idle_fraction 0.867570 # Percentage of non-idle cycles system.cpu2.idle_fraction 0.132430 # Percentage of idle cycles system.cpu2.Branches 31596 # Number of branches fetched +system.cpu2.op_class::No_OpClass 22386 13.58% 13.58% # Class of executed instruction +system.cpu2.op_class::IntAlu 75723 45.92% 59.50% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.50% # Class of executed instruction +system.cpu2.op_class::MemRead 49752 30.17% 89.67% # Class of executed instruction +system.cpu2.op_class::MemWrite 17037 10.33% 100.00% # Class of executed instruction +system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::total 164898 # Class of executed instruction system.cpu2.icache.tags.replacements 280 # number of replacements system.cpu2.icache.tags.tagsinuse 67.624960 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. @@ -1258,6 +1363,41 @@ system.cpu3.num_busy_cycles 455718.131202 # N system.cpu3.not_idle_fraction 0.867063 # Percentage of non-idle cycles system.cpu3.idle_fraction 0.132937 # Percentage of idle cycles system.cpu3.Branches 39890 # Number of branches fetched +system.cpu3.op_class::No_OpClass 30652 17.35% 17.35% # Class of executed instruction +system.cpu3.op_class::IntAlu 73353 41.52% 58.86% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.86% # Class of executed instruction +system.cpu3.op_class::MemRead 66272 37.51% 96.37% # Class of executed instruction +system.cpu3.op_class::MemWrite 6411 3.63% 100.00% # Class of executed instruction +system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::total 176688 # Class of executed instruction system.cpu3.icache.tags.replacements 281 # number of replacements system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index c44d33a13..bc520582f 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,93 +4,99 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 24940417343 # Simulator tick rate (ticks/s) -host_mem_usage 228644 # Number of bytes of host memory used -host_seconds 4.01 # Real time elapsed on the host +host_tick_rate 14337554787 # Simulator tick rate (ticks/s) +host_mem_usage 228672 # Number of bytes of host memory used +host_seconds 6.97 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory -system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory -system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3333299 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu 2133311360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3333300 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3333300 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 213331200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 213331200 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu 106798016 # Number of bytes read from this memory +system.physmem.bytes_read::total 106798016 # Number of bytes read from this memory +system.physmem.bytes_written::cpu 106535680 # Number of bytes written to this memory +system.physmem.bytes_written::total 106535680 # Number of bytes written to this memory +system.physmem.num_reads::cpu 1668719 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1668719 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu 1664620 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1664620 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu 1067980160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1067980160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu 1065356800 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1065356800 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu 2133336960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2133336960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1668720 # Number of read requests accepted +system.physmem.writeReqs 1664620 # Number of write requests accepted +system.physmem.readBursts 1668720 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1664620 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 106797184 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 896 # Total number of bytes read from write queue +system.physmem.bytesWritten 106533952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 106798080 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 106535680 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 14 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 8 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 217600 # Per bank write bursts -system.physmem.perBankRdBursts::1 217600 # Per bank write bursts -system.physmem.perBankRdBursts::2 217600 # Per bank write bursts -system.physmem.perBankRdBursts::3 217600 # Per bank write bursts -system.physmem.perBankRdBursts::4 210100 # Per bank write bursts -system.physmem.perBankRdBursts::5 204800 # Per bank write bursts -system.physmem.perBankRdBursts::6 204800 # Per bank write bursts -system.physmem.perBankRdBursts::7 204800 # Per bank write bursts -system.physmem.perBankRdBursts::8 204800 # Per bank write bursts -system.physmem.perBankRdBursts::9 204800 # Per bank write bursts -system.physmem.perBankRdBursts::10 204800 # Per bank write bursts -system.physmem.perBankRdBursts::11 204800 # Per bank write bursts -system.physmem.perBankRdBursts::12 204800 # Per bank write bursts -system.physmem.perBankRdBursts::13 204800 # Per bank write bursts -system.physmem.perBankRdBursts::14 204800 # Per bank write bursts -system.physmem.perBankRdBursts::15 204800 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.perBankRdBursts::0 104195 # Per bank write bursts +system.physmem.perBankRdBursts::1 104188 # Per bank write bursts +system.physmem.perBankRdBursts::2 104541 # Per bank write bursts +system.physmem.perBankRdBursts::3 104589 # Per bank write bursts +system.physmem.perBankRdBursts::4 103994 # Per bank write bursts +system.physmem.perBankRdBursts::5 104203 # Per bank write bursts +system.physmem.perBankRdBursts::6 104803 # Per bank write bursts +system.physmem.perBankRdBursts::7 104557 # Per bank write bursts +system.physmem.perBankRdBursts::8 104630 # Per bank write bursts +system.physmem.perBankRdBursts::9 104040 # Per bank write bursts +system.physmem.perBankRdBursts::10 104372 # Per bank write bursts +system.physmem.perBankRdBursts::11 104177 # Per bank write bursts +system.physmem.perBankRdBursts::12 103805 # Per bank write bursts +system.physmem.perBankRdBursts::13 104138 # Per bank write bursts +system.physmem.perBankRdBursts::14 103922 # Per bank write bursts +system.physmem.perBankRdBursts::15 104552 # Per bank write bursts +system.physmem.perBankWrBursts::0 103587 # Per bank write bursts +system.physmem.perBankWrBursts::1 104082 # Per bank write bursts +system.physmem.perBankWrBursts::2 103950 # Per bank write bursts +system.physmem.perBankWrBursts::3 104334 # Per bank write bursts +system.physmem.perBankWrBursts::4 104264 # Per bank write bursts +system.physmem.perBankWrBursts::5 104509 # Per bank write bursts +system.physmem.perBankWrBursts::6 103927 # Per bank write bursts +system.physmem.perBankWrBursts::7 104060 # Per bank write bursts +system.physmem.perBankWrBursts::8 104076 # Per bank write bursts +system.physmem.perBankWrBursts::9 104072 # Per bank write bursts +system.physmem.perBankWrBursts::10 104151 # Per bank write bursts +system.physmem.perBankWrBursts::11 104328 # Per bank write bursts +system.physmem.perBankWrBursts::12 103712 # Per bank write bursts +system.physmem.perBankWrBursts::13 103871 # Per bank write bursts +system.physmem.perBankWrBursts::14 103773 # Per bank write bursts +system.physmem.perBankWrBursts::15 103897 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 99999960000 # Total gap between requests +system.physmem.totGap 99999960227 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3333300 # Read request sizes (log2) +system.physmem.readPktSize::6 1668720 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2967921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 224361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17049 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 17179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 12823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 17049 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 12820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 5416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1664620 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 766507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 779035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 72986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -110,48 +116,48 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 21583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 101142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 110031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 109380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 103714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 100305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 100049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 122199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 111635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 105240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 100495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 98624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 98614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 98524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 98476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 98391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -174,49 +180,89 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 195487 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1024 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1024.000000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 195487 100.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 195487 # Bytes accessed per row activation -system.physmem.totQLat 27932046800 # Total ticks spent queuing -system.physmem.totMemAccLat 91374259300 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 16666500000 # Total ticks spent in databus transfers -system.physmem.totBankLat 46775712500 # Total ticks spent accessing banks -system.physmem.avgQLat 8379.70 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14032.85 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 3296563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 64.713043 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 64.189923 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 23.988602 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3288788 99.76% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5620 0.17% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 32 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 32 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 32 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 32 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 32 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1963 0.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 3296563 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97746 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.071819 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 15.727304 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 106.831001 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 97745 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32768-34815 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97746 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97746 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.029781 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.939241 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.836351 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 73134 74.82% 74.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 545 0.56% 75.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 655 0.67% 76.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1612 1.65% 77.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 16208 16.58% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5168 5.29% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 147 0.15% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 85 0.09% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 66 0.07% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 49 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 29 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 26 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 16 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97746 # Writes before turning the bus around for reads +system.physmem.totQLat 58049969454 # Total ticks spent queuing +system.physmem.totMemAccLat 89338206954 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8343530000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34787.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27412.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2133.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2133.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53537.42 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1067.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1065.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1067.98 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1065.36 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 16.67 # Data bus utilization in percentage -system.physmem.busUtilRead 16.67 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.33 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3112095 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 30000.29 # Average gap between requests -system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.11 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 2133311360 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3333300 # Transaction distribution -system.membus.trans_dist::ReadResp 3333299 # Transaction distribution -system.membus.pkt_count_system.monitor-master::system.physmem.port 6666599 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6666599 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213331136 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 213331136 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 213331136 # Total data (bytes) -system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 17200626050 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 17.2 # Layer utilization (%) -system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets +system.physmem.busUtilRead 8.34 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 8.32 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.19 # Average write queue length when enqueuing +system.physmem.readRowHits 32203 # Number of row buffer hits during reads +system.physmem.writeRowHits 4525 # Number of row buffer hits during writes +system.physmem.readRowHitRate 1.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 0.27 # Row buffer hit rate for writes +system.physmem.avgGap 29999.93 # Average gap between requests +system.physmem.pageHitRate 1.10 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 5508849 # Time in different power states +system.physmem.memoryStateTime::REF 3339180000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 96654451752 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 2133336960 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1668720 # Transaction distribution +system.membus.trans_dist::ReadResp 1668719 # Transaction distribution +system.membus.trans_dist::WriteReq 1664620 # Transaction distribution +system.membus.trans_dist::WriteResp 1664620 # Transaction distribution +system.membus.pkt_count_system.monitor-master::system.physmem.port 6666679 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6666679 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213333696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 213333696 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 213333696 # Total data (bytes) +system.membus.reqLayer0.occupancy 11669983278 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 11.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 11409038076 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 11.4 # Layer utilization (%) +system.monitor.readBurstLengthHist::samples 1668720 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::stdev 0 # Histogram of burst lengths of transmitted packets @@ -236,40 +282,40 @@ system.monitor.readBurstLengthHist::48-51 0 0.00% 0.00% # H system.monitor.readBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets -system.monitor.readBurstLengthHist::64-67 3333300 100.00% 100.00% # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::64-67 1668720 100.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets -system.monitor.readBurstLengthHist::total 3333300 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::samples 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::mean nan # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::gmean nan # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::stdev nan # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::0 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::1 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::2 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::3 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::4 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::5 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::6 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::7 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::8 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::9 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::10 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::11 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::12 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::13 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::14 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::15 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::16 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::17 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::18 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::19 0 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::total 0 # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::total 1668720 # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::samples 1664620 # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::stdev 0 # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::0-3 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::4-7 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::8-11 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::12-15 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::16-19 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::20-23 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::24-27 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::28-31 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::32-35 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::36-39 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::40-43 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::44-47 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::48-51 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::64-67 1664620 100.00% 100.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::total 1664620 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::mean 2133311360 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 2133311357.360062 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 106664.726883 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::mean 1067980160 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 1064651766.271052 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 107759819.009425 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -277,172 +323,172 @@ system.monitor.readBandwidthHist::4.02653e+08-5.36871e+08 0 0.00 system.monitor.readBandwidthHist::5.36871e+08-6.71089e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::6.71089e+08-8.05306e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::8.05306e+08-9.39524e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::9.39524e+08-1.07374e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::1.07374e+09-1.20796e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::1.20796e+09-1.34218e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::1.34218e+09-1.4764e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::1.4764e+09-1.61061e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::1.61061e+09-1.74483e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::1.74483e+09-1.87905e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::1.87905e+09-2.01327e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::2.01327e+09-2.14748e+09 100 100.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::9.39524e+08-1.07374e+09 99 99.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::1.07374e+09-1.20796e+09 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::1.20796e+09-1.34218e+09 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::1.34218e+09-1.4764e+09 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::1.4764e+09-1.61061e+09 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::1.61061e+09-1.74483e+09 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::1.74483e+09-1.87905e+09 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::1.87905e+09-2.01327e+09 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::2.01327e+09-2.14748e+09 1 1.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.14748e+09-2.2817e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.2817e+09-2.41592e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.41592e+09-2.55014e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.55014e+09-2.68435e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::total 100 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.averageReadBandwidth 2133311360 0.00% 0.00% # Average read bandwidth (bytes/s) -system.monitor.totalReadBytes 213331136 # Number of bytes read +system.monitor.averageReadBandwidth 1067980160 0.00% 0.00% # Average read bandwidth (bytes/s) +system.monitor.totalReadBytes 106798016 # Number of bytes read system.monitor.writeBandwidthHist::samples 100 # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::mean 0 # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::mean 1065356800 # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::gmean 0 # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::stdev 0 # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::0 100 100.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::1 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::2 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::3 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::4 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::5 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::6 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::7 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::8 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::9 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::10 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::11 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::12 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::13 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::14 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::15 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::16 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::17 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::18 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::19 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::stdev 107770982.104450 # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::0-6.71089e+07 1 1.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::6.71089e+07-1.34218e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::1.34218e+08-2.01327e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::2.01327e+08-2.68435e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::2.68435e+08-3.35544e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::3.35544e+08-4.02653e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::4.02653e+08-4.69762e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::4.69762e+08-5.36871e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::5.36871e+08-6.0398e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::6.0398e+08-6.71089e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::6.71089e+08-7.38198e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::7.38198e+08-8.05306e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::8.05306e+08-8.72415e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::8.72415e+08-9.39524e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::9.39524e+08-1.00663e+09 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::1.00663e+09-1.07374e+09 29 29.00% 30.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::1.07374e+09-1.14085e+09 70 70.00% 100.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::1.14085e+09-1.20796e+09 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::1.20796e+09-1.27507e+09 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::1.27507e+09-1.34218e+09 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::total 100 # Histogram of write bandwidth (bytes/s) -system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s) -system.monitor.totalWrittenBytes 0 # Number of bytes written -system.monitor.readLatencyHist::samples 3333299 # Read request-response latency -system.monitor.readLatencyHist::mean 47438.751234 # Read request-response latency -system.monitor.readLatencyHist::gmean 42490.722724 # Read request-response latency -system.monitor.readLatencyHist::stdev 40033.411924 # Read request-response latency -system.monitor.readLatencyHist::0-32767 0 0.00% 0.00% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 3182634 95.48% 95.48% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 17049 0.51% 95.99% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 18238 0.55% 96.54% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 15993 0.48% 97.02% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 17049 0.51% 97.53% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 18238 0.55% 98.08% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 15990 0.48% 98.56% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 17052 0.51% 99.07% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 13881 0.42% 99.48% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 17175 0.52% 100.00% # Read request-response latency -system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::458752-491519 0 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::491520-524287 0 0.00% 100.00% # Read request-response latency +system.monitor.averageWriteBandwidth 1065356800 0.00% 0.00% # Average write bandwidth (bytes/s) +system.monitor.totalWrittenBytes 106535680 # Number of bytes written +system.monitor.readLatencyHist::samples 1668719 # Read request-response latency +system.monitor.readLatencyHist::mean 73576.537902 # Read request-response latency +system.monitor.readLatencyHist::gmean 68507.812375 # Read request-response latency +system.monitor.readLatencyHist::stdev 39270.153648 # Read request-response latency +system.monitor.readLatencyHist::0-32767 14 0.00% 0.00% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 454232 27.22% 27.22% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 1043171 62.51% 89.73% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 73085 4.38% 94.11% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 46931 2.81% 96.93% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 12458 0.75% 97.67% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 7854 0.47% 98.14% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 7990 0.48% 98.62% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 8124 0.49% 99.11% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 7849 0.47% 99.58% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 4246 0.25% 99.83% # Read request-response latency +system.monitor.readLatencyHist::360448-393215 1108 0.07% 99.90% # Read request-response latency +system.monitor.readLatencyHist::393216-425983 866 0.05% 99.95% # Read request-response latency +system.monitor.readLatencyHist::425984-458751 601 0.04% 99.99% # Read request-response latency +system.monitor.readLatencyHist::458752-491519 183 0.01% 100.00% # Read request-response latency +system.monitor.readLatencyHist::491520-524287 7 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::524288-557055 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::total 3333299 # Read request-response latency -system.monitor.writeLatencyHist::samples 0 # Write request-response latency -system.monitor.writeLatencyHist::mean nan # Write request-response latency -system.monitor.writeLatencyHist::gmean nan # Write request-response latency -system.monitor.writeLatencyHist::stdev nan # Write request-response latency -system.monitor.writeLatencyHist::0 0 # Write request-response latency -system.monitor.writeLatencyHist::1 0 # Write request-response latency -system.monitor.writeLatencyHist::2 0 # Write request-response latency -system.monitor.writeLatencyHist::3 0 # Write request-response latency -system.monitor.writeLatencyHist::4 0 # Write request-response latency -system.monitor.writeLatencyHist::5 0 # Write request-response latency -system.monitor.writeLatencyHist::6 0 # Write request-response latency -system.monitor.writeLatencyHist::7 0 # Write request-response latency -system.monitor.writeLatencyHist::8 0 # Write request-response latency -system.monitor.writeLatencyHist::9 0 # Write request-response latency -system.monitor.writeLatencyHist::10 0 # Write request-response latency -system.monitor.writeLatencyHist::11 0 # Write request-response latency -system.monitor.writeLatencyHist::12 0 # Write request-response latency -system.monitor.writeLatencyHist::13 0 # Write request-response latency -system.monitor.writeLatencyHist::14 0 # Write request-response latency -system.monitor.writeLatencyHist::15 0 # Write request-response latency -system.monitor.writeLatencyHist::16 0 # Write request-response latency -system.monitor.writeLatencyHist::17 0 # Write request-response latency -system.monitor.writeLatencyHist::18 0 # Write request-response latency -system.monitor.writeLatencyHist::19 0 # Write request-response latency -system.monitor.writeLatencyHist::total 0 # Write request-response latency -system.monitor.ittReadRead::samples 3333299 # Read-to-read inter transaction time -system.monitor.ittReadRead::mean 30000.297003 # Read-to-read inter transaction time -system.monitor.ittReadRead::stdev 54.497186 # Read-to-read inter transaction time +system.monitor.readLatencyHist::total 1668719 # Read request-response latency +system.monitor.writeLatencyHist::samples 1664620 # Write request-response latency +system.monitor.writeLatencyHist::mean 10570.968616 # Write request-response latency +system.monitor.writeLatencyHist::gmean 10511.906115 # Write request-response latency +system.monitor.writeLatencyHist::stdev 1198.829619 # Write request-response latency +system.monitor.writeLatencyHist::0-1023 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::1024-2047 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::2048-3071 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::3072-4095 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::4096-5119 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::5120-6143 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::6144-7167 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::7168-8191 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::8192-9215 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::9216-10239 1266039 76.06% 76.06% # Write request-response latency +system.monitor.writeLatencyHist::10240-11263 92649 5.57% 81.62% # Write request-response latency +system.monitor.writeLatencyHist::11264-12287 113174 6.80% 88.42% # Write request-response latency +system.monitor.writeLatencyHist::12288-13311 92637 5.57% 93.99% # Write request-response latency +system.monitor.writeLatencyHist::13312-14335 63204 3.80% 97.78% # Write request-response latency +system.monitor.writeLatencyHist::14336-15359 32757 1.97% 99.75% # Write request-response latency +system.monitor.writeLatencyHist::15360-16383 4158 0.25% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::16384-17407 2 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::17408-18431 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::18432-19455 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::19456-20479 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::total 1664620 # Write request-response latency +system.monitor.ittReadRead::samples 1668719 # Read-to-read inter transaction time +system.monitor.ittReadRead::mean 59926.183034 # Read-to-read inter transaction time +system.monitor.ittReadRead::stdev 42757.593151 # Read-to-read inter transaction time system.monitor.ittReadRead::underflows 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::1-5000 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::5001-10000 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::10001-15000 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::15001-20000 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::20001-25000 0 0.00% 0.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::25001-30000 3333200 100.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::30001-35000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::35001-40000 99 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::40001-45000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::45001-50000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::50001-55000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::55001-60000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::60001-65000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::65001-70000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::70001-75000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::75001-80000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::80001-85000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::85001-90000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::90001-95000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::95001-100000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::overflows 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::min_value 30000 # Read-to-read inter transaction time -system.monitor.ittReadRead::max_value 40000 # Read-to-read inter transaction time -system.monitor.ittReadRead::total 3333299 # Read-to-read inter transaction time -system.monitor.ittWriteWrite::samples 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::mean nan # Write-to-write inter transaction time -system.monitor.ittWriteWrite::stdev nan # Write-to-write inter transaction time -system.monitor.ittWriteWrite::underflows 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::1-5000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::5001-10000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::10001-15000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::15001-20000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::20001-25000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::25001-30000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::30001-35000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::35001-40000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::40001-45000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::45001-50000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::50001-55000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::55001-60000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::60001-65000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::65001-70000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::70001-75000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::75001-80000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::80001-85000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::85001-90000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::90001-95000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::95001-100000 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::overflows 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::min_value 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::max_value 0 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::total 0 # Write-to-write inter transaction time -system.monitor.ittReqReq::samples 3333299 # Request-to-request inter transaction time -system.monitor.ittReqReq::mean 30000.297003 # Request-to-request inter transaction time -system.monitor.ittReqReq::stdev 54.497186 # Request-to-request inter transaction time +system.monitor.ittReadRead::25001-30000 438300 26.27% 26.27% # Read-to-read inter transaction time +system.monitor.ittReadRead::30001-35000 404751 24.26% 50.52% # Read-to-read inter transaction time +system.monitor.ittReadRead::35001-40000 3 0.00% 50.52% # Read-to-read inter transaction time +system.monitor.ittReadRead::40001-45000 3 0.00% 50.52% # Read-to-read inter transaction time +system.monitor.ittReadRead::45001-50000 0 0.00% 50.52% # Read-to-read inter transaction time +system.monitor.ittReadRead::50001-55000 3 0.00% 50.52% # Read-to-read inter transaction time +system.monitor.ittReadRead::55001-60000 204975 12.28% 62.80% # Read-to-read inter transaction time +system.monitor.ittReadRead::60001-65000 204546 12.26% 75.06% # Read-to-read inter transaction time +system.monitor.ittReadRead::65001-70000 3 0.00% 75.06% # Read-to-read inter transaction time +system.monitor.ittReadRead::70001-75000 3 0.00% 75.06% # Read-to-read inter transaction time +system.monitor.ittReadRead::75001-80000 2 0.00% 75.06% # Read-to-read inter transaction time +system.monitor.ittReadRead::80001-85000 527 0.03% 75.09% # Read-to-read inter transaction time +system.monitor.ittReadRead::85001-90000 102490 6.14% 81.24% # Read-to-read inter transaction time +system.monitor.ittReadRead::90001-95000 102495 6.14% 87.38% # Read-to-read inter transaction time +system.monitor.ittReadRead::95001-100000 551 0.03% 87.41% # Read-to-read inter transaction time +system.monitor.ittReadRead::overflows 210067 12.59% 100.00% # Read-to-read inter transaction time +system.monitor.ittReadRead::min_value 28000 # Read-to-read inter transaction time +system.monitor.ittReadRead::max_value 1041420 # Read-to-read inter transaction time +system.monitor.ittReadRead::total 1668719 # Read-to-read inter transaction time +system.monitor.ittWriteWrite::samples 1664619 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::mean 59472.389997 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::stdev 41840.398153 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::underflows 0 0.00% 0.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::1-5000 0 0.00% 0.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::5001-10000 0 0.00% 0.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::10001-15000 0 0.00% 0.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::15001-20000 0 0.00% 0.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::20001-25000 0 0.00% 0.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::25001-30000 419825 25.22% 25.22% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::30001-35000 419112 25.18% 50.40% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::35001-40000 4 0.00% 50.40% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::40001-45000 6 0.00% 50.40% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::45001-50000 6 0.00% 50.40% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::50001-55000 6 0.00% 50.40% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::55001-60000 208578 12.53% 62.93% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::60001-65000 207985 12.49% 75.42% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::65001-70000 3 0.00% 75.42% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::70001-75000 3 0.00% 75.42% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::75001-80000 3 0.00% 75.42% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::80001-85000 552 0.03% 75.46% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::85001-90000 102802 6.18% 81.63% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::90001-95000 102817 6.18% 87.81% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::95001-100000 552 0.03% 87.84% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::overflows 202365 12.16% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::min_value 28000 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::max_value 598079 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::total 1664619 # Write-to-write inter transaction time +system.monitor.ittReqReq::samples 3333339 # Request-to-request inter transaction time +system.monitor.ittReqReq::mean 29999.937068 # Request-to-request inter transaction time +system.monitor.ittReqReq::stdev 1278.967916 # Request-to-request inter transaction time system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::1-5000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::5001-10000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::10001-15000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::15001-20000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::20001-25000 0 0.00% 0.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::25001-30000 3333200 100.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::30001-35000 0 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::35001-40000 99 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::40001-45000 0 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::45001-50000 0 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::50001-55000 0 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::55001-60000 0 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::60001-65000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::25001-30000 1684541 50.54% 50.54% # Request-to-request inter transaction time +system.monitor.ittReqReq::30001-35000 1648718 49.46% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::35001-40000 18 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::40001-45000 15 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::45001-50000 11 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::50001-55000 20 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::55001-60000 13 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::60001-65000 2 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::65001-70000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::70001-75000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::75001-80000 0 0.00% 100.00% # Request-to-request inter transaction time @@ -450,22 +496,22 @@ system.monitor.ittReqReq::80001-85000 0 0.00% 100.00% # Re system.monitor.ittReqReq::85001-90000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::overflows 0 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::min_value 30000 # Request-to-request inter transaction time -system.monitor.ittReqReq::max_value 40000 # Request-to-request inter transaction time -system.monitor.ittReqReq::total 3333299 # Request-to-request inter transaction time +system.monitor.ittReqReq::overflows 1 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::min_value 28000 # Request-to-request inter transaction time +system.monitor.ittReqReq::max_value 1041420 # Request-to-request inter transaction time +system.monitor.ittReqReq::total 3333339 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions -system.monitor.outstandingReadsHist::mean 1.290000 # Outstanding read transactions -system.monitor.outstandingReadsHist::gmean 1.120561 # Outstanding read transactions -system.monitor.outstandingReadsHist::stdev 1.139688 # Outstanding read transactions -system.monitor.outstandingReadsHist::0 0 0.00% 0.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::1 92 92.00% 92.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::2 2 2.00% 94.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::3 0 0.00% 94.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::4 3 3.00% 97.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::5 0 0.00% 97.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::6 0 0.00% 97.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::7 3 3.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 1.030000 # Outstanding read transactions +system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 0.881402 # Outstanding read transactions +system.monitor.outstandingReadsHist::0 28 28.00% 28.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 47 47.00% 75.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 21 21.00% 96.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::3 3 3.00% 99.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::4 0 0.00% 99.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::5 1 1.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::6 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::7 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::8 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::9 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::10 0 0.00% 100.00% # Outstanding read transactions @@ -480,11 +526,11 @@ system.monitor.outstandingReadsHist::18 0 0.00% 100.00% # Ou system.monitor.outstandingReadsHist::19 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::total 100 # Outstanding read transactions system.monitor.outstandingWritesHist::samples 100 # Outstanding write transactions -system.monitor.outstandingWritesHist::mean 0 # Outstanding write transactions +system.monitor.outstandingWritesHist::mean 0.150000 # Outstanding write transactions system.monitor.outstandingWritesHist::gmean 0 # Outstanding write transactions -system.monitor.outstandingWritesHist::stdev 0 # Outstanding write transactions -system.monitor.outstandingWritesHist::0 100 100.00% 100.00% # Outstanding write transactions -system.monitor.outstandingWritesHist::1 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::stdev 0.358870 # Outstanding write transactions +system.monitor.outstandingWritesHist::0 85 85.00% 85.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::1 15 15.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::2 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::3 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::4 0 0.00% 100.00% # Outstanding write transactions @@ -505,9 +551,9 @@ system.monitor.outstandingWritesHist::18 0 0.00% 100.00% # Ou system.monitor.outstandingWritesHist::19 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::total 100 # Outstanding write transactions system.monitor.readTransHist::samples 100 # Histogram of read transactions per sample period -system.monitor.readTransHist::mean 33333 # Histogram of read transactions per sample period -system.monitor.readTransHist::gmean 33333.000000 # Histogram of read transactions per sample period -system.monitor.readTransHist::stdev 0 # Histogram of read transactions per sample period +system.monitor.readTransHist::mean 16687.200000 # Histogram of read transactions per sample period +system.monitor.readTransHist::gmean 16635.188141 # Histogram of read transactions per sample period +system.monitor.readTransHist::stdev 1683.853859 # Histogram of read transactions per sample period system.monitor.readTransHist::0-2047 0 0.00% 0.00% # Histogram of read transactions per sample period system.monitor.readTransHist::2048-4095 0 0.00% 0.00% # Histogram of read transactions per sample period system.monitor.readTransHist::4096-6143 0 0.00% 0.00% # Histogram of read transactions per sample period @@ -515,46 +561,46 @@ system.monitor.readTransHist::6144-8191 0 0.00% 0.00% # Hi system.monitor.readTransHist::8192-10239 0 0.00% 0.00% # Histogram of read transactions per sample period system.monitor.readTransHist::10240-12287 0 0.00% 0.00% # Histogram of read transactions per sample period system.monitor.readTransHist::12288-14335 0 0.00% 0.00% # Histogram of read transactions per sample period -system.monitor.readTransHist::14336-16383 0 0.00% 0.00% # Histogram of read transactions per sample period -system.monitor.readTransHist::16384-18431 0 0.00% 0.00% # Histogram of read transactions per sample period -system.monitor.readTransHist::18432-20479 0 0.00% 0.00% # Histogram of read transactions per sample period -system.monitor.readTransHist::20480-22527 0 0.00% 0.00% # Histogram of read transactions per sample period -system.monitor.readTransHist::22528-24575 0 0.00% 0.00% # Histogram of read transactions per sample period -system.monitor.readTransHist::24576-26623 0 0.00% 0.00% # Histogram of read transactions per sample period -system.monitor.readTransHist::26624-28671 0 0.00% 0.00% # Histogram of read transactions per sample period -system.monitor.readTransHist::28672-30719 0 0.00% 0.00% # Histogram of read transactions per sample period -system.monitor.readTransHist::30720-32767 0 0.00% 0.00% # Histogram of read transactions per sample period -system.monitor.readTransHist::32768-34815 100 100.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::14336-16383 5 5.00% 5.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::16384-18431 94 94.00% 99.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::18432-20479 0 0.00% 99.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::20480-22527 0 0.00% 99.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::22528-24575 0 0.00% 99.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::24576-26623 0 0.00% 99.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::26624-28671 0 0.00% 99.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::28672-30719 0 0.00% 99.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::30720-32767 0 0.00% 99.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::32768-34815 1 1.00% 100.00% # Histogram of read transactions per sample period system.monitor.readTransHist::34816-36863 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.readTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.readTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.readTransHist::total 100 # Histogram of read transactions per sample period system.monitor.writeTransHist::samples 100 # Histogram of read transactions per sample period -system.monitor.writeTransHist::mean 0 # Histogram of read transactions per sample period +system.monitor.writeTransHist::mean 16646.200000 # Histogram of read transactions per sample period system.monitor.writeTransHist::gmean 0 # Histogram of read transactions per sample period -system.monitor.writeTransHist::stdev 0 # Histogram of read transactions per sample period -system.monitor.writeTransHist::0 100 100.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::1 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::2 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::3 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::4 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::5 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::6 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::7 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::8 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::9 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::10 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::11 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::12 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::13 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::14 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::15 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::16 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::17 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period -system.monitor.writeTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::stdev 1683.921595 # Histogram of read transactions per sample period +system.monitor.writeTransHist::0-1023 1 1.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::1024-2047 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::2048-3071 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::3072-4095 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::4096-5119 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::5120-6143 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::6144-7167 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::7168-8191 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::8192-9215 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::9216-10239 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::10240-11263 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::11264-12287 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::12288-13311 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::13312-14335 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::14336-15359 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::15360-16383 0 0.00% 1.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::16384-17407 99 99.00% 100.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::17408-18431 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::18432-19455 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::19456-20479 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period -system.cpu.numPackets 3333300 # Number of packets generated +system.cpu.numPackets 3333340 # Number of packets generated system.cpu.numRetries 0 # Number of retries system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks) |