diff options
Diffstat (limited to 'tests/quick/se')
112 files changed, 15132 insertions, 0 deletions
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini new file mode 100644 index 000000000..bc26b879f --- /dev/null +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -0,0 +1,172 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=vortex lendian.raw +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..506aa6e28 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..faff61794 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,11 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:27:58 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 44221003000 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg new file mode 100644 index 000000000..472b08431 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg @@ -0,0 +1,158 @@ + + SYSTEM TYPE... + __ZTC__ := False + __UNIX__ := True + __RISC__ := True + SPEC_CPU2000_LP64 := True + __MAC__ := False + __BCC__ := False + __BORLANDC__ := False + __GUI__ := False + __WTC__ := False + __HP__ := False + + CODE OPTIONS... + __MACROIZE_HM__ := True + __MACROIZE_MEM__ := True + ENV01 := True + USE_HPP_STYPE_HDRS := False + USE_H_STYPE_HDRS := False + + CODE INCLUSION PARAMETERS... + INCLUDE_ALL_CODE := False + INCLUDE_DELETE_CODE := True + __SWAP_GRP_POS__ := True + __INCLUDE_MTRX__ := False + __BAD_CODE__ := False + API_INCLUDE := False + BE_CAREFUL := False + OLDWAY := False + NOTUSED := False + + SYSTEM PARAMETERS... + EXT_ENUM := 999999999L + CHUNK_CONSTANT := 55555555 + CORE_CONSTANT := 55555555 + CORE_LIMIT := 20971520 + CorePage_Size := 384000 + ALIGN_BYTES := True + CORE_BLOCK_ALIGN := 8 + FAR_MEM := False + + MEMORY MANAGEMENT PARAMETERS... + SYSTEM_ALLOC := True + SYSTEM_FREESTORE := True + __NO_DISKCACHE__ := False + __FREEZE_VCHUNKS__ := True + __FREEZE_GRP_PACKETS__ := True + __MINIMIZE_TREE_CACHE__:= True + + SYSTEM STD PARAMETERS... + __STDOUT__ := False + NULL := 0 + LPTR := False + False_Status := 1 + True_Status := 0 + LARGE := True + TWOBYTE_BOOL := False + __NOSTR__ := False + + MEMORY VALIDATION PARAMETERS... + CORE_CRC_CHECK := False + VALIDATE_MEM_CHUNKS := False + + SYSTEM DEBUG OPTIONS... + DEBUG := False + MCSTAT := False + TRACKBACK := False + FLUSH_FILES := False + DEBUG_CORE0 := False + DEBUG_RISC := False + __TREE_BUG__ := False + __TRACK_FILE_READS__ := False + PAGE_SPACE := False + LEAVE_NO_TRACE := True + NULL_TRACE_STRS := False + + TIME PARAMETERS... + CLOCK_IS_LONG := False + __DISPLAY_TIME__ := False + __TREE_TIME__ := False + __DISPLAY_ERRORS__ := False + + API MACROS... + __BMT01__ := True + OPTIMIZE := True + + END OF DEFINES. + + + + ... IMPLODE MEMORY ... + + SWAP to DiskCache := False + + FREEZE_GRP_PACKETS:= True + + QueBug := 1000 + + sizeof(boolean) = 4 + sizeof(sizetype) = 4 + sizeof(chunkstruc) = 32 + + sizeof(shorttype ) = 2 + sizeof(idtype ) = 2 + sizeof(sizetype ) = 4 + sizeof(indextype ) = 4 + sizeof(numtype ) = 4 + sizeof(handletype) = 4 + sizeof(tokentype ) = 8 + + sizeof(short ) = 2 + sizeof(int ) = 4 + + sizeof(lt64 ) = 4 + sizeof(farlongtype) = 4 + sizeof(long ) = 8 + sizeof(longaddr ) = 8 + + sizeof(float ) = 4 + sizeof(double ) = 8 + + sizeof(addrtype ) = 8 + sizeof(char * ) = 8 + ALLOC CORE_1 :: 16 + BHOOLE NATH + + OPEN File ./input/lendian.rnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 2030c0 + DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] + DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] + DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] + DB Handle Chunk's StackPtr = 20797 + + DB[ 1] LOADED; Handles= 20797 + KERNEL in CORE[ 1] Restored @ 4005c800 + + OPEN File ./input/lendian.wnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 21c40 + DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] + DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] + DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] + DB Handle Chunk's StackPtr = 17 + + DB[ 2] LOADED; Handles= 17 + VORTEx_Status == -8 || fffffff8 + + BE HERE NOW !!! + + + + ... VORTEx ON LINE ... + + + ... END OF SESSION ... diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every <mod 0>Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD <Query0> for <Part2> class:: + + if (link[1].length >= 5) :: + + Build Query2 for <Address> class:: + + if (State == CA || State == T*) + + Build Query1 for <Person> class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD <Query3> for <DrawObj> class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD <Query4> for <NamedDrawObj> class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET <DrawObjs> entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET <NamedDrawObjs> entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET <LibRectangles> entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST <DbRectangles> entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET <PersonNames > entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=<True>; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + <Part2 > Asserts = 2; NULL Asserts = 3. + <DrawObj > Asserts = 0; NULL Asserts = 5. + <NamedObj > Asserts = 0; NULL Asserts = 0. + <Person > Asserts = 0; NULL Asserts = 5. + <TestObj > Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=<True>; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt new file mode 100644 index 000000000..db2ebe7dc --- /dev/null +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,152 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.044221 # Number of seconds simulated +sim_ticks 44221003000 # Number of ticks simulated +final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 2813944 # Simulator instruction rate (inst/s) +host_op_rate 2813942 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1408584494 # Simulator tick rate (ticks/s) +host_mem_usage 287952 # Number of bytes of host memory used +host_seconds 31.39 # Real time elapsed on the host +sim_insts 88340673 # Number of instructions simulated +sim_ops 88340673 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory +system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory +system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory +system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory +system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 108714711 # Transaction distribution +system.membus.trans_dist::ReadResp 108714711 # Transaction distribution +system.membus.trans_dist::WriteReq 14613377 # Transaction distribution +system.membus.trans_dist::WriteResp 14613377 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 123328088 # Request fanout histogram +system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram +system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 123328088 # Request fanout histogram +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 20276638 # DTB read hits +system.cpu.dtb.read_misses 90148 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 20366786 # DTB read accesses +system.cpu.dtb.write_hits 14613377 # DTB write hits +system.cpu.dtb.write_misses 7252 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 14620629 # DTB write accesses +system.cpu.dtb.data_hits 34890015 # DTB hits +system.cpu.dtb.data_misses 97400 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 34987415 # DTB accesses +system.cpu.itb.fetch_hits 88438073 # ITB hits +system.cpu.itb.fetch_misses 3934 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 88442007 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.numCycles 88442007 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 88340673 # Number of instructions committed +system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses +system.cpu.num_func_calls 3321606 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls +system.cpu.num_int_insts 78039444 # number of integer instructions +system.cpu.num_fp_insts 267757 # number of float instructions +system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read +system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written +system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read +system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written +system.cpu.num_mem_refs 34987415 # number of memory refs +system.cpu.num_load_insts 20366786 # Number of load instructions +system.cpu.num_store_insts 14620629 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 88442007 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 13754477 # Number of branches fetched +system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction +system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction +system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction +system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction +system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction +system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction +system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction +system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction +system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 88438073 # Class of executed instruction + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini new file mode 100644 index 000000000..5ccaad7e0 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -0,0 +1,285 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=vortex lendian.raw +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..506aa6e28 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..b6a75fdf5 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,11 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:28:33 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 133634727000 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg new file mode 100644 index 000000000..472b08431 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg @@ -0,0 +1,158 @@ + + SYSTEM TYPE... + __ZTC__ := False + __UNIX__ := True + __RISC__ := True + SPEC_CPU2000_LP64 := True + __MAC__ := False + __BCC__ := False + __BORLANDC__ := False + __GUI__ := False + __WTC__ := False + __HP__ := False + + CODE OPTIONS... + __MACROIZE_HM__ := True + __MACROIZE_MEM__ := True + ENV01 := True + USE_HPP_STYPE_HDRS := False + USE_H_STYPE_HDRS := False + + CODE INCLUSION PARAMETERS... + INCLUDE_ALL_CODE := False + INCLUDE_DELETE_CODE := True + __SWAP_GRP_POS__ := True + __INCLUDE_MTRX__ := False + __BAD_CODE__ := False + API_INCLUDE := False + BE_CAREFUL := False + OLDWAY := False + NOTUSED := False + + SYSTEM PARAMETERS... + EXT_ENUM := 999999999L + CHUNK_CONSTANT := 55555555 + CORE_CONSTANT := 55555555 + CORE_LIMIT := 20971520 + CorePage_Size := 384000 + ALIGN_BYTES := True + CORE_BLOCK_ALIGN := 8 + FAR_MEM := False + + MEMORY MANAGEMENT PARAMETERS... + SYSTEM_ALLOC := True + SYSTEM_FREESTORE := True + __NO_DISKCACHE__ := False + __FREEZE_VCHUNKS__ := True + __FREEZE_GRP_PACKETS__ := True + __MINIMIZE_TREE_CACHE__:= True + + SYSTEM STD PARAMETERS... + __STDOUT__ := False + NULL := 0 + LPTR := False + False_Status := 1 + True_Status := 0 + LARGE := True + TWOBYTE_BOOL := False + __NOSTR__ := False + + MEMORY VALIDATION PARAMETERS... + CORE_CRC_CHECK := False + VALIDATE_MEM_CHUNKS := False + + SYSTEM DEBUG OPTIONS... + DEBUG := False + MCSTAT := False + TRACKBACK := False + FLUSH_FILES := False + DEBUG_CORE0 := False + DEBUG_RISC := False + __TREE_BUG__ := False + __TRACK_FILE_READS__ := False + PAGE_SPACE := False + LEAVE_NO_TRACE := True + NULL_TRACE_STRS := False + + TIME PARAMETERS... + CLOCK_IS_LONG := False + __DISPLAY_TIME__ := False + __TREE_TIME__ := False + __DISPLAY_ERRORS__ := False + + API MACROS... + __BMT01__ := True + OPTIMIZE := True + + END OF DEFINES. + + + + ... IMPLODE MEMORY ... + + SWAP to DiskCache := False + + FREEZE_GRP_PACKETS:= True + + QueBug := 1000 + + sizeof(boolean) = 4 + sizeof(sizetype) = 4 + sizeof(chunkstruc) = 32 + + sizeof(shorttype ) = 2 + sizeof(idtype ) = 2 + sizeof(sizetype ) = 4 + sizeof(indextype ) = 4 + sizeof(numtype ) = 4 + sizeof(handletype) = 4 + sizeof(tokentype ) = 8 + + sizeof(short ) = 2 + sizeof(int ) = 4 + + sizeof(lt64 ) = 4 + sizeof(farlongtype) = 4 + sizeof(long ) = 8 + sizeof(longaddr ) = 8 + + sizeof(float ) = 4 + sizeof(double ) = 8 + + sizeof(addrtype ) = 8 + sizeof(char * ) = 8 + ALLOC CORE_1 :: 16 + BHOOLE NATH + + OPEN File ./input/lendian.rnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 2030c0 + DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] + DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] + DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] + DB Handle Chunk's StackPtr = 20797 + + DB[ 1] LOADED; Handles= 20797 + KERNEL in CORE[ 1] Restored @ 4005c800 + + OPEN File ./input/lendian.wnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 21c40 + DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] + DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] + DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] + DB Handle Chunk's StackPtr = 17 + + DB[ 2] LOADED; Handles= 17 + VORTEx_Status == -8 || fffffff8 + + BE HERE NOW !!! + + + + ... VORTEx ON LINE ... + + + ... END OF SESSION ... diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every <mod 0>Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD <Query0> for <Part2> class:: + + if (link[1].length >= 5) :: + + Build Query2 for <Address> class:: + + if (State == CA || State == T*) + + Build Query1 for <Person> class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD <Query3> for <DrawObj> class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD <Query4> for <NamedDrawObj> class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET <DrawObjs> entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET <NamedDrawObjs> entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET <LibRectangles> entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST <DbRectangles> entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET <PersonNames > entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=<True>; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + <Part2 > Asserts = 2; NULL Asserts = 3. + <DrawObj > Asserts = 0; NULL Asserts = 5. + <NamedObj > Asserts = 0; NULL Asserts = 0. + <Person > Asserts = 0; NULL Asserts = 5. + <TestObj > Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=<True>; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt new file mode 100644 index 000000000..987ba828d --- /dev/null +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,525 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.133634 # Number of seconds simulated +sim_ticks 133634149500 # Number of ticks simulated +final_tick 133634149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1329181 # Simulator instruction rate (inst/s) +host_op_rate 1329181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2010669405 # Simulator tick rate (ticks/s) +host_mem_usage 301232 # Number of bytes of host memory used +host_seconds 66.46 # Real time elapsed on the host +sim_insts 88340673 # Number of instructions simulated +sim_ops 88340673 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10136896 # Number of bytes read from this memory +system.physmem.bytes_read::total 10569792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 432896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 432896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7294848 # Number of bytes written to this memory +system.physmem.bytes_written::total 7294848 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6764 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158389 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory +system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 3239411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75855581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 79094992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3239411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3239411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54588202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54588202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54588202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3239411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75855581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 133683195 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 20276638 # DTB read hits +system.cpu.dtb.read_misses 90148 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 20366786 # DTB read accesses +system.cpu.dtb.write_hits 14613377 # DTB write hits +system.cpu.dtb.write_misses 7252 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 14620629 # DTB write accesses +system.cpu.dtb.data_hits 34890015 # DTB hits +system.cpu.dtb.data_misses 97400 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 34987415 # DTB accesses +system.cpu.itb.fetch_hits 88438074 # ITB hits +system.cpu.itb.fetch_misses 3934 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 88442008 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.numCycles 267268299 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 88340673 # Number of instructions committed +system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses +system.cpu.num_func_calls 3321606 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls +system.cpu.num_int_insts 78039444 # number of integer instructions +system.cpu.num_fp_insts 267757 # number of float instructions +system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read +system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written +system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read +system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written +system.cpu.num_mem_refs 34987415 # number of memory refs +system.cpu.num_load_insts 20366786 # Number of load instructions +system.cpu.num_store_insts 14620629 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 267268299 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 13754477 # Number of branches fetched +system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction +system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction +system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction +system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction +system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction +system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction +system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction +system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction +system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 88438073 # Class of executed instruction +system.cpu.dcache.tags.replacements 200248 # number of replacements +system.cpu.dcache.tags.tagsinuse 4078.863526 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 936464000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863526 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits +system.cpu.dcache.overall_hits::total 34685671 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses +system.cpu.dcache.overall_misses::total 204344 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945427000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1945427000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363527000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7363527000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9308954000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9308954000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9308954000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9308954000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32015.057763 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32015.057763 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.900347 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.900347 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45555.308695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45555.308695 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks +system.cpu.dcache.writebacks::total 168375 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1854278000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1854278000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7148160000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7148160000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9002438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9002438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9002438000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9002438000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30515.057763 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30515.057763 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49785.900347 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49785.900347 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 74391 # number of replacements +system.cpu.icache.tags.tagsinuse 1871.686268 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686268 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses +system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88361638 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88361638 # number of overall hits +system.cpu.icache.overall_hits::total 88361638 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 76436 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 76436 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 76436 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses +system.cpu.icache.overall_misses::total 76436 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1277887500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1277887500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1277887500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1277887500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1277887500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1277887500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 88438074 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000864 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16718.398399 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16718.398399 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16718.398399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16718.398399 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1163233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1163233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1163233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1163233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1163233500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1163233500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15218.398399 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15218.398399 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 131235 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30728.805700 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27298.442194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.509533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853974 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.833082 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32056 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 654 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9977 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21193 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 117 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978271 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3900109 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3900109 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 69672 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33258 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 102930 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168375 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168375 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12697 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12697 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 69672 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 45955 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 115627 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 69672 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 45955 # number of overall hits +system.cpu.l2cache.overall_hits::total 115627 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 6764 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27508 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 34272 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 130881 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130881 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 6764 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158389 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 165153 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 6764 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158389 # number of overall misses +system.cpu.l2cache.overall_misses::total 165153 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 355241500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1444303000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1799544500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6871263500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6871263500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 355241500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8315566500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8670808000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 355241500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8315566500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8670808000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168375 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168375 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088492 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.452687 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.249792 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911567 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911567 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088492 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775110 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.588194 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088492 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775110 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.588194 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.441159 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.834957 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52507.717670 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.084046 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.084046 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.668150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.668150 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 113982 # number of writebacks +system.cpu.l2cache.writebacks::total 113982 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 6764 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27508 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34272 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130881 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130881 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6764 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165153 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158389 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165153 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 274073000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1114207000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1388280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5300691500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5300691500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 274073000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6414898500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6688971500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 274073000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6414898500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6688971500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911567 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911567 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.367238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40504.834957 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40507.703081 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.084046 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.084046 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 449155 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 449155 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 449155 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 34272 # Transaction distribution +system.membus.trans_dist::ReadResp 34272 # Transaction distribution +system.membus.trans_dist::Writeback 113982 # Transaction distribution +system.membus.trans_dist::ReadExReq 130881 # Transaction distribution +system.membus.trans_dist::ReadExResp 130881 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 279135 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 279135 # Request fanout histogram +system.membus.reqLayer0.occupancy 748161500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 825765500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.6 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini new file mode 100644 index 000000000..f73c6b128 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -0,0 +1,270 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[4] + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[3] + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=vortex lendian.raw +cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr new file mode 100755 index 000000000..1a4f96712 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout new file mode 100755 index 000000000..b32e4875d --- /dev/null +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:03:38 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x49b6380 +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 53932157000 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/smred.out b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every <mod 0>Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD <Query0> for <Part2> class:: + + if (link[1].length >= 5) :: + + Build Query2 for <Address> class:: + + if (State == CA || State == T*) + + Build Query1 for <Person> class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD <Query3> for <DrawObj> class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD <Query4> for <NamedDrawObj> class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET <DrawObjs> entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET <NamedDrawObjs> entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET <LibRectangles> entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST <DbRectangles> entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET <PersonNames > entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=<True>; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + <Part2 > Asserts = 2; NULL Asserts = 3. + <DrawObj > Asserts = 0; NULL Asserts = 5. + <NamedObj > Asserts = 0; NULL Asserts = 0. + <Person > Asserts = 0; NULL Asserts = 5. + <TestObj > Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=<True>; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..93e5e3e06 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,245 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.048960 # Number of seconds simulated +sim_ticks 48960011000 # Number of ticks simulated +final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1566427 # Simulator instruction rate (inst/s) +host_op_rate 2003243 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1081494789 # Simulator tick rate (ticks/s) +host_mem_usage 308080 # Number of bytes of host memory used +host_seconds 45.27 # Real time elapsed on the host +sim_insts 70913181 # Number of instructions simulated +sim_ops 90688136 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory +system.physmem.bytes_read::total 419153617 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 312580272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 312580272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory +system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 78145068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory +system.physmem.num_reads::total 101064798 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory +system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6384399546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2176742669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8561142215 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6384399546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6384399546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1606621596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1606621596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 97920023 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 70913181 # Number of instructions committed +system.cpu.committedOps 90688136 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses +system.cpu.num_func_calls 3311620 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls +system.cpu.num_int_insts 81528488 # number of integer instructions +system.cpu.num_fp_insts 56 # number of float instructions +system.cpu.num_int_register_reads 141479310 # number of times the integer registers were read +system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written +system.cpu.num_fp_register_reads 36 # number of times the floating registers were read +system.cpu.num_fp_register_writes 20 # number of times the floating registers were written +system.cpu.num_cc_register_reads 266608028 # number of times the CC registers were read +system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written +system.cpu.num_mem_refs 43422001 # number of memory refs +system.cpu.num_load_insts 22866262 # Number of load instructions +system.cpu.num_store_insts 20555739 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 97920022.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 13741485 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction +system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 90690083 # Class of executed instruction +system.membus.trans_dist::ReadReq 100925135 # Transaction distribution +system.membus.trans_dist::ReadResp 100941054 # Transaction distribution +system.membus.trans_dist::WriteReq 19849901 # Transaction distribution +system.membus.trans_dist::WriteResp 19849901 # Transaction distribution +system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution +system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution +system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution +system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 120930618 # Request fanout histogram +system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram +system.membus.snoop_fanout::3 78145068 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 120930618 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini new file mode 100644 index 000000000..8d05feb2e --- /dev/null +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -0,0 +1,383 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=vortex lendian.raw +cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr new file mode 100755 index 000000000..1a4f96712 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout new file mode 100755 index 000000000..4bb28ef2b --- /dev/null +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:04:30 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5604d00 +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 132689045000 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/smred.out b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every <mod 0>Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD <Query0> for <Part2> class:: + + if (link[1].length >= 5) :: + + Build Query2 for <Address> class:: + + if (State == CA || State == T*) + + Build Query1 for <Person> class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD <Query3> for <DrawObj> class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD <Query4> for <NamedDrawObj> class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET <DrawObjs> entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET <NamedDrawObjs> entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET <LibRectangles> entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST <DbRectangles> entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET <PersonNames > entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=<True>; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + <Part2 > Asserts = 2; NULL Asserts = 3. + <DrawObj > Asserts = 0; NULL Asserts = 5. + <NamedObj > Asserts = 0; NULL Asserts = 0. + <Person > Asserts = 0; NULL Asserts = 5. + <TestObj > Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=<True>; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt new file mode 100644 index 000000000..6d597c67f --- /dev/null +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,643 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.127293 # Number of seconds simulated +sim_ticks 127293405500 # Number of ticks simulated +final_tick 127293405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 802256 # Simulator instruction rate (inst/s) +host_op_rate 1024256 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1451138855 # Simulator tick rate (ticks/s) +host_mem_usage 317568 # Number of bytes of host memory used +host_seconds 87.72 # Real time elapsed on the host +sim_insts 70373628 # Number of instructions simulated +sim_ops 89847362 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory +system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory +system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory +system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62253657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64260737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 42187386 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 42187386 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 42187386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62253657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106448122 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 254586811 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 70373628 # Number of instructions committed +system.cpu.committedOps 89847362 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses +system.cpu.num_func_calls 3311620 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls +system.cpu.num_int_insts 81528488 # number of integer instructions +system.cpu.num_fp_insts 56 # number of float instructions +system.cpu.num_int_register_reads 141328474 # number of times the integer registers were read +system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written +system.cpu.num_fp_register_reads 36 # number of times the floating registers were read +system.cpu.num_fp_register_writes 20 # number of times the floating registers were written +system.cpu.num_cc_register_reads 334802003 # number of times the CC registers were read +system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written +system.cpu.num_mem_refs 43422001 # number of memory refs +system.cpu.num_load_insts 22866262 # Number of load instructions +system.cpu.num_store_insts 20555739 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 254586810.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 13741485 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction +system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 90690083 # Class of executed instruction +system.cpu.dcache.tags.replacements 155902 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.389361 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1061070000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389361 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22749839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22749839 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 42492708 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42492708 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42576331 # number of overall hits +system.cpu.dcache.overall_hits::total 42576331 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 30228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 30228 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 137260 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137260 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 177381 # number of overall misses +system.cpu.dcache.overall_misses::total 177381 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 517066000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 517066000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689116000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689116000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6206182000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6206182000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6206182000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6206182000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45214.789451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34987.862285 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks +system.cpu.dcache.writebacks::total 128239 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1120 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1120 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1120 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1120 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1120 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 457995500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 457995500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5528568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5528568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1058278000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1058278000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5986563500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5986563500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7044841500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7044841500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15734.351381 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15734.351381 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51653.412064 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51653.412064 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44357.364406 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44357.364406 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43973.582342 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43973.582342 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 16890 # number of replacements +system.cpu.icache.tags.tagsinuse 1733.672975 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672975 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 156309046 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156309046 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78126161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78126161 # number of overall hits +system.cpu.icache.overall_hits::total 78126161 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses +system.cpu.icache.overall_misses::total 18908 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413935000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413935000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413935000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413935000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413935000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413935000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78145069 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78145069 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78145069 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21892.056272 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21892.056272 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21892.056272 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21892.056272 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 385573000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 385573000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 385573000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 385573000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 385573000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 385573000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20392.056272 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20392.056272 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 94693 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30351.006010 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27796.868072 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.768401 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.369537 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.848293 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.042797 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.926239 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15103 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13917 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 607 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2689980 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 128239 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128239 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 14916 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36178 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 51094 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 14916 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36178 # number of overall hits +system.cpu.l2cache.overall_hits::total 51094 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3992 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21540 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 25532 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3992 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 123820 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 127812 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses +system.cpu.l2cache.overall_misses::total 127812 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210047000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1133331500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1343378500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371640000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5371640000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 210047000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6504971500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6715018500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 210047000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6504971500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6715018500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 128239 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128239 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.211128 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.406676 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.355233 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955602 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955602 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.211128 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.773885 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.714409 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52616.983968 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52615.204271 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52615.482532 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52518.967540 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52518.967540 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52538.247582 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52538.247582 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 83909 # number of writebacks +system.cpu.l2cache.writebacks::total 83909 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3992 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21540 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 25532 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3992 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 127812 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 161778000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 873989500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1035767500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4142346500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4142346500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161778000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5016336000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5178114000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161778000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5016336000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5178114000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40525.551102 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40575.185701 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40567.425192 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 25532 # Transaction distribution +system.membus.trans_dist::ReadResp 25532 # Transaction distribution +system.membus.trans_dist::Writeback 83909 # Transaction distribution +system.membus.trans_dist::ReadExReq 102280 # Transaction distribution +system.membus.trans_dist::ReadExResp 102280 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 214640 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 214640 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 214640 # Request fanout histogram +system.membus.reqLayer0.occupancy 566253984 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 642220500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..5fee4647b --- /dev/null +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,171 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=SparcInterrupts +eventq_index=0 + +[system.cpu.isa] +type=SparcISA +eventq_index=0 + +[system.cpu.itb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=vortex bendian.raw +cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..f7abb9a35 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,562 @@ +warn: Sockets disabled, not accepting gdb connections +warn: ignoring syscall time(4026528248, 4026527848, ...) +warn: ignoring syscall time(1375098, 4026527400, ...) +warn: ignoring syscall time(1, 4026527312, ...) +warn: ignoring syscall time(413, 4026527048, ...) +warn: ignoring syscall time(414, 4026527048, ...) +warn: ignoring syscall time(4026527688, 4026527288, ...) +warn: ignoring syscall time(1375098, 4026526840, ...) +warn: ignoring syscall time(409, 4026527048, ...) +warn: ignoring syscall time(409, 4026527048, ...) +warn: ignoring syscall time(409, 4026526960, ...) +warn: ignoring syscall time(409, 4026527040, ...) +warn: ignoring syscall time(409, 4026527000, ...) +warn: ignoring syscall time(409, 4026526984, ...) +warn: ignoring syscall time(409, 4026526984, ...) +warn: ignoring syscall time(409, 4026526872, ...) +warn: ignoring syscall time(19045, 4026526312, ...) +warn: ignoring syscall time(409, 4026526832, ...) +warn: ignoring syscall time(409, 4026526872, ...) +warn: ignoring syscall time(409, 4026526872, ...) +warn: ignoring syscall time(409, 4026526848, ...) +warn: ignoring syscall time(409, 4026526840, ...) +warn: ignoring syscall time(409, 4026526872, ...) +warn: ignoring syscall time(409, 4026526856, ...) +warn: ignoring syscall time(409, 4026526848, ...) +warn: ignoring syscall time(409, 4026526936, ...) +warn: ignoring syscall time(4026527408, 4026527008, ...) +warn: ignoring syscall time(1375098, 4026526560, ...) +warn: ignoring syscall time(18732, 4026527184, ...) +warn: ignoring syscall time(409, 4026526632, ...) +warn: ignoring syscall time(0, 4026526736, ...) +warn: ignoring syscall time(0, 4026527320, ...) +warn: ignoring syscall time(225, 4026527744, ...) +warn: ignoring syscall time(409, 4026527048, ...) +warn: ignoring syscall time(409, 4026526856, ...) +warn: ignoring syscall time(409, 4026526872, ...) +warn: ignoring syscall time(4026527496, 4026527096, ...) +warn: ignoring syscall time(1375098, 4026526648, ...) +warn: ignoring syscall time(0, 4026526824, ...) +warn: ignoring syscall time(0, 4026527320, ...) +warn: ignoring syscall time(1879089152, 4026527184, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall time(1595768, 4026527472, ...) +warn: ignoring syscall time(17300, 4026526912, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(19045, 4026526912, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(19045, 4026526912, ...) +warn: ignoring syscall time(17300, 4026526912, ...) +warn: ignoring syscall time(20500, 4026525968, ...) +warn: ignoring syscall time(4026526436, 4026525968, ...) +warn: ignoring syscall time(7004192, 4026526056, ...) +warn: ignoring syscall time(4, 4026527512, ...) +warn: ignoring syscall time(0, 4026525760, ...) diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..9c35a9a4f --- /dev/null +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,11 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 19:46:20 +gem5 executing on u200540-lin +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 68148672000 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg new file mode 100644 index 000000000..0ac2d9980 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg @@ -0,0 +1,158 @@ + + SYSTEM TYPE... + __ZTC__ := False + __UNIX__ := True + __RISC__ := True + SPEC_CPU2000_LP64 := False + __MAC__ := False + __BCC__ := False + __BORLANDC__ := False + __GUI__ := False + __WTC__ := False + __HP__ := False + + CODE OPTIONS... + __MACROIZE_HM__ := True + __MACROIZE_MEM__ := True + ENV01 := True + USE_HPP_STYPE_HDRS := False + USE_H_STYPE_HDRS := False + + CODE INCLUSION PARAMETERS... + INCLUDE_ALL_CODE := False + INCLUDE_DELETE_CODE := True + __SWAP_GRP_POS__ := True + __INCLUDE_MTRX__ := False + __BAD_CODE__ := False + API_INCLUDE := False + BE_CAREFUL := False + OLDWAY := False + NOTUSED := False + + SYSTEM PARAMETERS... + EXT_ENUM := 999999999L + CHUNK_CONSTANT := 55555555 + CORE_CONSTANT := 55555555 + CORE_LIMIT := 20971520 + CorePage_Size := 384000 + ALIGN_BYTES := True + CORE_BLOCK_ALIGN := 8 + FAR_MEM := False + + MEMORY MANAGEMENT PARAMETERS... + SYSTEM_ALLOC := True + SYSTEM_FREESTORE := True + __NO_DISKCACHE__ := False + __FREEZE_VCHUNKS__ := True + __FREEZE_GRP_PACKETS__ := True + __MINIMIZE_TREE_CACHE__:= True + + SYSTEM STD PARAMETERS... + __STDOUT__ := False + NULL := 0 + LPTR := False + False_Status := 1 + True_Status := 0 + LARGE := True + TWOBYTE_BOOL := False + __NOSTR__ := False + + MEMORY VALIDATION PARAMETERS... + CORE_CRC_CHECK := False + VALIDATE_MEM_CHUNKS := False + + SYSTEM DEBUG OPTIONS... + DEBUG := False + MCSTAT := False + TRACKBACK := False + FLUSH_FILES := False + DEBUG_CORE0 := False + DEBUG_RISC := False + __TREE_BUG__ := False + __TRACK_FILE_READS__ := False + PAGE_SPACE := False + LEAVE_NO_TRACE := True + NULL_TRACE_STRS := False + + TIME PARAMETERS... + CLOCK_IS_LONG := False + __DISPLAY_TIME__ := False + __TREE_TIME__ := False + __DISPLAY_ERRORS__ := False + + API MACROS... + __BMT01__ := True + OPTIMIZE := True + + END OF DEFINES. + + + + ... IMPLODE MEMORY ... + + SWAP to DiskCache := False + + FREEZE_GRP_PACKETS:= True + + QueBug := 1000 + + sizeof(boolean) = 4 + sizeof(sizetype) = 4 + sizeof(chunkstruc) = 32 + + sizeof(shorttype ) = 2 + sizeof(idtype ) = 2 + sizeof(sizetype ) = 4 + sizeof(indextype ) = 4 + sizeof(numtype ) = 4 + sizeof(handletype) = 4 + sizeof(tokentype ) = 8 + + sizeof(short ) = 2 + sizeof(int ) = 4 + + sizeof(lt64 ) = 4 + sizeof(farlongtype) = 4 + sizeof(long ) = 4 + sizeof(longaddr ) = 4 + + sizeof(float ) = 4 + sizeof(double ) = 8 + + sizeof(addrtype ) = 4 + sizeof(char * ) = 4 + ALLOC CORE_1 :: 8 + BHOOLE NATH + + OPEN File ./input/bendian.rnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 2030c0 + DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] + DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] + DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] + DB Handle Chunk's StackPtr = 20797 + + DB[ 1] LOADED; Handles= 20797 + KERNEL in CORE[ 1] Restored @ 1b4750 + + OPEN File ./input/bendian.wnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 21c40 + DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] + DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] + DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] + DB Handle Chunk's StackPtr = 17 + + DB[ 2] LOADED; Handles= 17 + VORTEx_Status == -8 || fffffff8 + + BE HERE NOW !!! + + + + ... VORTEx ON LINE ... + + + ... END OF SESSION ... diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every <mod 0>Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD <Query0> for <Part2> class:: + + if (link[1].length >= 5) :: + + Build Query2 for <Address> class:: + + if (State == CA || State == T*) + + Build Query1 for <Person> class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD <Query3> for <DrawObj> class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD <Query4> for <NamedDrawObj> class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET <DrawObjs> entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET <NamedDrawObjs> entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET <LibRectangles> entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST <DbRectangles> entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET <PersonNames > entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=<True>; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + <Part2 > Asserts = 2; NULL Asserts = 3. + <DrawObj > Asserts = 0; NULL Asserts = 5. + <NamedObj > Asserts = 0; NULL Asserts = 0. + <Person > Asserts = 0; NULL Asserts = 5. + <TestObj > Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=<True>; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..9acb631e8 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,124 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.068149 # Number of seconds simulated +sim_ticks 68148672000 # Number of ticks simulated +final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 2078407 # Simulator instruction rate (inst/s) +host_op_rate 2105318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1053881878 # Simulator tick rate (ticks/s) +host_mem_usage 288492 # Number of bytes of host memory used +host_seconds 64.66 # Real time elapsed on the host +sim_insts 134398962 # Number of instructions simulated +sim_ops 136139190 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory +system.physmem.bytes_read::total 685773640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 538214280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 538214280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory +system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 134553570 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory +system.physmem.num_reads::total 171784870 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory +system.physmem.num_other::total 15916 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7897648835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2165256573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10062905408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7897648835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7897648835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1318924454 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1318924454 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 171784870 # Transaction distribution +system.membus.trans_dist::ReadResp 171784870 # Transaction distribution +system.membus.trans_dist::WriteReq 20864304 # Transaction distribution +system.membus.trans_dist::WriteResp 20864304 # Transaction distribution +system.membus.trans_dist::SwapReq 15916 # Transaction distribution +system.membus.trans_dist::SwapResp 15916 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107140 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 385330180 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214280 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 775783918 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 192665090 # Request fanout histogram +system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram +system.membus.snoop_fanout::1 134553570 69.84% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 192665090 # Request fanout histogram +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 136297345 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 134398962 # Number of instructions committed +system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses +system.cpu.num_func_calls 1709332 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls +system.cpu.num_int_insts 115187746 # number of integer instructions +system.cpu.num_fp_insts 2326977 # number of float instructions +system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read +system.cpu.num_int_register_writes 113147734 # number of times the integer registers were written +system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written +system.cpu.num_mem_refs 58160248 # number of memory refs +system.cpu.num_load_insts 37275867 # Number of load instructions +system.cpu.num_store_insts 20884381 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 136297344.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 12719095 # Number of branches fetched +system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction +system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction +system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 136293798 # Class of executed instruction + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini new file mode 100644 index 000000000..5186e7456 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -0,0 +1,284 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=SparcInterrupts +eventq_index=0 + +[system.cpu.isa] +type=SparcISA +eventq_index=0 + +[system.cpu.itb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=vortex bendian.raw +cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..f7abb9a35 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,562 @@ +warn: Sockets disabled, not accepting gdb connections +warn: ignoring syscall time(4026528248, 4026527848, ...) +warn: ignoring syscall time(1375098, 4026527400, ...) +warn: ignoring syscall time(1, 4026527312, ...) +warn: ignoring syscall time(413, 4026527048, ...) +warn: ignoring syscall time(414, 4026527048, ...) +warn: ignoring syscall time(4026527688, 4026527288, ...) +warn: ignoring syscall time(1375098, 4026526840, ...) +warn: ignoring syscall time(409, 4026527048, ...) +warn: ignoring syscall time(409, 4026527048, ...) +warn: ignoring syscall time(409, 4026526960, ...) +warn: ignoring syscall time(409, 4026527040, ...) +warn: ignoring syscall time(409, 4026527000, ...) +warn: ignoring syscall time(409, 4026526984, ...) +warn: ignoring syscall time(409, 4026526984, ...) +warn: ignoring syscall time(409, 4026526872, ...) +warn: ignoring syscall time(19045, 4026526312, ...) +warn: ignoring syscall time(409, 4026526832, ...) +warn: ignoring syscall time(409, 4026526872, ...) +warn: ignoring syscall time(409, 4026526872, ...) +warn: ignoring syscall time(409, 4026526848, ...) +warn: ignoring syscall time(409, 4026526840, ...) +warn: ignoring syscall time(409, 4026526872, ...) +warn: ignoring syscall time(409, 4026526856, ...) +warn: ignoring syscall time(409, 4026526848, ...) +warn: ignoring syscall time(409, 4026526936, ...) +warn: ignoring syscall time(4026527408, 4026527008, ...) +warn: ignoring syscall time(1375098, 4026526560, ...) +warn: ignoring syscall time(18732, 4026527184, ...) +warn: ignoring syscall time(409, 4026526632, ...) +warn: ignoring syscall time(0, 4026526736, ...) +warn: ignoring syscall time(0, 4026527320, ...) +warn: ignoring syscall time(225, 4026527744, ...) +warn: ignoring syscall time(409, 4026527048, ...) +warn: ignoring syscall time(409, 4026526856, ...) +warn: ignoring syscall time(409, 4026526872, ...) +warn: ignoring syscall time(4026527496, 4026527096, ...) +warn: ignoring syscall time(1375098, 4026526648, ...) +warn: ignoring syscall time(0, 4026526824, ...) +warn: ignoring syscall time(0, 4026527320, ...) +warn: ignoring syscall time(1879089152, 4026527184, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall times(246, 4026527728, ...) +warn: ignoring syscall time(1595768, 4026527472, ...) +warn: ignoring syscall time(17300, 4026526912, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(19045, 4026526912, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(0, 4026527472, ...) +warn: ignoring syscall time(19045, 4026526912, ...) +warn: ignoring syscall time(17300, 4026526912, ...) +warn: ignoring syscall time(20500, 4026525968, ...) +warn: ignoring syscall time(4026526436, 4026525968, ...) +warn: ignoring syscall time(7004192, 4026526056, ...) +warn: ignoring syscall time(4, 4026527512, ...) +warn: ignoring syscall time(0, 4026525760, ...) diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..2ff984591 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,11 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 19:47:13 +gem5 executing on u200540-lin +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 202242260000 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg new file mode 100644 index 000000000..0ac2d9980 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg @@ -0,0 +1,158 @@ + + SYSTEM TYPE... + __ZTC__ := False + __UNIX__ := True + __RISC__ := True + SPEC_CPU2000_LP64 := False + __MAC__ := False + __BCC__ := False + __BORLANDC__ := False + __GUI__ := False + __WTC__ := False + __HP__ := False + + CODE OPTIONS... + __MACROIZE_HM__ := True + __MACROIZE_MEM__ := True + ENV01 := True + USE_HPP_STYPE_HDRS := False + USE_H_STYPE_HDRS := False + + CODE INCLUSION PARAMETERS... + INCLUDE_ALL_CODE := False + INCLUDE_DELETE_CODE := True + __SWAP_GRP_POS__ := True + __INCLUDE_MTRX__ := False + __BAD_CODE__ := False + API_INCLUDE := False + BE_CAREFUL := False + OLDWAY := False + NOTUSED := False + + SYSTEM PARAMETERS... + EXT_ENUM := 999999999L + CHUNK_CONSTANT := 55555555 + CORE_CONSTANT := 55555555 + CORE_LIMIT := 20971520 + CorePage_Size := 384000 + ALIGN_BYTES := True + CORE_BLOCK_ALIGN := 8 + FAR_MEM := False + + MEMORY MANAGEMENT PARAMETERS... + SYSTEM_ALLOC := True + SYSTEM_FREESTORE := True + __NO_DISKCACHE__ := False + __FREEZE_VCHUNKS__ := True + __FREEZE_GRP_PACKETS__ := True + __MINIMIZE_TREE_CACHE__:= True + + SYSTEM STD PARAMETERS... + __STDOUT__ := False + NULL := 0 + LPTR := False + False_Status := 1 + True_Status := 0 + LARGE := True + TWOBYTE_BOOL := False + __NOSTR__ := False + + MEMORY VALIDATION PARAMETERS... + CORE_CRC_CHECK := False + VALIDATE_MEM_CHUNKS := False + + SYSTEM DEBUG OPTIONS... + DEBUG := False + MCSTAT := False + TRACKBACK := False + FLUSH_FILES := False + DEBUG_CORE0 := False + DEBUG_RISC := False + __TREE_BUG__ := False + __TRACK_FILE_READS__ := False + PAGE_SPACE := False + LEAVE_NO_TRACE := True + NULL_TRACE_STRS := False + + TIME PARAMETERS... + CLOCK_IS_LONG := False + __DISPLAY_TIME__ := False + __TREE_TIME__ := False + __DISPLAY_ERRORS__ := False + + API MACROS... + __BMT01__ := True + OPTIMIZE := True + + END OF DEFINES. + + + + ... IMPLODE MEMORY ... + + SWAP to DiskCache := False + + FREEZE_GRP_PACKETS:= True + + QueBug := 1000 + + sizeof(boolean) = 4 + sizeof(sizetype) = 4 + sizeof(chunkstruc) = 32 + + sizeof(shorttype ) = 2 + sizeof(idtype ) = 2 + sizeof(sizetype ) = 4 + sizeof(indextype ) = 4 + sizeof(numtype ) = 4 + sizeof(handletype) = 4 + sizeof(tokentype ) = 8 + + sizeof(short ) = 2 + sizeof(int ) = 4 + + sizeof(lt64 ) = 4 + sizeof(farlongtype) = 4 + sizeof(long ) = 4 + sizeof(longaddr ) = 4 + + sizeof(float ) = 4 + sizeof(double ) = 8 + + sizeof(addrtype ) = 4 + sizeof(char * ) = 4 + ALLOC CORE_1 :: 8 + BHOOLE NATH + + OPEN File ./input/bendian.rnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 2030c0 + DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] + DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] + DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] + DB Handle Chunk's StackPtr = 20797 + + DB[ 1] LOADED; Handles= 20797 + KERNEL in CORE[ 1] Restored @ 1b4750 + + OPEN File ./input/bendian.wnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 21c40 + DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] + DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] + DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] + DB Handle Chunk's StackPtr = 17 + + DB[ 2] LOADED; Handles= 17 + VORTEx_Status == -8 || fffffff8 + + BE HERE NOW !!! + + + + ... VORTEx ON LINE ... + + + ... END OF SESSION ... diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/smred.out b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every <mod 0>Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD <Query0> for <Part2> class:: + + if (link[1].length >= 5) :: + + Build Query2 for <Address> class:: + + if (State == CA || State == T*) + + Build Query1 for <Person> class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD <Query3> for <DrawObj> class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD <Query4> for <NamedDrawObj> class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET <DrawObjs> entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET <NamedDrawObjs> entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET <LibRectangles> entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST <DbRectangles> entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET <PersonNames > entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=<True>; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + <Part2 > Asserts = 2; NULL Asserts = 3. + <DrawObj > Asserts = 0; NULL Asserts = 5. + <NamedObj > Asserts = 0; NULL Asserts = 0. + <Person > Asserts = 0; NULL Asserts = 5. + <TestObj > Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=<True>; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt new file mode 100644 index 000000000..718e317fa --- /dev/null +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,514 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.202242 # Number of seconds simulated +sim_ticks 202242028500 # Number of ticks simulated +final_tick 202242028500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1201078 # Simulator instruction rate (inst/s) +host_op_rate 1216630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1807368744 # Simulator tick rate (ticks/s) +host_mem_usage 300888 # Number of bytes of host memory used +host_seconds 111.90 # Real time elapsed on the host +sim_insts 134398962 # Number of instructions simulated +sim_ops 136139190 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7826624 # Number of bytes read from this memory +system.physmem.bytes_read::total 8418112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 591488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 591488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5303552 # Number of bytes written to this memory +system.physmem.bytes_written::total 5303552 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9242 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122291 # Number of read requests responded to by this memory +system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory +system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2924654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38699295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41623950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2924654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2924654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26223788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26223788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26223788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2924654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38699295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67847737 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 404484057 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 134398962 # Number of instructions committed +system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses +system.cpu.num_func_calls 1709332 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls +system.cpu.num_int_insts 115187746 # number of integer instructions +system.cpu.num_fp_insts 2326977 # number of float instructions +system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read +system.cpu.num_int_register_writes 113147733 # number of times the integer registers were written +system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written +system.cpu.num_mem_refs 58160248 # number of memory refs +system.cpu.num_load_insts 37275867 # Number of load instructions +system.cpu.num_store_insts 20884381 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 404484056.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 12719095 # Number of branches fetched +system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction +system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction +system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 136293798 # Class of executed instruction +system.cpu.dcache.tags.replacements 146582 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.648320 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 769041000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648320 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits +system.cpu.dcache.overall_hits::total 57944941 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses +system.cpu.dcache.overall_misses::total 150663 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475000000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1475000000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619674000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5619674000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7094674000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7094674000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7094674000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7094674000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32418.294908 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32418.294908 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.240881 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.240881 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47089.690236 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47089.690236 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks +system.cpu.dcache.writebacks::total 123970 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1406751500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1406751500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5461928000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5461928000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 382500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 382500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6868679500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6868679500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6868679500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6868679500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30918.294908 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30918.294908 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51937.240881 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51937.240881 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 184976 # number of replacements +system.cpu.icache.tags.tagsinuse 2004.815289 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 143972077000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815289 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 269294166 # Number of tag accesses +system.cpu.icache.tags.data_accesses 269294166 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 134366547 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 134366547 # number of overall hits +system.cpu.icache.overall_hits::total 134366547 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses +system.cpu.icache.overall_misses::total 187024 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819561500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2819561500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2819561500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2819561500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2819561500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2819561500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 134553571 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 134553571 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 134553571 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15075.934105 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15075.934105 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15075.934105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15075.934105 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2539025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2539025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2539025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2539025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2539025500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2539025500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13575.934105 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13575.934105 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 98540 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30850.758845 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 26245.549112 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.945467 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264265 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 30994 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 533 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12212 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17536 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 585 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945862 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3928089 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3928089 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 123970 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 123970 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3923 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3923 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 177782 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 28387 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 206169 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 177782 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 28387 # number of overall hits +system.cpu.l2cache.overall_hits::total 206169 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 9242 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21035 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 30277 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 101256 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101256 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 9242 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 122291 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 131533 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 9242 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 122291 # number of overall misses +system.cpu.l2cache.overall_misses::total 131533 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 485290500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1104380500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1589671000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5315940000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5315940000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 485290500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6420320500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6905611000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 485290500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6420320500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6905611000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 123970 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 123970 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 150678 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 337702 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.049416 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.462318 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.130211 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962702 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.962702 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.049416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.811605 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.389494 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.049416 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.811605 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.389494 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52509.251244 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52502.044212 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52504.244146 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.976941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.976941 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 82868 # number of writebacks +system.cpu.l2cache.writebacks::total 82868 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9242 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21035 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 30277 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101256 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101256 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9242 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122291 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 131533 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9242 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 122291 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 131533 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 374386000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 851960500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1226346500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4100868000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4100868000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 374386000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4952828500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5327214500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 374386000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4952828500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5327214500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.462318 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.130211 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.389494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.389494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40509.197143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40502.044212 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40504.227632 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374048 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 425326 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 799374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 461672 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 461672 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 461672 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 30277 # Transaction distribution +system.membus.trans_dist::ReadResp 30277 # Transaction distribution +system.membus.trans_dist::Writeback 82868 # Transaction distribution +system.membus.trans_dist::ReadExReq 101256 # Transaction distribution +system.membus.trans_dist::ReadExResp 101256 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 214401 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 214401 # Request fanout histogram +system.membus.reqLayer0.occupancy 558284500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 657665500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/test.py b/tests/quick/se/50.vortex/test.py new file mode 100644 index 000000000..794a11aa1 --- /dev/null +++ b/tests/quick/se/50.vortex/test.py @@ -0,0 +1,33 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +m5.util.addToPath('../configs/common') +from cpu2000 import vortex + +workload = vortex(isa, opsys, 'smred') +root.system.cpu[0].workload = workload.makeLiveProcess() diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini new file mode 100644 index 000000000..31653027e --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -0,0 +1,172 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..de77515a1 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..53155afb5 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,26 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 19:22:57 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 45951567500 because target called exit() diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out new file mode 100644 index 000000000..98777e0af --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt new file mode 100644 index 000000000..366983cab --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,152 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.045952 # Number of seconds simulated +sim_ticks 45951567500 # Number of ticks simulated +final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 2845952 # Simulator instruction rate (inst/s) +host_op_rate 2845951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1422976169 # Simulator tick rate (ticks/s) +host_mem_usage 283520 # Number of bytes of host memory used +host_seconds 32.29 # Real time elapsed on the host +sim_insts 91903056 # Number of instructions simulated +sim_ops 91903056 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory +system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 367612356 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 367612356 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 30920974 # Number of bytes written to this memory +system.physmem.bytes_written::total 30920974 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 91903089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 19996198 # Number of read requests responded to by this memory +system.physmem.num_reads::total 111899287 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 6501103 # Number of write requests responded to by this memory +system.physmem.num_writes::total 6501103 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999995996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2357645819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10357641815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999995996 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999995996 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 672903574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 672903574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 111899287 # Transaction distribution +system.membus.trans_dist::ReadResp 111899287 # Transaction distribution +system.membus.trans_dist::WriteReq 6501103 # Transaction distribution +system.membus.trans_dist::WriteResp 6501103 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 118400390 # Request fanout histogram +system.membus.snoop_fanout::mean 0.776206 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.416786 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 26497301 22.38% 22.38% # Request fanout histogram +system.membus.snoop_fanout::1 91903089 77.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 118400390 # Request fanout histogram +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 19996198 # DTB read hits +system.cpu.dtb.read_misses 10 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 19996208 # DTB read accesses +system.cpu.dtb.write_hits 6501103 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 6501126 # DTB write accesses +system.cpu.dtb.data_hits 26497301 # DTB hits +system.cpu.dtb.data_misses 33 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 26497334 # DTB accesses +system.cpu.itb.fetch_hits 91903089 # ITB hits +system.cpu.itb.fetch_misses 47 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 91903136 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.numCycles 91903136 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 91903056 # Number of instructions committed +system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses +system.cpu.num_func_calls 2059216 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls +system.cpu.num_int_insts 79581109 # number of integer instructions +system.cpu.num_fp_insts 6862064 # number of float instructions +system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read +system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read +system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written +system.cpu.num_mem_refs 26497334 # number of memory refs +system.cpu.num_load_insts 19996208 # Number of load instructions +system.cpu.num_store_insts 6501126 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 91903136 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 10240685 # Number of branches fetched +system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction +system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction +system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction +system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction +system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction +system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91903089 # Class of executed instruction + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini new file mode 100644 index 000000000..fa4a217dd --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -0,0 +1,290 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..de77515a1 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..078852d80 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,26 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 19:23:43 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 118729316000 because target called exit() diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out new file mode 100644 index 000000000..98777e0af --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt new file mode 100644 index 000000000..85445221a --- /dev/null +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,518 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.118729 # Number of seconds simulated +sim_ticks 118729316500 # Number of ticks simulated +final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1507080 # Simulator instruction rate (inst/s) +host_op_rate 1507080 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1946992285 # Simulator tick rate (ticks/s) +host_mem_usage 297820 # Number of bytes of host memory used +host_seconds 60.98 # Real time elapsed on the host +sim_insts 91903056 # Number of instructions simulated +sim_ops 91903056 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory +system.physmem.bytes_read::total 304960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1412827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1155704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2568532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1412827 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1412827 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 19996198 # DTB read hits +system.cpu.dtb.read_misses 10 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 19996208 # DTB read accesses +system.cpu.dtb.write_hits 6501103 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 6501126 # DTB write accesses +system.cpu.dtb.data_hits 26497301 # DTB hits +system.cpu.dtb.data_misses 33 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 26497334 # DTB accesses +system.cpu.itb.fetch_hits 91903090 # ITB hits +system.cpu.itb.fetch_misses 47 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 91903137 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.numCycles 237458633 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 91903056 # Number of instructions committed +system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses +system.cpu.num_func_calls 2059216 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls +system.cpu.num_int_insts 79581109 # number of integer instructions +system.cpu.num_fp_insts 6862064 # number of float instructions +system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read +system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read +system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written +system.cpu.num_mem_refs 26497334 # number of memory refs +system.cpu.num_load_insts 19996208 # Number of load instructions +system.cpu.num_store_insts 6501126 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 237458633 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 10240685 # Number of branches fetched +system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction +system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction +system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction +system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction +system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction +system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91903089 # Class of executed instruction +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1442.043377 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043377 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits +system.cpu.dcache.overall_hits::total 26495078 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses +system.cpu.dcache.overall_misses::total 2223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 115612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115612500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 115612500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48813.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48813.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52875.286041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52875.286041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 6681 # number of replacements +system.cpu.icache.tags.tagsinuse 1418.052759 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052759 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 585 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 953 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses +system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits +system.cpu.icache.overall_hits::total 91894580 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses +system.cpu.icache.overall_misses::total 8510 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 220712500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 220712500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 220712500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 220712500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 220712500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.663925 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25935.663925 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25935.663925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25935.663925 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 207947500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 207947500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 207947500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 207947500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 207947500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 207947500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24435.663925 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24435.663925 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2074.070538 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.795177 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.017985 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257376 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3109 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 91577 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 91577 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits +system.cpu.l2cache.overall_hits::total 5968 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2621 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3043 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4765 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses +system.cpu.l2cache.overall_misses::total 4765 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137603000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22155000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 159758000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90405000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 90405000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137603000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112560000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 250163000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137603000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112560000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 250163000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.338676 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.190767 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.164312 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.104932 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.104932 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2621 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3043 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106150500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17091000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 123241500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69741000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69741000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106150500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 192982500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106150500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86832000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 192982500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21573 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10840 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10840 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10840 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3043 # Transaction distribution +system.membus.trans_dist::ReadResp 3043 # Transaction distribution +system.membus.trans_dist::ReadExReq 1722 # Transaction distribution +system.membus.trans_dist::ReadExResp 1722 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4765 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4765 # Request fanout histogram +system.membus.reqLayer0.occupancy 4765500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 23825500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini new file mode 100644 index 000000000..52b17d81d --- /dev/null +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -0,0 +1,270 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[4] + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[3] + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr new file mode 100755 index 000000000..1a4f96712 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout new file mode 100755 index 000000000..cd4551b05 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -0,0 +1,25 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:37:39 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5fbc6c0 +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University +info: Increasing stack size by one page. + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 103106766000 because target called exit() diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/smred.out b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..e6a9622eb --- /dev/null +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,245 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.099596 # Number of seconds simulated +sim_ticks 99596491000 # Number of ticks simulated +final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1940320 # Simulator instruction rate (inst/s) +host_op_rate 2045410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1121471108 # Simulator tick rate (ticks/s) +host_mem_usage 304628 # Number of bytes of host memory used +host_seconds 88.81 # Real time elapsed on the host +sim_insts 172317409 # Number of instructions simulated +sim_ops 181650341 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory +system.physmem.bytes_read::total 869973865 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 759440204 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 759440204 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory +system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 189860051 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory +system.physmem.num_reads::total 217637772 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory +system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7625170288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1109814813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8734985101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7625170288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7625170288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 454362795 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 454362795 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 199192983 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 172317409 # Number of instructions committed +system.cpu.committedOps 181650341 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses +system.cpu.num_func_calls 3545028 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls +system.cpu.num_int_insts 143085668 # number of integer instructions +system.cpu.num_fp_insts 1752310 # number of float instructions +system.cpu.num_int_register_reads 241970171 # number of times the integer registers were read +system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written +system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written +system.cpu.num_cc_register_reads 543309967 # number of times the CC registers were read +system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written +system.cpu.num_mem_refs 40540779 # number of memory refs +system.cpu.num_load_insts 27896144 # Number of load instructions +system.cpu.num_store_insts 12644635 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 199192982.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 40300311 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction +system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction +system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction +system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 181650742 # Class of executed instruction +system.membus.trans_dist::ReadReq 217614902 # Transaction distribution +system.membus.trans_dist::ReadResp 217637309 # Transaction distribution +system.membus.trans_dist::WriteReq 12364287 # Transaction distribution +system.membus.trans_dist::WriteResp 12364287 # Transaction distribution +system.membus.trans_dist::SoftPFReq 463 # Transaction distribution +system.membus.trans_dist::SoftPFResp 463 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution +system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution +system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 230024466 # Request fanout histogram +system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram +system.membus.snoop_fanout::3 189860051 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 230024466 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini new file mode 100644 index 000000000..0035560c6 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -0,0 +1,383 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr new file mode 100755 index 000000000..1a4f96712 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout new file mode 100755 index 000000000..aba76e9d8 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -0,0 +1,25 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:39:21 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5d0ed00 +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University +info: Increasing stack size by one page. + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 232072304000 because target called exit() diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/smred.out b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt new file mode 100644 index 000000000..6ce1a7f0e --- /dev/null +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,630 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.230173 # Number of seconds simulated +sim_ticks 230173357500 # Number of ticks simulated +final_tick 230173357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1098511 # Simulator instruction rate (inst/s) +host_op_rate 1158108 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1471393960 # Simulator tick rate (ticks/s) +host_mem_usage 313104 # Number of bytes of host memory used +host_seconds 156.43 # Real time elapsed on the host +sim_insts 171842483 # Number of instructions simulated +sim_ops 181165370 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory +system.physmem.bytes_read::total 220992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 460346715 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 171842483 # Number of instructions committed +system.cpu.committedOps 181165370 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses +system.cpu.num_func_calls 3545028 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls +system.cpu.num_int_insts 143085668 # number of integer instructions +system.cpu.num_fp_insts 1752310 # number of float instructions +system.cpu.num_int_register_reads 242291225 # number of times the integer registers were read +system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written +system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written +system.cpu.num_cc_register_reads 626384527 # number of times the CC registers were read +system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written +system.cpu.num_mem_refs 40540779 # number of memory refs +system.cpu.num_load_insts 27896144 # Number of load instructions +system.cpu.num_store_insts 12644635 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 460346714.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 40300311 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction +system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction +system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction +system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 181650742 # Class of executed instruction +system.cpu.dcache.tags.replacements 40 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.619277 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619277 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits +system.cpu.dcache.overall_hits::total 40117812 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses +system.cpu.dcache.overall_misses::total 1789 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34437000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34437000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58544500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 58544500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92981500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92981500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93035000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 93035000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50053.779070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50053.779070 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53222.272727 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53222.272727 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52003.076063 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52003.076063 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52003.912800 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52003.912800 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 1506 # number of replacements +system.cpu.icache.tags.tagsinuse 1147.992598 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992598 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 379723155 # Number of tag accesses +system.cpu.icache.tags.data_accesses 379723155 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 189857001 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 189857001 # number of overall hits +system.cpu.icache.overall_hits::total 189857001 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses +system.cpu.icache.overall_misses::total 3051 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 189860052 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 189860052 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 189860052 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36830.875123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 107794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 107794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 107794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 107794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 107794500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 107794500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35330.875123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35330.875123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 1675.663349 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036753 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588818 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 42317 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 42317 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1322 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 65 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1387 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits +system.cpu.l2cache.overall_hits::total 1387 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1729 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2361 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses +system.cpu.l2cache.overall_misses::total 3453 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 90862500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33203000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 124065500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57360500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 57360500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 90862500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 90563500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 181426000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 90862500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 90563500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 181426000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.631283 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52536.392405 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52547.861076 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52541.558065 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 632 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2361 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70024500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25596000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 95620500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44226000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44226000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70024500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69822000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 139846500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70024500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69822000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 139846500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6102 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3594 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9696 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 2361 # Transaction distribution +system.membus.trans_dist::ReadResp 2361 # Transaction distribution +system.membus.trans_dist::ReadExReq 1092 # Transaction distribution +system.membus.trans_dist::ReadExResp 1092 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3453 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3453 # Request fanout histogram +system.membus.reqLayer0.occupancy 3596500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 17408500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..fd6e14d22 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,171 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=SparcInterrupts +eventq_index=0 + +[system.cpu.isa] +type=SparcISA +eventq_index=0 + +[system.cpu.itb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..1a4f96712 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..522507bd6 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,26 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 19:48:57 +gem5 executing on u200540-lin +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic +Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav +Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +info: Increasing stack size by one page. +122 123 124 Exiting @ tick 96722945000 because target called exit() diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..aa452dcbd --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,124 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.096723 # Number of seconds simulated +sim_ticks 96722945000 # Number of ticks simulated +final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 2119754 # Simulator instruction rate (inst/s) +host_op_rate 2119756 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1059884256 # Simulator tick rate (ticks/s) +host_mem_usage 284956 # Number of bytes of host memory used +host_seconds 91.26 # Real time elapsed on the host +sim_insts 193444518 # Number of instructions simulated +sim_ops 193444756 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory +system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 773782140 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 773782140 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory +system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 193445535 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 57735068 # Number of read requests responded to by this memory +system.physmem.num_reads::total 251180603 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory +system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory +system.physmem.num_other::total 22406 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2310345420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10310330739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 745070490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 745070490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 251180603 # Transaction distribution +system.membus.trans_dist::ReadResp 251180603 # Transaction distribution +system.membus.trans_dist::WriteReq 18976439 # Transaction distribution +system.membus.trans_dist::WriteResp 18976439 # Transaction distribution +system.membus.trans_dist::SwapReq 22406 # Transaction distribution +system.membus.trans_dist::SwapResp 22406 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 270179448 # Request fanout histogram +system.membus.snoop_fanout::mean 0.715989 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.450942 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 76733913 28.40% 28.40% # Request fanout histogram +system.membus.snoop_fanout::1 193445535 71.60% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 270179448 # Request fanout histogram +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 401 # Number of system calls +system.cpu.numCycles 193445891 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 193444518 # Number of instructions committed +system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses +system.cpu.num_func_calls 1957920 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls +system.cpu.num_int_insts 167974806 # number of integer instructions +system.cpu.num_fp_insts 1970372 # number of float instructions +system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read +system.cpu.num_int_register_writes 163060124 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written +system.cpu.num_mem_refs 76733958 # number of memory refs +system.cpu.num_load_insts 57735091 # Number of load instructions +system.cpu.num_store_insts 18998867 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 193445890.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 15132745 # Number of branches fetched +system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction +system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction +system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 193445773 # Class of executed instruction + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini new file mode 100644 index 000000000..fc5d4f341 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -0,0 +1,284 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=SparcInterrupts +eventq_index=0 + +[system.cpu.isa] +type=SparcISA +eventq_index=0 + +[system.cpu.itb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..1a4f96712 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..cbae3bd7a --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,26 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 19:50:23 +gem5 executing on u200540-lin +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +info: Increasing stack size by one page. +122 123 124 Exiting @ tick 270563082000 because target called exit() diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.out b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt new file mode 100644 index 000000000..e9f2af2a4 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,501 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.270563 # Number of seconds simulated +sim_ticks 270563082500 # Number of ticks simulated +final_tick 270563082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1283602 # Simulator instruction rate (inst/s) +host_op_rate 1283603 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1795321724 # Simulator tick rate (ticks/s) +host_mem_usage 297332 # Number of bytes of host memory used +host_seconds 150.70 # Real time elapsed on the host +sim_insts 193444518 # Number of instructions simulated +sim_ops 193444756 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory +system.physmem.bytes_read::total 331072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 850848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 372793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 401 # Number of system calls +system.cpu.numCycles 541126165 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 193444518 # Number of instructions committed +system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses +system.cpu.num_func_calls 1957920 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls +system.cpu.num_int_insts 167974806 # number of integer instructions +system.cpu.num_fp_insts 1970372 # number of float instructions +system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read +system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written +system.cpu.num_mem_refs 76733958 # number of memory refs +system.cpu.num_load_insts 57735091 # Number of load instructions +system.cpu.num_store_insts 18998867 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 541126164.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 15132745 # Number of branches fetched +system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction +system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction +system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 193445773 # Class of executed instruction +system.cpu.dcache.tags.replacements 2 # number of replacements +system.cpu.dcache.tags.tagsinuse 1237.203936 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203936 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits +system.cpu.dcache.overall_hits::total 76709932 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses +system.cpu.dcache.overall_misses::total 1575 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2 # number of writebacks +system.cpu.dcache.writebacks::total 2 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26643000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26643000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57619500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57619500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 53500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84262500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 84262500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84262500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 84262500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 10362 # number of replacements +system.cpu.icache.tags.tagsinuse 1591.579164 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579164 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses +system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits +system.cpu.icache.overall_hits::total 193433248 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses +system.cpu.icache.overall_misses::total 12288 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 310818500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 310818500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 310818500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 310818500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 310818500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.474284 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25294.474284 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25294.474284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25294.474284 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292386500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 292386500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292386500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 292386500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292386500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 292386500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23794.474284 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23794.474284 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2678.340853 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282913 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057487 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 116103 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 116103 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits +system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits +system.cpu.l2cache.overall_hits::total 8691 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3597 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 498 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4095 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses +system.cpu.l2cache.overall_misses::total 5173 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188843000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26145000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 214988000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56595000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 56595000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 188843000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 82740000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 271583000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 188843000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 82740000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 271583000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 12288 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 498 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 12786 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.320272 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.139005 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.122100 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.096656 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.096656 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4095 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145678500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20169000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 165847500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43659000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43659000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145678500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63828000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 209506500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145678500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63828000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 209506500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24576 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 13866 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13866 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 13866 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4095 # Transaction distribution +system.membus.trans_dist::ReadResp 4095 # Transaction distribution +system.membus.trans_dist::ReadExReq 1078 # Transaction distribution +system.membus.trans_dist::ReadExResp 1078 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5173 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5173 # Request fanout histogram +system.membus.reqLayer0.occupancy 5173500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 25865500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini new file mode 100644 index 000000000..994d45013 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -0,0 +1,207 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=apic_clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 + +[system.cpu.dtb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.membus.slave[4] + +[system.cpu.interrupts] +type=X86LocalApic +clk_domain=system.cpu.apic_clk_domain +eventq_index=0 +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=100000 +system=system +int_master=system.membus.slave[5] +int_slave=system.membus.master[2] +pio=system.membus.master[1] + +[system.cpu.isa] +type=X86ISA +eventq_index=0 + +[system.cpu.itb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.membus.slave[3] + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..1a4f96712 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout new file mode 100755 index 000000000..45d32ca68 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -0,0 +1,27 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 22:11:10 +gem5 executing on u200540-lin +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University +info: Increasing stack size by one page. +info: Increasing stack size by one page. + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 131393279000 because target called exit() diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.out b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..7b91ddd8b --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,129 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.131393 # Number of seconds simulated +sim_ticks 131393279000 # Number of ticks simulated +final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1264426 # Simulator instruction rate (inst/s) +host_op_rate 2119294 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1257935779 # Simulator tick rate (ticks/s) +host_mem_usage 324376 # Number of bytes of host memory used +host_seconds 104.45 # Real time elapsed on the host +sim_insts 132071193 # Number of instructions simulated +sim_ops 221363385 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory +system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 99822191 # Number of bytes written to this memory +system.physmem.bytes_written::total 99822191 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 56682005 # Number of read requests responded to by this memory +system.physmem.num_reads::total 230176372 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 20515731 # Number of write requests responded to by this memory +system.physmem.num_writes::total 20515731 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 10563363260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2362554267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12925917527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10563363260 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10563363260 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 759720678 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 759720678 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 230176372 # Transaction distribution +system.membus.trans_dist::ReadResp 230176372 # Transaction distribution +system.membus.trans_dist::WriteReq 20515731 # Transaction distribution +system.membus.trans_dist::WriteResp 20515731 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 250692103 # Request fanout histogram +system.membus.snoop_fanout::mean 2.692062 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 77197736 30.79% 30.79% # Request fanout histogram +system.membus.snoop_fanout::3 173494367 69.21% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 250692103 # Request fanout histogram +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 262786559 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 132071193 # Number of instructions committed +system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses +system.cpu.num_func_calls 1595632 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls +system.cpu.num_int_insts 219019986 # number of integer instructions +system.cpu.num_fp_insts 2162459 # number of float instructions +system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read +system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read +system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written +system.cpu.num_mem_refs 77165304 # number of memory refs +system.cpu.num_load_insts 56649587 # Number of load instructions +system.cpu.num_store_insts 20515717 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 262786558.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 12326938 # Number of branches fetched +system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction +system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction +system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction +system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction +system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction +system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 221363385 # Class of executed instruction + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..1228cbb9c --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,323 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=X86LocalApic +clk_domain=system.cpu.apic_clk_domain +eventq_index=0 +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=100000 +system=system +int_master=system.membus.slave[2] +int_slave=system.membus.master[2] +pio=system.membus.master[1] + +[system.cpu.isa] +type=X86ISA +eventq_index=0 + +[system.cpu.itb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..1a4f96712 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..cc37865c7 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -0,0 +1,27 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 22:12:53 +gem5 executing on u200540-lin +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University +info: Increasing stack size by one page. +info: Increasing stack size by one page. + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 250953957000 because target called exit() diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.out b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pin b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1 b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2 b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sav b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2 b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.twf b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..0e62e6e73 --- /dev/null +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,493 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.250954 # Number of seconds simulated +sim_ticks 250953957500 # Number of ticks simulated +final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 722726 # Simulator instruction rate (inst/s) +host_op_rate 1211354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1373280924 # Simulator tick rate (ticks/s) +host_mem_usage 338728 # Number of bytes of host memory used +host_seconds 182.74 # Real time elapsed on the host +sim_insts 132071193 # Number of instructions simulated +sim_ops 221363385 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory +system.physmem.bytes_read::total 303040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 724276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 483276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1207552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 501907915 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 132071193 # Number of instructions committed +system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses +system.cpu.num_func_calls 1595632 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls +system.cpu.num_int_insts 219019986 # number of integer instructions +system.cpu.num_fp_insts 2162459 # number of float instructions +system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read +system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read +system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written +system.cpu.num_mem_refs 77165304 # number of memory refs +system.cpu.num_load_insts 56649587 # Number of load instructions +system.cpu.num_store_insts 20515717 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 501907914.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 12326938 # Number of branches fetched +system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction +system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction +system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction +system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction +system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction +system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 221363385 # Class of executed instruction +system.cpu.dcache.tags.replacements 41 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.457564 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457564 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits +system.cpu.dcache.overall_hits::total 77195831 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses +system.cpu.dcache.overall_misses::total 1905 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 7 # number of writebacks +system.cpu.dcache.writebacks::total 7 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17202000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17202000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84297000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84297000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 101499000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 101499000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 101499000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 101499000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.504587 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.504587 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53420.152091 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53420.152091 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 2836 # number of replacements +system.cpu.icache.tags.tagsinuse 1455.296636 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296636 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses +system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits +system.cpu.icache.overall_hits::total 173489673 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses +system.cpu.icache.overall_misses::total 4694 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 180319500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 180319500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 180319500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 180319500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 180319500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.891351 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 38414.891351 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 38414.891351 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 38414.891351 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 173278500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 173278500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 173278500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 173278500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 173278500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 173278500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36914.891351 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36914.891351 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2058.178675 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978570 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178361 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 516 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 57590 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 57590 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits +system.cpu.l2cache.overall_hits::total 1864 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2840 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 320 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3160 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses +system.cpu.l2cache.overall_misses::total 4735 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149117500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16801500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 165919000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82687500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 82687500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 149117500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 99489000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 248606500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 149117500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 99489000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 248606500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.629357 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.687500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52506.012658 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52504.012672 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52504.012672 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115020000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 127980000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63787500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63787500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115020000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76747500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 191767500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115020000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76747500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 191767500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 6606 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3160 # Transaction distribution +system.membus.trans_dist::ReadResp 3160 # Transaction distribution +system.membus.trans_dist::ReadExReq 1575 # Transaction distribution +system.membus.trans_dist::ReadExResp 1575 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4735 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4735 # Request fanout histogram +system.membus.reqLayer0.occupancy 4754000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 23694000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/test.py b/tests/quick/se/70.twolf/test.py new file mode 100644 index 000000000..5b99b86fa --- /dev/null +++ b/tests/quick/se/70.twolf/test.py @@ -0,0 +1,47 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +m5.util.addToPath('../configs/common') +from cpu2000 import twolf +import os + +workload = twolf(isa, opsys, 'smred') +root.system.cpu[0].workload = workload.makeLiveProcess() +cwd = root.system.cpu[0].workload[0].cwd + +#Remove two files who's presence or absence affects execution +sav_file = os.path.join(cwd, workload.input_set + '.sav') +sv2_file = os.path.join(cwd, workload.input_set + '.sv2') +try: + os.unlink(sav_file) +except: + print "Couldn't unlink ", sav_file +try: + os.unlink(sv2_file) +except: + print "Couldn't unlink ", sv2_file |