diff options
Diffstat (limited to 'tests/quick/se')
74 files changed, 0 insertions, 21272 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini deleted file mode 100644 index 220cfeeae..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini +++ /dev/null @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr deleted file mode 100755 index b68e0fd83..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr +++ /dev/null @@ -1,4 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout deleted file mode 100755 index fff19a530..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout +++ /dev/null @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28071 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 22083000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt deleted file mode 100644 index 23238c1fc..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ /dev/null @@ -1,759 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22083000 # Number of ticks simulated -final_tick 22083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166693 # Simulator instruction rate (inst/s) -host_op_rate 166561 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1421880228 # Simulator tick rate (ticks/s) -host_mem_usage 251952 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 2585 # Number of instructions simulated -sim_ops 2585 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory -system.physmem.bytes_read::total 19840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory -system.physmem.num_reads::total 310 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 652085314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 246343341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 898428656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 652085314 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 652085314 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 652085314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 246343341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 898428656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 310 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 310 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 19840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 19840 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 0 # Per bank write bursts -system.physmem.perBankRdBursts::1 1 # Per bank write bursts -system.physmem.perBankRdBursts::2 3 # Per bank write bursts -system.physmem.perBankRdBursts::3 24 # Per bank write bursts -system.physmem.perBankRdBursts::4 21 # Per bank write bursts -system.physmem.perBankRdBursts::5 0 # Per bank write bursts -system.physmem.perBankRdBursts::6 27 # Per bank write bursts -system.physmem.perBankRdBursts::7 48 # Per bank write bursts -system.physmem.perBankRdBursts::8 68 # Per bank write bursts -system.physmem.perBankRdBursts::9 2 # Per bank write bursts -system.physmem.perBankRdBursts::10 15 # Per bank write bursts -system.physmem.perBankRdBursts::11 15 # Per bank write bursts -system.physmem.perBankRdBursts::12 18 # Per bank write bursts -system.physmem.perBankRdBursts::13 52 # Per bank write bursts -system.physmem.perBankRdBursts::14 15 # Per bank write bursts -system.physmem.perBankRdBursts::15 1 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21988500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 310 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 429.268293 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 281.212133 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.776868 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 14.63% 53.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 4.88% 58.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 7.32% 65.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 4.88% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7 17.07% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 4.88% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation -system.physmem.totQLat 3615250 # Total ticks spent queuing -system.physmem.totMemAccLat 9427750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11662.10 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30412.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 898.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 898.43 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.02 # Data bus utilization in percentage -system.physmem.busUtilRead 7.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 260 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70930.65 # Average gap between requests -system.physmem.pageHitRate 83.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 114240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 45540 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 885360 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1636470 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7529700 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 729120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12201870 # Total energy per rank (pJ) -system.physmem_0.averagePower 552.527084 # Core power per rank (mW) -system.physmem_0.totalIdleTime 18356500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 27500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1898500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 3124750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 16512250 # Time in different power states -system.physmem_1.actEnergy 242760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 110055 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1328040 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2565570 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 217440 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7221900 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 12935685 # Total energy per rank (pJ) -system.physmem_1.averagePower 585.755816 # Core power per rank (mW) -system.physmem_1.totalIdleTime 15168500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 498000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 53000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5182750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 15829250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 793 # Number of BP lookups -system.cpu.branchPred.condPredicted 395 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 561 # Number of BTB lookups -system.cpu.branchPred.BTBHits 54 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 9.625668 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 144 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 83 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 0 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 83 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 32 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 506 # DTB read hits -system.cpu.dtb.read_misses 6 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 512 # DTB read accesses -system.cpu.dtb.write_hits 307 # DTB write hits -system.cpu.dtb.write_misses 6 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 313 # DTB write accesses -system.cpu.dtb.data_hits 813 # DTB hits -system.cpu.dtb.data_misses 12 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 825 # DTB accesses -system.cpu.itb.fetch_hits 980 # ITB hits -system.cpu.itb.fetch_misses 13 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 993 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22083000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44166 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2585 # Number of instructions committed -system.cpu.committedOps 2585 # Number of ops (including micro ops) committed -system.cpu.discardedOps 573 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 17.085493 # CPI: cycles per instruction -system.cpu.ipc 0.058529 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 189 7.31% 7.31% # Class of committed instruction -system.cpu.op_class_0::IntAlu 1678 64.91% 72.22% # Class of committed instruction -system.cpu.op_class_0::IntMult 1 0.04% 72.26% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::MemRead 419 16.21% 88.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 292 11.30% 99.77% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 0 0.00% 99.77% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 6 0.23% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 2585 # Class of committed instruction -system.cpu.tickCycles 5429 # Number of cycles that the object actually ticked -system.cpu.idleCycles 38737 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.291787 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.291787 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011790 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011790 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1673 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1673 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 441 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 692 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 692 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 692 # number of overall hits -system.cpu.dcache.overall_hits::total 692 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 59 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 59 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 102 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 102 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 102 # number of overall misses -system.cpu.dcache.overall_misses::total 102 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5143500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5143500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3553000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3553000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8696500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8696500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8696500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8696500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 794 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 794 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 794 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 794 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.118000 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.118000 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.146259 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.128463 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.128463 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.128463 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.128463 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87177.966102 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 87177.966102 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82627.906977 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 82627.906977 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85259.803922 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85259.803922 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85259.803922 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85259.803922 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5007000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5007000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2203500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2203500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7210500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7210500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116000 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116000 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107053 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.107053 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107053 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.107053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86327.586207 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86327.586207 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81611.111111 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81611.111111 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84829.411765 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84829.411765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84829.411765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84829.411765 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 118.973491 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 755 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 225 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.355556 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 118.973491 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.058093 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.058093 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 225 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.109863 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2185 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2185 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 755 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 755 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 755 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 755 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 755 # number of overall hits -system.cpu.icache.overall_hits::total 755 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 225 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 225 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 225 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 225 # number of overall misses -system.cpu.icache.overall_misses::total 225 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18729500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18729500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18729500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18729500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18729500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18729500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 980 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 980 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 980 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 980 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 980 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 980 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229592 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.229592 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.229592 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.229592 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.229592 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.229592 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83242.222222 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 83242.222222 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 83242.222222 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 83242.222222 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 83242.222222 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 83242.222222 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 225 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 225 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 225 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18504500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18504500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18504500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18504500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18504500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18504500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229592 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.229592 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.229592 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82242.222222 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82242.222222 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82242.222222 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 82242.222222 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82242.222222 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 82242.222222 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 167.412677 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 310 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.080474 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.332203 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003634 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001475 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005109 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009460 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2790 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2790 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 58 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 58 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 310 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses -system.cpu.l2cache.overall_misses::total 310 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2163000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2163000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18167000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 18167000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4919000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4919000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18167000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7082000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25249000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18167000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7082000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25249000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 225 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 225 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 58 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 58 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 225 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 310 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 225 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 310 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80111.111111 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80111.111111 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80742.222222 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80742.222222 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84810.344828 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84810.344828 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80742.222222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83317.647059 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81448.387097 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80742.222222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83317.647059 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81448.387097 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 58 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 58 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 310 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 310 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1893000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1893000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 15917000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 15917000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4339000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4339000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15917000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6232000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22149000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15917000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6232000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22149000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70111.111111 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70111.111111 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70742.222222 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70742.222222 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74810.344828 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74810.344828 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70742.222222 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73317.647059 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71448.387097 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70742.222222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73317.647059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71448.387097 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 225 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 450 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 620 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 19840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 310 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 310 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 310 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 155000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 337500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 283 # Transaction distribution -system.membus.trans_dist::ReadExReq 27 # Transaction distribution -system.membus.trans_dist::ReadExResp 27 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 283 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 620 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 620 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19840 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 310 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 310 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 310 # Request fanout histogram -system.membus.reqLayer0.occupancy 362500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1648750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.5 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index ff6825b17..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index 4e7b90c23..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,5 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index 35f169b23..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:49 -gem5 executing on e108600-lin, pid 28097 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 13358500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index ed65513bb..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,1016 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13358500 # Number of ticks simulated -final_tick 13358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102485 # Simulator instruction rate (inst/s) -host_op_rate 102439 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 573050673 # Simulator tick rate (ticks/s) -host_mem_usage 252720 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 2387 # Number of instructions simulated -sim_ops 2387 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory -system.physmem.bytes_read::total 17408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 11968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory -system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 895908972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 407231351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1303140323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 895908972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 895908972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 895908972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 407231351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1303140323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 272 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 17408 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 17408 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 0 # Per bank write bursts -system.physmem.perBankRdBursts::1 1 # Per bank write bursts -system.physmem.perBankRdBursts::2 2 # Per bank write bursts -system.physmem.perBankRdBursts::3 24 # Per bank write bursts -system.physmem.perBankRdBursts::4 18 # Per bank write bursts -system.physmem.perBankRdBursts::5 0 # Per bank write bursts -system.physmem.perBankRdBursts::6 24 # Per bank write bursts -system.physmem.perBankRdBursts::7 37 # Per bank write bursts -system.physmem.perBankRdBursts::8 60 # Per bank write bursts -system.physmem.perBankRdBursts::9 2 # Per bank write bursts -system.physmem.perBankRdBursts::10 15 # Per bank write bursts -system.physmem.perBankRdBursts::11 9 # Per bank write bursts -system.physmem.perBankRdBursts::12 17 # Per bank write bursts -system.physmem.perBankRdBursts::13 50 # Per bank write bursts -system.physmem.perBankRdBursts::14 12 # Per bank write bursts -system.physmem.perBankRdBursts::15 1 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 13255000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 272 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 235.532687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 344.140835 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4 11.11% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 11.11% 55.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 16.67% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 5.56% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 2.78% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 2.78% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 3364250 # Total ticks spent queuing -system.physmem.totMemAccLat 8464250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12368.57 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31118.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1303.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1303.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.18 # Data bus utilization in percentage -system.physmem.busUtilRead 10.18 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 224 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48731.62 # Average gap between requests -system.physmem.pageHitRate 82.35 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 99960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 37950 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1355460 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 21600 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 4583370 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 107040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 7576860 # Total energy per rank (pJ) -system.physmem_0.averagePower 567.183307 # Core power per rank (mW) -system.physmem_0.totalIdleTime 10278500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 28500 # Time in different power states -system.physmem_0.memoryStateTime::REF 260000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 279000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2735250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 10055750 # Time in different power states -system.physmem_1.actEnergy 242760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 98670 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1185240 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1822290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 183840 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 4050420 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 8198340 # Total energy per rank (pJ) -system.physmem_1.averagePower 613.705624 # Core power per rank (mW) -system.physmem_1.totalIdleTime 8246250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 450500 # Time in different power states -system.physmem_1.memoryStateTime::REF 260000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3767500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 8879250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 994 # Number of BP lookups -system.cpu.branchPred.condPredicted 488 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 684 # Number of BTB lookups -system.cpu.branchPred.BTBHits 175 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 25.584795 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 18 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 99 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 97 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 33 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 705 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 715 # DTB read accesses -system.cpu.dtb.write_hits 349 # DTB write hits -system.cpu.dtb.write_misses 16 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 365 # DTB write accesses -system.cpu.dtb.data_hits 1054 # DTB hits -system.cpu.dtb.data_misses 26 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1080 # DTB accesses -system.cpu.itb.fetch_hits 872 # ITB hits -system.cpu.itb.fetch_misses 32 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 904 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 13358500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 26718 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4379 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6026 # Number of instructions fetch has processed -system.cpu.fetch.Branches 994 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 395 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1172 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1202 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 872 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 147 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.858649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.260497 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5993 85.39% 85.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 27 0.38% 85.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 97 1.38% 87.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 87 1.24% 88.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 140 1.99% 90.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 81 1.15% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 45 0.64% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 75 1.07% 93.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 473 6.74% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.037203 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.225541 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5261 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 642 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 913 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 39 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 163 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5228 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 263 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 163 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5336 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 333 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 302 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 873 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5015 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3598 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5603 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5596 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1830 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 838 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 424 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4336 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3724 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1954 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 987 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7018 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.530636 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.266302 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5580 79.51% 79.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 466 6.64% 86.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 341 4.86% 91.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 254 3.62% 94.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 190 2.71% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 104 1.48% 98.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 55 0.78% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 20 0.28% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7018 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 9.84% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 30 49.18% 59.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 24 39.34% 98.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1 1.64% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2606 69.98% 69.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 745 20.01% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 366 9.83% 99.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 6 0.16% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3724 # Type of FU issued -system.cpu.iq.rate 0.139382 # Inst issue rate -system.cpu.iq.fu_busy_cnt 61 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016380 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14533 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6293 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3394 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3778 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 423 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 130 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 42 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 163 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 304 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 4648 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 838 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 424 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 132 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 165 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3600 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 717 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 124 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 306 # number of nop insts executed -system.cpu.iew.exec_refs 1082 # number of memory reference insts executed -system.cpu.iew.exec_branches 595 # Number of branches executed -system.cpu.iew.exec_stores 365 # Number of stores executed -system.cpu.iew.exec_rate 0.134741 # Inst execution rate -system.cpu.iew.wb_sent 3453 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3400 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1619 # num instructions producing a value -system.cpu.iew.wb_consumers 2076 # num instructions consuming a value -system.cpu.iew.wb_rate 0.127255 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.779865 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2070 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6610 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.389713 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.245121 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5740 86.84% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 197 2.98% 89.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 319 4.83% 94.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 117 1.77% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 63 0.95% 97.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.80% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 36 0.54% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23 0.35% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 62 0.94% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6610 # Number of insts commited each cycle -system.cpu.commit.committedInsts 2576 # Number of instructions committed -system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 709 # Number of memory references committed -system.cpu.commit.loads 415 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 396 # Number of branches committed -system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. -system.cpu.commit.int_insts 2367 # Number of committed integer instructions. -system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 189 7.34% 7.34% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1677 65.10% 72.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 1 0.04% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 415 16.11% 88.59% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 288 11.18% 99.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 6 0.23% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 62 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 10947 # The number of ROB reads -system.cpu.rob.rob_writes 9704 # The number of ROB writes -system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19700 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 2387 # Number of Instructions Simulated -system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 11.193129 # CPI: Cycles Per Instruction -system.cpu.cpi_total 11.193129 # CPI: Total CPI of All Threads -system.cpu.ipc 0.089341 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.089341 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4344 # number of integer regfile reads -system.cpu.int_regfile_writes 2618 # number of integer regfile writes -system.cpu.fp_regfile_reads 6 # number of floating regfile reads -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.378002 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 743 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.741176 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.378002 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011079 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011079 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1935 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1935 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 530 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 743 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 743 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 743 # number of overall hits -system.cpu.dcache.overall_hits::total 743 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses -system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7124500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7124500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6134000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6134000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13258500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13258500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13258500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13258500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 631 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 631 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 925 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 925 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 925 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 925 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.160063 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.160063 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.196757 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.196757 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.196757 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.196757 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70539.603960 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70539.603960 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75728.395062 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75728.395062 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72848.901099 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72848.901099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72848.901099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72848.901099 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.250000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 97 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 97 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 97 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5157500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5157500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2004000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2004000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7161500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7161500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7161500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7161500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096672 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096672 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091892 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091892 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091892 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091892 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84549.180328 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84549.180328 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84252.941176 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84252.941176 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84252.941176 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84252.941176 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 89.996713 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 618 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.304813 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 89.996713 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.043944 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.043944 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1931 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1931 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 618 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 618 # number of overall hits -system.cpu.icache.overall_hits::total 618 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 254 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 254 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 254 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 254 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 254 # number of overall misses -system.cpu.icache.overall_misses::total 254 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20808999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20808999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20808999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20808999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20808999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20808999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 872 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 872 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 872 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 872 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.291284 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.291284 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.291284 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.291284 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.291284 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.291284 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81925.192913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 81925.192913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 81925.192913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 81925.192913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 81925.192913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 81925.192913 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15635499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15635499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15635499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15635499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15635499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15635499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.214450 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.214450 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.214450 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83612.294118 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83612.294118 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83612.294118 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83612.294118 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83612.294118 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83612.294118 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 135.588512 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 272 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.143699 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.444813 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002751 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001387 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004138 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 272 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008301 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 187 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 187 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 61 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 61 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 187 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 272 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses -system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1966500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1966500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15354000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 15354000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5066000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5066000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15354000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7032500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22386500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15354000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7032500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22386500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 187 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 61 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 187 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 272 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 187 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 272 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81937.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81937.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82106.951872 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82106.951872 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83049.180328 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83049.180328 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82106.951872 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82735.294118 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82303.308824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82106.951872 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82735.294118 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82303.308824 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 187 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 187 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 61 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 61 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1726500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1726500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13484000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13484000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4456000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4456000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13484000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6182500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19666500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13484000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6182500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19666500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71937.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71937.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72106.951872 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72106.951872 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73049.180328 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73049.180328 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72106.951872 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72735.294118 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72303.308824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72106.951872 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72735.294118 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72303.308824 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 187 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 248 # Transaction distribution -system.membus.trans_dist::ReadExReq 24 # Transaction distribution -system.membus.trans_dist::ReadExResp 24 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 248 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 272 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 337500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1437500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 10.8 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index 21de058a2..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index 05d0e3f61..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index 4e010ba65..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:25 -gem5 executing on e108600-lin, pid 39590 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt deleted file mode 100644 index b12c3ecf5..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ /dev/null @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1297500 # Number of ticks simulated -final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 601225 # Simulator instruction rate (inst/s) -host_op_rate 599847 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 301371607 # Simulator tick rate (ticks/s) -host_mem_usage 241196 # Number of bytes of host memory used -host_seconds 0.00 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory -system.physmem.bytes_read::total 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory -system.physmem.bytes_written::total 2058 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7969171484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2324470135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10293641618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7969171484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7969171484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1586127168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1586127168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2585 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2596 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1297500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2596 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2596 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 3000 # Transaction distribution -system.membus.trans_dist::ReadResp 3000 # Transaction distribution -system.membus.trans_dist::WriteReq 294 # Transaction distribution -system.membus.trans_dist::WriteResp 294 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 5170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6588 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 10340 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 5074 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15414 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3294 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3294 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3294 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini deleted file mode 100644 index 41209dc7f..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini +++ /dev/null @@ -1,1456 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory requestToDir responseFromDir responseFromMemory responseToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=6 -eventq_index=0 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_mem_ctrl_latency=1 -transitions_per_cycle=4 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[6] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[6] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache mandatoryQueue optionalQueue prefetcher requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer unblockFromL1Cache -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -buffer_size=0 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -enable_prefetch=false -eventq_index=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -number_of_TBEs=256 -optionalQueue=system.ruby.l1_cntrl0.optionalQueue -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -prefetcher=system.ruby.l1_cntrl0.prefetcher -recycle_latency=10 -requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache -requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache -responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache -responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -to_l2_latency=1 -transitions_per_cycle=4 -unblockFromL1Cache=system.ruby.l1_cntrl0.unblockFromL1Cache -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=true -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.optionalQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.prefetcher] -type=Prefetcher -cross_page=false -eventq_index=0 -nonunit_filter=8 -num_startup_pfs=1 -num_streams=4 -pf_per_stream=1 -sys=system -train_misses=4 -unit_filter=8 - -[system.ruby.l1_cntrl0.requestFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.requestToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.responseFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.l1_cntrl0.unblockFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.l2_cntrl0] -type=L2Cache_Controller -children=DirRequestFromL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache responseFromL2Cache responseToL2Cache unblockToL2Cache -DirRequestFromL2Cache=system.ruby.l2_cntrl0.DirRequestFromL2Cache -L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache -L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache -L2cache=system.ruby.l2_cntrl0.L2cache -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -l2_request_latency=2 -l2_response_latency=2 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache -responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache -ruby_system=system.ruby -system=system -to_l1_latency=1 -transitions_per_cycle=4 -unblockToL2Cache=system.ruby.l2_cntrl0.unblockToL2Cache -version=0 - -[system.ruby.l2_cntrl0.DirRequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.l2_cntrl0.L1RequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.l2_cntrl0.L1RequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.l2_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l2_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l2_cntrl0.responseFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.l2_cntrl0.responseToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.l2_cntrl0.unblockToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 -netifs= -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l2_cntrl0.unblockToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave -slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l1_cntrl0.unblockFromL1Cache.master system.ruby.l2_cntrl0.DirRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.responseFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l2_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=6 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links4] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=7 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links5] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=8 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 -power_model=Null -router_id=0 -virt_nets=3 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 -power_model=Null -router_id=1 -virt_nets=3 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 -power_model=Null -router_id=2 -virt_nets=3 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 -power_model=Null -router_id=3 -virt_nets=3 - -[system.ruby.network.routers3.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr deleted file mode 100755 index 63982fce4..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr +++ /dev/null @@ -1,11 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout deleted file mode 100755 index fcadeb2be..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout +++ /dev/null @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout -Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:28:06 -gem5 started Oct 13 2016 20:28:32 -gem5 executing on e108600-lin, pid 8237 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 48659 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt deleted file mode 100644 index 28d393468..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ /dev/null @@ -1,758 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000049 # Number of seconds simulated -sim_ticks 48659 # Number of ticks simulated -final_tick 48659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 67712 # Simulator instruction rate (inst/s) -host_op_rate 67695 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1277923 # Simulator tick rate (ticks/s) -host_mem_usage 411644 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 35008 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 35008 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6592 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 6592 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 547 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 547 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 103 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 103 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 719455805 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 719455805 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 135473396 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 135473396 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 854929201 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 854929201 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 547 # Number of read requests accepted -system.mem_ctrls.writeReqs 103 # Number of write requests accepted -system.mem_ctrls.readBursts 547 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 103 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 28032 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 35008 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 6592 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 57 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 31 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 84 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 84 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 37 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 64 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 12 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 5 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 7 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 48574 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 547 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 103 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 438 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 83 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 339.277108 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 221.785975 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 292.728223 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 23 27.71% 27.71% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 19 22.89% 50.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6 7.23% 57.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 10 12.05% 69.88% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 11 13.25% 83.13% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 4 4.82% 87.95% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 3 3.61% 91.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 3.61% 95.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 4 4.82% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 83 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 268 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 268.000000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::256-271 1 100.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 5659 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 13981 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 2190 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.92 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.92 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 576.09 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 21.04 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 719.46 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 135.47 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.67 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.50 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.16 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.48 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 349 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.68 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 74.73 # Average gap between requests -system.mem_ctrls.pageHitRate 75.21 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 199920 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 92736 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 2124864 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 3071616 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 85248 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 18833256 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 153600 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 28249080 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 580.552005 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 41659 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 54 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 400 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 5344 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 41301 # Time in different power states -system.mem_ctrls_1.actEnergy 442680 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 227976 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2878848 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 4289136 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 272256 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 17021568 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 466944 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 29420880 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 604.633881 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 37647 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 541 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 1216 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 8014 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 37328 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 48659 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 48659 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 48659 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 3612 # delay histogram for all message -system.ruby.delayHist::mean 0.144518 # delay histogram for all message -system.ruby.delayHist::stdev 0.930805 # delay histogram for all message -system.ruby.delayHist | 3486 96.51% 96.51% | 0 0.00% 96.51% | 81 2.24% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 45 1.25% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 3612 # delay histogram for all message -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 3295 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 13.772010 -system.ruby.latency_hist_seqr::gmean 2.084389 -system.ruby.latency_hist_seqr::stdev 31.264017 -system.ruby.latency_hist_seqr | 2856 86.70% 86.70% | 431 13.08% 99.79% | 1 0.03% 99.82% | 0 0.00% 99.82% | 2 0.06% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 3294 -system.ruby.hit_latency_hist_seqr::bucket_size 1 -system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 2722 -system.ruby.hit_latency_hist_seqr::mean 1 -system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 2722 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 2722 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 572 -system.ruby.miss_latency_hist_seqr::mean 74.550699 -system.ruby.miss_latency_hist_seqr::gmean 68.693513 -system.ruby.miss_latency_hist_seqr::stdev 34.041428 -system.ruby.miss_latency_hist_seqr | 134 23.43% 23.43% | 431 75.35% 98.78% | 1 0.17% 98.95% | 0 0.00% 98.95% | 2 0.35% 99.30% | 4 0.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 572 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 272 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 2285 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 300 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed -system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching -system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made -system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted -system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped -system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed -system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched -system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages -system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 4.088658 -system.ruby.network.routers0.msg_count.Control::0 572 -system.ruby.network.routers0.msg_count.Request_Control::2 431 -system.ruby.network.routers0.msg_count.Response_Data::1 572 -system.ruby.network.routers0.msg_count.Response_Control::1 493 -system.ruby.network.routers0.msg_count.Response_Control::2 272 -system.ruby.network.routers0.msg_count.Writeback_Data::0 45 -system.ruby.network.routers0.msg_count.Writeback_Data::1 62 -system.ruby.network.routers0.msg_count.Writeback_Control::0 79 -system.ruby.network.routers0.msg_bytes.Control::0 4576 -system.ruby.network.routers0.msg_bytes.Request_Control::2 3448 -system.ruby.network.routers0.msg_bytes.Response_Data::1 41184 -system.ruby.network.routers0.msg_bytes.Response_Control::1 3944 -system.ruby.network.routers0.msg_bytes.Response_Control::2 2176 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.876241 -system.ruby.network.routers1.msg_count.Control::0 1119 -system.ruby.network.routers1.msg_count.Request_Control::2 431 -system.ruby.network.routers1.msg_count.Response_Data::1 1222 -system.ruby.network.routers1.msg_count.Response_Control::1 1468 -system.ruby.network.routers1.msg_count.Response_Control::2 272 -system.ruby.network.routers1.msg_count.Writeback_Data::0 45 -system.ruby.network.routers1.msg_count.Writeback_Data::1 62 -system.ruby.network.routers1.msg_count.Writeback_Control::0 79 -system.ruby.network.routers1.msg_bytes.Control::0 8952 -system.ruby.network.routers1.msg_bytes.Request_Control::2 3448 -system.ruby.network.routers1.msg_bytes.Response_Data::1 87984 -system.ruby.network.routers1.msg_bytes.Response_Control::1 11744 -system.ruby.network.routers1.msg_bytes.Response_Control::2 2176 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.787583 -system.ruby.network.routers2.msg_count.Control::0 547 -system.ruby.network.routers2.msg_count.Response_Data::1 650 -system.ruby.network.routers2.msg_count.Response_Control::1 975 -system.ruby.network.routers2.msg_bytes.Control::0 4376 -system.ruby.network.routers2.msg_bytes.Response_Data::1 46800 -system.ruby.network.routers2.msg_bytes.Response_Control::1 7800 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 5.250827 -system.ruby.network.routers3.msg_count.Control::0 1119 -system.ruby.network.routers3.msg_count.Request_Control::2 431 -system.ruby.network.routers3.msg_count.Response_Data::1 1222 -system.ruby.network.routers3.msg_count.Response_Control::1 1468 -system.ruby.network.routers3.msg_count.Response_Control::2 272 -system.ruby.network.routers3.msg_count.Writeback_Data::0 45 -system.ruby.network.routers3.msg_count.Writeback_Data::1 62 -system.ruby.network.routers3.msg_count.Writeback_Control::0 79 -system.ruby.network.routers3.msg_bytes.Control::0 8952 -system.ruby.network.routers3.msg_bytes.Request_Control::2 3448 -system.ruby.network.routers3.msg_bytes.Response_Data::1 87984 -system.ruby.network.routers3.msg_bytes.Response_Control::1 11744 -system.ruby.network.routers3.msg_bytes.Response_Control::2 2176 -system.ruby.network.routers3.msg_bytes.Writeback_Data::0 3240 -system.ruby.network.routers3.msg_bytes.Writeback_Data::1 4464 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 632 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 3357 -system.ruby.network.msg_count.Request_Control 1293 -system.ruby.network.msg_count.Response_Data 3666 -system.ruby.network.msg_count.Response_Control 5220 -system.ruby.network.msg_count.Writeback_Data 321 -system.ruby.network.msg_count.Writeback_Control 237 -system.ruby.network.msg_byte.Control 26856 -system.ruby.network.msg_byte.Request_Control 10344 -system.ruby.network.msg_byte.Response_Data 263952 -system.ruby.network.msg_byte.Response_Control 41760 -system.ruby.network.msg_byte.Writeback_Data 23112 -system.ruby.network.msg_byte.Writeback_Control 1896 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 5.860170 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 431 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 124 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 3448 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 41184 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 992 -system.ruby.network.routers0.throttle1.link_utilization 2.317146 -system.ruby.network.routers0.throttle1.msg_count.Control::0 572 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 369 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 272 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 45 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 62 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 79 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 4576 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 2952 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 2176 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 3240 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 4464 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers1.throttle0.link_utilization 7.929674 -system.ruby.network.routers1.throttle0.msg_count.Control::0 572 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 547 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 908 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 272 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 45 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 62 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 79 -system.ruby.network.routers1.throttle0.msg_bytes.Control::0 4576 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 39384 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7264 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 2176 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 3240 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 4464 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers1.throttle1.link_utilization 7.822808 -system.ruby.network.routers1.throttle1.msg_count.Control::0 547 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 431 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 675 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 560 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 4376 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 3448 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 48600 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 4480 -system.ruby.network.routers2.throttle0.link_utilization 1.962638 -system.ruby.network.routers2.throttle0.msg_count.Control::0 547 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 103 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 436 -system.ruby.network.routers2.throttle0.msg_bytes.Control::0 4376 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 7416 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 3488 -system.ruby.network.routers2.throttle1.link_utilization 5.612528 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 547 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 539 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 39384 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 4312 -system.ruby.network.routers3.throttle0.link_utilization 5.860170 -system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 431 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 572 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 124 -system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 3448 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 41184 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 992 -system.ruby.network.routers3.throttle1.link_utilization 7.929674 -system.ruby.network.routers3.throttle1.msg_count.Control::0 572 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 547 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 908 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 272 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 45 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 62 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 79 -system.ruby.network.routers3.throttle1.msg_bytes.Control::0 4576 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 39384 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7264 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 2176 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 3240 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 4464 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers3.throttle2.link_utilization 1.962638 -system.ruby.network.routers3.throttle2.msg_count.Control::0 547 -system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 103 -system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 436 -system.ruby.network.routers3.throttle2.msg_bytes.Control::0 4376 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 7416 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 3488 -system.ruby.delayVCHist.vnet_0::bucket_size 1 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::max_bucket 9 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 968 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.371901 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 1.685180 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 923 95.35% 95.35% | 0 0.00% 95.35% | 0 0.00% 95.35% | 0 0.00% 95.35% | 0 0.00% 95.35% | 0 0.00% 95.35% | 0 0.00% 95.35% | 0 0.00% 95.35% | 45 4.65% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 968 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 2213 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.073204 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.375650 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 2132 96.34% 96.34% | 0 0.00% 96.34% | 81 3.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 2213 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 431 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 431 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 431 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 64 -system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 33.824096 -system.ruby.LD.latency_hist_seqr::gmean 7.531942 -system.ruby.LD.latency_hist_seqr::stdev 41.807535 -system.ruby.LD.latency_hist_seqr | 298 71.81% 71.81% | 115 27.71% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 415 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 211 -system.ruby.LD.hit_latency_hist_seqr::mean 1 -system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 211 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 211 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 204 -system.ruby.LD.miss_latency_hist_seqr::mean 67.774510 -system.ruby.LD.miss_latency_hist_seqr::gmean 60.800044 -system.ruby.LD.miss_latency_hist_seqr::stdev 35.866860 -system.ruby.LD.miss_latency_hist_seqr | 87 42.65% 42.65% | 115 56.37% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 2 0.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 204 -system.ruby.ST.latency_hist_seqr::bucket_size 16 -system.ruby.ST.latency_hist_seqr::max_bucket 159 -system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 14.469388 -system.ruby.ST.latency_hist_seqr::gmean 2.523301 -system.ruby.ST.latency_hist_seqr::stdev 26.779037 -system.ruby.ST.latency_hist_seqr | 226 76.87% 76.87% | 4 1.36% 78.23% | 33 11.22% 89.46% | 1 0.34% 89.80% | 14 4.76% 94.56% | 14 4.76% 99.32% | 2 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 294 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 226 -system.ruby.ST.hit_latency_hist_seqr::mean 1 -system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 226 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 226 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 -system.ruby.ST.miss_latency_hist_seqr::samples 68 -system.ruby.ST.miss_latency_hist_seqr::mean 59.235294 -system.ruby.ST.miss_latency_hist_seqr::gmean 54.692111 -system.ruby.ST.miss_latency_hist_seqr::stdev 22.140068 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 4 5.88% 5.88% | 33 48.53% 54.41% | 1 1.47% 55.88% | 14 20.59% 76.47% | 14 20.59% 97.06% | 2 2.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 68 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 10.473501 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.659469 -system.ruby.IFETCH.latency_hist_seqr::stdev 28.438724 -system.ruby.IFETCH.latency_hist_seqr | 2294 88.74% 88.74% | 286 11.06% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 2585 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 2285 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 2285 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 300 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 82.630000 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 78.596235 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 32.857141 -system.ruby.IFETCH.miss_latency_hist_seqr | 9 3.00% 3.00% | 286 95.33% 98.33% | 1 0.33% 98.67% | 0 0.00% 98.67% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 300 -system.ruby.Directory_Controller.Fetch 547 0.00% 0.00% -system.ruby.Directory_Controller.Data 103 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 547 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 103 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 436 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 547 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 103 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 436 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 547 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 103 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% -system.ruby.L1Cache_Controller.Inv 431 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 502 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_Exclusive 204 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_all_Acks 368 0.00% 0.00% -system.ruby.L1Cache_Controller.WB_Ack 124 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 182 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Ifetch 270 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Store 58 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Inv 162 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 22 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 30 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 10 0.00% 0.00% -system.ruby.L1Cache_Controller.I.L1_Replacement 206 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Ifetch 2285 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Inv 124 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 172 0.00% 0.00% -system.ruby.L1Cache_Controller.E.Load 140 0.00% 0.00% -system.ruby.L1Cache_Controller.E.Store 41 0.00% 0.00% -system.ruby.L1Cache_Controller.E.Inv 83 0.00% 0.00% -system.ruby.L1Cache_Controller.E.L1_Replacement 79 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 71 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 185 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Inv 62 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 45 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive 204 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks 300 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks 68 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack 124 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GET_INSTR 300 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 204 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 68 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 124 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 43 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 496 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 547 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 539 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 62 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 369 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 272 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 291 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 192 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 64 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 9 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 286 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 12 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 4 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 39 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 69 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 124 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 141 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 539 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 60 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 81 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 286 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 192 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 291 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 64 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 272 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini deleted file mode 100644 index 70212c16a..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ /dev/null @@ -1,1448 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory forwardFromDir requestToDir responseFromDir responseFromMemory responseToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=6 -eventq_index=0 -forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=4 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.forwardFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[6] - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[6] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache mandatoryQueue requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer triggerQueue -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -buffer_size=0 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -l2_select_num_bits=0 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache -requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache -request_latency=2 -responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache -responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=4 -triggerQueue=system.ruby.l1_cntrl0.triggerQueue -use_timeout_latency=50 -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=true -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.requestFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.requestToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.responseFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.l1_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.l2_cntrl0] -type=L2Cache_Controller -children=GlobalRequestFromL2Cache GlobalRequestToL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache responseFromL2Cache responseToL2Cache triggerQueue -GlobalRequestFromL2Cache=system.ruby.l2_cntrl0.GlobalRequestFromL2Cache -GlobalRequestToL2Cache=system.ruby.l2_cntrl0.GlobalRequestToL2Cache -L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache -L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache -L2cache=system.ruby.l2_cntrl0.L2cache -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -request_latency=2 -responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache -responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache -response_latency=2 -ruby_system=system.ruby -system=system -transitions_per_cycle=4 -triggerQueue=system.ruby.l2_cntrl0.triggerQueue -version=0 - -[system.ruby.l2_cntrl0.GlobalRequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.l2_cntrl0.GlobalRequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.l2_cntrl0.L1RequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.l2_cntrl0.L1RequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.l2_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l2_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l2_cntrl0.responseFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.l2_cntrl0.responseToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.l2_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 -netifs= -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l2_cntrl0.GlobalRequestToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave -slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l2_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=6 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links4] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=7 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links5] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=8 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 -power_model=Null -router_id=0 -virt_nets=3 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 -power_model=Null -router_id=1 -virt_nets=3 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 -power_model=Null -router_id=2 -virt_nets=3 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 -power_model=Null -router_id=3 -virt_nets=3 - -[system.ruby.network.routers3.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr deleted file mode 100755 index 63982fce4..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr +++ /dev/null @@ -1,11 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout deleted file mode 100755 index 42fdb4cc6..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ /dev/null @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:30:58 -gem5 started Oct 13 2016 20:31:25 -gem5 executing on e108600-lin, pid 17791 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 44230 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt deleted file mode 100644 index 9060cd787..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ /dev/null @@ -1,752 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000044 # Number of seconds simulated -sim_ticks 44230 # Number of ticks simulated -final_tick 44230 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 73967 # Simulator instruction rate (inst/s) -host_op_rate 73941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1268663 # Simulator tick rate (ticks/s) -host_mem_usage 415828 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 29696 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 29696 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4992 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 4992 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 464 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 464 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 78 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 78 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 671399503 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 671399503 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 112864572 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 112864572 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 784264074 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 784264074 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 464 # Number of read requests accepted -system.mem_ctrls.writeReqs 78 # Number of write requests accepted -system.mem_ctrls.readBursts 464 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 78 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 24576 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 5120 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 29696 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 4992 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 80 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 32 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 36 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 69 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 71 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 30 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 16 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 29 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 66 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 10 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 5 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 7 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 44144 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 464 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 78 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 384 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 308.906667 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 203.362375 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 281.413861 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 21 28.00% 28.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 20 26.67% 54.67% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 8 10.67% 65.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 8 10.67% 76.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 6 8.00% 84.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 3 4.00% 88.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 4 5.33% 93.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1 1.33% 94.67% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 4 5.33% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 75 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 248 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 248.000000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::248-255 1 100.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 4911 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 12207 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1920 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.79 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.79 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 555.64 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 23.15 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 671.40 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 112.86 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.52 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.34 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.18 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.61 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 302 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 78.65 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 81.45 # Average gap between requests -system.mem_ctrls.pageHitRate 73.72 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 178500 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 81144 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1793568 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 2736456 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 72192 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 16199400 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 966144 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 25100604 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 567.501786 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 37998 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 48 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 2516 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 4841 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 35525 # Time in different power states -system.mem_ctrls_1.actEnergy 414120 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 208656 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2593248 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 3830856 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 258048 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 15964560 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 56448 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 26532768 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 599.881709 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 34371 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 532 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 147 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 7241 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 35010 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 44230 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44230 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 44230 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 3295 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 12.427444 -system.ruby.latency_hist_seqr::gmean 1.971908 -system.ruby.latency_hist_seqr::stdev 29.452789 -system.ruby.latency_hist_seqr | 2910 88.34% 88.34% | 377 11.45% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 3 0.09% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 3294 -system.ruby.hit_latency_hist_seqr::bucket_size 1 -system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 2750 -system.ruby.hit_latency_hist_seqr::mean 1 -system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 2750 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 544 -system.ruby.miss_latency_hist_seqr::mean 70.194853 -system.ruby.miss_latency_hist_seqr::gmean 61.035379 -system.ruby.miss_latency_hist_seqr::stdev 35.442152 -system.ruby.miss_latency_hist_seqr | 160 29.41% 29.41% | 377 69.30% 98.71% | 2 0.37% 99.08% | 0 0.00% 99.08% | 3 0.55% 99.63% | 2 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 544 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 435 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 274 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 80 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 464 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 6.413068 -system.ruby.network.routers0.msg_count.Request_Control::0 544 -system.ruby.network.routers0.msg_count.Response_Data::2 464 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 80 -system.ruby.network.routers0.msg_count.Writeback_Data::2 482 -system.ruby.network.routers0.msg_count.Writeback_Control::0 1004 -system.ruby.network.routers0.msg_count.Unblock_Control::2 564 -system.ruby.network.routers0.msg_bytes.Request_Control::0 4352 -system.ruby.network.routers0.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 5760 -system.ruby.network.routers0.msg_bytes.Writeback_Data::2 34704 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032 -system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 9.782388 -system.ruby.network.routers1.msg_count.Request_Control::0 544 -system.ruby.network.routers1.msg_count.Request_Control::1 464 -system.ruby.network.routers1.msg_count.Response_Data::2 928 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 80 -system.ruby.network.routers1.msg_count.Writeback_Data::2 560 -system.ruby.network.routers1.msg_count.Writeback_Control::0 1004 -system.ruby.network.routers1.msg_count.Writeback_Control::1 156 -system.ruby.network.routers1.msg_count.Unblock_Control::2 1027 -system.ruby.network.routers1.msg_bytes.Request_Control::0 4352 -system.ruby.network.routers1.msg_bytes.Request_Control::1 3712 -system.ruby.network.routers1.msg_bytes.Response_Data::2 66816 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 5760 -system.ruby.network.routers1.msg_bytes.Writeback_Data::2 40320 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 8032 -system.ruby.network.routers1.msg_bytes.Writeback_Control::1 1248 -system.ruby.network.routers1.msg_bytes.Unblock_Control::2 8216 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.369319 -system.ruby.network.routers2.msg_count.Request_Control::1 464 -system.ruby.network.routers2.msg_count.Response_Data::2 464 -system.ruby.network.routers2.msg_count.Writeback_Data::2 78 -system.ruby.network.routers2.msg_count.Writeback_Control::1 156 -system.ruby.network.routers2.msg_count.Unblock_Control::2 463 -system.ruby.network.routers2.msg_bytes.Request_Control::1 3712 -system.ruby.network.routers2.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers2.msg_bytes.Writeback_Data::2 5616 -system.ruby.network.routers2.msg_bytes.Writeback_Control::1 1248 -system.ruby.network.routers2.msg_bytes.Unblock_Control::2 3704 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 6.521592 -system.ruby.network.routers3.msg_count.Request_Control::0 544 -system.ruby.network.routers3.msg_count.Request_Control::1 464 -system.ruby.network.routers3.msg_count.Response_Data::2 928 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 80 -system.ruby.network.routers3.msg_count.Writeback_Data::2 560 -system.ruby.network.routers3.msg_count.Writeback_Control::0 1004 -system.ruby.network.routers3.msg_count.Writeback_Control::1 156 -system.ruby.network.routers3.msg_count.Unblock_Control::2 1027 -system.ruby.network.routers3.msg_bytes.Request_Control::0 4352 -system.ruby.network.routers3.msg_bytes.Request_Control::1 3712 -system.ruby.network.routers3.msg_bytes.Response_Data::2 66816 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 5760 -system.ruby.network.routers3.msg_bytes.Writeback_Data::2 40320 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 8032 -system.ruby.network.routers3.msg_bytes.Writeback_Control::1 1248 -system.ruby.network.routers3.msg_bytes.Unblock_Control::2 8216 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 3024 -system.ruby.network.msg_count.Response_Data 2784 -system.ruby.network.msg_count.ResponseL2hit_Data 240 -system.ruby.network.msg_count.Writeback_Data 1680 -system.ruby.network.msg_count.Writeback_Control 3480 -system.ruby.network.msg_count.Unblock_Control 3081 -system.ruby.network.msg_byte.Request_Control 24192 -system.ruby.network.msg_byte.Response_Data 200448 -system.ruby.network.msg_byte.ResponseL2hit_Data 17280 -system.ruby.network.msg_byte.Writeback_Data 120960 -system.ruby.network.msg_byte.Writeback_Control 27840 -system.ruby.network.msg_byte.Unblock_Control 24648 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.102193 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 464 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 80 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 502 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 5760 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers0.throttle1.link_utilization 6.723943 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 544 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 482 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 502 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 564 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 4352 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 34704 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers1.throttle0.link_utilization 11.532896 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 544 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 464 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 482 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 502 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 78 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 564 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 4352 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 34704 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers1.throttle1.link_utilization 8.031879 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 464 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 464 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 80 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 78 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 502 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 78 -system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 463 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 3712 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 5760 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 5616 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 3704 -system.ruby.network.routers2.throttle0.link_utilization 1.929686 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 464 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 78 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 78 -system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 463 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 3712 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 5616 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 3704 -system.ruby.network.routers2.throttle1.link_utilization 4.808953 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 464 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 78 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers3.throttle0.link_utilization 6.102193 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 464 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 80 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 502 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 5760 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers3.throttle1.link_utilization 11.532896 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 544 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 464 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 482 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 502 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 78 -system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 564 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 4352 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 34704 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers3.throttle2.link_utilization 1.929686 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 464 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 78 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 78 -system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 463 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 3712 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 5616 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 3704 -system.ruby.LD.latency_hist_seqr::bucket_size 64 -system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 27.790361 -system.ruby.LD.latency_hist_seqr::gmean 5.600782 -system.ruby.LD.latency_hist_seqr::stdev 40.269706 -system.ruby.LD.latency_hist_seqr | 320 77.11% 77.11% | 92 22.17% 99.28% | 1 0.24% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 415 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 233 -system.ruby.LD.hit_latency_hist_seqr::mean 1 -system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 233 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 182 -system.ruby.LD.miss_latency_hist_seqr::mean 62.087912 -system.ruby.LD.miss_latency_hist_seqr::gmean 50.836003 -system.ruby.LD.miss_latency_hist_seqr::stdev 40.030554 -system.ruby.LD.miss_latency_hist_seqr | 87 47.80% 47.80% | 92 50.55% 98.35% | 1 0.55% 98.90% | 0 0.00% 98.90% | 1 0.55% 99.45% | 1 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 182 -system.ruby.ST.latency_hist_seqr::bucket_size 16 -system.ruby.ST.latency_hist_seqr::max_bucket 159 -system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 19.755102 -system.ruby.ST.latency_hist_seqr::gmean 3.497030 -system.ruby.ST.latency_hist_seqr::stdev 31.010753 -system.ruby.ST.latency_hist_seqr | 202 68.71% 68.71% | 12 4.08% 72.79% | 34 11.56% 84.35% | 1 0.34% 84.69% | 0 0.00% 84.69% | 44 14.97% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 294 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 202 -system.ruby.ST.hit_latency_hist_seqr::mean 1 -system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 202 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 202 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 -system.ruby.ST.miss_latency_hist_seqr::samples 92 -system.ruby.ST.miss_latency_hist_seqr::mean 60.934783 -system.ruby.ST.miss_latency_hist_seqr::gmean 54.635401 -system.ruby.ST.miss_latency_hist_seqr::stdev 24.518127 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 12 13.04% 13.04% | 34 36.96% 50.00% | 1 1.09% 51.09% | 0 0.00% 51.09% | 44 47.83% 98.91% | 1 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 92 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 9.127660 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.562445 -system.ruby.IFETCH.latency_hist_seqr::stdev 26.109704 -system.ruby.IFETCH.latency_hist_seqr | 2341 90.56% 90.56% | 240 9.28% 99.85% | 1 0.04% 99.88% | 0 0.00% 99.88% | 2 0.08% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 2585 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 2315 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 2315 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 270 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.814815 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 71.697206 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 33.251813 -system.ruby.IFETCH.miss_latency_hist_seqr | 26 9.63% 9.63% | 240 88.89% 98.52% | 1 0.37% 98.89% | 0 0.00% 98.89% | 2 0.74% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 270 -system.ruby.Directory_Controller.GETX 80 0.00% 0.00% -system.ruby.Directory_Controller.GETS 384 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 78 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 262 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 121 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 78 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 464 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 78 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 40 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 262 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 77 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 40 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 122 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 78 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 262 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 262 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 121 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 122 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 80 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 1 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 78 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 508 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 436 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 108 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 20 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack_Data 482 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks 92 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_Timeout 108 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 182 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 270 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 58 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Load 108 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Ifetch 2315 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Store 34 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 396 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 9 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 4 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 10 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Load 14 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Store 2 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Use_Timeout 14 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 89 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 84 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement 96 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Load 13 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Store 112 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement 6 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Use_Timeout 94 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 58 0.00% 0.00% -system.ruby.L1Cache_Controller.SM.Exclusive_Data 34 0.00% 0.00% -system.ruby.L1Cache_Controller.OM.All_acks 92 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 436 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 16 0.00% 0.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack 20 0.00% 0.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 376 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 106 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 452 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 93 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 106 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS_only 396 0.00% 0.00% -system.ruby.L2Cache_Controller.All_Acks 80 0.00% 0.00% -system.ruby.L2Cache_Controller.Data 464 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBCLEANDATA 376 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 106 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Ack 78 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 455 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 108 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 443 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 384 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 45 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_GETX 32 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 376 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTX 106 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS 52 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 335 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 20 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L2_Replacement 30 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 16 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 12 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 78 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 376 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.Unblock 20 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 106 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data 384 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Unblock 383 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.Data 46 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.Data 34 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.All_Acks 80 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 12 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.Unblock 52 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 16 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.Writeback_Ack 78 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini deleted file mode 100644 index cf25b799b..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ /dev/null @@ -1,2138 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persistentToDir requestFromDir requestToDir responseFromDir responseFromMemory responseToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=5 -distributed_persistent=true -dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir -dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir -eventq_index=0 -fixed_timeout_latency=100 -l2_select_num_bits=0 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir -persistentToDir=system.ruby.dir_cntrl0.persistentToDir -power_model=Null -recycle_latency=10 -reissue_wakeup_latency=10 -requestFromDir=system.ruby.dir_cntrl0.requestFromDir -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=4 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.dmaRequestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[10] - -[system.ruby.dir_cntrl0.dmaResponseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[9] - -[system.ruby.dir_cntrl0.persistentFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[8] - -[system.ruby.dir_cntrl0.persistentToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[9] - -[system.ruby.dir_cntrl0.requestFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[6] - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[7] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[7] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[8] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache mandatoryQueue persistentFromL1Cache persistentToL1Cache requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -N_tokens=2 -buffer_size=0 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -dynamic_timeout_enabled=true -eventq_index=0 -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -no_mig_atomic=true -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache -persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache -power_model=Null -recycle_latency=10 -reissue_wakeup_latency=10 -requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache -requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache -responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache -responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache -retry_threshold=1 -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=4 -use_timeout_latency=50 -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.persistentFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.l1_cntrl0.persistentToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.l1_cntrl0.requestFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.requestToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.responseFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.l2_cntrl0] -type=L2Cache_Controller -children=GlobalRequestFromL2Cache GlobalRequestToL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache persistentToL2Cache responseFromL2Cache responseToL2Cache -GlobalRequestFromL2Cache=system.ruby.l2_cntrl0.GlobalRequestFromL2Cache -GlobalRequestToL2Cache=system.ruby.l2_cntrl0.GlobalRequestToL2Cache -L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache -L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache -L2cache=system.ruby.l2_cntrl0.L2cache -N_tokens=2 -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -filtering_enabled=true -l2_request_latency=5 -l2_response_latency=5 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache -power_model=Null -recycle_latency=10 -responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache -responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache -ruby_system=system.ruby -system=system -transitions_per_cycle=4 -version=0 - -[system.ruby.l2_cntrl0.GlobalRequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.l2_cntrl0.GlobalRequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.l2_cntrl0.L1RequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.l2_cntrl0.L1RequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.l2_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l2_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l2_cntrl0.persistentToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[6] - -[system.ruby.l2_cntrl0.responseFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.l2_cntrl0.responseToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 -netifs= -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l1_cntrl0.persistentToL1Cache.slave system.ruby.l2_cntrl0.GlobalRequestToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.l2_cntrl0.persistentToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave system.ruby.dir_cntrl0.persistentToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave -slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l1_cntrl0.persistentFromL1Cache.master system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.requestFromDir.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.persistentFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l2_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers36] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers37] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers38] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers39] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers40] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers41] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers42] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers43] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers44] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers45] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers46] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers47] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers48] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers49] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers50] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers51] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers52] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers53] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers54] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers55] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers56] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers57] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers58] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers59] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers60] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers61] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers62] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers63] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers64] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers65] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers66] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers67] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers68] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers69] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers70] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers71] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=6 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links4] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=7 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links5] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=8 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 system.ruby.network.routers0.port_buffers18 system.ruby.network.routers0.port_buffers19 system.ruby.network.routers0.port_buffers20 system.ruby.network.routers0.port_buffers21 system.ruby.network.routers0.port_buffers22 system.ruby.network.routers0.port_buffers23 -power_model=Null -router_id=0 -virt_nets=6 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 system.ruby.network.routers1.port_buffers18 system.ruby.network.routers1.port_buffers19 system.ruby.network.routers1.port_buffers20 system.ruby.network.routers1.port_buffers21 system.ruby.network.routers1.port_buffers22 system.ruby.network.routers1.port_buffers23 -power_model=Null -router_id=1 -virt_nets=6 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 -power_model=Null -router_id=2 -virt_nets=6 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35 -power_model=Null -router_id=3 -virt_nets=6 - -[system.ruby.network.routers3.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr deleted file mode 100755 index 63982fce4..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr +++ /dev/null @@ -1,11 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout deleted file mode 100755 index 57e88573f..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ /dev/null @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:33:48 -gem5 started Oct 13 2016 20:34:16 -gem5 executing on e108600-lin, pid 27527 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 42756 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt deleted file mode 100644 index 7864412c9..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ /dev/null @@ -1,850 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000043 # Number of seconds simulated -sim_ticks 42756 # Number of ticks simulated -final_tick 42756 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 103649 # Simulator instruction rate (inst/s) -host_op_rate 103608 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1718399 # Simulator tick rate (ticks/s) -host_mem_usage 412956 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28672 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 28672 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5376 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 5376 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 448 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 448 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 84 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 84 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 670595940 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 670595940 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 125736739 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 125736739 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 796332678 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 796332678 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 448 # Number of read requests accepted -system.mem_ctrls.writeReqs 84 # Number of write requests accepted -system.mem_ctrls.readBursts 448 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 84 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 24000 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 4672 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 28672 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 5376 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 73 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 38 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 37 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 70 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 72 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 29 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 16 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 23 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 60 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 11 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 5 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 7 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 42675 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 448 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 84 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 375 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 72 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 326.222222 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 214.888456 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 283.209683 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 20 27.78% 27.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 16 22.22% 50.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 10 13.89% 63.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 5 6.94% 70.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 9 12.50% 83.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 2 2.78% 86.11% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 6 8.33% 94.44% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 2 2.78% 97.22% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 2 2.78% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 72 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 245 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 245.000000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::240-247 1 100.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 4832 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 11957 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.89 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.89 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 561.32 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 23.95 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 670.60 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 125.74 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.57 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.39 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.19 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.84 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 296 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 78.93 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 80.22 # Average gap between requests -system.mem_ctrls.pageHitRate 73.87 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 178500 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 81144 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1816416 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 2612424 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 73344 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 15837336 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 808320 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 24480684 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 572.567219 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 36801 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 51 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 2105 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 4569 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 34731 # Time in different power states -system.mem_ctrls_1.actEnergy 392700 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 197064 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2467584 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 3542208 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 293376 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 15524520 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 68736 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 25693020 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 600.921976 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 33391 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 512 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 179 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 6720 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 34045 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 42756 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 42756 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 42756 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 3295 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 11.979964 -system.ruby.latency_hist_seqr::gmean 1.922311 -system.ruby.latency_hist_seqr::stdev 28.863148 -system.ruby.latency_hist_seqr | 2919 88.62% 88.62% | 368 11.17% 99.79% | 2 0.06% 99.85% | 1 0.03% 99.88% | 0 0.00% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 3294 -system.ruby.hit_latency_hist_seqr::bucket_size 4 -system.ruby.hit_latency_hist_seqr::max_bucket 39 -system.ruby.hit_latency_hist_seqr::samples 2846 -system.ruby.hit_latency_hist_seqr::mean 1.555868 -system.ruby.hit_latency_hist_seqr::gmean 1.080822 -system.ruby.hit_latency_hist_seqr::stdev 3.505788 -system.ruby.hit_latency_hist_seqr | 2776 97.54% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 8 0.28% 97.82% | 62 2.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 2846 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 448 -system.ruby.miss_latency_hist_seqr::mean 78.200893 -system.ruby.miss_latency_hist_seqr::gmean 74.547837 -system.ruby.miss_latency_hist_seqr::stdev 31.179064 -system.ruby.miss_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 0 0.00% 99.11% | 4 0.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 448 -system.ruby.Directory.incomplete_times_seqr 447 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 461 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 248 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 5.680489 -system.ruby.network.routers0.msg_count.Request_Control::1 518 -system.ruby.network.routers0.msg_count.Response_Data::4 448 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 70 -system.ruby.network.routers0.msg_count.Response_Control::4 1 -system.ruby.network.routers0.msg_count.Writeback_Data::4 502 -system.ruby.network.routers0.msg_count.Persistent_Control::3 16 -system.ruby.network.routers0.msg_bytes.Request_Control::1 4144 -system.ruby.network.routers0.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 5040 -system.ruby.network.routers0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers0.msg_bytes.Writeback_Data::4 36144 -system.ruby.network.routers0.msg_bytes.Persistent_Control::3 128 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 4.239171 -system.ruby.network.routers1.msg_count.Request_Control::1 518 -system.ruby.network.routers1.msg_count.Request_Control::2 454 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 70 -system.ruby.network.routers1.msg_count.Response_Control::4 1 -system.ruby.network.routers1.msg_count.Writeback_Data::4 586 -system.ruby.network.routers1.msg_count.Writeback_Control::4 365 -system.ruby.network.routers1.msg_count.Persistent_Control::3 8 -system.ruby.network.routers1.msg_bytes.Request_Control::1 4144 -system.ruby.network.routers1.msg_bytes.Request_Control::2 3632 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 5040 -system.ruby.network.routers1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers1.msg_bytes.Writeback_Data::4 42192 -system.ruby.network.routers1.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers1.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.283165 -system.ruby.network.routers2.msg_count.Request_Control::2 454 -system.ruby.network.routers2.msg_count.Response_Data::4 448 -system.ruby.network.routers2.msg_count.Writeback_Data::4 84 -system.ruby.network.routers2.msg_count.Writeback_Control::4 365 -system.ruby.network.routers2.msg_count.Persistent_Control::3 8 -system.ruby.network.routers2.msg_bytes.Request_Control::2 3632 -system.ruby.network.routers2.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers2.msg_bytes.Writeback_Data::4 6048 -system.ruby.network.routers2.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers2.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 4.400942 -system.ruby.network.routers3.msg_count.Request_Control::1 518 -system.ruby.network.routers3.msg_count.Request_Control::2 454 -system.ruby.network.routers3.msg_count.Response_Data::4 448 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 70 -system.ruby.network.routers3.msg_count.Response_Control::4 1 -system.ruby.network.routers3.msg_count.Writeback_Data::4 586 -system.ruby.network.routers3.msg_count.Writeback_Control::4 365 -system.ruby.network.routers3.msg_count.Persistent_Control::3 16 -system.ruby.network.routers3.msg_bytes.Request_Control::1 4144 -system.ruby.network.routers3.msg_bytes.Request_Control::2 3632 -system.ruby.network.routers3.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 5040 -system.ruby.network.routers3.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.msg_bytes.Writeback_Data::4 42192 -system.ruby.network.routers3.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers3.msg_bytes.Persistent_Control::3 128 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 2916 -system.ruby.network.msg_count.Response_Data 1344 -system.ruby.network.msg_count.ResponseL2hit_Data 210 -system.ruby.network.msg_count.Response_Control 3 -system.ruby.network.msg_count.Writeback_Data 1758 -system.ruby.network.msg_count.Writeback_Control 1095 -system.ruby.network.msg_count.Persistent_Control 48 -system.ruby.network.msg_byte.Request_Control 23328 -system.ruby.network.msg_byte.Response_Data 96768 -system.ruby.network.msg_byte.ResponseL2hit_Data 15120 -system.ruby.network.msg_byte.Response_Control 24 -system.ruby.network.msg_byte.Writeback_Data 126576 -system.ruby.network.msg_byte.Writeback_Control 8760 -system.ruby.network.msg_byte.Persistent_Control 384 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 5.462391 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 8 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 5040 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers0.throttle1.link_utilization 5.898587 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 518 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 502 -system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 8 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 4144 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 36144 -system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers1.throttle0.link_utilization 5.898587 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 518 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 502 -system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 8 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 4144 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 36144 -system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers1.throttle1.link_utilization 2.579755 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 454 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 70 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 84 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 365 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 3632 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 5040 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 6048 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers2.throttle0.link_utilization 1.851202 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 454 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 84 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 365 -system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 8 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 3632 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 6048 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers2.throttle1.link_utilization 4.715128 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 448 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers3.throttle0.link_utilization 5.453036 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 448 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 70 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 5040 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.throttle1.link_utilization 5.898587 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 518 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 502 -system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 8 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 4144 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 36144 -system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers3.throttle2.link_utilization 1.851202 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 454 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 84 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 365 -system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 8 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 3632 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 6048 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 64 -system.ruby.LD.latency_hist_seqr::bucket_size 16 -system.ruby.LD.latency_hist_seqr::max_bucket 159 -system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 27.997590 -system.ruby.LD.latency_hist_seqr::gmean 5.837138 -system.ruby.LD.latency_hist_seqr::stdev 35.585408 -system.ruby.LD.latency_hist_seqr | 233 56.14% 56.14% | 33 7.95% 64.10% | 48 11.57% 75.66% | 2 0.48% 76.14% | 68 16.39% 92.53% | 18 4.34% 96.87% | 10 2.41% 99.28% | 1 0.24% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% -system.ruby.LD.latency_hist_seqr::total 415 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 4 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 39 -system.ruby.LD.hit_latency_hist_seqr::samples 266 -system.ruby.LD.hit_latency_hist_seqr::mean 3.845865 -system.ruby.LD.hit_latency_hist_seqr::gmean 1.482816 -system.ruby.LD.hit_latency_hist_seqr::stdev 7.577195 -system.ruby.LD.hit_latency_hist_seqr | 233 87.59% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 1 0.38% 87.97% | 32 12.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 266 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 16 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 159 -system.ruby.LD.miss_latency_hist_seqr::samples 149 -system.ruby.LD.miss_latency_hist_seqr::mean 71.114094 -system.ruby.LD.miss_latency_hist_seqr::gmean 67.393219 -system.ruby.LD.miss_latency_hist_seqr::stdev 22.792700 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 68 45.64% 79.19% | 18 12.08% 91.28% | 10 6.71% 97.99% | 1 0.67% 98.66% | 0 0.00% 98.66% | 2 1.34% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 149 -system.ruby.ST.latency_hist_seqr::bucket_size 16 -system.ruby.ST.latency_hist_seqr::max_bucket 159 -system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 13.153061 -system.ruby.ST.latency_hist_seqr::gmean 2.398410 -system.ruby.ST.latency_hist_seqr::stdev 25.296880 -system.ruby.ST.latency_hist_seqr | 228 77.55% 77.55% | 14 4.76% 82.31% | 20 6.80% 89.12% | 3 1.02% 90.14% | 23 7.82% 97.96% | 6 2.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 294 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 4 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 39 -system.ruby.ST.hit_latency_hist_seqr::samples 242 -system.ruby.ST.hit_latency_hist_seqr::mean 2.223140 -system.ruby.ST.hit_latency_hist_seqr::gmean 1.195990 -system.ruby.ST.hit_latency_hist_seqr::stdev 4.967926 -system.ruby.ST.hit_latency_hist_seqr | 228 94.21% 94.21% | 0 0.00% 94.21% | 0 0.00% 94.21% | 0 0.00% 94.21% | 0 0.00% 94.21% | 7 2.89% 97.11% | 7 2.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 242 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 -system.ruby.ST.miss_latency_hist_seqr::samples 52 -system.ruby.ST.miss_latency_hist_seqr::mean 64.019231 -system.ruby.ST.miss_latency_hist_seqr::gmean 61.135942 -system.ruby.ST.miss_latency_hist_seqr::stdev 18.838311 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 52 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 9.275048 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.568384 -system.ruby.IFETCH.latency_hist_seqr::stdev 27.157574 -system.ruby.IFETCH.latency_hist_seqr | 2338 90.44% 90.44% | 242 9.36% 99.81% | 0 0.00% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 4 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 2585 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 4 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 39 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 2338 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.226262 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.031758 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev 2.270469 -system.ruby.IFETCH.hit_latency_hist_seqr | 2315 99.02% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 23 0.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 2338 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 247 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 85.461538 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 82.604305 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.418255 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 0 0.00% 98.38% | 4 1.62% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 247 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 2776 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 2776 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 2776 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 4 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 39 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 70 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.600000 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.569187 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.159710 -system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 11.43% 11.43% | 62 88.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 70 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 448 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 78.200893 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 74.547837 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 31.179064 -system.ruby.Directory.miss_mach_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 0 0.00% 99.11% | 4 0.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 448 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 16 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 159 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 82 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 82.000000 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 233 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 233 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 33 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.939394 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.936802 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 0.348155 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 3.03% 3.03% | 32 96.97% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 33 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 149 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 71.114094 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 67.393219 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 22.792700 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 68 45.64% 79.19% | 18 12.08% 91.28% | 10 6.71% 97.99% | 1 0.67% 98.66% | 0 0.00% 98.66% | 2 1.34% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 149 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 228 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 228 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 228 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 14 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.142857 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.058564 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.994498 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 50.00% 50.00% | 7 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 14 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 52 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 64.019231 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 61.135942 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 18.838311 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 52 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 2315 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 2315 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 23 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.000000 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 23 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 23 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 247 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 85.461538 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 82.604305 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.418255 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 0 0.00% 98.38% | 4 1.62% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 247 -system.ruby.Directory_Controller.GETX 61 0.00% 0.00% -system.ruby.Directory_Controller.GETS 398 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 4 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 4 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 3 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 81 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 16 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 334 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 15 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 448 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 52 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 396 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 15 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 1 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 334 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 4 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 3 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 3 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 445 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 504 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_Shared 56 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_All_Tokens 462 0.00% 0.00% -system.ruby.L1Cache_Controller.Ack 1 0.00% 0.00% -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 8 0.00% 0.00% -system.ruby.L1Cache_Controller.Request_Timeout 4 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 461 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 182 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Ifetch 270 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Store 58 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Load 29 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Ifetch 158 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Store 8 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 48 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 66 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 1098 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 29 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 358 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 4 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 96 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 103 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement 96 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Load 36 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Ifetch 1059 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Store 3 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 392 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Load 6 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Store 93 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 69 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_All_Tokens 58 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Ack 1 0.00% 0.00% -system.ruby.L1Cache_Controller.SM.Data_All_Tokens 8 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_Shared 56 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_All_Tokens 396 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 4 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Request_Timeout 4 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 448 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS_Last_Token 4 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 66 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 458 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Shared_Data 21 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_All_Tokens 481 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS 4 0.00% 0.00% -system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 4 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 396 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 50 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 18 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 448 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 4 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L2_Replacement 9 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 3 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 6 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 4 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 15 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L1_GETX 6 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L2_Replacement 19 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 27 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 52 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 8 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 415 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETS 4 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini deleted file mode 100644 index 8207d6ac7..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ /dev/null @@ -1,1514 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter requestToDir responseFromDir responseFromMemory responseToDir triggerQueue unblockToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir -dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir -eventq_index=0 -forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir -from_memory_controller_latency=2 -full_bit_dir_enabled=false -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -probeFilter=system.ruby.dir_cntrl0.probeFilter -probe_filter_enabled=false -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=4 -triggerQueue=system.ruby.dir_cntrl0.triggerQueue -unblockToDir=system.ruby.dir_cntrl0.unblockToDir -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.dmaRequestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.dir_cntrl0.dmaResponseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.dir_cntrl0.forwardFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.dir_cntrl0.probeFilter] -type=RubyCache -children=replacement_policy -assoc=4 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.dir_cntrl0.probeFilter.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=1024 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.dir_cntrl0.probeFilter.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=4 -block_size=64 -eventq_index=0 -size=1024 - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.dir_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.dir_cntrl0.unblockToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache L2cache forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer triggerQueue unblockFromCache -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -L2cache=system.ruby.l1_cntrl0.L2cache -buffer_size=0 -cache_response_latency=10 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -forwardToCache=system.ruby.l1_cntrl0.forwardToCache -issue_latency=2 -l2_cache_hit_latency=10 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -no_mig_atomic=true -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestFromCache=system.ruby.l1_cntrl0.requestFromCache -responseFromCache=system.ruby.l1_cntrl0.responseFromCache -responseToCache=system.ruby.l1_cntrl0.responseToCache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=4 -triggerQueue=system.ruby.l1_cntrl0.triggerQueue -unblockFromCache=system.ruby.l1_cntrl0.unblockFromCache -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=true -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l1_cntrl0.forwardToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.requestFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.responseFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.l1_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.unblockFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 -netifs= -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.unblockToDir.slave system.ruby.dir_cntrl0.responseToDir.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave -slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.l1_cntrl0.unblockFromCache.master system.ruby.dir_cntrl0.forwardFromDir.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers36] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers37] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers38] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers39] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers40] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers41] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers42] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers43] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers44] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers45] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers46] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers47] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=2 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 -power_model=Null -router_id=0 -virt_nets=6 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 -power_model=Null -router_id=1 -virt_nets=6 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 -power_model=Null -router_id=2 -virt_nets=6 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr deleted file mode 100755 index 63982fce4..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr +++ /dev/null @@ -1,11 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout deleted file mode 100755 index 35b481dda..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ /dev/null @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout -Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:24:36 -gem5 started Oct 13 2016 20:24:58 -gem5 executing on e108600-lin, pid 38874 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 35056 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt deleted file mode 100644 index af200054c..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ /dev/null @@ -1,778 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 35056 # Number of ticks simulated -final_tick 35056 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 89727 # Simulator instruction rate (inst/s) -host_op_rate 89697 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1219820 # Simulator tick rate (ticks/s) -host_mem_usage 412632 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28224 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 28224 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5184 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 5184 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 441 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 441 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 81 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 81 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 805111821 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 805111821 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 147877681 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 147877681 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 952989503 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 952989503 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 441 # Number of read requests accepted -system.mem_ctrls.writeReqs 81 # Number of write requests accepted -system.mem_ctrls.readBursts 441 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 81 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 24000 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 4224 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 28224 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 5184 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 66 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 35 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 37 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 72 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 71 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 29 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 16 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 23 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 59 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 11 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 5 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 7 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 34986 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 441 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 81 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 375 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 67 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 356.298507 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 230.035457 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 306.978482 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 19 28.36% 28.36% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 11 16.42% 44.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 10 14.93% 59.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 7 10.45% 70.15% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 6 8.96% 79.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 4 5.97% 85.07% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 3 4.48% 89.55% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 4.48% 94.03% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 4 5.97% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 67 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 245 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 245.000000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::240-247 1 100.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 4501 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 11626 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.00 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.00 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 684.62 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 29.21 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 805.11 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 147.88 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 5.58 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 5.35 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.23 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.49 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 302 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 80.53 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 67.02 # Average gap between requests -system.mem_ctrls.pageHitRate 75.30 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 164220 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 77280 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1839264 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 2689032 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 56064 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 13011960 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 183552 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 20479932 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 584.206184 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 29013 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 34 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 478 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 4969 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 28535 # Time in different power states -system.mem_ctrls_1.actEnergy 364140 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 181608 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2444736 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 3405408 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 211968 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 12011952 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 266496 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 21478500 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 612.691123 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 26306 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 440 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 694 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 6540 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 26342 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 35056 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 35056 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 35056 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 3295 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 32 -system.ruby.latency_hist_seqr::max_bucket 319 -system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 9.642380 -system.ruby.latency_hist_seqr::gmean 1.819734 -system.ruby.latency_hist_seqr::stdev 23.663336 -system.ruby.latency_hist_seqr | 2910 88.34% 88.34% | 293 8.89% 97.24% | 85 2.58% 99.82% | 2 0.06% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 4 0.12% 100.00% -system.ruby.latency_hist_seqr::total 3294 -system.ruby.hit_latency_hist_seqr::bucket_size 2 -system.ruby.hit_latency_hist_seqr::max_bucket 19 -system.ruby.hit_latency_hist_seqr::samples 2853 -system.ruby.hit_latency_hist_seqr::mean 1.241851 -system.ruby.hit_latency_hist_seqr::gmean 1.059708 -system.ruby.hit_latency_hist_seqr::stdev 1.536503 -system.ruby.hit_latency_hist_seqr | 2784 97.58% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 69 2.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 2853 -system.ruby.miss_latency_hist_seqr::bucket_size 32 -system.ruby.miss_latency_hist_seqr::max_bucket 319 -system.ruby.miss_latency_hist_seqr::samples 441 -system.ruby.miss_latency_hist_seqr::mean 63.988662 -system.ruby.miss_latency_hist_seqr::gmean 60.139666 -system.ruby.miss_latency_hist_seqr::stdev 27.525151 -system.ruby.miss_latency_hist_seqr | 57 12.93% 12.93% | 293 66.44% 79.37% | 85 19.27% 98.64% | 2 0.45% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 4 0.91% 100.00% -system.ruby.miss_latency_hist_seqr::total 441 -system.ruby.Directory.incomplete_times_seqr 440 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.fully_busy_cycles 5 # cycles for which number of transistions == max transitions -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 4.830129 -system.ruby.network.routers0.msg_count.Request_Control::2 441 -system.ruby.network.routers0.msg_count.Response_Data::4 441 -system.ruby.network.routers0.msg_count.Writeback_Data::5 81 -system.ruby.network.routers0.msg_count.Writeback_Control::2 425 -system.ruby.network.routers0.msg_count.Writeback_Control::3 425 -system.ruby.network.routers0.msg_count.Writeback_Control::5 344 -system.ruby.network.routers0.msg_count.Unblock_Control::5 440 -system.ruby.network.routers0.msg_bytes.Request_Control::2 3528 -system.ruby.network.routers0.msg_bytes.Response_Data::4 31752 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 5832 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 3400 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 2752 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 4.830129 -system.ruby.network.routers1.msg_count.Request_Control::2 441 -system.ruby.network.routers1.msg_count.Response_Data::4 441 -system.ruby.network.routers1.msg_count.Writeback_Data::5 81 -system.ruby.network.routers1.msg_count.Writeback_Control::2 425 -system.ruby.network.routers1.msg_count.Writeback_Control::3 425 -system.ruby.network.routers1.msg_count.Writeback_Control::5 344 -system.ruby.network.routers1.msg_count.Unblock_Control::5 440 -system.ruby.network.routers1.msg_bytes.Request_Control::2 3528 -system.ruby.network.routers1.msg_bytes.Response_Data::4 31752 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 5832 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 3400 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 2752 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 4.830129 -system.ruby.network.routers2.msg_count.Request_Control::2 441 -system.ruby.network.routers2.msg_count.Response_Data::4 441 -system.ruby.network.routers2.msg_count.Writeback_Data::5 81 -system.ruby.network.routers2.msg_count.Writeback_Control::2 425 -system.ruby.network.routers2.msg_count.Writeback_Control::3 425 -system.ruby.network.routers2.msg_count.Writeback_Control::5 344 -system.ruby.network.routers2.msg_count.Unblock_Control::5 440 -system.ruby.network.routers2.msg_bytes.Request_Control::2 3528 -system.ruby.network.routers2.msg_bytes.Response_Data::4 31752 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 5832 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 3400 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 2752 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 1323 -system.ruby.network.msg_count.Response_Data 1323 -system.ruby.network.msg_count.Writeback_Data 243 -system.ruby.network.msg_count.Writeback_Control 3582 -system.ruby.network.msg_count.Unblock_Control 1320 -system.ruby.network.msg_byte.Request_Control 10584 -system.ruby.network.msg_byte.Response_Data 95256 -system.ruby.network.msg_byte.Writeback_Data 17496 -system.ruby.network.msg_byte.Writeback_Control 28656 -system.ruby.network.msg_byte.Unblock_Control 10560 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.267115 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 31752 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers0.throttle1.link_utilization 3.393142 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 441 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 81 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 425 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 344 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 440 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 3528 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 5832 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 3400 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 2752 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers1.throttle0.link_utilization 3.393142 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 441 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 81 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 425 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 344 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 440 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 3528 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 5832 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 3400 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 2752 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers1.throttle1.link_utilization 6.267115 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 441 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 425 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 31752 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers2.throttle0.link_utilization 6.267115 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 441 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 425 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 31752 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers2.throttle1.link_utilization 3.393142 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 441 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 81 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 425 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 344 -system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 440 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 3528 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 5832 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 3400 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 2752 -system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 3520 -system.ruby.LD.latency_hist_seqr::bucket_size 16 -system.ruby.LD.latency_hist_seqr::max_bucket 159 -system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 21.354217 -system.ruby.LD.latency_hist_seqr::gmean 4.945859 -system.ruby.LD.latency_hist_seqr::stdev 28.670834 -system.ruby.LD.latency_hist_seqr | 269 64.82% 64.82% | 42 10.12% 74.94% | 3 0.72% 75.66% | 69 16.63% 92.29% | 18 4.34% 96.63% | 14 3.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 415 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 2 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 19 -system.ruby.LD.hit_latency_hist_seqr::samples 269 -system.ruby.LD.hit_latency_hist_seqr::mean 2.338290 -system.ruby.LD.hit_latency_hist_seqr::gmean 1.378379 -system.ruby.LD.hit_latency_hist_seqr::stdev 3.411031 -system.ruby.LD.hit_latency_hist_seqr | 233 86.62% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 36 13.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 269 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 16 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 159 -system.ruby.LD.miss_latency_hist_seqr::samples 146 -system.ruby.LD.miss_latency_hist_seqr::mean 56.390411 -system.ruby.LD.miss_latency_hist_seqr::gmean 52.068669 -system.ruby.LD.miss_latency_hist_seqr::stdev 20.461022 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 69 47.26% 78.08% | 18 12.33% 90.41% | 14 9.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 146 -system.ruby.ST.latency_hist_seqr::bucket_size 8 -system.ruby.ST.latency_hist_seqr::max_bucket 79 -system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 9.778912 -system.ruby.ST.latency_hist_seqr::gmean 2.043604 -system.ruby.ST.latency_hist_seqr::stdev 20.538869 -system.ruby.ST.latency_hist_seqr | 236 80.27% 80.27% | 11 3.74% 84.01% | 0 0.00% 84.01% | 15 5.10% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 22 7.48% 96.60% | 5 1.70% 98.30% | 5 1.70% 100.00% -system.ruby.ST.latency_hist_seqr::total 294 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 2 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 19 -system.ruby.ST.hit_latency_hist_seqr::samples 247 -system.ruby.ST.hit_latency_hist_seqr::mean 1.445344 -system.ruby.ST.hit_latency_hist_seqr::gmean 1.112699 -system.ruby.ST.hit_latency_hist_seqr::stdev 2.066980 -system.ruby.ST.hit_latency_hist_seqr | 236 95.55% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 11 4.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 247 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 8 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 79 -system.ruby.ST.miss_latency_hist_seqr::samples 47 -system.ruby.ST.miss_latency_hist_seqr::mean 53.574468 -system.ruby.ST.miss_latency_hist_seqr::gmean 49.876949 -system.ruby.ST.miss_latency_hist_seqr::stdev 18.206240 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 5 10.64% 89.36% | 5 10.64% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 47 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 7.746615 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.529553 -system.ruby.IFETCH.latency_hist_seqr::stdev 22.548460 -system.ruby.IFETCH.latency_hist_seqr | 2337 90.41% 90.41% | 199 7.70% 98.10% | 43 1.66% 99.77% | 2 0.08% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 4 0.15% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 2585 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 2337 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.094138 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.022830 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev 0.965875 -system.ruby.IFETCH.hit_latency_hist_seqr | 2315 99.06% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 22 0.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 2337 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 248 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 70.435484 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 67.827440 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 30.751253 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 199 80.24% 80.24% | 43 17.34% 97.58% | 2 0.81% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 4 1.61% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 248 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 2784 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 2784 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 2784 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 2 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 19 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 69 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 11 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 69 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 69 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 32 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 319 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 441 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 63.988662 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 60.139666 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 27.525151 -system.ruby.Directory.miss_mach_latency_hist_seqr | 57 12.93% 12.93% | 293 66.44% 79.37% | 85 19.27% 98.64% | 2 0.45% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 4 0.91% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 441 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 8 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 79 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::mean 75 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::gmean 75.000000 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 233 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 233 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 36 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 36 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 146 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.390411 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.068669 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 20.461022 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 69 47.26% 78.08% | 18 12.33% 90.41% | 14 9.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 146 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 236 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 236 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 236 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 11 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 11 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 8 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 79 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 47 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 53.574468 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 49.876949 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 18.206240 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 5 10.64% 89.36% | 5 10.64% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 47 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 2315 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 2315 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 22 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 22 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 22 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 248 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 70.435484 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 67.827440 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 30.751253 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 199 80.24% 80.24% | 43 17.34% 97.58% | 2 0.81% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 4 1.61% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 248 -system.ruby.Directory_Controller.GETX 51 0.00% 0.00% -system.ruby.Directory_Controller.GETS 410 0.00% 0.00% -system.ruby.Directory_Controller.PUT 425 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 440 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 344 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 81 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 441 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 81 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 425 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 47 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 394 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 440 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 441 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 4 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 14 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 344 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 81 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 422 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 2591 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 298 0.00% 0.00% -system.ruby.L1Cache_Controller.L2_Replacement 425 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_to_L2 502 0.00% 0.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 47 0.00% 0.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 22 0.00% 0.00% -system.ruby.L1Cache_Controller.Complete_L2_to_L1 69 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 441 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 425 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers 441 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 146 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 248 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 47 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 109 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 2315 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 35 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L2_Replacement 344 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_to_L2 397 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 23 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1I 22 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 124 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 201 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L2_Replacement 81 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_to_L2 105 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 24 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Load 22 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Ifetch 22 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Store 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Load 14 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Store 10 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 47 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 394 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 47 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 394 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Load 7 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Ifetch 6 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Store 4 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 425 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 45 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 24 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini deleted file mode 100644 index 7199cc5b0..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ /dev/null @@ -1,1266 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=5 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=12 -dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir -dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir -eventq_index=0 -forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=4 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.dmaRequestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.dir_cntrl0.dmaResponseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.dir_cntrl0.forwardFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer -buffer_size=0 -cacheMemory=system.ruby.l1_cntrl0.cacheMemory -cache_response_latency=12 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -forwardToCache=system.ruby.l1_cntrl0.forwardToCache -issue_latency=2 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestFromCache=system.ruby.l1_cntrl0.requestFromCache -responseFromCache=system.ruby.l1_cntrl0.responseFromCache -responseToCache=system.ruby.l1_cntrl0.responseToCache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=4 -version=0 - -[system.ruby.l1_cntrl0.cacheMemory] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.forwardToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.requestFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.responseFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.cacheMemory -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.cacheMemory -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 -netifs= -number_of_virtual_networks=5 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave -slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers36] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers37] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers38] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers39] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=2 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 -power_model=Null -router_id=0 -virt_nets=5 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 -power_model=Null -router_id=1 -virt_nets=5 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 -power_model=Null -router_id=2 -virt_nets=5 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr deleted file mode 100755 index 63982fce4..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr +++ /dev/null @@ -1,11 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout deleted file mode 100755 index d4c6f5ba8..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ /dev/null @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:46 -gem5 executing on e108600-lin, pid 28078 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 43520 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt deleted file mode 100644 index 38f9f0d34..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ /dev/null @@ -1,654 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000044 # Number of seconds simulated -sim_ticks 43520 # Number of ticks simulated -final_tick 43520 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 112756 # Simulator instruction rate (inst/s) -host_op_rate 112704 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1902499 # Simulator tick rate (ticks/s) -host_mem_usage 412460 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 40064 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 40064 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39808 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 39808 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 626 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 626 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 622 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 622 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 920588235 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 920588235 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 914705882 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 914705882 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1835294118 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1835294118 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 626 # Number of read requests accepted -system.mem_ctrls.writeReqs 622 # Number of write requests accepted -system.mem_ctrls.readBursts 626 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 622 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 24512 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 15552 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 23424 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 40064 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 39808 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 243 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 231 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 30 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 53 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 53 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 68 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 5 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 25 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 14 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 30 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 68 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 10 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 32 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 48 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 43 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 68 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 5 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 23 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 15 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 31 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 65 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 10 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 43487 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 626 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 622 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 383 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 17 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 26 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 28 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 113 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 404.389381 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 273.588270 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 327.373952 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 20 17.70% 17.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 26 23.01% 40.71% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 16 14.16% 54.87% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 15 13.27% 68.14% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 5 4.42% 72.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 6 5.31% 77.88% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 8 7.08% 84.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 4.42% 89.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 12 10.62% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 113 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 22 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 17 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 16.662586 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 4.253850 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 8 36.36% 36.36% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 8 36.36% 72.73% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 5 22.73% 95.45% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 4.55% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 22 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 22 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.636364 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.596436 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.216766 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 17 77.27% 77.27% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 1 4.55% 81.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 4 18.18% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 22 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 6435 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 13712 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1915 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 16.80 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 35.80 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 563.24 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 538.24 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 920.59 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 914.71 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.61 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.40 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.20 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.70 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 286 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 342 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 74.67 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 87.47 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 34.85 # Average gap between requests -system.mem_ctrls.pageHitRate 81.14 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 264180 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 127512 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1850688 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 1236096 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 3917040 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 69120 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 15256848 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 496128 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 26290812 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 604.108732 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 34684 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 40 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 1292 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 7430 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 33458 # Time in different power states -system.mem_ctrls_1.actEnergy 599760 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 309120 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2524704 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 1820736 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 5746968 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 231168 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 13781232 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 35712 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 28122600 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 646.199449 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 29649 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 448 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 93 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 11457 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 30222 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 43520 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 43520 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 43520 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 1248 # delay histogram for all message -system.ruby.delayHist | 1248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1248 # delay histogram for all message -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 3295 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 12.211900 -system.ruby.latency_hist_seqr::gmean 2.131468 -system.ruby.latency_hist_seqr::stdev 27.594720 -system.ruby.latency_hist_seqr | 2924 88.77% 88.77% | 353 10.72% 99.48% | 12 0.36% 99.85% | 0 0.00% 99.85% | 2 0.06% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 3294 -system.ruby.hit_latency_hist_seqr::bucket_size 1 -system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 2668 -system.ruby.hit_latency_hist_seqr::mean 1 -system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 2668 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 626 -system.ruby.miss_latency_hist_seqr::mean 59.996805 -system.ruby.miss_latency_hist_seqr::gmean 53.641558 -system.ruby.miss_latency_hist_seqr::stdev 34.472574 -system.ruby.miss_latency_hist_seqr | 256 40.89% 40.89% | 353 56.39% 97.28% | 12 1.92% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 626 -system.ruby.Directory.incomplete_times_seqr 625 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.169118 -system.ruby.network.routers0.msg_count.Control::2 626 -system.ruby.network.routers0.msg_count.Data::2 622 -system.ruby.network.routers0.msg_count.Response_Data::4 626 -system.ruby.network.routers0.msg_count.Writeback_Control::3 622 -system.ruby.network.routers0.msg_bytes.Control::2 5008 -system.ruby.network.routers0.msg_bytes.Data::2 44784 -system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.169118 -system.ruby.network.routers1.msg_count.Control::2 626 -system.ruby.network.routers1.msg_count.Data::2 622 -system.ruby.network.routers1.msg_count.Response_Data::4 626 -system.ruby.network.routers1.msg_count.Writeback_Control::3 622 -system.ruby.network.routers1.msg_bytes.Control::2 5008 -system.ruby.network.routers1.msg_bytes.Data::2 44784 -system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.169118 -system.ruby.network.routers2.msg_count.Control::2 626 -system.ruby.network.routers2.msg_count.Data::2 622 -system.ruby.network.routers2.msg_count.Response_Data::4 626 -system.ruby.network.routers2.msg_count.Writeback_Control::3 622 -system.ruby.network.routers2.msg_bytes.Control::2 5008 -system.ruby.network.routers2.msg_bytes.Data::2 44784 -system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 1878 -system.ruby.network.msg_count.Data 1866 -system.ruby.network.msg_count.Response_Data 1878 -system.ruby.network.msg_count.Writeback_Control 1866 -system.ruby.network.msg_byte.Control 15024 -system.ruby.network.msg_byte.Data 134352 -system.ruby.network.msg_byte.Response_Data 135216 -system.ruby.network.msg_byte.Writeback_Control 14928 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.187500 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers0.throttle1.link_utilization 7.150735 -system.ruby.network.routers0.throttle1.msg_count.Control::2 626 -system.ruby.network.routers0.throttle1.msg_count.Data::2 622 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 5008 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 44784 -system.ruby.network.routers1.throttle0.link_utilization 7.150735 -system.ruby.network.routers1.throttle0.msg_count.Control::2 626 -system.ruby.network.routers1.throttle0.msg_count.Data::2 622 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 5008 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 44784 -system.ruby.network.routers1.throttle1.link_utilization 7.187500 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 626 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 622 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.throttle0.link_utilization 7.187500 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 626 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 622 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.throttle1.link_utilization 7.150735 -system.ruby.network.routers2.throttle1.msg_count.Control::2 626 -system.ruby.network.routers2.throttle1.msg_count.Data::2 622 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 5008 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 44784 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 626 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 626 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 626 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 622 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 622 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 64 -system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 33.354217 -system.ruby.LD.latency_hist_seqr::gmean 9.992707 -system.ruby.LD.latency_hist_seqr::stdev 38.395820 -system.ruby.LD.latency_hist_seqr | 297 71.57% 71.57% | 114 27.47% 99.04% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 415 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 170 -system.ruby.LD.hit_latency_hist_seqr::mean 1 -system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 170 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 170 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 245 -system.ruby.LD.miss_latency_hist_seqr::mean 55.804082 -system.ruby.LD.miss_latency_hist_seqr::gmean 49.356103 -system.ruby.LD.miss_latency_hist_seqr::stdev 35.580698 -system.ruby.LD.miss_latency_hist_seqr | 127 51.84% 51.84% | 114 46.53% 98.37% | 2 0.82% 99.18% | 0 0.00% 99.18% | 0 0.00% 99.18% | 2 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 245 -system.ruby.ST.latency_hist_seqr::bucket_size 32 -system.ruby.ST.latency_hist_seqr::max_bucket 319 -system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 16.173469 -system.ruby.ST.latency_hist_seqr::gmean 3.033104 -system.ruby.ST.latency_hist_seqr::stdev 28.208400 -system.ruby.ST.latency_hist_seqr | 210 71.43% 71.43% | 44 14.97% 86.39% | 36 12.24% 98.64% | 1 0.34% 98.98% | 2 0.68% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 294 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 210 -system.ruby.ST.hit_latency_hist_seqr::mean 1 -system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 210 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 210 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 -system.ruby.ST.miss_latency_hist_seqr::samples 84 -system.ruby.ST.miss_latency_hist_seqr::mean 54.107143 -system.ruby.ST.miss_latency_hist_seqr::gmean 48.596564 -system.ruby.ST.miss_latency_hist_seqr::stdev 27.751487 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 44 52.38% 52.38% | 36 42.86% 95.24% | 1 1.19% 96.43% | 2 2.38% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 84 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 8.367118 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.597827 -system.ruby.IFETCH.latency_hist_seqr::stdev 23.571466 -system.ruby.IFETCH.latency_hist_seqr | 2373 91.80% 91.80% | 202 7.81% 99.61% | 7 0.27% 99.88% | 0 0.00% 99.88% | 2 0.08% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 2585 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 2288 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2288 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 2288 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 297 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.121212 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 59.083052 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.625488 -system.ruby.IFETCH.miss_latency_hist_seqr | 85 28.62% 28.62% | 202 68.01% 96.63% | 7 2.36% 98.99% | 0 0.00% 98.99% | 2 0.67% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 297 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 626 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.996805 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 53.641558 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 34.472574 -system.ruby.Directory.miss_mach_latency_hist_seqr | 256 40.89% 40.89% | 353 56.39% 97.28% | 12 1.92% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 626 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 245 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 55.804082 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.356103 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.580698 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 127 51.84% 51.84% | 114 46.53% 98.37% | 2 0.82% 99.18% | 0 0.00% 99.18% | 0 0.00% 99.18% | 2 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 245 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 84 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 54.107143 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.596564 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 27.751487 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 44 52.38% 52.38% | 36 42.86% 95.24% | 1 1.19% 96.43% | 2 2.38% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 84 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 297 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.121212 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 59.083052 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.625488 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 85 28.62% 28.62% | 202 68.01% 96.63% | 7 2.36% 98.99% | 0 0.00% 98.99% | 2 0.67% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 297 -system.ruby.Directory_Controller.GETX 626 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 626 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 622 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 626 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 622 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 626 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 622 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 626 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 622 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 622 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 245 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 297 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 84 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 170 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 2288 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 210 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 622 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 622 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 542 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 84 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini deleted file mode 100644 index 14ec42af5..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ /dev/null @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr deleted file mode 100755 index 05d0e3f61..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout deleted file mode 100755 index af6b46ed3..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout +++ /dev/null @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:23 -gem5 executing on e108600-lin, pid 39547 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 18239500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index 55cc07d2c..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,519 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18484500 # Number of ticks simulated -final_tick 18484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 287292 # Simulator instruction rate (inst/s) -host_op_rate 286342 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2049000197 # Simulator tick rate (ticks/s) -host_mem_usage 250420 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory -system.physmem.bytes_read::total 15680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10432 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory -system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 564364738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283913549 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 848278287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 564364738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 564364738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 564364738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283913549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 848278287 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 18484500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 36969 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 36969 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.258408 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.258408 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011538 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011538 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits -system.cpu.dcache.overall_hits::total 627 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses -system.cpu.dcache.overall_misses::total 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1701000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1701000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 5166000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 5166000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 5166000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 5166000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5084000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5084000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5084000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5084000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 79.631047 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 79.631047 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.038882 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.038882 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5335 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2423 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2423 # number of overall hits -system.cpu.icache.overall_hits::total 2423 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 163 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses -system.cpu.icache.overall_misses::total 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10269500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10269500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10269500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10269500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10269500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10269500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2586 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.063032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63003.067485 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63003.067485 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63003.067485 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63003.067485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63003.067485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63003.067485 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10106500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10106500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10106500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10106500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10106500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10106500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62003.067485 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62003.067485 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62003.067485 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62003.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62003.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62003.067485 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 127.028625 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 245 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.723638 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47.304987 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002433 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001444 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003877 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 245 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007477 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 163 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 163 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses -system.cpu.l2cache.overall_misses::total 245 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1633500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1633500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9862000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 9862000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9862000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4961000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14823000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9862000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4961000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14823000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 163 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 163 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.067485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.067485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.067485 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60502.040816 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.067485 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60502.040816 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 163 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 163 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1363500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1363500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8232000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8232000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8232000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4141000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12373000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8232000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4141000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12373000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.067485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50502.040816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.067485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50502.040816 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 245 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 245 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 218 # Transaction distribution -system.membus.trans_dist::ReadExReq 27 # Transaction distribution -system.membus.trans_dist::ReadExResp 27 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 218 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 245 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 245 # Request fanout histogram -system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1225000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index 5f021cba5..000000000 --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index 870cfd899..000000000 --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,52 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index 4aef5499e..000000000 --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,17 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:27 -gem5 executing on e108600-lin, pid 4289 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/30.eon/alpha/tru64/simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Eon, Version 1.1 -info: Increasing stack size by one page. -OO-style eon Time= 0.183333 -Exiting @ tick 199332411500 because target called exit() diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt deleted file mode 100644 index 79bf3fe5b..000000000 --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ /dev/null @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.199332 # Number of seconds simulated -sim_ticks 199332411500 # Number of ticks simulated -final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2875345 # Simulator instruction rate (inst/s) -host_op_rate 2875345 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1437672996 # Simulator tick rate (ticks/s) -host_mem_usage 248448 # Number of bytes of host memory used -host_seconds 138.65 # Real time elapsed on the host -sim_insts 398664595 # Number of instructions simulated -sim_ops 398664595 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 199332411500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory -system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1594658604 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1594658604 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 492356798 # Number of bytes written to this memory -system.physmem.bytes_written::total 492356798 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 398664651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 94754489 # Number of read requests responded to by this memory -system.physmem.num_reads::total 493419140 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 73520729 # Number of write requests responded to by this memory -system.physmem.num_writes::total 73520729 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999996548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3323339471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11323336020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999996548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999996548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2470028804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2470028804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 199332411500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754489 # DTB read hits -system.cpu.dtb.read_misses 21 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754510 # DTB read accesses -system.cpu.dtb.write_hits 73520729 # DTB write hits -system.cpu.dtb.write_misses 35 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73520764 # DTB write accesses -system.cpu.dtb.data_hits 168275218 # DTB hits -system.cpu.dtb.data_misses 56 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275274 # DTB accesses -system.cpu.itb.fetch_hits 398664651 # ITB hits -system.cpu.itb.fetch_misses 173 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398664824 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 199332411500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 398664824 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 398664595 # Number of instructions committed -system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses -system.cpu.num_func_calls 16015498 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls -system.cpu.num_int_insts 316365907 # number of integer instructions -system.cpu.num_fp_insts 155295119 # number of float instructions -system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read -system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read -system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written -system.cpu.num_mem_refs 168275274 # number of memory refs -system.cpu.num_load_insts 94754510 # Number of load instructions -system.cpu.num_store_insts 73520764 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 398664824 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 44587532 # Number of branches fetched -system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction -system.cpu.op_class::IntAlu 141652555 35.53% 41.33% # Class of executed instruction -system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction -system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction -system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction -system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction -system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 57.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::MemRead 46072315 11.56% 69.35% # Class of executed instruction -system.cpu.op_class::MemWrite 30396984 7.62% 76.97% # Class of executed instruction -system.cpu.op_class::FloatMemRead 48682195 12.21% 89.18% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 43123780 10.82% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 398664651 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 199332411500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 493419140 # Transaction distribution -system.membus.trans_dist::ReadResp 493419140 # Transaction distribution -system.membus.trans_dist::WriteReq 73520729 # Transaction distribution -system.membus.trans_dist::WriteResp 73520729 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 566939869 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 566939869 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 566939869 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index 2d4d209f1..000000000 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index 96524c915..000000000 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index 0d37b2b08..000000000 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,14 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:27 -gem5 executing on e108600-lin, pid 4293 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/alpha/tru64/simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 44221003000 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg deleted file mode 100644 index 472b08431..000000000 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg +++ /dev/null @@ -1,158 +0,0 @@ - - SYSTEM TYPE... - __ZTC__ := False - __UNIX__ := True - __RISC__ := True - SPEC_CPU2000_LP64 := True - __MAC__ := False - __BCC__ := False - __BORLANDC__ := False - __GUI__ := False - __WTC__ := False - __HP__ := False - - CODE OPTIONS... - __MACROIZE_HM__ := True - __MACROIZE_MEM__ := True - ENV01 := True - USE_HPP_STYPE_HDRS := False - USE_H_STYPE_HDRS := False - - CODE INCLUSION PARAMETERS... - INCLUDE_ALL_CODE := False - INCLUDE_DELETE_CODE := True - __SWAP_GRP_POS__ := True - __INCLUDE_MTRX__ := False - __BAD_CODE__ := False - API_INCLUDE := False - BE_CAREFUL := False - OLDWAY := False - NOTUSED := False - - SYSTEM PARAMETERS... - EXT_ENUM := 999999999L - CHUNK_CONSTANT := 55555555 - CORE_CONSTANT := 55555555 - CORE_LIMIT := 20971520 - CorePage_Size := 384000 - ALIGN_BYTES := True - CORE_BLOCK_ALIGN := 8 - FAR_MEM := False - - MEMORY MANAGEMENT PARAMETERS... - SYSTEM_ALLOC := True - SYSTEM_FREESTORE := True - __NO_DISKCACHE__ := False - __FREEZE_VCHUNKS__ := True - __FREEZE_GRP_PACKETS__ := True - __MINIMIZE_TREE_CACHE__:= True - - SYSTEM STD PARAMETERS... - __STDOUT__ := False - NULL := 0 - LPTR := False - False_Status := 1 - True_Status := 0 - LARGE := True - TWOBYTE_BOOL := False - __NOSTR__ := False - - MEMORY VALIDATION PARAMETERS... - CORE_CRC_CHECK := False - VALIDATE_MEM_CHUNKS := False - - SYSTEM DEBUG OPTIONS... - DEBUG := False - MCSTAT := False - TRACKBACK := False - FLUSH_FILES := False - DEBUG_CORE0 := False - DEBUG_RISC := False - __TREE_BUG__ := False - __TRACK_FILE_READS__ := False - PAGE_SPACE := False - LEAVE_NO_TRACE := True - NULL_TRACE_STRS := False - - TIME PARAMETERS... - CLOCK_IS_LONG := False - __DISPLAY_TIME__ := False - __TREE_TIME__ := False - __DISPLAY_ERRORS__ := False - - API MACROS... - __BMT01__ := True - OPTIMIZE := True - - END OF DEFINES. - - - - ... IMPLODE MEMORY ... - - SWAP to DiskCache := False - - FREEZE_GRP_PACKETS:= True - - QueBug := 1000 - - sizeof(boolean) = 4 - sizeof(sizetype) = 4 - sizeof(chunkstruc) = 32 - - sizeof(shorttype ) = 2 - sizeof(idtype ) = 2 - sizeof(sizetype ) = 4 - sizeof(indextype ) = 4 - sizeof(numtype ) = 4 - sizeof(handletype) = 4 - sizeof(tokentype ) = 8 - - sizeof(short ) = 2 - sizeof(int ) = 4 - - sizeof(lt64 ) = 4 - sizeof(farlongtype) = 4 - sizeof(long ) = 8 - sizeof(longaddr ) = 8 - - sizeof(float ) = 4 - sizeof(double ) = 8 - - sizeof(addrtype ) = 8 - sizeof(char * ) = 8 - ALLOC CORE_1 :: 16 - BHOOLE NATH - - OPEN File ./input/lendian.rnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 2030c0 - DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] - DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] - DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] - DB Handle Chunk's StackPtr = 20797 - - DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 4005c800 - - OPEN File ./input/lendian.wnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 21c40 - DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] - DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] - DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] - DB Handle Chunk's StackPtr = 17 - - DB[ 2] LOADED; Handles= 17 - VORTEx_Status == -8 || fffffff8 - - BE HERE NOW !!! - - - - ... VORTEx ON LINE ... - - - ... END OF SESSION ... diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out deleted file mode 100644 index 726b45c60..000000000 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out +++ /dev/null @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every <mod 0>Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD <Query0> for <Part2> class:: - - if (link[1].length >= 5) :: - - Build Query2 for <Address> class:: - - if (State == CA || State == T*) - - Build Query1 for <Person> class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD <Query3> for <DrawObj> class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD <Query4> for <NamedDrawObj> class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET <DrawObjs> entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET <NamedDrawObjs> entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET <LibRectangles> entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST <DbRectangles> entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET <PersonNames > entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=<True>; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - <Part2 > Asserts = 2; NULL Asserts = 3. - <DrawObj > Asserts = 0; NULL Asserts = 5. - <NamedObj > Asserts = 0; NULL Asserts = 0. - <Person > Asserts = 0; NULL Asserts = 5. - <TestObj > Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=<True>; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt deleted file mode 100644 index 4f8d8987a..000000000 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ /dev/null @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.044221 # Number of seconds simulated -sim_ticks 44221003000 # Number of ticks simulated -final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2866684 # Simulator instruction rate (inst/s) -host_op_rate 2866683 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1434985124 # Simulator tick rate (ticks/s) -host_mem_usage 250568 # Number of bytes of host memory used -host_seconds 30.82 # Real time elapsed on the host -sim_insts 88340673 # Number of instructions simulated -sim_ops 88340673 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory -system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory -system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory -system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory -system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.data_hits 34890015 # DTB hits -system.cpu.dtb.data_misses 97400 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 34987415 # DTB accesses -system.cpu.itb.fetch_hits 88438073 # ITB hits -system.cpu.itb.fetch_misses 3934 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 88442007 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 44221003000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 88442007 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88340673 # Number of instructions committed -system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses -system.cpu.num_func_calls 3321606 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls -system.cpu.num_int_insts 78039444 # number of integer instructions -system.cpu.num_fp_insts 267757 # number of float instructions -system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read -system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written -system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read -system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written -system.cpu.num_mem_refs 34987415 # number of memory refs -system.cpu.num_load_insts 20366786 # Number of load instructions -system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 88442007 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 13754477 # Number of branches fetched -system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction -system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::MemRead 20366476 23.03% 83.47% # Class of executed instruction -system.cpu.op_class::MemWrite 14619024 16.53% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 310 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 1605 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 88438073 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 108714711 # Transaction distribution -system.membus.trans_dist::ReadResp 108714711 # Transaction distribution -system.membus.trans_dist::WriteReq 14613377 # Transaction distribution -system.membus.trans_dist::WriteResp 14613377 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 123328088 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 123328088 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 123328088 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini deleted file mode 100644 index d07d610d6..000000000 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ /dev/null @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr deleted file mode 100755 index 96524c915..000000000 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout deleted file mode 100755 index d72d31595..000000000 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout +++ /dev/null @@ -1,14 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:27 -gem5 executing on e108600-lin, pid 4294 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/alpha/tru64/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 134741611500 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg deleted file mode 100644 index 472b08431..000000000 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg +++ /dev/null @@ -1,158 +0,0 @@ - - SYSTEM TYPE... - __ZTC__ := False - __UNIX__ := True - __RISC__ := True - SPEC_CPU2000_LP64 := True - __MAC__ := False - __BCC__ := False - __BORLANDC__ := False - __GUI__ := False - __WTC__ := False - __HP__ := False - - CODE OPTIONS... - __MACROIZE_HM__ := True - __MACROIZE_MEM__ := True - ENV01 := True - USE_HPP_STYPE_HDRS := False - USE_H_STYPE_HDRS := False - - CODE INCLUSION PARAMETERS... - INCLUDE_ALL_CODE := False - INCLUDE_DELETE_CODE := True - __SWAP_GRP_POS__ := True - __INCLUDE_MTRX__ := False - __BAD_CODE__ := False - API_INCLUDE := False - BE_CAREFUL := False - OLDWAY := False - NOTUSED := False - - SYSTEM PARAMETERS... - EXT_ENUM := 999999999L - CHUNK_CONSTANT := 55555555 - CORE_CONSTANT := 55555555 - CORE_LIMIT := 20971520 - CorePage_Size := 384000 - ALIGN_BYTES := True - CORE_BLOCK_ALIGN := 8 - FAR_MEM := False - - MEMORY MANAGEMENT PARAMETERS... - SYSTEM_ALLOC := True - SYSTEM_FREESTORE := True - __NO_DISKCACHE__ := False - __FREEZE_VCHUNKS__ := True - __FREEZE_GRP_PACKETS__ := True - __MINIMIZE_TREE_CACHE__:= True - - SYSTEM STD PARAMETERS... - __STDOUT__ := False - NULL := 0 - LPTR := False - False_Status := 1 - True_Status := 0 - LARGE := True - TWOBYTE_BOOL := False - __NOSTR__ := False - - MEMORY VALIDATION PARAMETERS... - CORE_CRC_CHECK := False - VALIDATE_MEM_CHUNKS := False - - SYSTEM DEBUG OPTIONS... - DEBUG := False - MCSTAT := False - TRACKBACK := False - FLUSH_FILES := False - DEBUG_CORE0 := False - DEBUG_RISC := False - __TREE_BUG__ := False - __TRACK_FILE_READS__ := False - PAGE_SPACE := False - LEAVE_NO_TRACE := True - NULL_TRACE_STRS := False - - TIME PARAMETERS... - CLOCK_IS_LONG := False - __DISPLAY_TIME__ := False - __TREE_TIME__ := False - __DISPLAY_ERRORS__ := False - - API MACROS... - __BMT01__ := True - OPTIMIZE := True - - END OF DEFINES. - - - - ... IMPLODE MEMORY ... - - SWAP to DiskCache := False - - FREEZE_GRP_PACKETS:= True - - QueBug := 1000 - - sizeof(boolean) = 4 - sizeof(sizetype) = 4 - sizeof(chunkstruc) = 32 - - sizeof(shorttype ) = 2 - sizeof(idtype ) = 2 - sizeof(sizetype ) = 4 - sizeof(indextype ) = 4 - sizeof(numtype ) = 4 - sizeof(handletype) = 4 - sizeof(tokentype ) = 8 - - sizeof(short ) = 2 - sizeof(int ) = 4 - - sizeof(lt64 ) = 4 - sizeof(farlongtype) = 4 - sizeof(long ) = 8 - sizeof(longaddr ) = 8 - - sizeof(float ) = 4 - sizeof(double ) = 8 - - sizeof(addrtype ) = 8 - sizeof(char * ) = 8 - ALLOC CORE_1 :: 16 - BHOOLE NATH - - OPEN File ./input/lendian.rnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 2030c0 - DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] - DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] - DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] - DB Handle Chunk's StackPtr = 20797 - - DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 4005c800 - - OPEN File ./input/lendian.wnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 21c40 - DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] - DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] - DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] - DB Handle Chunk's StackPtr = 17 - - DB[ 2] LOADED; Handles= 17 - VORTEx_Status == -8 || fffffff8 - - BE HERE NOW !!! - - - - ... VORTEx ON LINE ... - - - ... END OF SESSION ... diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out deleted file mode 100644 index 726b45c60..000000000 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out +++ /dev/null @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every <mod 0>Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD <Query0> for <Part2> class:: - - if (link[1].length >= 5) :: - - Build Query2 for <Address> class:: - - if (State == CA || State == T*) - - Build Query1 for <Person> class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD <Query3> for <DrawObj> class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD <Query4> for <NamedDrawObj> class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET <DrawObjs> entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET <NamedDrawObjs> entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET <LibRectangles> entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST <DbRectangles> entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET <PersonNames > entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=<True>; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - <Part2 > Asserts = 2; NULL Asserts = 3. - <DrawObj > Asserts = 0; NULL Asserts = 5. - <NamedObj > Asserts = 0; NULL Asserts = 0. - <Person > Asserts = 0; NULL Asserts = 5. - <TestObj > Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=<True>; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index d5c3e5af1..000000000 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,569 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.134921 # Number of seconds simulated -sim_ticks 134921160500 # Number of ticks simulated -final_tick 134921160500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1865262 # Simulator instruction rate (inst/s) -host_op_rate 1865262 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2848781352 # Simulator tick rate (ticks/s) -host_mem_usage 261840 # Number of bytes of host memory used -host_seconds 47.36 # Real time elapsed on the host -sim_insts 88340673 # Number of instructions simulated -sim_ops 88340673 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 369920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10155520 # Number of bytes read from this memory -system.physmem.bytes_read::total 10525440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 369920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 369920 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7371264 # Number of bytes written to this memory -system.physmem.bytes_written::total 7371264 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5780 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158680 # Number of read requests responded to by this memory -system.physmem.num_reads::total 164460 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115176 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115176 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2741749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75270031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 78011781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2741749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2741749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54633862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54633862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54633862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2741749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75270031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 132645642 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.data_hits 34890015 # DTB hits -system.cpu.dtb.data_misses 97400 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 34987415 # DTB accesses -system.cpu.itb.fetch_hits 88438074 # ITB hits -system.cpu.itb.fetch_misses 3934 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 88442008 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 269842321 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88340673 # Number of instructions committed -system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses -system.cpu.num_func_calls 3321606 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls -system.cpu.num_int_insts 78039444 # number of integer instructions -system.cpu.num_fp_insts 267757 # number of float instructions -system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read -system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written -system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read -system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written -system.cpu.num_mem_refs 34987415 # number of memory refs -system.cpu.num_load_insts 20366786 # Number of load instructions -system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 269842321 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 13754477 # Number of branches fetched -system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction -system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::MemRead 20366476 23.03% 83.47% # Class of executed instruction -system.cpu.op_class::MemWrite 14619024 16.53% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 310 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 1605 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 88438073 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200248 # number of replacements -system.cpu.dcache.tags.tagsinuse 4078.334496 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 990170500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4078.334496 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995687 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995687 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 445 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3604 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits -system.cpu.dcache.overall_hits::total 34685671 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses -system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2178421500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2178421500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8412226500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8412226500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10590648000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10590648000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10590648000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10590648000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35849.348320 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35849.348320 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58589.940659 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58589.940659 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51827.545707 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51827.545707 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51827.545707 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51827.545707 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 167988 # number of writebacks -system.cpu.dcache.writebacks::total 167988 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2117655500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2117655500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8268648500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8268648500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10386304000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10386304000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10386304000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10386304000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34849.348320 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34849.348320 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57589.940659 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57589.940659 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50827.545707 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50827.545707 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50827.545707 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50827.545707 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 74391 # number of replacements -system.cpu.icache.tags.tagsinuse 1870.340281 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1870.340281 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.913252 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.913252 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses -system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88361638 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88361638 # number of overall hits -system.cpu.icache.overall_hits::total 88361638 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 76436 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 76436 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses -system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1283204500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1283204500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1283204500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1283204500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1283204500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1283204500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 88438074 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000864 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16787.959862 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16787.959862 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16787.959862 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16787.959862 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16787.959862 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16787.959862 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 74391 # number of writebacks -system.cpu.icache.writebacks::total 74391 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1206768500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1206768500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1206768500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1206768500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1206768500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1206768500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15787.959862 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15787.959862 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15787.959862 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15787.959862 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15787.959862 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15787.959862 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 133742 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31970.307618 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 388803 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 166510 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.335013 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 30559527000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 658.522624 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1588.260241 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29723.524754 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.020097 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048470 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.907090 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.975656 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7663 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 24220 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 111 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4609862 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4609862 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 167988 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 167988 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 74391 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 74391 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12665 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12665 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 70656 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 70656 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 32999 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 32999 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 70656 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 45664 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 116320 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 70656 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 45664 # number of overall hits -system.cpu.l2cache.overall_hits::total 116320 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130913 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130913 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 5780 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 5780 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27767 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 27767 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 5780 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158680 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 164460 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 5780 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158680 # number of overall misses -system.cpu.l2cache.overall_misses::total 164460 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7920287500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7920287500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 349972000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 349972000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1679964000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1679964000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 349972000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9600251500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9950223500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 349972000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9600251500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9950223500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 167988 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 167988 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 74391 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 74391 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 76436 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 76436 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 60766 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 60766 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911790 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911790 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.075619 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.075619 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.456950 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.456950 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.075619 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.776534 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.585725 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.075619 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.776534 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.585725 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.389572 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.389572 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60548.788927 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60548.788927 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60502.178845 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60502.178845 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60548.788927 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.702672 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60502.392679 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60548.788927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.702672 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60502.392679 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 115177 # number of writebacks -system.cpu.l2cache.writebacks::total 115177 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 106 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 106 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130913 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130913 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 5780 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 5780 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27767 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27767 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5780 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158680 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 164460 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5780 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158680 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 164460 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6611157500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6611157500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 292172000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 292172000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1402294000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1402294000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 292172000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8013451500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8305623500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 292172000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8013451500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8305623500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911790 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911790 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.075619 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075619 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456950 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456950 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.075619 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.776534 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.585725 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.075619 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.776534 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.585725 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.389572 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.389572 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50548.788927 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50548.788927 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.178845 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.178845 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50548.788927 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.702672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50502.392679 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50548.788927 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.702672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50502.392679 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4055 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4055 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283165 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 50825 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 60766 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 227263 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9652928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23829248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33482176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133742 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7371328 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 414522 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009782 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098421 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 410467 99.02% 99.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4055 0.98% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 414522 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 520088500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 294252 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 129792 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 33547 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115176 # Transaction distribution -system.membus.trans_dist::CleanEvict 14616 # Transaction distribution -system.membus.trans_dist::ReadExReq 130913 # Transaction distribution -system.membus.trans_dist::ReadExResp 130913 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33547 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 458712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 458712 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17896704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17896704 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 164460 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 164460 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 164460 # Request fanout histogram -system.membus.reqLayer0.occupancy 755151000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 822300000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index 9503e5d69..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=twolf smred -cwd=build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index 96524c915..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index 0dad23f1c..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4296 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/alpha/tru64/simple-atomic - -Couldn't unlink build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/smred.sav -Couldn't unlink build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 45951567500 because target called exit() diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out deleted file mode 100644 index 98777e0af..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out +++ /dev/null @@ -1,276 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - - -NOTE: Restart file .rs2 not used - -TimberWolf will perform a global route step -rowSep: 1.000000 -feedThruWidth: 4 - -****************** -BLOCK DATA -block:1 desire:85 -block:2 desire:85 -Total Desired Length: 170 -total cell length: 168 -total block length: 168 -block x-span:84 block y-span:78 -implicit feed thru range: -84 -Using default value of bin.penalty.control:1.000000 -numBins automatically set to:5 -binWidth = average_cell_width + 0 sigma= 17 -average_cell_width is:16 -standard deviation of cell length is:23.6305 -TimberWolfSC starting from the beginning - - - -THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 -The number of nets with 1 pin is 4 -The number of nets with 2 pin is 9 -The number of nets with 3 pin is 0 -The number of nets with 4 pin is 2 -The number of nets with 5 pin is 0 -The number of nets with 6 pin is 0 -The number of nets with 7 pin is 0 -The number of nets with 8 pin is 0 -The number of nets with 9 pin is 0 -The number of nets with 10 pin or more is 0 - -New Cost Function: Initial Horizontal Cost:242 -New Cost Function: FEEDS:0 MISSING_ROWS:-46 - -bdxlen:86 bdylen:78 -l:0 t:78 r:86 b:0 - - - -THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 - - - -THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 - -The rand generator seed was at utemp() : 1 - - - tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 - tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 - tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 - tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 - - I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs - 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 - 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 - 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 - 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 - 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 - 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 - 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 - 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 - 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 - 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 - 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 - 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 - 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 - 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 - 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 - 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 - 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 - 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 - 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 - 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 - 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 - 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 - 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 - 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 - 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 - 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 - 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 - 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 - 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 - 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 - 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 - 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 - 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 - 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 - 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 - 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 - 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 - 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 - 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 - 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 - 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 - 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 - 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 - 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 - 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 - 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 - 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 - 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 - 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 - 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 - 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 - 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 - 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 - 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 - 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 - 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 - 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 - 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 - 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 - 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 - 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 - 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 - 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 - 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 - 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 - 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 - 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 - 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 - 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 - 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 - 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 - 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 - 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 - 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 - 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 - 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 - 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 - 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 - 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 - 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 - 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 - 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 - 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 - 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 - 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 - 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 - 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 - 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 - 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 - 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 - 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 - 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 - 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 - 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 - 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 - 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 - 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 -100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 -101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 -102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 -103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 -104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 -105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 -106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 -107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 -108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 -109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 -110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 -111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 -112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 -113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 -114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 -115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 -116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 -117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 -118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 -119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 -120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 -121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 - -Initial Wiring Cost: 645 Final Wiring Cost: 732 -############## Percent Wire Cost Reduction: -13 - - -Initial Wire Length: 645 Final Wire Length: 732 -************** Percent Wire Length Reduction: -13 - - -Initial Horiz. Wire: 216 Final Horiz. Wire: 147 -$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 - - -Initial Vert. Wire: 429 Final Vert. Wire: 585 -@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 - -Before Feeds are Added: -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 82 -20 - 2 86 -16 - -LONGEST Block is:2 Its length is:86 -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 86 -16 - 2 86 -16 - -LONGEST Block is:1 Its length is:86 -Added: 1 feed-through cells - -Removed the cell overlaps --- Will do neighbor interchanges only now - -TOTAL INTERCONNECT LENGTH: 994 -OVERLAP PENALTY: 0 - -initialRowControl: 1.650 -finalRowControl: 0.300 -iter T Wire accept - 122 0.001 976 16% - 123 0.001 971 0% - 124 0.001 971 0% -Total Feed-Alignment Movement (Pass 1): 0 -Total Feed-Alignment Movement (Pass 2): 0 -Total Feed-Alignment Movement (Pass 3): 0 -Total Feed-Alignment Movement (Pass 4): 0 -Total Feed-Alignment Movement (Pass 5): 0 -Total Feed-Alignment Movement (Pass 6): 0 -Total Feed-Alignment Movement (Pass 7): 0 -Total Feed-Alignment Movement (Pass 8): 0 - -The rand generator seed was at globroute() : 987654321 - - -Total Number of Net Segments: 9 -Number of Switchable Net Segments: 0 - -Number of channels: 3 - - - -THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 - - -no. of accepted flips: 0 -no. of attempted flips: 0 -THIS IS THE NUMBER OF TRACKS: 5 - - - -FINAL NUMBER OF ROUTING TRACKS: 5 - -MAX OF CHANNEL: 1 is: 0 -MAX OF CHANNEL: 2 is: 4 -MAX OF CHANNEL: 3 is: 1 -FINAL TOTAL INTERCONNECT LENGTH: 978 -FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 -MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 - - -cost_scale_factor:3.90616 - -Number of Feed Thrus: 0 -Number of Implicit Feed Thrus: 0 - -Statistics: -Number of Standard Cells: 10 -Number of Pads: 0 -Number of Nets: 15 -Number of Pins: 46 -Usage statistics not available diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin deleted file mode 100644 index 62b922e4e..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin +++ /dev/null @@ -1,17 +0,0 @@ -$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 -$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 -B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 -B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 -B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 deleted file mode 100644 index bdc569e39..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 +++ /dev/null @@ -1,11 +0,0 @@ -$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 -$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 -$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 -ACOUNT_1 14 0 18 26 2 1 -twfeed1 18 0 22 26 0 1 -$COUNT_1/$FJK3_1 22 0 86 26 0 1 -$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 -$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 -$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 -$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 -$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 deleted file mode 100644 index 6e2601e82..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 +++ /dev/null @@ -1,2 +0,0 @@ -1 0 0 86 26 0 0 -2 0 52 86 78 0 0 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav deleted file mode 100644 index 04c8e9935..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav +++ /dev/null @@ -1,18 +0,0 @@ -0.009592 -121 -0 -1 -0.000000 -0.500000 -3.906156 -1 -1 1 2 37 13 -2 2 0 34 65 -3 2 2 63 65 -4 1 0 59 13 -5 1 2 32 13 -6 2 0 23 65 -7 1 2 12 13 -8 2 0 6 65 -9 1 0 70 13 -10 2 0 70 65 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 deleted file mode 100644 index 9dd68ecdb..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 +++ /dev/null @@ -1,19 +0,0 @@ -0.001000 -123 -0 -2 -0.000000 -0.500000 -3.906156 -1 -1 1 2 16 13 -2 2 2 19 65 -3 2 2 14 65 -4 1 0 11 13 -5 1 2 6 13 -6 2 0 3 65 -7 1 0 2 13 -8 2 2 9 65 -9 1 0 50 13 -10 2 0 54 65 -11 1 0 84 13 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf deleted file mode 100644 index a4c2eac35..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf +++ /dev/null @@ -1,29 +0,0 @@ -net 1 -segment channel 2 - pin1 1 pin2 7 0 0 -net 2 -segment channel 3 -pin1 41 pin2 42 0 0 -segment channel 2 -pin1 12 pin2 3 0 0 -net 3 -segment channel 2 -pin1 35 pin2 36 0 0 -segment channel 2 -pin1 19 pin2 35 0 0 -net 4 -segment channel 2 - pin1 5 pin2 38 0 0 -net 5 -net 7 -segment channel 2 - pin1 14 pin2 43 0 0 -net 8 -segment channel 2 - pin1 23 pin2 17 0 0 -net 9 -net 11 -segment channel 2 - pin1 25 pin2 31 0 0 -net 14 -net 15 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt deleted file mode 100644 index 8f24d441f..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ /dev/null @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.045952 # Number of seconds simulated -sim_ticks 45951567500 # Number of ticks simulated -final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3055578 # Simulator instruction rate (inst/s) -host_op_rate 3055577 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1527789176 # Simulator tick rate (ticks/s) -host_mem_usage 246136 # Number of bytes of host memory used -host_seconds 30.08 # Real time elapsed on the host -sim_insts 91903056 # Number of instructions simulated -sim_ops 91903056 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory -system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 367612356 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 367612356 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 30920974 # Number of bytes written to this memory -system.physmem.bytes_written::total 30920974 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 91903089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 19996198 # Number of read requests responded to by this memory -system.physmem.num_reads::total 111899287 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 6501103 # Number of write requests responded to by this memory -system.physmem.num_writes::total 6501103 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999995996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2357645819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10357641815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999995996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999995996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 672903574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 672903574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996198 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996208 # DTB read accesses -system.cpu.dtb.write_hits 6501103 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501126 # DTB write accesses -system.cpu.dtb.data_hits 26497301 # DTB hits -system.cpu.dtb.data_misses 33 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26497334 # DTB accesses -system.cpu.itb.fetch_hits 91903089 # ITB hits -system.cpu.itb.fetch_misses 47 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 91903136 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 45951567500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 91903136 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 91903056 # Number of instructions committed -system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses -system.cpu.num_func_calls 2059216 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls -system.cpu.num_int_insts 79581109 # number of integer instructions -system.cpu.num_fp_insts 6862064 # number of float instructions -system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read -system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read -system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written -system.cpu.num_mem_refs 26497334 # number of memory refs -system.cpu.num_load_insts 19996208 # Number of load instructions -system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 91903136 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 10240685 # Number of branches fetched -system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction -system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction -system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction -system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::MemRead 19433628 21.15% 92.31% # Class of executed instruction -system.cpu.op_class::MemWrite 6424338 6.99% 99.30% # Class of executed instruction -system.cpu.op_class::FloatMemRead 562580 0.61% 99.92% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 76788 0.08% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91903089 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 111899287 # Transaction distribution -system.membus.trans_dist::ReadResp 111899287 # Transaction distribution -system.membus.trans_dist::WriteReq 6501103 # Transaction distribution -system.membus.trans_dist::WriteResp 6501103 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 118400390 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 118400390 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 118400390 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini deleted file mode 100644 index 5f464084f..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ /dev/null @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=twolf smred -cwd=build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr deleted file mode 100755 index 96524c915..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout deleted file mode 100755 index 833b11d37..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout +++ /dev/null @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4297 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/alpha/tru64/simple-timing - -Couldn't unlink build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 118762761500 because target called exit() diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out deleted file mode 100644 index 98777e0af..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out +++ /dev/null @@ -1,276 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - - -NOTE: Restart file .rs2 not used - -TimberWolf will perform a global route step -rowSep: 1.000000 -feedThruWidth: 4 - -****************** -BLOCK DATA -block:1 desire:85 -block:2 desire:85 -Total Desired Length: 170 -total cell length: 168 -total block length: 168 -block x-span:84 block y-span:78 -implicit feed thru range: -84 -Using default value of bin.penalty.control:1.000000 -numBins automatically set to:5 -binWidth = average_cell_width + 0 sigma= 17 -average_cell_width is:16 -standard deviation of cell length is:23.6305 -TimberWolfSC starting from the beginning - - - -THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 -The number of nets with 1 pin is 4 -The number of nets with 2 pin is 9 -The number of nets with 3 pin is 0 -The number of nets with 4 pin is 2 -The number of nets with 5 pin is 0 -The number of nets with 6 pin is 0 -The number of nets with 7 pin is 0 -The number of nets with 8 pin is 0 -The number of nets with 9 pin is 0 -The number of nets with 10 pin or more is 0 - -New Cost Function: Initial Horizontal Cost:242 -New Cost Function: FEEDS:0 MISSING_ROWS:-46 - -bdxlen:86 bdylen:78 -l:0 t:78 r:86 b:0 - - - -THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 - - - -THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 - -The rand generator seed was at utemp() : 1 - - - tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 - tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 - tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 - tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 - - I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs - 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 - 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 - 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 - 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 - 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 - 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 - 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 - 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 - 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 - 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 - 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 - 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 - 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 - 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 - 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 - 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 - 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 - 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 - 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 - 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 - 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 - 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 - 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 - 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 - 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 - 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 - 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 - 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 - 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 - 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 - 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 - 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 - 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 - 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 - 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 - 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 - 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 - 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 - 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 - 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 - 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 - 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 - 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 - 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 - 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 - 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 - 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 - 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 - 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 - 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 - 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 - 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 - 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 - 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 - 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 - 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 - 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 - 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 - 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 - 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 - 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 - 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 - 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 - 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 - 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 - 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 - 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 - 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 - 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 - 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 - 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 - 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 - 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 - 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 - 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 - 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 - 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 - 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 - 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 - 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 - 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 - 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 - 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 - 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 - 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 - 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 - 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 - 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 - 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 - 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 - 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 - 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 - 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 - 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 - 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 - 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 - 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 -100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 -101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 -102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 -103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 -104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 -105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 -106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 -107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 -108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 -109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 -110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 -111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 -112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 -113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 -114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 -115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 -116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 -117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 -118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 -119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 -120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 -121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 - -Initial Wiring Cost: 645 Final Wiring Cost: 732 -############## Percent Wire Cost Reduction: -13 - - -Initial Wire Length: 645 Final Wire Length: 732 -************** Percent Wire Length Reduction: -13 - - -Initial Horiz. Wire: 216 Final Horiz. Wire: 147 -$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 - - -Initial Vert. Wire: 429 Final Vert. Wire: 585 -@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 - -Before Feeds are Added: -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 82 -20 - 2 86 -16 - -LONGEST Block is:2 Its length is:86 -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 86 -16 - 2 86 -16 - -LONGEST Block is:1 Its length is:86 -Added: 1 feed-through cells - -Removed the cell overlaps --- Will do neighbor interchanges only now - -TOTAL INTERCONNECT LENGTH: 994 -OVERLAP PENALTY: 0 - -initialRowControl: 1.650 -finalRowControl: 0.300 -iter T Wire accept - 122 0.001 976 16% - 123 0.001 971 0% - 124 0.001 971 0% -Total Feed-Alignment Movement (Pass 1): 0 -Total Feed-Alignment Movement (Pass 2): 0 -Total Feed-Alignment Movement (Pass 3): 0 -Total Feed-Alignment Movement (Pass 4): 0 -Total Feed-Alignment Movement (Pass 5): 0 -Total Feed-Alignment Movement (Pass 6): 0 -Total Feed-Alignment Movement (Pass 7): 0 -Total Feed-Alignment Movement (Pass 8): 0 - -The rand generator seed was at globroute() : 987654321 - - -Total Number of Net Segments: 9 -Number of Switchable Net Segments: 0 - -Number of channels: 3 - - - -THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 - - -no. of accepted flips: 0 -no. of attempted flips: 0 -THIS IS THE NUMBER OF TRACKS: 5 - - - -FINAL NUMBER OF ROUTING TRACKS: 5 - -MAX OF CHANNEL: 1 is: 0 -MAX OF CHANNEL: 2 is: 4 -MAX OF CHANNEL: 3 is: 1 -FINAL TOTAL INTERCONNECT LENGTH: 978 -FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 -MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 - - -cost_scale_factor:3.90616 - -Number of Feed Thrus: 0 -Number of Implicit Feed Thrus: 0 - -Statistics: -Number of Standard Cells: 10 -Number of Pads: 0 -Number of Nets: 15 -Number of Pins: 46 -Usage statistics not available diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin deleted file mode 100644 index 62b922e4e..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin +++ /dev/null @@ -1,17 +0,0 @@ -$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 -$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 -B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 -B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 -B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 deleted file mode 100644 index bdc569e39..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 +++ /dev/null @@ -1,11 +0,0 @@ -$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 -$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 -$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 -ACOUNT_1 14 0 18 26 2 1 -twfeed1 18 0 22 26 0 1 -$COUNT_1/$FJK3_1 22 0 86 26 0 1 -$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 -$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 -$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 -$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 -$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 deleted file mode 100644 index 6e2601e82..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 +++ /dev/null @@ -1,2 +0,0 @@ -1 0 0 86 26 0 0 -2 0 52 86 78 0 0 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav deleted file mode 100644 index 04c8e9935..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav +++ /dev/null @@ -1,18 +0,0 @@ -0.009592 -121 -0 -1 -0.000000 -0.500000 -3.906156 -1 -1 1 2 37 13 -2 2 0 34 65 -3 2 2 63 65 -4 1 0 59 13 -5 1 2 32 13 -6 2 0 23 65 -7 1 2 12 13 -8 2 0 6 65 -9 1 0 70 13 -10 2 0 70 65 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 deleted file mode 100644 index 9dd68ecdb..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 +++ /dev/null @@ -1,19 +0,0 @@ -0.001000 -123 -0 -2 -0.000000 -0.500000 -3.906156 -1 -1 1 2 16 13 -2 2 2 19 65 -3 2 2 14 65 -4 1 0 11 13 -5 1 2 6 13 -6 2 0 3 65 -7 1 0 2 13 -8 2 2 9 65 -9 1 0 50 13 -10 2 0 54 65 -11 1 0 84 13 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf deleted file mode 100644 index a4c2eac35..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf +++ /dev/null @@ -1,29 +0,0 @@ -net 1 -segment channel 2 - pin1 1 pin2 7 0 0 -net 2 -segment channel 3 -pin1 41 pin2 42 0 0 -segment channel 2 -pin1 12 pin2 3 0 0 -net 3 -segment channel 2 -pin1 35 pin2 36 0 0 -segment channel 2 -pin1 19 pin2 35 0 0 -net 4 -segment channel 2 - pin1 5 pin2 38 0 0 -net 5 -net 7 -segment channel 2 - pin1 14 pin2 43 0 0 -net 8 -segment channel 2 - pin1 23 pin2 17 0 0 -net 9 -net 11 -segment channel 2 - pin1 25 pin2 31 0 0 -net 14 -net 15 diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index 9a7bbe1ce..000000000 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,555 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.118768 # Number of seconds simulated -sim_ticks 118767526500 # Number of ticks simulated -final_tick 118767526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2099166 # Simulator instruction rate (inst/s) -host_op_rate 2099165 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2712778064 # Simulator tick rate (ticks/s) -host_mem_usage 256380 # Number of bytes of host memory used -host_seconds 43.78 # Real time elapsed on the host -sim_insts 91903056 # Number of instructions simulated -sim_ops 91903056 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory -system.physmem.bytes_read::total 304960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1412373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1155333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2567705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1412373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1412373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1412373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1155333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2567705 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996198 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996208 # DTB read accesses -system.cpu.dtb.write_hits 6501103 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501126 # DTB write accesses -system.cpu.dtb.data_hits 26497301 # DTB hits -system.cpu.dtb.data_misses 33 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26497334 # DTB accesses -system.cpu.itb.fetch_hits 91903090 # ITB hits -system.cpu.itb.fetch_misses 47 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 91903137 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 237535053 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 91903056 # Number of instructions committed -system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses -system.cpu.num_func_calls 2059216 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls -system.cpu.num_int_insts 79581109 # number of integer instructions -system.cpu.num_fp_insts 6862064 # number of float instructions -system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read -system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read -system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written -system.cpu.num_mem_refs 26497334 # number of memory refs -system.cpu.num_load_insts 19996208 # Number of load instructions -system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237535053 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 10240685 # Number of branches fetched -system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction -system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction -system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction -system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::MemRead 19433628 21.15% 92.31% # Class of executed instruction -system.cpu.op_class::MemWrite 6424338 6.99% 99.30% # Class of executed instruction -system.cpu.op_class::FloatMemRead 562580 0.61% 99.92% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 76788 0.08% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91903089 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.932454 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.932454 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352034 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352034 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 491 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits -system.cpu.dcache.overall_hits::total 26495078 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses -system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27278500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27278500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108825000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108825000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 136103500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 136103500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 136103500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 136103500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57428.421053 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 57428.421053 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62256.864989 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62256.864989 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61225.146199 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61225.146199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61225.146199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61225.146199 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26803500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26803500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 107077000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 107077000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133880500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 133880500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133880500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 133880500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56428.421053 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56428.421053 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61256.864989 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61256.864989 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60225.146199 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60225.146199 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60225.146199 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60225.146199 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 6681 # number of replacements -system.cpu.icache.tags.tagsinuse 1417.939126 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1417.939126 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.692353 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.692353 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 585 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 953 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses -system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits -system.cpu.icache.overall_hits::total 91894580 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses -system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 241766000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 241766000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 241766000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 241766000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 241766000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 241766000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28409.635723 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28409.635723 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28409.635723 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28409.635723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28409.635723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28409.635723 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 6681 # number of writebacks -system.cpu.icache.writebacks::total 6681 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 233256000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 233256000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 233256000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 233256000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 233256000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 233256000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27409.635723 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27409.635723 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27409.635723 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27409.635723 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27409.635723 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27409.635723 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3172.251150 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 12806 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4765 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.687513 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1704.876553 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1467.374597 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052029 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.044781 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.096809 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4765 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 346 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1127 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3196 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.145416 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 145333 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 145333 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6681 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5889 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 5889 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 5968 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2621 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2621 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 422 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 422 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 4765 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses -system.cpu.l2cache.overall_misses::total 4765 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104182000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 104182000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 158585000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 158585000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 25532500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 25532500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 158585000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 129714500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 288299500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 158585000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 129714500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 288299500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 6681 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6681 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8510 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 8510 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 475 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 475 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.307991 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.888421 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.888421 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.580720 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.580720 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60505.532240 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60505.532240 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60503.554502 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60503.554502 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60505.532240 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.166045 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60503.567681 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60505.532240 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.166045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60503.567681 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2621 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2621 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 422 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 422 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 86962000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 86962000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 132375000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 132375000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 21312500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 21312500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132375000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108274500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 240649500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132375000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108274500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 240649500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.307991 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.888421 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.580720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.580720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50505.532240 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50505.532240 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50503.554502 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50503.554502 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50505.532240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.166045 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.567681 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50505.532240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.166045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.567681 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 8510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 475 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23701 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 28304 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 972224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1121344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 10733 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10733 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10733 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15573500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 4765 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3043 # Transaction distribution -system.membus.trans_dist::ReadExReq 1722 # Transaction distribution -system.membus.trans_dist::ReadExResp 1722 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3043 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4765 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4765 # Request fanout histogram -system.membus.reqLayer0.occupancy 4782000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 23825000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |