summaryrefslogtreecommitdiff
path: root/tests/quick/se
diff options
context:
space:
mode:
Diffstat (limited to 'tests/quick/se')
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini40
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini42
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini40
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini42
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini40
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini44
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini369
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini40
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini42
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini42
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini40
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini42
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini43
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini40
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini42
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini48
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout72
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini19
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout60
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini7
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr150
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr150
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr150
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr150
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr150
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini21
-rwxr-xr-xtests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr147
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest/config.ini10
-rwxr-xr-xtests/quick/se/50.memtest/ref/null/none/memtest/simerr146
-rw-r--r--tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini35
-rw-r--r--tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini2
65 files changed, 1520 insertions, 880 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
index ad6cd6709..bbd960583 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -665,6 +666,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index 48d1fef73..67de80452 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -581,10 +581,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -614,6 +615,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -632,10 +634,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -644,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -654,6 +682,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -667,19 +696,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
index e3af4adf8..50fa51df7 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
index 1a2ad4916..c9e0c15f4 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 850afe8f9..4de69a578 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index f2c71623d..fe6b478bf 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 07e8d6849..8663b4c78 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 253b90903..a87c15412 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
index 0eb5daf95..091cdad96 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -234,6 +235,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
index a68327a1f..c9efff137 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -665,6 +666,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index fb08ec46d..5f42de628 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -581,10 +581,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -614,6 +615,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -632,10 +634,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -644,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -654,6 +682,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -667,19 +696,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 79159fdc0..f69c898cb 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
index 00c794fb7..4519f7012 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 46d0fbb12..7e18a82ef 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index be173178b..8de8f1e38 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index 1143e388b..e617d5b21 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 670d15d2e..25deca5e4 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 42a419874..402442761 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -234,6 +235,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
index f4127b6ce..300b9d035 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -763,6 +764,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index 6c1f65269..78a71faf3 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -75,6 +75,7 @@ dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -98,7 +99,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
-numPhysCCRegs=0
+numPhysCCRegs=1280
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
@@ -128,7 +129,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -829,10 +829,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -862,6 +863,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -880,10 +882,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -892,8 +895,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -902,6 +930,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -915,19 +944,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index db525069f..a1b6a8304 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
type=DerivO3CPU
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu.dcache]
type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
-size=262144
+size=32768
system=system
tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
-size=262144
+size=32768
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
@@ -249,10 +249,10 @@ opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu.icache]
type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
-size=131072
+size=32768
system=system
tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
-size=131072
+size=32768
[system.cpu.interrupts]
type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
-children=tags
+children=prefetcher tags
addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=20
+hit_latency=12
is_top_level=false
max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
sequential_access=false
-size=2097152
+size=1048576
system=system
tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=20
+hit_latency=12
sequential_access=false
-size=2097152
+size=1048576
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -712,6 +688,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
index a0f588ff6..91da4c557 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -369,6 +366,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -387,10 +385,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
index d8b9bcc6e..2e24c6545 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
index 017bc1348..54668155a 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -332,6 +333,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
index a47df6208..93ee36e3b 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -237,10 +237,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -270,6 +271,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -288,10 +290,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -300,8 +303,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -310,6 +338,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -323,19 +352,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index 1f8305e4e..946ab8388 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -583,10 +583,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -616,6 +617,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -634,10 +636,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -646,8 +649,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -656,6 +684,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -669,19 +698,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
index a20aef42c..4e242dacc 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -127,6 +124,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -145,10 +143,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index e05997c32..03c785312 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -128,6 +128,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index 1ce9455cf..e0e01d26c 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -203,10 +203,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -236,6 +237,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -254,10 +256,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index e341fc69a..709f4f73b 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -75,6 +75,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -127,7 +128,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -581,10 +581,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -614,6 +615,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -632,10 +634,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -644,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -654,6 +682,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -667,19 +696,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
index 0aa78ac08..00428c3e1 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -69,9 +69,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
index facfb2ae6..a3c44273d 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -267,6 +268,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -297,8 +300,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -307,6 +335,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -320,19 +349,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
index f6abe18a9..10cf57bb4 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -124,6 +121,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index abf61111c..583cc8b93 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -125,6 +125,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index 102ae8d7c..e38847653 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -200,10 +200,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -233,6 +234,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 2be4f154a..4263ec382 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -614,10 +614,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -647,6 +648,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -665,10 +667,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -677,8 +680,33 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -687,6 +715,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -700,19 +729,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
index db49faad7..960bf1b41 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -158,6 +155,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index 93964b6e7..cf742c468 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -159,6 +159,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index a819aa859..5b07510f0 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -267,6 +268,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index d28531788..d358e4bd4 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload0 system.cpu.workload1
dcache_port=system.cpu.dcache.cpu_side
@@ -586,10 +586,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -619,6 +620,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu.workload1]
type=LiveProcess
@@ -639,6 +641,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -657,10 +660,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -669,8 +673,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -679,6 +708,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -692,19 +722,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
index d6d7e175a..c6b990bda 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -267,6 +268,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -297,8 +300,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -307,6 +335,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -320,19 +349,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 2560e1b90..144f058d7 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +580,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -613,6 +614,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -631,10 +633,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -643,8 +646,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -653,6 +681,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -666,19 +695,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index a0349a47c..fc4381d3d 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -124,6 +121,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
index 0cf6b950c..727287e35 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -200,10 +200,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -233,6 +234,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index ea05b9577..144007094 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu0.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu0.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu0.workload
dcache_port=system.cpu0.dcache.cpu_side
@@ -567,6 +567,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu1]
type=DerivO3CPU
@@ -599,6 +600,7 @@ do_statistics_insts=true
dtb=system.cpu1.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -651,7 +653,6 @@ switched_out=false
system=system
tracer=system.cpu1.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu0.workload
dcache_port=system.cpu1.dcache.cpu_side
@@ -1104,6 +1105,7 @@ do_statistics_insts=true
dtb=system.cpu2.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -1156,7 +1158,6 @@ switched_out=false
system=system
tracer=system.cpu2.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu0.workload
dcache_port=system.cpu2.dcache.cpu_side
@@ -1609,6 +1610,7 @@ do_statistics_insts=true
dtb=system.cpu3.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -1661,7 +1663,6 @@ switched_out=false
system=system
tracer=system.cpu3.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu0.workload
dcache_port=system.cpu3.dcache.cpu_side
@@ -2135,10 +2136,11 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -2147,8 +2149,33 @@ slave=system.system_port system.l2c.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -2157,6 +2184,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -2170,29 +2198,37 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 33ff09cf3..90080e4d5 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:07:38
-gem5 started Jun 21 2014 11:08:21
-gem5 executing on phenom
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+gem5 compiled Oct 11 2014 05:01:31
+gem5 started Oct 11 2014 05:01:48
+gem5 executing on ribera.cs.wisc.edu
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
@@ -17,54 +17,54 @@ Init done
[Iteration 1, Thread 3] Got lock
[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
Iteration 1 completed
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
Iteration 2 completed
-[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 3, Thread 3] Got lock
+[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
Iteration 3 completed
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
Iteration 4 completed
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
Iteration 5 completed
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 6, Thread 1] Got lock
[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
Iteration 6 completed
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
Iteration 7 completed
-[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 8, Thread 3] Got lock
[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
Iteration 8 completed
[Iteration 9, Thread 3] Got lock
[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
@@ -75,10 +75,10 @@ Iteration 8 completed
Iteration 9 completed
[Iteration 10, Thread 1] Got lock
[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
Iteration 10 completed
PASSED :-)
-Exiting @ tick 110970500 because target called exit()
+Exiting @ tick 105696000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index 742ce1ca7..dc830ef72 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -194,6 +191,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu1]
type=AtomicSimpleCPU
@@ -220,9 +218,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -352,9 +347,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -484,9 +476,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -643,10 +632,11 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -667,10 +657,11 @@ range=0:134217727
port=system.membus.master[0]
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index 79edf9761..17be690b9 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 17:04:27
-gem5 started Jan 22 2014 17:29:52
-gem5 executing on u200540-lin
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+gem5 compiled Oct 11 2014 05:01:31
+gem5 started Oct 11 2014 05:01:48
+gem5 executing on ribera.cs.wisc.edu
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
@@ -29,54 +31,54 @@ Iteration 2 completed
[Iteration 3, Thread 1] Got lock
[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
Iteration 3 completed
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 4, Thread 1] Got lock
[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
-[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
Iteration 4 completed
[Iteration 5, Thread 3] Got lock
[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
Iteration 5 completed
[Iteration 6, Thread 2] Got lock
[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
Iteration 6 completed
[Iteration 7, Thread 2] Got lock
[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1
Iteration 7 completed
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
Iteration 8 completed
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
Iteration 9 completed
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
Iteration 10 completed
PASSED :-)
Exiting @ tick 87707000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index d83d155ae..2ad22e920 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -187,6 +187,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu1]
type=TimingSimpleCPU
@@ -615,10 +616,11 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -639,10 +641,11 @@ range=0:134217727
port=system.membus.master[0]
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
index 1c907dde7..58228c89a 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
index b779cf15d..215e9ea82 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: rounding error > tolerance
0.072760 rounded to 0
-system.cpu7: completed 10000 read, 5432 write accesses @720734
-system.cpu0: completed 10000 read, 5512 write accesses @730548
-system.cpu1: completed 10000 read, 5469 write accesses @733316
-system.cpu3: completed 10000 read, 5348 write accesses @734089
-system.cpu5: completed 10000 read, 5304 write accesses @739554
-system.cpu4: completed 10000 read, 5523 write accesses @742146
-system.cpu2: completed 10000 read, 5353 write accesses @742448
-system.cpu6: completed 10000 read, 5456 write accesses @746526
-system.cpu0: completed 20000 read, 10918 write accesses @1452216
-system.cpu7: completed 20000 read, 10905 write accesses @1455831
-system.cpu2: completed 20000 read, 10616 write accesses @1456643
-system.cpu1: completed 20000 read, 10900 write accesses @1468694
-system.cpu3: completed 20000 read, 10595 write accesses @1471954
-system.cpu6: completed 20000 read, 10732 write accesses @1476612
-system.cpu5: completed 20000 read, 10777 write accesses @1484015
-system.cpu4: completed 20000 read, 10962 write accesses @1484193
-system.cpu7: completed 30000 read, 16301 write accesses @2190709
-system.cpu3: completed 30000 read, 15930 write accesses @2193108
-system.cpu0: completed 30000 read, 16492 write accesses @2204699
-system.cpu2: completed 30000 read, 16137 write accesses @2208852
-system.cpu1: completed 30000 read, 16294 write accesses @2211342
-system.cpu6: completed 30000 read, 16138 write accesses @2217558
-system.cpu5: completed 30000 read, 16017 write accesses @2217893
-system.cpu4: completed 30000 read, 16364 write accesses @2220770
-system.cpu7: completed 40000 read, 21683 write accesses @2923239
-system.cpu3: completed 40000 read, 21410 write accesses @2936019
-system.cpu2: completed 40000 read, 21422 write accesses @2936262
-system.cpu0: completed 40000 read, 21993 write accesses @2938221
-system.cpu5: completed 40000 read, 21407 write accesses @2949381
-system.cpu4: completed 40000 read, 21696 write accesses @2954856
-system.cpu6: completed 40000 read, 21664 write accesses @2955212
-system.cpu1: completed 40000 read, 21772 write accesses @2957373
-system.cpu7: completed 50000 read, 26880 write accesses @3637356
-system.cpu0: completed 50000 read, 27433 write accesses @3667809
-system.cpu2: completed 50000 read, 26841 write accesses @3676541
-system.cpu3: completed 50000 read, 26846 write accesses @3676934
-system.cpu1: completed 50000 read, 27155 write accesses @3679587
-system.cpu5: completed 50000 read, 26712 write accesses @3699925
-system.cpu4: completed 50000 read, 27199 write accesses @3700680
-system.cpu6: completed 50000 read, 27119 write accesses @3709288
-system.cpu7: completed 60000 read, 32133 write accesses @4356266
-system.cpu0: completed 60000 read, 32774 write accesses @4396377
-system.cpu3: completed 60000 read, 32241 write accesses @4405248
-system.cpu2: completed 60000 read, 32179 write accesses @4410455
-system.cpu1: completed 60000 read, 32548 write accesses @4418337
-system.cpu4: completed 60000 read, 32496 write accesses @4444142
-system.cpu6: completed 60000 read, 32520 write accesses @4446125
-system.cpu5: completed 60000 read, 32111 write accesses @4457785
-system.cpu7: completed 70000 read, 37528 write accesses @5092190
-system.cpu3: completed 70000 read, 37618 write accesses @5124227
-system.cpu0: completed 70000 read, 38140 write accesses @5138553
-system.cpu2: completed 70000 read, 37630 write accesses @5148204
-system.cpu4: completed 70000 read, 37860 write accesses @5162780
-system.cpu1: completed 70000 read, 37968 write accesses @5169201
-system.cpu6: completed 70000 read, 38023 write accesses @5190771
-system.cpu5: completed 70000 read, 37447 write accesses @5193894
-system.cpu7: completed 80000 read, 42859 write accesses @5808723
-system.cpu3: completed 80000 read, 43086 write accesses @5863853
-system.cpu2: completed 80000 read, 43034 write accesses @5892131
-system.cpu0: completed 80000 read, 43586 write accesses @5894007
-system.cpu4: completed 80000 read, 43221 write accesses @5909816
-system.cpu1: completed 80000 read, 43381 write accesses @5910301
-system.cpu6: completed 80000 read, 43445 write accesses @5922153
-system.cpu5: completed 80000 read, 42916 write accesses @5926434
-system.cpu7: completed 90000 read, 48423 write accesses @6537227
-system.cpu3: completed 90000 read, 48562 write accesses @6619736
-system.cpu0: completed 90000 read, 48962 write accesses @6625530
-system.cpu2: completed 90000 read, 48441 write accesses @6629626
-system.cpu1: completed 90000 read, 48846 write accesses @6644848
-system.cpu6: completed 90000 read, 48899 write accesses @6650109
-system.cpu4: completed 90000 read, 48617 write accesses @6655860
-system.cpu5: completed 90000 read, 48309 write accesses @6656682
-system.cpu7: completed 100000 read, 53646 write accesses @7259586
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+system.cpu2: completed 10000 read, 5361 write accesses @731568
+system.cpu5: completed 10000 read, 5557 write accesses @735340
+system.cpu3: completed 10000 read, 5535 write accesses @738863
+system.cpu6: completed 10000 read, 5476 write accesses @748316
+system.cpu0: completed 10000 read, 5560 write accesses @752250
+system.cpu4: completed 10000 read, 5465 write accesses @757289
+system.cpu7: completed 10000 read, 5564 write accesses @760144
+system.cpu1: completed 10000 read, 5530 write accesses @768416
+system.cpu5: completed 20000 read, 11151 write accesses @1477095
+system.cpu2: completed 20000 read, 10827 write accesses @1478088
+system.cpu3: completed 20000 read, 11078 write accesses @1481757
+system.cpu0: completed 20000 read, 11117 write accesses @1493889
+system.cpu6: completed 20000 read, 11080 write accesses @1512346
+system.cpu1: completed 20000 read, 11091 write accesses @1512763
+system.cpu4: completed 20000 read, 10986 write accesses @1520589
+system.cpu7: completed 20000 read, 11078 write accesses @1523748
+system.cpu5: completed 30000 read, 16568 write accesses @2200051
+system.cpu3: completed 30000 read, 16616 write accesses @2221845
+system.cpu2: completed 30000 read, 16217 write accesses @2232672
+system.cpu0: completed 30000 read, 16692 write accesses @2249618
+system.cpu1: completed 30000 read, 16648 write accesses @2263101
+system.cpu6: completed 30000 read, 16745 write accesses @2274150
+system.cpu4: completed 30000 read, 16620 write accesses @2276386
+system.cpu7: completed 30000 read, 16733 write accesses @2277359
+system.cpu5: completed 40000 read, 21987 write accesses @2947352
+system.cpu3: completed 40000 read, 22027 write accesses @2968674
+system.cpu1: completed 40000 read, 22148 write accesses @2995890
+system.cpu0: completed 40000 read, 22166 write accesses @2998152
+system.cpu2: completed 40000 read, 21828 write accesses @3001342
+system.cpu7: completed 40000 read, 22152 write accesses @3022463
+system.cpu6: completed 40000 read, 22388 write accesses @3028895
+system.cpu4: completed 40000 read, 22197 write accesses @3031091
+system.cpu5: completed 50000 read, 27444 write accesses @3696748
+system.cpu3: completed 50000 read, 27708 write accesses @3723471
+system.cpu1: completed 50000 read, 27649 write accesses @3746058
+system.cpu0: completed 50000 read, 27719 write accesses @3747410
+system.cpu2: completed 50000 read, 27424 write accesses @3760076
+system.cpu7: completed 50000 read, 27568 write accesses @3771426
+system.cpu6: completed 50000 read, 28012 write accesses @3777023
+system.cpu4: completed 50000 read, 27741 write accesses @3802071
+system.cpu5: completed 60000 read, 33062 write accesses @4446684
+system.cpu3: completed 60000 read, 33331 write accesses @4487796
+system.cpu2: completed 60000 read, 33035 write accesses @4498626
+system.cpu0: completed 60000 read, 33211 write accesses @4505229
+system.cpu1: completed 60000 read, 33219 write accesses @4525223
+system.cpu6: completed 60000 read, 33545 write accesses @4528416
+system.cpu7: completed 60000 read, 33210 write accesses @4528425
+system.cpu4: completed 60000 read, 33325 write accesses @4560641
+system.cpu5: completed 70000 read, 38698 write accesses @5188287
+system.cpu2: completed 70000 read, 38579 write accesses @5235379
+system.cpu7: completed 70000 read, 38633 write accesses @5255909
+system.cpu0: completed 70000 read, 38682 write accesses @5255973
+system.cpu6: completed 70000 read, 38964 write accesses @5261147
+system.cpu3: completed 70000 read, 38993 write accesses @5267174
+system.cpu1: completed 70000 read, 38888 write accesses @5283161
+system.cpu4: completed 70000 read, 38789 write accesses @5300670
+system.cpu5: completed 80000 read, 44039 write accesses @5937946
+system.cpu2: completed 80000 read, 43995 write accesses @5990383
+system.cpu7: completed 80000 read, 44179 write accesses @5992827
+system.cpu0: completed 80000 read, 44154 write accesses @6000956
+system.cpu6: completed 80000 read, 44514 write accesses @6013988
+system.cpu3: completed 80000 read, 44595 write accesses @6025710
+system.cpu1: completed 80000 read, 44663 write accesses @6042332
+system.cpu4: completed 80000 read, 44390 write accesses @6048987
+system.cpu5: completed 90000 read, 49553 write accesses @6694237
+system.cpu7: completed 90000 read, 49635 write accesses @6734659
+system.cpu2: completed 90000 read, 49508 write accesses @6735285
+system.cpu0: completed 90000 read, 49652 write accesses @6748849
+system.cpu6: completed 90000 read, 50083 write accesses @6767267
+system.cpu1: completed 90000 read, 50078 write accesses @6778899
+system.cpu3: completed 90000 read, 50108 write accesses @6783497
+system.cpu4: completed 90000 read, 50077 write accesses @6811616
+system.cpu5: completed 100000 read, 55112 write accesses @7430292
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
index cce9b7e46..a6cce7aa1 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
index 96061ea38..327665b25 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: rounding error > tolerance
0.072760 rounded to 0
-system.cpu6: completed 10000 read, 5376 write accesses @740514
-system.cpu0: completed 10000 read, 5364 write accesses @745186
-system.cpu3: completed 10000 read, 5423 write accesses @748707
-system.cpu4: completed 10000 read, 5537 write accesses @749784
-system.cpu7: completed 10000 read, 5400 write accesses @749868
-system.cpu1: completed 10000 read, 5530 write accesses @750998
-system.cpu5: completed 10000 read, 5459 write accesses @756529
-system.cpu2: completed 10000 read, 5543 write accesses @771097
-system.cpu6: completed 20000 read, 10651 write accesses @1479754
-system.cpu3: completed 20000 read, 10879 write accesses @1495041
-system.cpu7: completed 20000 read, 10760 write accesses @1499008
-system.cpu1: completed 20000 read, 10977 write accesses @1499104
-system.cpu5: completed 20000 read, 10867 write accesses @1505086
-system.cpu0: completed 20000 read, 10799 write accesses @1507389
-system.cpu4: completed 20000 read, 11068 write accesses @1508085
-system.cpu2: completed 20000 read, 10878 write accesses @1527233
-system.cpu6: completed 30000 read, 16119 write accesses @2225328
-system.cpu3: completed 30000 read, 16305 write accesses @2244855
-system.cpu5: completed 30000 read, 16187 write accesses @2247278
-system.cpu7: completed 30000 read, 16155 write accesses @2249487
-system.cpu1: completed 30000 read, 16466 write accesses @2250992
-system.cpu0: completed 30000 read, 16273 write accesses @2255206
-system.cpu4: completed 30000 read, 16428 write accesses @2263136
-system.cpu2: completed 30000 read, 16197 write accesses @2278056
-system.cpu6: completed 40000 read, 21573 write accesses @2978557
-system.cpu7: completed 40000 read, 21410 write accesses @2982935
-system.cpu4: completed 40000 read, 21729 write accesses @2999959
-system.cpu3: completed 40000 read, 21781 write accesses @3000904
-system.cpu1: completed 40000 read, 21951 write accesses @3003109
-system.cpu5: completed 40000 read, 21639 write accesses @3013039
-system.cpu0: completed 40000 read, 21607 write accesses @3015250
-system.cpu2: completed 40000 read, 21696 write accesses @3037769
-system.cpu6: completed 50000 read, 26913 write accesses @3719593
-system.cpu7: completed 50000 read, 26968 write accesses @3753645
-system.cpu4: completed 50000 read, 27060 write accesses @3754051
-system.cpu1: completed 50000 read, 27365 write accesses @3755861
-system.cpu0: completed 50000 read, 27035 write accesses @3755945
-system.cpu3: completed 50000 read, 27265 write accesses @3757400
-system.cpu5: completed 50000 read, 27001 write accesses @3763589
-system.cpu2: completed 50000 read, 27364 write accesses @3806785
-system.cpu6: completed 60000 read, 32204 write accesses @4458868
-system.cpu1: completed 60000 read, 32673 write accesses @4480776
-system.cpu0: completed 60000 read, 32481 write accesses @4498229
-system.cpu7: completed 60000 read, 32335 write accesses @4506920
-system.cpu3: completed 60000 read, 32750 write accesses @4507998
-system.cpu4: completed 60000 read, 32435 write accesses @4514030
-system.cpu5: completed 60000 read, 32505 write accesses @4516999
-system.cpu2: completed 60000 read, 32812 write accesses @4572908
-system.cpu6: completed 70000 read, 37702 write accesses @5219683
-system.cpu0: completed 70000 read, 38094 write accesses @5237731
-system.cpu1: completed 70000 read, 38271 write accesses @5247271
-system.cpu5: completed 70000 read, 37826 write accesses @5260789
-system.cpu3: completed 70000 read, 38167 write accesses @5262755
-system.cpu4: completed 70000 read, 37927 write accesses @5268995
-system.cpu7: completed 70000 read, 37729 write accesses @5271169
-system.cpu2: completed 70000 read, 38312 write accesses @5320578
-system.cpu6: completed 80000 read, 43265 write accesses @5963960
-system.cpu0: completed 80000 read, 43558 write accesses @5996302
-system.cpu5: completed 80000 read, 43163 write accesses @6000784
-system.cpu3: completed 80000 read, 43563 write accesses @6009019
-system.cpu1: completed 80000 read, 43846 write accesses @6010830
-system.cpu4: completed 80000 read, 43375 write accesses @6021719
-system.cpu7: completed 80000 read, 43151 write accesses @6032005
-system.cpu2: completed 80000 read, 43642 write accesses @6070842
-system.cpu6: completed 90000 read, 48756 write accesses @6719511
-system.cpu5: completed 90000 read, 48675 write accesses @6752879
-system.cpu0: completed 90000 read, 49075 write accesses @6759943
-system.cpu4: completed 90000 read, 48792 write accesses @6772472
-system.cpu1: completed 90000 read, 49329 write accesses @6774290
-system.cpu3: completed 90000 read, 49090 write accesses @6783540
-system.cpu7: completed 90000 read, 48766 write accesses @6785808
-system.cpu2: completed 90000 read, 49113 write accesses @6821790
-system.cpu6: completed 100000 read, 54332 write accesses @7481441
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+system.cpu6: completed 10000 read, 5503 write accesses @757269
+system.cpu4: completed 10000 read, 5478 write accesses @761080
+system.cpu2: completed 10000 read, 5550 write accesses @763319
+system.cpu1: completed 10000 read, 5614 write accesses @768345
+system.cpu0: completed 10000 read, 5587 write accesses @769447
+system.cpu7: completed 10000 read, 5757 write accesses @772728
+system.cpu5: completed 10000 read, 5702 write accesses @774176
+system.cpu3: completed 10000 read, 5518 write accesses @779096
+system.cpu7: completed 20000 read, 10973 write accesses @1520367
+system.cpu4: completed 20000 read, 10979 write accesses @1526709
+system.cpu6: completed 20000 read, 11106 write accesses @1529725
+system.cpu2: completed 20000 read, 10993 write accesses @1531224
+system.cpu1: completed 20000 read, 11181 write accesses @1533339
+system.cpu5: completed 20000 read, 11353 write accesses @1534479
+system.cpu0: completed 20000 read, 11156 write accesses @1538403
+system.cpu3: completed 20000 read, 11059 write accesses @1546200
+system.cpu7: completed 30000 read, 16565 write accesses @2285511
+system.cpu5: completed 30000 read, 16777 write accesses @2288641
+system.cpu2: completed 30000 read, 16597 write accesses @2294136
+system.cpu4: completed 30000 read, 16631 write accesses @2299512
+system.cpu0: completed 30000 read, 16690 write accesses @2299577
+system.cpu1: completed 30000 read, 16784 write accesses @2300367
+system.cpu3: completed 30000 read, 16611 write accesses @2300731
+system.cpu6: completed 30000 read, 16728 write accesses @2302250
+system.cpu4: completed 40000 read, 22149 write accesses @3049466
+system.cpu6: completed 40000 read, 22257 write accesses @3061175
+system.cpu7: completed 40000 read, 22207 write accesses @3063273
+system.cpu5: completed 40000 read, 22390 write accesses @3065947
+system.cpu2: completed 40000 read, 22266 write accesses @3066692
+system.cpu3: completed 40000 read, 22073 write accesses @3067947
+system.cpu0: completed 40000 read, 22351 write accesses @3070634
+system.cpu1: completed 40000 read, 22419 write accesses @3080538
+system.cpu4: completed 50000 read, 27758 write accesses @3814226
+system.cpu5: completed 50000 read, 27788 write accesses @3821800
+system.cpu2: completed 50000 read, 27879 write accesses @3832783
+system.cpu6: completed 50000 read, 27794 write accesses @3833668
+system.cpu7: completed 50000 read, 27831 write accesses @3833943
+system.cpu3: completed 50000 read, 27630 write accesses @3836295
+system.cpu1: completed 50000 read, 28014 write accesses @3838264
+system.cpu0: completed 50000 read, 27900 write accesses @3845606
+system.cpu4: completed 60000 read, 33195 write accesses @4581871
+system.cpu6: completed 60000 read, 33436 write accesses @4591130
+system.cpu5: completed 60000 read, 33441 write accesses @4592195
+system.cpu2: completed 60000 read, 33425 write accesses @4596449
+system.cpu7: completed 60000 read, 33475 write accesses @4602310
+system.cpu1: completed 60000 read, 33528 write accesses @4604165
+system.cpu3: completed 60000 read, 33269 write accesses @4608944
+system.cpu0: completed 60000 read, 33561 write accesses @4617814
+system.cpu4: completed 70000 read, 38745 write accesses @5357021
+system.cpu1: completed 70000 read, 39092 write accesses @5358188
+system.cpu7: completed 70000 read, 39078 write accesses @5359639
+system.cpu6: completed 70000 read, 39017 write accesses @5360015
+system.cpu5: completed 70000 read, 39077 write accesses @5360709
+system.cpu2: completed 70000 read, 39142 write accesses @5362206
+system.cpu3: completed 70000 read, 38953 write accesses @5383557
+system.cpu0: completed 70000 read, 39148 write accesses @5384346
+system.cpu1: completed 80000 read, 44697 write accesses @6109229
+system.cpu4: completed 80000 read, 44391 write accesses @6113222
+system.cpu6: completed 80000 read, 44634 write accesses @6116932
+system.cpu2: completed 80000 read, 44686 write accesses @6124384
+system.cpu7: completed 80000 read, 44658 write accesses @6130030
+system.cpu5: completed 80000 read, 44817 write accesses @6133468
+system.cpu0: completed 80000 read, 44666 write accesses @6150195
+system.cpu3: completed 80000 read, 44619 write accesses @6165694
+system.cpu1: completed 90000 read, 50286 write accesses @6886139
+system.cpu5: completed 90000 read, 50291 write accesses @6887562
+system.cpu6: completed 90000 read, 50249 write accesses @6888221
+system.cpu4: completed 90000 read, 50068 write accesses @6890175
+system.cpu2: completed 90000 read, 50264 write accesses @6897909
+system.cpu7: completed 90000 read, 50336 write accesses @6907186
+system.cpu3: completed 90000 read, 50220 write accesses @6927421
+system.cpu0: completed 90000 read, 50337 write accesses @6930851
+system.cpu5: completed 100000 read, 55860 write accesses @7645897
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
index c165a6832..319711992 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
index 78259ab68..1e742ef57 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: rounding error > tolerance
0.072760 rounded to 0
-system.cpu3: completed 10000 read, 5373 write accesses @610961
-system.cpu5: completed 10000 read, 5365 write accesses @611018
-system.cpu4: completed 10000 read, 5553 write accesses @613027
-system.cpu2: completed 10000 read, 5350 write accesses @617677
-system.cpu1: completed 10000 read, 5430 write accesses @618344
-system.cpu0: completed 10000 read, 5583 write accesses @619157
-system.cpu7: completed 10000 read, 5389 write accesses @620153
-system.cpu6: completed 10000 read, 5612 write accesses @620650
-system.cpu5: completed 20000 read, 10789 write accesses @1225454
-system.cpu1: completed 20000 read, 10846 write accesses @1236230
-system.cpu4: completed 20000 read, 10993 write accesses @1237289
-system.cpu0: completed 20000 read, 11135 write accesses @1237437
-system.cpu7: completed 20000 read, 10790 write accesses @1238914
-system.cpu3: completed 20000 read, 10722 write accesses @1239177
-system.cpu6: completed 20000 read, 11153 write accesses @1244507
-system.cpu2: completed 20000 read, 10728 write accesses @1245295
-system.cpu5: completed 30000 read, 16089 write accesses @1837067
-system.cpu1: completed 30000 read, 16220 write accesses @1844516
-system.cpu3: completed 30000 read, 16042 write accesses @1846213
-system.cpu6: completed 30000 read, 16442 write accesses @1852618
-system.cpu0: completed 30000 read, 16510 write accesses @1857227
-system.cpu7: completed 30000 read, 16238 write accesses @1862399
-system.cpu2: completed 30000 read, 16227 write accesses @1874504
-system.cpu4: completed 30000 read, 16481 write accesses @1879909
-system.cpu5: completed 40000 read, 21666 write accesses @2447180
-system.cpu1: completed 40000 read, 21716 write accesses @2464865
-system.cpu0: completed 40000 read, 21907 write accesses @2473366
-system.cpu7: completed 40000 read, 21535 write accesses @2473664
-system.cpu3: completed 40000 read, 21446 write accesses @2475585
-system.cpu6: completed 40000 read, 21928 write accesses @2479522
-system.cpu4: completed 40000 read, 21651 write accesses @2491724
-system.cpu2: completed 40000 read, 21571 write accesses @2492947
-system.cpu5: completed 50000 read, 27225 write accesses @3067865
-system.cpu7: completed 50000 read, 26823 write accesses @3086290
-system.cpu3: completed 50000 read, 26661 write accesses @3087077
-system.cpu1: completed 50000 read, 27045 write accesses @3088502
-system.cpu6: completed 50000 read, 27350 write accesses @3091373
-system.cpu0: completed 50000 read, 27240 write accesses @3099902
-system.cpu4: completed 50000 read, 27063 write accesses @3101501
-system.cpu2: completed 50000 read, 27064 write accesses @3114914
-system.cpu5: completed 60000 read, 32586 write accesses @3679414
-system.cpu1: completed 60000 read, 32546 write accesses @3694760
-system.cpu3: completed 60000 read, 32032 write accesses @3702088
-system.cpu7: completed 60000 read, 32061 write accesses @3707072
-system.cpu0: completed 60000 read, 32607 write accesses @3710014
-system.cpu2: completed 60000 read, 32411 write accesses @3717514
-system.cpu6: completed 60000 read, 32905 write accesses @3719411
-system.cpu4: completed 60000 read, 32455 write accesses @3724218
-system.cpu1: completed 70000 read, 37971 write accesses @4303479
-system.cpu3: completed 70000 read, 37478 write accesses @4307612
-system.cpu5: completed 70000 read, 38121 write accesses @4312096
-system.cpu0: completed 70000 read, 38044 write accesses @4316156
-system.cpu7: completed 70000 read, 37345 write accesses @4323040
-system.cpu2: completed 70000 read, 37853 write accesses @4334714
-system.cpu6: completed 70000 read, 38341 write accesses @4338265
-system.cpu4: completed 70000 read, 37883 write accesses @4348139
-system.cpu3: completed 80000 read, 42790 write accesses @4909950
-system.cpu0: completed 80000 read, 43447 write accesses @4922258
-system.cpu1: completed 80000 read, 43458 write accesses @4929896
-system.cpu5: completed 80000 read, 43556 write accesses @4929946
-system.cpu7: completed 80000 read, 42733 write accesses @4945136
-system.cpu2: completed 80000 read, 43278 write accesses @4954988
-system.cpu6: completed 80000 read, 43794 write accesses @4962728
-system.cpu4: completed 80000 read, 43313 write accesses @4970893
-system.cpu3: completed 90000 read, 48235 write accesses @5529277
-system.cpu1: completed 90000 read, 48908 write accesses @5532854
-system.cpu0: completed 90000 read, 48795 write accesses @5538200
-system.cpu5: completed 90000 read, 49134 write accesses @5544337
-system.cpu2: completed 90000 read, 48427 write accesses @5551687
-system.cpu7: completed 90000 read, 48273 write accesses @5561660
-system.cpu4: completed 90000 read, 48720 write accesses @5589754
-system.cpu6: completed 90000 read, 49134 write accesses @5592253
-system.cpu0: completed 100000 read, 54250 write accesses @6151475
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+system.cpu5: completed 10000 read, 5530 write accesses @619922
+system.cpu6: completed 10000 read, 5474 write accesses @621650
+system.cpu7: completed 10000 read, 5669 write accesses @623678
+system.cpu2: completed 10000 read, 5566 write accesses @627878
+system.cpu4: completed 10000 read, 5488 write accesses @628250
+system.cpu1: completed 10000 read, 5485 write accesses @629308
+system.cpu3: completed 10000 read, 5616 write accesses @630755
+system.cpu0: completed 10000 read, 5556 write accesses @631832
+system.cpu0: completed 20000 read, 11113 write accesses @1242739
+system.cpu2: completed 20000 read, 11184 write accesses @1249193
+system.cpu5: completed 20000 read, 11055 write accesses @1252676
+system.cpu1: completed 20000 read, 11025 write accesses @1255481
+system.cpu6: completed 20000 read, 10958 write accesses @1259795
+system.cpu3: completed 20000 read, 11192 write accesses @1262410
+system.cpu4: completed 20000 read, 11069 write accesses @1265165
+system.cpu7: completed 20000 read, 11154 write accesses @1271872
+system.cpu2: completed 30000 read, 16789 write accesses @1882328
+system.cpu5: completed 30000 read, 16628 write accesses @1882366
+system.cpu4: completed 30000 read, 16634 write accesses @1884079
+system.cpu0: completed 30000 read, 16724 write accesses @1885096
+system.cpu1: completed 30000 read, 16623 write accesses @1888139
+system.cpu3: completed 30000 read, 16738 write accesses @1892924
+system.cpu6: completed 30000 read, 16532 write accesses @1894586
+system.cpu7: completed 30000 read, 16931 write accesses @1919912
+system.cpu0: completed 40000 read, 22182 write accesses @2505116
+system.cpu4: completed 40000 read, 22117 write accesses @2510993
+system.cpu1: completed 40000 read, 22260 write accesses @2513447
+system.cpu5: completed 40000 read, 22212 write accesses @2514125
+system.cpu3: completed 40000 read, 22396 write accesses @2516765
+system.cpu2: completed 40000 read, 22468 write accesses @2519189
+system.cpu6: completed 40000 read, 22230 write accesses @2538281
+system.cpu7: completed 40000 read, 22488 write accesses @2557526
+system.cpu0: completed 50000 read, 27789 write accesses @3133555
+system.cpu2: completed 50000 read, 28077 write accesses @3139915
+system.cpu4: completed 50000 read, 27742 write accesses @3146518
+system.cpu1: completed 50000 read, 27886 write accesses @3150027
+system.cpu5: completed 50000 read, 27798 write accesses @3154334
+system.cpu3: completed 50000 read, 28034 write accesses @3161717
+system.cpu6: completed 50000 read, 27710 write accesses @3168082
+system.cpu7: completed 50000 read, 28032 write accesses @3187555
+system.cpu0: completed 60000 read, 33311 write accesses @3767660
+system.cpu4: completed 60000 read, 33304 write accesses @3772541
+system.cpu1: completed 60000 read, 33446 write accesses @3773198
+system.cpu2: completed 60000 read, 33652 write accesses @3776350
+system.cpu5: completed 60000 read, 33271 write accesses @3781457
+system.cpu6: completed 60000 read, 33278 write accesses @3794854
+system.cpu3: completed 60000 read, 33612 write accesses @3795827
+system.cpu7: completed 60000 read, 33548 write accesses @3811016
+system.cpu0: completed 70000 read, 38763 write accesses @4391942
+system.cpu5: completed 70000 read, 38783 write accesses @4406065
+system.cpu4: completed 70000 read, 38931 write accesses @4406093
+system.cpu1: completed 70000 read, 39120 write accesses @4408424
+system.cpu2: completed 70000 read, 39282 write accesses @4411507
+system.cpu6: completed 70000 read, 38935 write accesses @4431425
+system.cpu3: completed 70000 read, 39112 write accesses @4436411
+system.cpu7: completed 70000 read, 39053 write accesses @4450257
+system.cpu4: completed 80000 read, 44397 write accesses @5015840
+system.cpu0: completed 80000 read, 44355 write accesses @5031328
+system.cpu1: completed 80000 read, 44681 write accesses @5033509
+system.cpu5: completed 80000 read, 44411 write accesses @5035544
+system.cpu2: completed 80000 read, 44867 write accesses @5051495
+system.cpu6: completed 80000 read, 44501 write accesses @5065596
+system.cpu3: completed 80000 read, 44674 write accesses @5067973
+system.cpu7: completed 80000 read, 44457 write accesses @5071578
+system.cpu5: completed 90000 read, 50018 write accesses @5653124
+system.cpu4: completed 90000 read, 50091 write accesses @5657891
+system.cpu0: completed 90000 read, 50057 write accesses @5659483
+system.cpu1: completed 90000 read, 50245 write accesses @5662169
+system.cpu2: completed 90000 read, 50468 write accesses @5689246
+system.cpu7: completed 90000 read, 50055 write accesses @5700359
+system.cpu6: completed 90000 read, 50091 write accesses @5701022
+system.cpu3: completed 90000 read, 50159 write accesses @5709281
+system.cpu0: completed 100000 read, 55570 write accesses @6284915
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
index 77392538d..c8c135618 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
index f2f8ae71c..80cafee63 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: rounding error > tolerance
0.072760 rounded to 0
-system.cpu5: completed 10000 read, 5516 write accesses @570851
-system.cpu3: completed 10000 read, 5324 write accesses @572812
-system.cpu1: completed 10000 read, 5481 write accesses @576530
-system.cpu2: completed 10000 read, 5411 write accesses @581924
-system.cpu6: completed 10000 read, 5498 write accesses @589277
-system.cpu4: completed 10000 read, 5455 write accesses @592697
-system.cpu7: completed 10000 read, 5509 write accesses @593396
-system.cpu0: completed 10000 read, 5411 write accesses @595334
-system.cpu5: completed 20000 read, 10869 write accesses @1154450
-system.cpu3: completed 20000 read, 10943 write accesses @1161279
-system.cpu1: completed 20000 read, 10969 write accesses @1165235
-system.cpu2: completed 20000 read, 10883 write accesses @1170873
-system.cpu4: completed 20000 read, 10908 write accesses @1171882
-system.cpu0: completed 20000 read, 10807 write accesses @1172431
-system.cpu6: completed 20000 read, 10859 write accesses @1174037
-system.cpu7: completed 20000 read, 11017 write accesses @1183706
-system.cpu5: completed 30000 read, 16441 write accesses @1743020
-system.cpu3: completed 30000 read, 16218 write accesses @1743361
-system.cpu0: completed 30000 read, 16106 write accesses @1749355
-system.cpu6: completed 30000 read, 16285 write accesses @1751262
-system.cpu2: completed 30000 read, 16334 write accesses @1752944
-system.cpu1: completed 30000 read, 16624 write accesses @1754412
-system.cpu4: completed 30000 read, 16300 write accesses @1756493
-system.cpu7: completed 30000 read, 16545 write accesses @1761662
-system.cpu5: completed 40000 read, 21903 write accesses @2321871
-system.cpu2: completed 40000 read, 21777 write accesses @2328122
-system.cpu6: completed 40000 read, 21684 write accesses @2328788
-system.cpu0: completed 40000 read, 21584 write accesses @2333159
-system.cpu4: completed 40000 read, 21691 write accesses @2333509
-system.cpu3: completed 40000 read, 21802 write accesses @2335052
-system.cpu1: completed 40000 read, 21911 write accesses @2336699
-system.cpu7: completed 40000 read, 21984 write accesses @2354153
-system.cpu3: completed 50000 read, 27199 write accesses @2900098
-system.cpu6: completed 50000 read, 26980 write accesses @2908928
-system.cpu2: completed 50000 read, 27238 write accesses @2909195
-system.cpu5: completed 50000 read, 27250 write accesses @2913605
-system.cpu4: completed 50000 read, 26997 write accesses @2920489
-system.cpu0: completed 50000 read, 27072 write accesses @2924735
-system.cpu1: completed 50000 read, 27407 write accesses @2925503
-system.cpu7: completed 50000 read, 27387 write accesses @2927681
-system.cpu2: completed 60000 read, 32632 write accesses @3474793
-system.cpu6: completed 60000 read, 32472 write accesses @3482759
-system.cpu3: completed 60000 read, 32504 write accesses @3487367
-system.cpu0: completed 60000 read, 32401 write accesses @3493294
-system.cpu4: completed 60000 read, 32171 write accesses @3498890
-system.cpu5: completed 60000 read, 32778 write accesses @3503066
-system.cpu1: completed 60000 read, 32891 write accesses @3509381
-system.cpu7: completed 60000 read, 32765 write accesses @3516772
-system.cpu2: completed 70000 read, 38066 write accesses @4058828
-system.cpu3: completed 70000 read, 37916 write accesses @4058910
-system.cpu6: completed 70000 read, 37885 write accesses @4063852
-system.cpu4: completed 70000 read, 37622 write accesses @4080369
-system.cpu0: completed 70000 read, 37925 write accesses @4085861
-system.cpu5: completed 70000 read, 38249 write accesses @4094801
-system.cpu1: completed 70000 read, 38488 write accesses @4095495
-system.cpu7: completed 70000 read, 38117 write accesses @4097708
-system.cpu2: completed 80000 read, 43433 write accesses @4639406
-system.cpu3: completed 80000 read, 43416 write accesses @4647614
-system.cpu6: completed 80000 read, 43333 write accesses @4648301
-system.cpu5: completed 80000 read, 43562 write accesses @4662354
-system.cpu0: completed 80000 read, 43227 write accesses @4664558
-system.cpu4: completed 80000 read, 43117 write accesses @4665549
-system.cpu1: completed 80000 read, 43838 write accesses @4675271
-system.cpu7: completed 80000 read, 43557 write accesses @4676998
-system.cpu2: completed 90000 read, 48793 write accesses @5208478
-system.cpu3: completed 90000 read, 48771 write accesses @5220479
-system.cpu6: completed 90000 read, 48900 write accesses @5227295
-system.cpu5: completed 90000 read, 48930 write accesses @5242795
-system.cpu1: completed 90000 read, 49220 write accesses @5246394
-system.cpu0: completed 90000 read, 48602 write accesses @5246963
-system.cpu4: completed 90000 read, 48456 write accesses @5248509
-system.cpu7: completed 90000 read, 48936 write accesses @5260982
-system.cpu2: completed 100000 read, 54294 write accesses @5795833
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+system.cpu4: completed 10000 read, 5516 write accesses @584228
+system.cpu5: completed 10000 read, 5515 write accesses @587183
+system.cpu1: completed 10000 read, 5491 write accesses @591446
+system.cpu7: completed 10000 read, 5626 write accesses @595409
+system.cpu2: completed 10000 read, 5637 write accesses @596437
+system.cpu6: completed 10000 read, 5437 write accesses @597608
+system.cpu3: completed 10000 read, 5738 write accesses @597986
+system.cpu0: completed 10000 read, 5730 write accesses @601184
+system.cpu4: completed 20000 read, 11120 write accesses @1170250
+system.cpu6: completed 20000 read, 10900 write accesses @1171579
+system.cpu3: completed 20000 read, 11193 write accesses @1184267
+system.cpu1: completed 20000 read, 11047 write accesses @1190135
+system.cpu5: completed 20000 read, 11070 write accesses @1191953
+system.cpu7: completed 20000 read, 11317 write accesses @1192073
+system.cpu2: completed 20000 read, 11059 write accesses @1192934
+system.cpu0: completed 20000 read, 11218 write accesses @1196582
+system.cpu6: completed 30000 read, 16404 write accesses @1756097
+system.cpu4: completed 30000 read, 16698 write accesses @1768219
+system.cpu7: completed 30000 read, 16835 write accesses @1769427
+system.cpu3: completed 30000 read, 16672 write accesses @1773026
+system.cpu1: completed 30000 read, 16602 write accesses @1773962
+system.cpu0: completed 30000 read, 16781 write accesses @1777262
+system.cpu5: completed 30000 read, 16565 write accesses @1782900
+system.cpu2: completed 30000 read, 16614 write accesses @1785263
+system.cpu6: completed 40000 read, 22003 write accesses @2340507
+system.cpu1: completed 40000 read, 22145 write accesses @2358116
+system.cpu0: completed 40000 read, 22355 write accesses @2364775
+system.cpu7: completed 40000 read, 22565 write accesses @2374538
+system.cpu2: completed 40000 read, 22222 write accesses @2375711
+system.cpu4: completed 40000 read, 22294 write accesses @2376781
+system.cpu3: completed 40000 read, 22360 write accesses @2377205
+system.cpu5: completed 40000 read, 22099 write accesses @2379118
+system.cpu6: completed 50000 read, 27600 write accesses @2941333
+system.cpu1: completed 50000 read, 27821 write accesses @2946145
+system.cpu0: completed 50000 read, 27935 write accesses @2959151
+system.cpu2: completed 50000 read, 27794 write accesses @2968804
+system.cpu3: completed 50000 read, 27849 write accesses @2971166
+system.cpu5: completed 50000 read, 27657 write accesses @2977357
+system.cpu4: completed 50000 read, 27828 write accesses @2978259
+system.cpu7: completed 50000 read, 28284 write accesses @2978857
+system.cpu6: completed 60000 read, 33178 write accesses @3536924
+system.cpu1: completed 60000 read, 33394 write accesses @3543961
+system.cpu2: completed 60000 read, 33230 write accesses @3549333
+system.cpu0: completed 60000 read, 33564 write accesses @3564287
+system.cpu3: completed 60000 read, 33336 write accesses @3569137
+system.cpu4: completed 60000 read, 33587 write accesses @3570593
+system.cpu5: completed 60000 read, 33166 write accesses @3576647
+system.cpu7: completed 60000 read, 33832 write accesses @3577075
+system.cpu6: completed 70000 read, 38652 write accesses @4137461
+system.cpu2: completed 70000 read, 38824 write accesses @4141010
+system.cpu1: completed 70000 read, 39043 write accesses @4142171
+system.cpu4: completed 70000 read, 39136 write accesses @4148986
+system.cpu5: completed 70000 read, 38716 write accesses @4161730
+system.cpu0: completed 70000 read, 39119 write accesses @4165271
+system.cpu3: completed 70000 read, 38875 write accesses @4169555
+system.cpu7: completed 70000 read, 39501 write accesses @4176068
+system.cpu6: completed 80000 read, 44287 write accesses @4740297
+system.cpu2: completed 80000 read, 44433 write accesses @4742323
+system.cpu4: completed 80000 read, 44799 write accesses @4743294
+system.cpu0: completed 80000 read, 44555 write accesses @4750388
+system.cpu1: completed 80000 read, 44835 write accesses @4751884
+system.cpu5: completed 80000 read, 44235 write accesses @4755731
+system.cpu3: completed 80000 read, 44536 write accesses @4756531
+system.cpu7: completed 80000 read, 45051 write accesses @4789789
+system.cpu2: completed 90000 read, 50085 write accesses @5331779
+system.cpu1: completed 90000 read, 50520 write accesses @5335067
+system.cpu6: completed 90000 read, 50077 write accesses @5343428
+system.cpu4: completed 90000 read, 50348 write accesses @5344112
+system.cpu5: completed 90000 read, 49814 write accesses @5348125
+system.cpu3: completed 90000 read, 50170 write accesses @5349617
+system.cpu0: completed 90000 read, 50102 write accesses @5350612
+system.cpu7: completed 90000 read, 50733 write accesses @5394074
+system.cpu1: completed 100000 read, 56034 write accesses @5920895
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index 12c7c969e..0a7886e85 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
index 5a7e36bf9..b3b846e79 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: rounding error > tolerance
0.072760 rounded to 0
-system.cpu4: completed 10000 read, 5267 write accesses @855219
-system.cpu7: completed 10000 read, 5381 write accesses @861031
-system.cpu1: completed 10000 read, 5262 write accesses @863126
-system.cpu2: completed 10000 read, 5381 write accesses @864460
-system.cpu0: completed 10000 read, 5401 write accesses @867419
-system.cpu3: completed 10000 read, 5382 write accesses @869141
-system.cpu5: completed 10000 read, 5455 write accesses @872828
-system.cpu6: completed 10000 read, 5482 write accesses @879392
-system.cpu7: completed 20000 read, 10628 write accesses @1724117
-system.cpu2: completed 20000 read, 10953 write accesses @1730360
-system.cpu1: completed 20000 read, 10550 write accesses @1730621
-system.cpu3: completed 20000 read, 10808 write accesses @1733195
-system.cpu4: completed 20000 read, 10816 write accesses @1737229
-system.cpu0: completed 20000 read, 10790 write accesses @1746955
-system.cpu6: completed 20000 read, 11016 write accesses @1749077
-system.cpu5: completed 20000 read, 10800 write accesses @1759742
-system.cpu3: completed 30000 read, 16255 write accesses @2586824
-system.cpu7: completed 30000 read, 15936 write accesses @2587214
-system.cpu0: completed 30000 read, 16091 write accesses @2589409
-system.cpu2: completed 30000 read, 16288 write accesses @2595682
-system.cpu4: completed 30000 read, 16193 write accesses @2610317
-system.cpu6: completed 30000 read, 16368 write accesses @2614352
-system.cpu5: completed 30000 read, 16095 write accesses @2624564
-system.cpu1: completed 30000 read, 16153 write accesses @2637701
-system.cpu7: completed 40000 read, 21310 write accesses @3438977
-system.cpu0: completed 40000 read, 21543 write accesses @3451234
-system.cpu2: completed 40000 read, 21712 write accesses @3460847
-system.cpu3: completed 40000 read, 21652 write accesses @3468818
-system.cpu6: completed 40000 read, 21709 write accesses @3479513
-system.cpu4: completed 40000 read, 21724 write accesses @3497567
-system.cpu5: completed 40000 read, 21477 write accesses @3498797
-system.cpu1: completed 40000 read, 21640 write accesses @3521390
-system.cpu7: completed 50000 read, 26683 write accesses @4309027
-system.cpu2: completed 50000 read, 27008 write accesses @4319999
-system.cpu0: completed 50000 read, 26993 write accesses @4330940
-system.cpu6: completed 50000 read, 27072 write accesses @4336165
-system.cpu3: completed 50000 read, 27085 write accesses @4352827
-system.cpu5: completed 50000 read, 26964 write accesses @4357459
-system.cpu4: completed 50000 read, 27198 write accesses @4384075
-system.cpu1: completed 50000 read, 27029 write accesses @4398757
-system.cpu7: completed 60000 read, 32063 write accesses @5160248
-system.cpu0: completed 60000 read, 32443 write accesses @5203475
-system.cpu2: completed 60000 read, 32367 write accesses @5205683
-system.cpu6: completed 60000 read, 32517 write accesses @5225171
-system.cpu3: completed 60000 read, 32534 write accesses @5227022
-system.cpu5: completed 60000 read, 32552 write accesses @5229640
-system.cpu1: completed 60000 read, 32592 write accesses @5258417
-system.cpu4: completed 60000 read, 32682 write accesses @5263781
-system.cpu7: completed 70000 read, 37467 write accesses @6033043
-system.cpu0: completed 70000 read, 37995 write accesses @6081225
-system.cpu6: completed 70000 read, 37873 write accesses @6089309
-system.cpu3: completed 70000 read, 38002 write accesses @6091981
-system.cpu2: completed 70000 read, 37862 write accesses @6093259
-system.cpu5: completed 70000 read, 38035 write accesses @6114916
-system.cpu1: completed 70000 read, 38024 write accesses @6119174
-system.cpu4: completed 70000 read, 38117 write accesses @6129370
-system.cpu7: completed 80000 read, 42779 write accesses @6903893
-system.cpu0: completed 80000 read, 43420 write accesses @6927865
-system.cpu6: completed 80000 read, 43280 write accesses @6952004
-system.cpu3: completed 80000 read, 43445 write accesses @6966407
-system.cpu5: completed 80000 read, 43493 write accesses @6966458
-system.cpu2: completed 80000 read, 43456 write accesses @6967571
-system.cpu1: completed 80000 read, 43311 write accesses @6981707
-system.cpu4: completed 80000 read, 43712 write accesses @7010960
-system.cpu7: completed 90000 read, 48212 write accesses @7781504
-system.cpu0: completed 90000 read, 49018 write accesses @7809551
-system.cpu6: completed 90000 read, 48768 write accesses @7821401
-system.cpu2: completed 90000 read, 48919 write accesses @7841558
-system.cpu1: completed 90000 read, 48631 write accesses @7843811
-system.cpu3: completed 90000 read, 49017 write accesses @7850422
-system.cpu5: completed 90000 read, 49075 write accesses @7851926
-system.cpu4: completed 90000 read, 49432 write accesses @7874435
-system.cpu7: completed 100000 read, 53796 write accesses @8664886
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+system.cpu0: completed 10000 read, 5556 write accesses @879323
+system.cpu7: completed 10000 read, 5668 write accesses @879866
+system.cpu4: completed 10000 read, 5446 write accesses @880130
+system.cpu2: completed 10000 read, 5618 write accesses @882610
+system.cpu3: completed 10000 read, 5567 write accesses @889766
+system.cpu5: completed 10000 read, 5601 write accesses @889804
+system.cpu6: completed 10000 read, 5691 write accesses @907393
+system.cpu1: completed 10000 read, 5703 write accesses @911150
+system.cpu0: completed 20000 read, 11066 write accesses @1759277
+system.cpu7: completed 20000 read, 11260 write accesses @1770595
+system.cpu4: completed 20000 read, 11011 write accesses @1777119
+system.cpu2: completed 20000 read, 11410 write accesses @1779287
+system.cpu3: completed 20000 read, 11162 write accesses @1783007
+system.cpu5: completed 20000 read, 11166 write accesses @1789252
+system.cpu6: completed 20000 read, 11205 write accesses @1795677
+system.cpu1: completed 20000 read, 11246 write accesses @1799288
+system.cpu0: completed 30000 read, 16538 write accesses @2628765
+system.cpu4: completed 30000 read, 16331 write accesses @2649038
+system.cpu3: completed 30000 read, 16729 write accesses @2656841
+system.cpu7: completed 30000 read, 16821 write accesses @2657779
+system.cpu2: completed 30000 read, 16942 write accesses @2665738
+system.cpu6: completed 30000 read, 16767 write accesses @2683028
+system.cpu5: completed 30000 read, 16740 write accesses @2683223
+system.cpu1: completed 30000 read, 16843 write accesses @2687354
+system.cpu0: completed 40000 read, 21978 write accesses @3518323
+system.cpu4: completed 40000 read, 21923 write accesses @3532643
+system.cpu2: completed 40000 read, 22312 write accesses @3539629
+system.cpu7: completed 40000 read, 22397 write accesses @3540563
+system.cpu3: completed 40000 read, 22394 write accesses @3545743
+system.cpu1: completed 40000 read, 22522 write accesses @3569491
+system.cpu6: completed 40000 read, 22217 write accesses @3571115
+system.cpu5: completed 40000 read, 22361 write accesses @3575245
+system.cpu0: completed 50000 read, 27412 write accesses @4395937
+system.cpu4: completed 50000 read, 27504 write accesses @4402816
+system.cpu2: completed 50000 read, 27861 write accesses @4421377
+system.cpu7: completed 50000 read, 28050 write accesses @4432946
+system.cpu3: completed 50000 read, 28057 write accesses @4453484
+system.cpu5: completed 50000 read, 28091 write accesses @4459262
+system.cpu6: completed 50000 read, 27767 write accesses @4466993
+system.cpu1: completed 50000 read, 28057 write accesses @4473556
+system.cpu0: completed 60000 read, 33045 write accesses @5302811
+system.cpu2: completed 60000 read, 33521 write accesses @5307713
+system.cpu4: completed 60000 read, 33106 write accesses @5309735
+system.cpu3: completed 60000 read, 33613 write accesses @5326889
+system.cpu7: completed 60000 read, 33738 write accesses @5327419
+system.cpu1: completed 60000 read, 33648 write accesses @5345018
+system.cpu6: completed 60000 read, 33262 write accesses @5350442
+system.cpu5: completed 60000 read, 33765 write accesses @5365882
+system.cpu4: completed 70000 read, 38688 write accesses @6177299
+system.cpu0: completed 70000 read, 38751 write accesses @6203477
+system.cpu2: completed 70000 read, 39098 write accesses @6206063
+system.cpu3: completed 70000 read, 39126 write accesses @6219412
+system.cpu1: completed 70000 read, 39169 write accesses @6222370
+system.cpu6: completed 70000 read, 38802 write accesses @6223076
+system.cpu7: completed 70000 read, 39595 write accesses @6226670
+system.cpu5: completed 70000 read, 39326 write accesses @6257626
+system.cpu4: completed 80000 read, 44383 write accesses @7068978
+system.cpu2: completed 80000 read, 44769 write accesses @7095466
+system.cpu3: completed 80000 read, 44569 write accesses @7095782
+system.cpu0: completed 80000 read, 44509 write accesses @7100023
+system.cpu6: completed 80000 read, 44542 write accesses @7108504
+system.cpu1: completed 80000 read, 44592 write accesses @7113439
+system.cpu7: completed 80000 read, 45281 write accesses @7113500
+system.cpu5: completed 80000 read, 44911 write accesses @7150684
+system.cpu4: completed 90000 read, 50048 write accesses @7961758
+system.cpu0: completed 90000 read, 49958 write accesses @7968130
+system.cpu2: completed 90000 read, 50371 write accesses @7973060
+system.cpu3: completed 90000 read, 50104 write accesses @7976843
+system.cpu7: completed 90000 read, 50805 write accesses @7986452
+system.cpu6: completed 90000 read, 50102 write accesses @7998542
+system.cpu1: completed 90000 read, 50241 write accesses @7999593
+system.cpu5: completed 90000 read, 50481 write accesses @8039612
+system.cpu7: completed 100000 read, 56250 write accesses @8851106
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
index b9c14dc5f..6605d530a 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
@@ -10,13 +10,14 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem l2c membus physmem toL2Bus voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem l2c membus physmem toL2Bus voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
+kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -37,7 +38,9 @@ system_port=system.membus.slave[1]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu0]
@@ -491,11 +494,21 @@ size=32768
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -553,7 +566,7 @@ sequential_access=false
size=65536
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
eventq_index=0
@@ -585,7 +598,7 @@ range=0:134217727
port=system.membus.master[0]
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
index 70113e2a8..16ab1a5b8 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
@@ -1,74 +1,73 @@
-warn: failed to generate dot output from build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/config.dot
-system.cpu6: completed 10000 read, 5415 write accesses @145109000
-system.cpu2: completed 10000 read, 5349 write accesses @145417500
-system.cpu1: completed 10000 read, 5329 write accesses @146140000
-system.cpu0: completed 10000 read, 5371 write accesses @146497000
-system.cpu4: completed 10000 read, 5466 write accesses @147507000
-system.cpu3: completed 10000 read, 5586 write accesses @147982000
-system.cpu5: completed 10000 read, 5427 write accesses @148047500
-system.cpu7: completed 10000 read, 5356 write accesses @148467500
-system.cpu6: completed 20000 read, 10673 write accesses @289538000
-system.cpu2: completed 20000 read, 10526 write accesses @290832000
-system.cpu1: completed 20000 read, 10766 write accesses @292890999
-system.cpu5: completed 20000 read, 10736 write accesses @293627000
-system.cpu7: completed 20000 read, 10730 write accesses @293693000
-system.cpu0: completed 20000 read, 10671 write accesses @294206500
-system.cpu4: completed 20000 read, 10944 write accesses @296769500
-system.cpu3: completed 20000 read, 10962 write accesses @297951000
-system.cpu2: completed 30000 read, 15840 write accesses @436954000
-system.cpu1: completed 30000 read, 16134 write accesses @439432500
-system.cpu6: completed 30000 read, 16128 write accesses @439710500
-system.cpu7: completed 30000 read, 16048 write accesses @440819000
-system.cpu5: completed 30000 read, 16126 write accesses @441698000
-system.cpu3: completed 30000 read, 16409 write accesses @444974000
-system.cpu4: completed 30000 read, 16439 write accesses @445869500
-system.cpu0: completed 30000 read, 16254 write accesses @446194000
-system.cpu2: completed 40000 read, 21231 write accesses @582932500
-system.cpu6: completed 40000 read, 21466 write accesses @586141500
-system.cpu1: completed 40000 read, 21414 write accesses @588066500
-system.cpu3: completed 40000 read, 21735 write accesses @588220000
-system.cpu5: completed 40000 read, 21572 write accesses @588767000
-system.cpu7: completed 40000 read, 21513 write accesses @590091000
-system.cpu0: completed 40000 read, 21682 write accesses @592843000
-system.cpu4: completed 40000 read, 21885 write accesses @593488000
-system.cpu2: completed 50000 read, 26639 write accesses @730512000
-system.cpu3: completed 50000 read, 26953 write accesses @733051500
-system.cpu6: completed 50000 read, 26889 write accesses @736295000
-system.cpu1: completed 50000 read, 26860 write accesses @736946500
-system.cpu4: completed 50000 read, 27157 write accesses @739104500
-system.cpu5: completed 50000 read, 27043 write accesses @739175000
-system.cpu7: completed 50000 read, 27030 write accesses @739274500
-system.cpu0: completed 50000 read, 27007 write accesses @740081999
-system.cpu2: completed 60000 read, 31935 write accesses @875520000
-system.cpu3: completed 60000 read, 32327 write accesses @878608000
-system.cpu1: completed 60000 read, 32037 write accesses @880758000
-system.cpu5: completed 60000 read, 32374 write accesses @883996500
-system.cpu4: completed 60000 read, 32578 write accesses @885209000
-system.cpu6: completed 60000 read, 32302 write accesses @886481999
-system.cpu0: completed 60000 read, 32356 write accesses @886645000
-system.cpu7: completed 60000 read, 32534 write accesses @888148500
-system.cpu3: completed 70000 read, 37577 write accesses @1026143000
-system.cpu2: completed 70000 read, 37542 write accesses @1027029999
-system.cpu1: completed 70000 read, 37457 write accesses @1029024000
-system.cpu5: completed 70000 read, 37722 write accesses @1029495500
-system.cpu6: completed 70000 read, 37640 write accesses @1032918500
-system.cpu0: completed 70000 read, 37692 write accesses @1034293500
-system.cpu7: completed 70000 read, 37955 write accesses @1034390500
-system.cpu4: completed 70000 read, 38136 write accesses @1036569000
-system.cpu3: completed 80000 read, 42898 write accesses @1173212500
-system.cpu2: completed 80000 read, 42932 write accesses @1173575000
-system.cpu1: completed 80000 read, 42886 write accesses @1177639500
-system.cpu5: completed 80000 read, 43232 write accesses @1178175000
-system.cpu0: completed 80000 read, 42958 write accesses @1178771500
-system.cpu6: completed 80000 read, 42919 write accesses @1180797000
-system.cpu7: completed 80000 read, 43430 write accesses @1183823000
-system.cpu4: completed 80000 read, 43550 write accesses @1185935999
-system.cpu2: completed 90000 read, 48239 write accesses @1319473000
-system.cpu3: completed 90000 read, 48329 write accesses @1322081500
-system.cpu1: completed 90000 read, 48223 write accesses @1323240500
-system.cpu5: completed 90000 read, 48632 write accesses @1326787000
-system.cpu0: completed 90000 read, 48351 write accesses @1327807500
-system.cpu6: completed 90000 read, 48287 write accesses @1329208000
-system.cpu7: completed 90000 read, 48796 write accesses @1329462500
-system.cpu4: completed 90000 read, 48969 write accesses @1334198500
-system.cpu2: completed 100000 read, 53603 write accesses @1466014000
+system.cpu4: completed 10000 read, 5317 write accesses @146612000
+system.cpu3: completed 10000 read, 5592 write accesses @148872500
+system.cpu7: completed 10000 read, 5446 write accesses @149754500
+system.cpu0: completed 10000 read, 5432 write accesses @150141500
+system.cpu1: completed 10000 read, 5693 write accesses @151929000
+system.cpu2: completed 10000 read, 5680 write accesses @152039000
+system.cpu6: completed 10000 read, 5624 write accesses @152462500
+system.cpu5: completed 10000 read, 5650 write accesses @153139000
+system.cpu4: completed 20000 read, 10841 write accesses @294897500
+system.cpu3: completed 20000 read, 11252 write accesses @295891500
+system.cpu0: completed 20000 read, 10771 write accesses @296321000
+system.cpu6: completed 20000 read, 11129 write accesses @300503000
+system.cpu1: completed 20000 read, 11154 write accesses @303003500
+system.cpu7: completed 20000 read, 11162 write accesses @303067000
+system.cpu5: completed 20000 read, 11275 write accesses @305007000
+system.cpu2: completed 20000 read, 11301 write accesses @305237000
+system.cpu4: completed 30000 read, 16293 write accesses @441647000
+system.cpu0: completed 30000 read, 16339 write accesses @446349998
+system.cpu6: completed 30000 read, 16630 write accesses @450155000
+system.cpu1: completed 30000 read, 16474 write accesses @451775000
+system.cpu3: completed 30000 read, 16954 write accesses @452288000
+system.cpu7: completed 30000 read, 16778 write accesses @453662000
+system.cpu5: completed 30000 read, 16839 write accesses @456398000
+system.cpu2: completed 30000 read, 16838 write accesses @457529500
+system.cpu4: completed 40000 read, 21515 write accesses @587133500
+system.cpu0: completed 40000 read, 21712 write accesses @594544000
+system.cpu6: completed 40000 read, 22199 write accesses @599911000
+system.cpu3: completed 40000 read, 22436 write accesses @600303500
+system.cpu1: completed 40000 read, 22001 write accesses @603916500
+system.cpu7: completed 40000 read, 22291 write accesses @604899500
+system.cpu5: completed 40000 read, 22433 write accesses @607477000
+system.cpu2: completed 40000 read, 22541 write accesses @610042000
+system.cpu4: completed 50000 read, 27094 write accesses @738435000
+system.cpu0: completed 50000 read, 27172 write accesses @744686500
+system.cpu3: completed 50000 read, 27887 write accesses @749000500
+system.cpu1: completed 50000 read, 27549 write accesses @751936500
+system.cpu6: completed 50000 read, 27775 write accesses @752183500
+system.cpu7: completed 50000 read, 27920 write accesses @756029000
+system.cpu5: completed 50000 read, 27984 write accesses @756496000
+system.cpu2: completed 50000 read, 27916 write accesses @758896000
+system.cpu4: completed 60000 read, 32601 write accesses @886900500
+system.cpu0: completed 60000 read, 32631 write accesses @892444000
+system.cpu1: completed 60000 read, 33102 write accesses @899938000
+system.cpu3: completed 60000 read, 33481 write accesses @900956500
+system.cpu6: completed 60000 read, 33392 write accesses @901773000
+system.cpu5: completed 60000 read, 33565 write accesses @904995500
+system.cpu2: completed 60000 read, 33466 write accesses @909744500
+system.cpu7: completed 60000 read, 33536 write accesses @910295999
+system.cpu4: completed 70000 read, 38175 write accesses @1036375499
+system.cpu0: completed 70000 read, 38106 write accesses @1040049000
+system.cpu6: completed 70000 read, 38841 write accesses @1048673000
+system.cpu1: completed 70000 read, 38668 write accesses @1049885000
+system.cpu3: completed 70000 read, 39114 write accesses @1053709500
+system.cpu5: completed 70000 read, 39200 write accesses @1055942500
+system.cpu2: completed 70000 read, 38856 write accesses @1057747499
+system.cpu7: completed 70000 read, 39064 write accesses @1059368500
+system.cpu4: completed 80000 read, 43619 write accesses @1185369000
+system.cpu0: completed 80000 read, 43549 write accesses @1189974500
+system.cpu6: completed 80000 read, 44374 write accesses @1198657499
+system.cpu1: completed 80000 read, 43973 write accesses @1199665500
+system.cpu3: completed 80000 read, 44602 write accesses @1199968000
+system.cpu5: completed 80000 read, 44843 write accesses @1207585500
+system.cpu2: completed 80000 read, 44389 write accesses @1209591000
+system.cpu7: completed 80000 read, 44629 write accesses @1211090500
+system.cpu4: completed 90000 read, 49142 write accesses @1333753500
+system.cpu0: completed 90000 read, 49249 write accesses @1339029000
+system.cpu1: completed 90000 read, 49469 write accesses @1348019000
+system.cpu6: completed 90000 read, 50013 write accesses @1351048500
+system.cpu3: completed 90000 read, 50231 write accesses @1351323000
+system.cpu5: completed 90000 read, 50311 write accesses @1355589000
+system.cpu7: completed 90000 read, 50146 write accesses @1357457500
+system.cpu2: completed 90000 read, 49997 write accesses @1360771999
+system.cpu4: completed 100000 read, 54692 write accesses @1486654500
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
index 62f705803..06da0f372 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
@@ -22,7 +22,7 @@ load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
-memories=system.funcmem system.physmem
+memories=system.physmem system.funcmem
num_work_ids=16
readfile=
symbolfile=
@@ -508,7 +508,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -566,10 +566,11 @@ sequential_access=false
size=65536
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=16
@@ -590,10 +591,11 @@ range=0:134217727
port=system.membus.master[0]
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=16
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
index 084f6f6ab..b2fb4093d 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
@@ -1,73 +1,73 @@
-system.cpu6: completed 10000 read, 5217 write accesses @68085999
-system.cpu4: completed 10000 read, 5435 write accesses @69661000
-system.cpu2: completed 10000 read, 5368 write accesses @70121500
-system.cpu3: completed 10000 read, 5457 write accesses @70317500
-system.cpu1: completed 10000 read, 5387 write accesses @70875500
-system.cpu7: completed 10000 read, 5470 write accesses @70949000
-system.cpu0: completed 10000 read, 5435 write accesses @71227500
-system.cpu5: completed 10000 read, 5514 write accesses @71894000
-system.cpu6: completed 20000 read, 10518 write accesses @132327500
-system.cpu4: completed 20000 read, 10839 write accesses @133525000
-system.cpu1: completed 20000 read, 10784 write accesses @134714500
-system.cpu7: completed 20000 read, 10701 write accesses @135318500
-system.cpu0: completed 20000 read, 10821 write accesses @135563500
-system.cpu2: completed 20000 read, 10843 write accesses @135684500
-system.cpu3: completed 20000 read, 10685 write accesses @135938500
-system.cpu5: completed 20000 read, 11031 write accesses @136425000
-system.cpu6: completed 30000 read, 16001 write accesses @197849500
-system.cpu4: completed 30000 read, 16254 write accesses @198725500
-system.cpu0: completed 30000 read, 16109 write accesses @199579499
-system.cpu1: completed 30000 read, 16209 write accesses @200016500
-system.cpu5: completed 30000 read, 16414 write accesses @200525000
-system.cpu3: completed 30000 read, 15978 write accesses @200724000
-system.cpu7: completed 30000 read, 16153 write accesses @201563500
-system.cpu2: completed 30000 read, 16316 write accesses @202401999
-system.cpu4: completed 40000 read, 21506 write accesses @263053500
-system.cpu6: completed 40000 read, 21338 write accesses @263431500
-system.cpu5: completed 40000 read, 21670 write accesses @263987000
-system.cpu3: completed 40000 read, 21219 write accesses @264608000
-system.cpu1: completed 40000 read, 21536 write accesses @265348500
-system.cpu0: completed 40000 read, 21604 write accesses @265426500
-system.cpu7: completed 40000 read, 21465 write accesses @265674000
-system.cpu2: completed 40000 read, 21690 write accesses @268754000
-system.cpu6: completed 50000 read, 26563 write accesses @327819000
-system.cpu4: completed 50000 read, 27066 write accesses @328101000
-system.cpu5: completed 50000 read, 26900 write accesses @328372000
-system.cpu3: completed 50000 read, 26596 write accesses @328811500
-system.cpu1: completed 50000 read, 26845 write accesses @328908500
-system.cpu7: completed 50000 read, 26873 write accesses @331316999
-system.cpu0: completed 50000 read, 26988 write accesses @331358000
-system.cpu2: completed 50000 read, 27102 write accesses @333876000
-system.cpu1: completed 60000 read, 32156 write accesses @392077000
-system.cpu6: completed 60000 read, 31998 write accesses @392784000
-system.cpu5: completed 60000 read, 32223 write accesses @393227500
-system.cpu4: completed 60000 read, 32446 write accesses @394175000
-system.cpu3: completed 60000 read, 32090 write accesses @394842000
-system.cpu0: completed 60000 read, 32282 write accesses @395716500
-system.cpu7: completed 60000 read, 32292 write accesses @397180000
-system.cpu2: completed 60000 read, 32266 write accesses @397288500
-system.cpu6: completed 70000 read, 37440 write accesses @457780500
-system.cpu1: completed 70000 read, 37577 write accesses @458242500
-system.cpu5: completed 70000 read, 37616 write accesses @458643500
-system.cpu4: completed 70000 read, 37952 write accesses @459569500
-system.cpu3: completed 70000 read, 37486 write accesses @460007500
-system.cpu0: completed 70000 read, 37804 write accesses @461418499
-system.cpu2: completed 70000 read, 37588 write accesses @461790000
-system.cpu7: completed 70000 read, 37743 write accesses @462130500
-system.cpu1: completed 80000 read, 42976 write accesses @523192500
-system.cpu5: completed 80000 read, 43028 write accesses @523895500
-system.cpu6: completed 80000 read, 42870 write accesses @524155000
-system.cpu4: completed 80000 read, 43341 write accesses @524226000
-system.cpu3: completed 80000 read, 42885 write accesses @524383000
-system.cpu2: completed 80000 read, 43005 write accesses @527239000
-system.cpu7: completed 80000 read, 43156 write accesses @528371000
-system.cpu0: completed 80000 read, 43239 write accesses @528519000
-system.cpu3: completed 90000 read, 48037 write accesses @586595000
-system.cpu1: completed 90000 read, 48299 write accesses @588010000
-system.cpu4: completed 90000 read, 48806 write accesses @589147500
-system.cpu6: completed 90000 read, 48454 write accesses @589844000
-system.cpu5: completed 90000 read, 48341 write accesses @590185000
-system.cpu2: completed 90000 read, 48395 write accesses @591584000
-system.cpu7: completed 90000 read, 48496 write accesses @592485000
-system.cpu0: completed 90000 read, 48680 write accesses @594831500
-system.cpu3: completed 100000 read, 53536 write accesses @652606500
+system.cpu1: completed 10000 read, 5362 write accesses @70749500
+system.cpu6: completed 10000 read, 5537 write accesses @71195000
+system.cpu7: completed 10000 read, 5519 write accesses @71360000
+system.cpu4: completed 10000 read, 5569 write accesses @71442000
+system.cpu3: completed 10000 read, 5551 write accesses @71947000
+system.cpu5: completed 10000 read, 5610 write accesses @72351000
+system.cpu2: completed 10000 read, 5548 write accesses @72366000
+system.cpu0: completed 10000 read, 5597 write accesses @72604000
+system.cpu1: completed 20000 read, 10810 write accesses @136799000
+system.cpu6: completed 20000 read, 11150 write accesses @137085000
+system.cpu4: completed 20000 read, 11041 write accesses @137243000
+system.cpu5: completed 20000 read, 11255 write accesses @138165500
+system.cpu7: completed 20000 read, 11207 write accesses @138180500
+system.cpu3: completed 20000 read, 11018 write accesses @138711500
+system.cpu2: completed 20000 read, 11094 write accesses @139138500
+system.cpu0: completed 20000 read, 11219 write accesses @140219500
+system.cpu5: completed 30000 read, 16778 write accesses @203366500
+system.cpu6: completed 30000 read, 16566 write accesses @203972500
+system.cpu4: completed 30000 read, 16724 write accesses @204003000
+system.cpu1: completed 30000 read, 16364 write accesses @204656500
+system.cpu2: completed 30000 read, 16663 write accesses @204765000
+system.cpu7: completed 30000 read, 16867 write accesses @205681500
+system.cpu3: completed 30000 read, 16606 write accesses @205970500
+system.cpu0: completed 30000 read, 16763 write accesses @207333500
+system.cpu5: completed 40000 read, 22274 write accesses @268156500
+system.cpu6: completed 40000 read, 22009 write accesses @269534000
+system.cpu2: completed 40000 read, 22255 write accesses @271458500
+system.cpu4: completed 40000 read, 22360 write accesses @272143500
+system.cpu0: completed 40000 read, 22178 write accesses @272544500
+system.cpu1: completed 40000 read, 22131 write accesses @272652000
+system.cpu3: completed 40000 read, 22246 write accesses @273210500
+system.cpu7: completed 40000 read, 22431 write accesses @273722500
+system.cpu5: completed 50000 read, 27739 write accesses @335077500
+system.cpu6: completed 50000 read, 27540 write accesses @335500500
+system.cpu4: completed 50000 read, 27805 write accesses @337842000
+system.cpu7: completed 50000 read, 27755 write accesses @337879500
+system.cpu2: completed 50000 read, 27750 write accesses @338436000
+system.cpu0: completed 50000 read, 27692 write accesses @339374000
+system.cpu1: completed 50000 read, 27828 write accesses @340225500
+system.cpu3: completed 50000 read, 27884 write accesses @341199000
+system.cpu5: completed 60000 read, 33220 write accesses @401069000
+system.cpu6: completed 60000 read, 33064 write accesses @401171000
+system.cpu7: completed 60000 read, 33318 write accesses @402700500
+system.cpu4: completed 60000 read, 33407 write accesses @404241000
+system.cpu2: completed 60000 read, 33248 write accesses @404642000
+system.cpu0: completed 60000 read, 33222 write accesses @405992500
+system.cpu1: completed 60000 read, 33452 write accesses @407711000
+system.cpu3: completed 60000 read, 33293 write accesses @408190000
+system.cpu6: completed 70000 read, 38545 write accesses @467631000
+system.cpu5: completed 70000 read, 38773 write accesses @467786500
+system.cpu7: completed 70000 read, 38817 write accesses @468768499
+system.cpu2: completed 70000 read, 38804 write accesses @470615500
+system.cpu4: completed 70000 read, 38942 write accesses @471024500
+system.cpu1: completed 70000 read, 38924 write accesses @472741500
+system.cpu0: completed 70000 read, 38792 write accesses @473888500
+system.cpu3: completed 70000 read, 38873 write accesses @474437500
+system.cpu5: completed 80000 read, 44156 write accesses @533178500
+system.cpu6: completed 80000 read, 44068 write accesses @534028500
+system.cpu7: completed 80000 read, 44398 write accesses @535850500
+system.cpu2: completed 80000 read, 44302 write accesses @537573000
+system.cpu4: completed 80000 read, 44462 write accesses @538315000
+system.cpu0: completed 80000 read, 44312 write accesses @540158500
+system.cpu1: completed 80000 read, 44676 write accesses @540667000
+system.cpu3: completed 80000 read, 44446 write accesses @541285000
+system.cpu5: completed 90000 read, 49777 write accesses @600496000
+system.cpu6: completed 90000 read, 49628 write accesses @600631500
+system.cpu7: completed 90000 read, 49999 write accesses @603063500
+system.cpu4: completed 90000 read, 49890 write accesses @603847000
+system.cpu2: completed 90000 read, 50013 write accesses @605897999
+system.cpu1: completed 90000 read, 50188 write accesses @606811500
+system.cpu3: completed 90000 read, 49928 write accesses @606922500
+system.cpu0: completed 90000 read, 49837 write accesses @607047500
+system.cpu6: completed 100000 read, 55113 write accesses @666669000
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
index a7dfb0cb5..b1d661d27 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
@@ -67,7 +67,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -106,8 +106,33 @@ slave=system.cpu.port
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -116,6 +141,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -129,19 +155,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
index bda575e80..c210da503 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
@@ -67,7 +67,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1