diff options
Diffstat (limited to 'tests/quick/se')
| -rw-r--r-- | tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt | 2847 | ||||
| -rw-r--r-- | tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt | 24 |
2 files changed, 1435 insertions, 1436 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 159c48ed1..08d964bc4 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,634 +1,633 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000759 # Number of seconds simulated -sim_ticks 758619000 # Number of ticks simulated -final_tick 758619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000758 # Number of seconds simulated +sim_ticks 758227000 # Number of ticks simulated +final_tick 758227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 45315591 # Simulator tick rate (ticks/s) -host_mem_usage 399988 # Number of bytes of host memory used -host_seconds 16.74 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 93443 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 93419 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 89535 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 90172 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 93283 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 92172 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 94553 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 91950 # Number of bytes read from this memory -system.physmem.bytes_read::total 738527 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 485568 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5315 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5220 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5162 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5331 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5296 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5419 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5320 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5436 # Number of bytes written to this memory -system.physmem.bytes_written::total 528067 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11039 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11015 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11163 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11194 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11154 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 88997 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7587 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5315 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5220 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5162 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5331 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5296 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5419 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5320 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5436 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50086 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 123175138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 123143502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 118023672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 118863356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 122964228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 121499725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 124638323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 121207088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 973515032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 640068335 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7006152 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6880924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 6804470 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 7027243 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 6981106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 7143243 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 7012743 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 7165652 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 696089869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 640068335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 130181290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 130024426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 124828142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 125890599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 129945335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 128642968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 131651066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 128372740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1669604900 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 15559 # number of replacements -system.l2c.tagsinuse 800.707629 # Cycle average of tags in use -system.l2c.total_refs 151038 # Total number of references to valid blocks. -system.l2c.sampled_refs 16357 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.233845 # Average number of references to valid blocks. +host_tick_rate 200763174 # Simulator tick rate (ticks/s) +host_mem_usage 353776 # Number of bytes of host memory used +host_seconds 3.78 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 94296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 93084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 90684 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 91125 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 90329 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 98961 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 91564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 94442 # Number of bytes read from this memory +system.physmem.bytes_read::total 744485 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 495744 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5338 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5288 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5371 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5302 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5445 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5231 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5370 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5430 # Number of bytes written to this memory +system.physmem.bytes_written::total 538519 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10932 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11202 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11345 # Number of read requests responded to by this memory +system.physmem.num_reads::total 89033 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 7746 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5338 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5288 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5371 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5302 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5445 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5231 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5370 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5430 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50521 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 124363812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 122765346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 119600067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 120181687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 119131869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 130516323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 120760669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 124556366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 981876140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 653820030 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7040108 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6974165 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 7083631 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 6992629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 7181227 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 6898989 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7082312 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7161444 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 710234534 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 653820030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 131403920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 129739511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 126683698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 127174316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 126313096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 137415312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 127842981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 131717810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1692110674 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 15709 # number of replacements +system.l2c.tagsinuse 802.621152 # Cycle average of tags in use +system.l2c.total_refs 152986 # Total number of references to valid blocks. +system.l2c.sampled_refs 16508 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.267386 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 736.955948 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.896049 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.875266 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 7.499139 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 7.819632 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 8.127236 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 8.346952 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 8.379667 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 7.807741 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.719684 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.007711 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007691 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.007323 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007636 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007937 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.008151 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.008183 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.007625 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.781941 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10425 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10868 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10852 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10879 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10927 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10945 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10774 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10623 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86293 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 76698 # number of Writeback hits -system.l2c.Writeback_hits::total 76698 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 360 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 388 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 372 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 365 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 360 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 369 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2938 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2007 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 2095 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1980 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2070 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 2022 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2061 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1961 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2103 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16299 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12432 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12963 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12832 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12949 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12949 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 13006 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12735 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12726 # number of demand (read+write) hits -system.l2c.demand_hits::total 102592 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12432 # number of overall hits -system.l2c.overall_hits::cpu1 12963 # number of overall hits -system.l2c.overall_hits::cpu2 12832 # number of overall hits -system.l2c.overall_hits::cpu3 12949 # number of overall hits -system.l2c.overall_hits::cpu4 12949 # number of overall hits -system.l2c.overall_hits::cpu5 13006 # number of overall hits -system.l2c.overall_hits::cpu6 12735 # number of overall hits -system.l2c.overall_hits::cpu7 12726 # number of overall hits -system.l2c.overall_hits::total 102592 # number of overall hits -system.l2c.ReadReq_misses::cpu0 852 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 872 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 800 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 819 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 876 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 871 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 869 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 848 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6807 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1921 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1804 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1923 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1810 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1803 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1840 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1866 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1868 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 14835 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4250 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4373 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4213 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4295 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4281 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4251 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4294 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4308 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34265 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5102 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5245 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5013 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5114 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5157 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5122 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5163 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5156 # number of demand (read+write) misses -system.l2c.demand_misses::total 41072 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5102 # number of overall misses -system.l2c.overall_misses::cpu1 5245 # number of overall misses -system.l2c.overall_misses::cpu2 5013 # number of overall misses -system.l2c.overall_misses::cpu3 5114 # number of overall misses -system.l2c.overall_misses::cpu4 5157 # number of overall misses -system.l2c.overall_misses::cpu5 5122 # number of overall misses -system.l2c.overall_misses::cpu6 5163 # number of overall misses -system.l2c.overall_misses::cpu7 5156 # number of overall misses -system.l2c.overall_misses::total 41072 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 50457953 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 52232944 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 47803944 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 49059449 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 51558931 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 52310430 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 51043945 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 50050941 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 404518537 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 54750899 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 49983404 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 56149902 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 53493906 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 50935912 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 51769923 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 53458903 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 54181398 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 424724247 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 228244633 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 234983117 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 226986626 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 231330611 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 230611636 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 229068598 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 231365116 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 232157113 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1844747450 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 278702586 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 287216061 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 274790570 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 280390060 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 282170567 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 281379028 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 282409061 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 282208054 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2249265987 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 278702586 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 287216061 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 274790570 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 280390060 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 93100 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 76698 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 76698 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2283 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2164 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2311 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2182 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2165 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2205 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2226 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2237 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 17773 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6257 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6468 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6193 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6365 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6303 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6312 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6255 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6411 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50564 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17534 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18208 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17845 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18063 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18106 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18128 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17898 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17882 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143664 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17534 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18208 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17845 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18063 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18106 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 18128 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17898 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17882 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143664 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.075552 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.074276 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.068658 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.070012 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.074218 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.073714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.074637 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.073926 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.073115 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.841437 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.833641 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.832107 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.829514 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.832794 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.834467 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.838275 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.835047 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.834693 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.679239 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.676098 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.680284 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.674784 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.679200 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.673479 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.686491 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.671970 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.677656 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.290978 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.288060 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.280919 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.283120 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.284823 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.282546 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.288468 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.288335 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.285889 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.290978 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.288060 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.280919 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.283120 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.284823 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.282546 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.288468 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.288335 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.285889 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 59222.949531 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 59900.165138 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 59754.930000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 59901.647131 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 58857.227169 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 60057.898967 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 58738.716916 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 59022.336085 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 59426.845453 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28501.248829 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 27706.986696 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29199.117005 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 29554.644199 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28250.644481 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28135.827717 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28648.929796 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29005.031049 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28629.878463 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53704.619529 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53734.991310 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53877.670544 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53860.444936 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53868.637234 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 53885.814632 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53881.023754 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53889.766249 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53837.660878 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 54626.143865 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54759.973499 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54815.593457 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54827.935080 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54716.030056 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 54935.382273 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54698.636645 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54733.912723 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54763.975141 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 54626.143865 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54759.973499 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54815.593457 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54827.935080 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54716.030056 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 54935.382273 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54698.636645 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54733.912723 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54763.975141 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 10793 # number of cycles access was blocked +system.l2c.occ_blocks::writebacks 738.344301 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 7.856749 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 7.750709 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 7.581062 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 8.075895 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 7.623690 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 8.411297 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 8.326520 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 8.650930 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.721039 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.007673 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.007569 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.007403 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.007887 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.007445 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.008214 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.008131 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.008448 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783810 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 11060 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10905 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10917 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10908 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 11025 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10769 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 11003 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 11044 # number of ReadReq hits +system.l2c.ReadReq_hits::total 87631 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 77283 # number of Writeback hits +system.l2c.Writeback_hits::total 77283 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 381 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 372 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 389 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 412 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 335 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 347 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 375 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 371 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2982 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 2017 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 2086 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1996 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 2001 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 2062 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1995 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 2076 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 2009 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16242 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 13077 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12991 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12913 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12909 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 13087 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12764 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 13079 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 13053 # number of demand (read+write) hits +system.l2c.demand_hits::total 103873 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 13077 # number of overall hits +system.l2c.overall_hits::cpu1 12991 # number of overall hits +system.l2c.overall_hits::cpu2 12913 # number of overall hits +system.l2c.overall_hits::cpu3 12909 # number of overall hits +system.l2c.overall_hits::cpu4 13087 # number of overall hits +system.l2c.overall_hits::cpu5 12764 # number of overall hits +system.l2c.overall_hits::cpu6 13079 # number of overall hits +system.l2c.overall_hits::cpu7 13053 # number of overall hits +system.l2c.overall_hits::total 103873 # number of overall hits +system.l2c.ReadReq_misses::cpu0 831 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 825 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 807 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 851 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 828 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 911 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 848 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 890 # number of ReadReq misses +system.l2c.ReadReq_misses::total 6791 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1940 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1902 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1837 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1834 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1940 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1893 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1907 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1914 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15167 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4262 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4280 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4275 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4377 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4319 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4433 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4324 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34643 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5093 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5105 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5180 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5126 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5205 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5230 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5281 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5214 # number of demand (read+write) misses +system.l2c.demand_misses::total 41434 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5093 # number of overall misses +system.l2c.overall_misses::cpu1 5105 # number of overall misses +system.l2c.overall_misses::cpu2 5180 # number of overall misses +system.l2c.overall_misses::cpu3 5126 # number of overall misses +system.l2c.overall_misses::cpu4 5205 # number of overall misses +system.l2c.overall_misses::cpu5 5230 # number of overall misses +system.l2c.overall_misses::cpu6 5281 # number of overall misses +system.l2c.overall_misses::cpu7 5214 # number of overall misses +system.l2c.overall_misses::total 41434 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 50386435 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 49587933 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 48886937 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 50664930 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 50580935 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 54458446 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 51430439 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 53097926 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 409093981 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 55854416 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 53852396 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 53210404 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 50920923 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 55308908 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 55911401 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 54499902 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 55745405 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 435303755 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 229815657 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 230400614 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 235881114 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 230703609 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 235441620 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 233239630 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 238696088 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 232987140 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1867165472 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 280202092 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 279988547 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 284768051 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 281368539 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 286022555 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 287698076 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 290126527 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 286085066 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2276259453 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 280202092 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 279988547 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 284768051 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 281368539 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 286022555 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 287698076 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 290126527 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 286085066 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2276259453 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11891 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11730 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11724 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11759 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11853 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11680 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11851 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11934 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 94422 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 77283 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77283 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2321 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2274 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2226 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2246 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2275 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2240 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2282 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2285 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18149 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6279 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6366 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6369 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6276 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6439 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6314 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6509 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6333 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50885 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18096 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18093 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18035 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18292 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17994 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18360 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18267 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 145307 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 18170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18096 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18093 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18035 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18292 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17994 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18360 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18267 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 145307 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.069885 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.070332 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.068833 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.072370 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.069856 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.077997 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.071555 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.074577 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.071922 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.835847 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.836412 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.825247 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.816563 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.852747 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.845089 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.835670 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.837637 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.835693 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.678771 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.672322 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.686607 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.681166 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.679764 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.684035 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.681057 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.682773 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.680810 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.280297 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.282107 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.286299 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.284225 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.284551 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.290652 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.287636 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.285433 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.285148 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.280297 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.282107 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.286299 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.284225 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.284551 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.290652 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.287636 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.285433 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.285148 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 60633.495788 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 60106.585455 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 60578.608426 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 59535.757932 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61088.085749 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 59778.755214 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 60649.102594 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 59660.591011 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 60240.609778 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28790.936082 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28313.562566 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 28965.924878 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 27764.952563 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28509.746392 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 29535.869519 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28578.868380 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29125.080982 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28700.715699 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 53922.021821 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 53831.919159 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 53940.341642 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 53965.756491 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 53790.637423 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54003.155823 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 53845.271374 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 53882.317299 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53897.337759 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55017.100334 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 54845.944564 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 54974.527220 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 54890.468006 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 54951.499520 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55009.192352 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 54937.800985 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 54868.635596 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 54936.995052 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55017.100334 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 54845.944564 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 54974.527220 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 54890.468006 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 54951.499520 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55009.192352 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 54937.800985 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 54868.635596 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 54936.995052 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 12946 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1480 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1808 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.292568 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.160398 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7587 # number of writebacks -system.l2c.writebacks::total 7587 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 7746 # number of writebacks +system.l2c.writebacks::total 7746 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu0 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu3 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu6 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 32 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 13 # number of demand (read+write) MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 29 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 8 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 13 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 92 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 845 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 865 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 794 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 809 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 871 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 865 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 859 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 839 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6747 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1921 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1804 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1923 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1809 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1803 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1840 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1865 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1868 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 14833 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4243 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4367 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4211 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4291 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4278 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4245 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4291 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4307 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34233 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5088 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5232 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5005 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5100 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5149 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5110 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5150 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5146 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40980 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5088 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5232 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5005 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5100 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5149 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5110 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5150 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5146 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40980 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 39952953 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 41536444 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 37955945 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 38925950 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 40835431 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 41565931 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 40269445 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 39637942 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 320680041 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78868808 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 73978329 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 78794825 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 74230834 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 74073835 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 75455362 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 76452812 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 76637320 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 608492125 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 176592133 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 181884117 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 175861127 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 179102612 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 178683137 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 177427598 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 179259117 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 179911613 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1428721454 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 216545086 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 223420561 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 213817072 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 218028562 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 219518568 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 218993529 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 219528562 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 219549555 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1749401495 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 216545086 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 223420561 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 213817072 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 218028562 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 219518568 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 218993529 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 219528562 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 219549555 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1749401495 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 402081632 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 400575089 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 409123618 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 408517090 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 408283130 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 406615614 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 405150633 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 405778615 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3246125421 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 225621486 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 222590493 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 219789492 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 227766486 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 225717983 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 229461987 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 226436485 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 231064489 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1808448901 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 627703118 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 623165582 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 628913110 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 636283576 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 634001113 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 636077601 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 631587118 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 636843104 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5054574322 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.074931 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.073680 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068143 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.069157 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.073795 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.073206 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.073778 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.073141 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.072470 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.841437 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.833641 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.832107 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.829056 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.832794 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.834467 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.837826 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.835047 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.834581 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.678121 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.675170 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.679961 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.674156 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.678724 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.672529 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.686011 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.671814 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.677023 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.290179 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.287346 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.280471 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.282345 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.284381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.281884 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.287742 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.287775 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.285249 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.290179 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.287346 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.280471 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.282345 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.284381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.281884 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.287742 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.287775 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.285249 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 47281.601183 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48019.010405 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 47803.457179 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 48116.131026 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46883.388060 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48053.099422 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46879.447031 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47244.269368 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 47529.278346 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41056.120770 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41007.942905 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40974.947998 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41034.181316 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41083.657793 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41008.348913 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40993.464879 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41026.402570 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41022.862873 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41619.640113 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41649.671857 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41762.319402 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41739.131205 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41767.914212 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41796.842874 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41775.604055 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41771.909218 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41735.210294 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42559.961871 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42702.706613 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42720.693706 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42750.698431 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 42633.242960 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42855.876517 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42626.905243 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42664.118733 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42689.153123 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42559.961871 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42702.706613 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42720.693706 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42750.698431 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 42633.242960 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42855.876517 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42626.905243 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42664.118733 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42689.153123 # average overall mshr miss latency +system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 828 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 815 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 804 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 844 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 824 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 909 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 843 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 883 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 6750 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1940 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1901 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1837 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1834 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1940 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1892 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1907 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1914 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15165 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4255 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4276 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4373 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4271 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4372 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4316 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4430 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4321 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34614 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5083 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5091 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5177 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5115 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5196 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5225 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5273 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5204 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 41364 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5083 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5091 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5177 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5115 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5196 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5225 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5273 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5204 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 41364 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 40211435 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 39357435 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 39064937 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 40158430 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 40512435 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 43385946 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 40969439 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 42146427 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 325806484 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 79643349 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 78062835 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 75255324 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 75287345 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 79635834 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 77713835 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 78284820 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 78593341 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 622476683 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 178045657 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 178454114 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 182867114 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 178794609 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 182240620 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 180819630 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 184924089 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 180516140 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1446661973 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 218257092 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 217811549 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 221932051 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 218953039 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 222753055 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 224205576 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 225893528 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 222662567 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1772468457 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 218257092 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 217811549 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 221932051 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 218953039 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 222753055 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 224205576 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 225893528 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 222662567 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1772468457 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 410453631 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 397457157 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 406979111 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 406829637 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 405432120 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 405171118 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 400882109 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 414057617 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3247262500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 226073488 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 225167477 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 228704981 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 225137481 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 230851979 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 222187990 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 228117990 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 230091986 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1816333372 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 636527119 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 622624634 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 635684092 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 631967118 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 636284099 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 627359108 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 629000099 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 644149603 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5063595872 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.069632 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.069480 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068577 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.071775 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.069518 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.077825 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.071133 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.073990 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.071488 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.835847 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.835972 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.825247 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.816563 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.852747 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.844643 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.835670 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.837637 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.835583 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.677656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.671693 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.686607 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.680529 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.678987 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.683560 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.680596 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.682299 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.680240 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.279747 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.281333 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.286133 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.283615 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.284059 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.290375 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.287200 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.284885 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.284666 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.279747 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.281333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.286133 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.283615 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.284059 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.290375 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.287200 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.284885 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.284666 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48564.535024 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48291.331288 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 48588.230100 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 47581.078199 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49165.576456 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 47729.313531 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 48599.571767 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47730.947905 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 48267.627259 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41053.272680 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41064.089953 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40966.425694 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41050.896947 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41049.398969 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41074.965645 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41051.295228 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41062.351620 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41046.929311 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41843.867685 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41733.890084 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41817.313972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41862.469913 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41683.581885 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41895.187674 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41743.586682 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41776.473039 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41794.128763 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42938.637025 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42783.647417 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 42868.852811 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 42806.068231 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42870.102964 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42910.158086 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42839.660156 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42786.811491 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42850.509066 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42938.637025 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42783.647417 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 42868.852811 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 42806.068231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42870.102964 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42910.158086 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42839.660156 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42786.811491 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42850.509066 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -657,114 +656,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 97622 # number of read accesses completed -system.cpu0.num_writes 53016 # number of write accesses completed +system.cpu0.num_reads 98877 # number of read accesses completed +system.cpu0.num_writes 53303 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 21387 # number of replacements -system.cpu0.l1c.tagsinuse 393.959213 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13124 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 21798 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.602074 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 22594 # number of replacements +system.cpu0.l1c.tagsinuse 395.326045 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13097 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 23010 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.569187 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 393.959213 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.769452 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.769452 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8513 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8513 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1098 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1098 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9611 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9611 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9611 # number of overall hits -system.cpu0.l1c.overall_hits::total 9611 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35379 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35379 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 22892 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 22892 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 58271 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 58271 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 58271 # number of overall misses -system.cpu0.l1c.overall_misses::total 58271 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1332854037 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1332854037 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1090035309 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1090035309 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 2422889346 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 2422889346 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 2422889346 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 2422889346 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 43892 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 43892 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 23990 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 23990 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 67882 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 67882 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 67882 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 67882 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806047 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.806047 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954231 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954231 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858416 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858416 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858416 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858416 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37673.592724 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 37673.592724 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 47616.429713 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 47616.429713 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 41579.676786 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 41579.676786 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 41579.676786 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 41579.676786 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1432667 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 395.326045 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.772121 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.772121 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8525 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8525 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1042 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1042 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9567 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9567 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9567 # number of overall hits +system.cpu0.l1c.overall_hits::total 9567 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36170 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36170 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23033 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23033 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 59203 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 59203 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 59203 # number of overall misses +system.cpu0.l1c.overall_misses::total 59203 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1338428684 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1338428684 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1081120140 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1081120140 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 2419548824 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 2419548824 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 2419548824 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 2419548824 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44695 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44695 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24075 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24075 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68770 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68770 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68770 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68770 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809263 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.809263 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956719 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.956719 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.860884 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.860884 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.860884 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.860884 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37003.834227 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 37003.834227 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 46937.877827 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 46937.877827 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 40868.686114 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 40868.686114 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 40868.686114 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 40868.686114 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1431079 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 66221 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 67309 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.634633 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.261332 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9284 # number of writebacks -system.cpu0.l1c.writebacks::total 9284 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35379 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35379 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 22892 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 22892 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 58271 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 58271 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 58271 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 58271 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1262100037 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1262100037 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1044251309 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1044251309 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2306351346 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 2306351346 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2306351346 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 2306351346 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 709848172 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 709848172 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 441878494 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 441878494 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1151726666 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1151726666 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806047 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806047 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954231 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954231 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858416 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858416 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858416 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858416 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35673.705786 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35673.705786 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 45616.429713 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 45616.429713 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 39579.745431 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 39579.745431 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 39579.745431 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 39579.745431 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9829 # number of writebacks +system.cpu0.l1c.writebacks::total 9829 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36170 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36170 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23033 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 59203 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 59203 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 59203 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 59203 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1266094684 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1266094684 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1035054140 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1035054140 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2301148824 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 2301148824 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2301148824 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 2301148824 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 713940998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 713940998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 425679500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 425679500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1139620498 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1139620498 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809263 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809263 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956719 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956719 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860884 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.860884 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860884 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.860884 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35004.000111 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35004.000111 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 44937.877827 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 44937.877827 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 38868.787460 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 38868.787460 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 38868.787460 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 38868.787460 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -772,114 +771,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98743 # number of read accesses completed -system.cpu1.num_writes 53079 # number of write accesses completed +system.cpu1.num_reads 98330 # number of read accesses completed +system.cpu1.num_writes 53283 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 22269 # number of replacements -system.cpu1.l1c.tagsinuse 395.693103 # Cycle average of tags in use -system.cpu1.l1c.total_refs 13156 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22645 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.580967 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 22413 # number of replacements +system.cpu1.l1c.tagsinuse 397.274781 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13337 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22810 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.584700 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 395.693103 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.772838 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.772838 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8677 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8677 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1112 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1112 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9789 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9789 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9789 # number of overall hits -system.cpu1.l1c.overall_hits::total 9789 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 35979 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 35979 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 22841 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 22841 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 58820 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 58820 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 58820 # number of overall misses -system.cpu1.l1c.overall_misses::total 58820 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1346712982 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1346712982 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1084415887 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1084415887 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 2431128869 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 2431128869 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 2431128869 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 2431128869 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44656 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44656 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 23953 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 23953 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 68609 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 68609 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 68609 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 68609 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805692 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805692 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953576 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.953576 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857322 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857322 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857322 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857322 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37430.528419 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 37430.528419 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47476.725494 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 47476.725494 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 41331.670673 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 41331.670673 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 41331.670673 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 41331.670673 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1432282 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 397.274781 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.775927 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.775927 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8758 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8758 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1087 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1087 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9845 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9845 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9845 # number of overall hits +system.cpu1.l1c.overall_hits::total 9845 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35763 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35763 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23060 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23060 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58823 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58823 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58823 # number of overall misses +system.cpu1.l1c.overall_misses::total 58823 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1339256827 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1339256827 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 1098702208 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 1098702208 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 2437959035 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 2437959035 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 2437959035 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 2437959035 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44521 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44521 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24147 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24147 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68668 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68668 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68668 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68668 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.803284 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.803284 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954984 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954984 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.856629 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.856629 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.856629 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.856629 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37448.111931 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 37448.111931 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47645.368951 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 47645.368951 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 41445.676606 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 41445.676606 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 41445.676606 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 41445.676606 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1431601 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 66708 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66652 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.470918 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.478740 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9759 # number of writebacks -system.cpu1.l1c.writebacks::total 9759 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35979 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 35979 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22841 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 22841 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 58820 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 58820 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 58820 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 58820 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1274756982 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1274756982 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1038739887 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1038739887 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2313496869 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 2313496869 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2313496869 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 2313496869 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 702867762 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 702867762 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 426288670 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 426288670 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1129156432 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1129156432 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805692 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805692 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953576 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953576 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857322 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857322 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857322 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857322 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35430.584007 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35430.584007 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45476.988179 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45476.988179 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39331.806681 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39331.806681 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39331.806681 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39331.806681 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9847 # number of writebacks +system.cpu1.l1c.writebacks::total 9847 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35763 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35763 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23060 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23060 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58823 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58823 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58823 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58823 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1267732827 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1267732827 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1052584208 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1052584208 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2320317035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 2320317035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2320317035 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 2320317035 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 694424746 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 694424746 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 428704098 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 428704098 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1123128844 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1123128844 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.803284 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.803284 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954984 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954984 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.856629 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.856629 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.856629 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.856629 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35448.167855 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35448.167855 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45645.455681 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45645.455681 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39445.744607 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39445.744607 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39445.744607 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39445.744607 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -887,114 +886,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 98534 # number of read accesses completed -system.cpu2.num_writes 52787 # number of write accesses completed +system.cpu2.num_reads 98918 # number of read accesses completed +system.cpu2.num_writes 53026 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 21873 # number of replacements -system.cpu2.l1c.tagsinuse 394.149978 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13285 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22270 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.596542 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 22091 # number of replacements +system.cpu2.l1c.tagsinuse 394.122068 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13053 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 22474 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.580804 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 394.149978 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.769824 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.769824 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8620 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8620 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1112 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1112 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9732 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9732 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9732 # number of overall hits -system.cpu2.l1c.overall_hits::total 9732 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 35901 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 35901 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22666 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22666 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 58567 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 58567 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 58567 # number of overall misses -system.cpu2.l1c.overall_misses::total 58567 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1333102057 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1333102057 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1080309021 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1080309021 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 2413411078 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 2413411078 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 2413411078 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 2413411078 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44521 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44521 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 23778 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 23778 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68299 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68299 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68299 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68299 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806384 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806384 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953234 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953234 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.857509 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.857509 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.857509 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.857509 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37132.727696 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 37132.727696 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47662.093929 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 47662.093929 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 41207.695084 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 41207.695084 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 41207.695084 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 41207.695084 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1432337 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 394.122068 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.769770 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.769770 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1062 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1062 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9719 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9719 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9719 # number of overall hits +system.cpu2.l1c.overall_hits::total 9719 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 35792 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 35792 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22782 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22782 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 58574 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 58574 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 58574 # number of overall misses +system.cpu2.l1c.overall_misses::total 58574 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1334540137 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1334540137 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1086319531 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1086319531 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 2420859668 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 2420859668 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 2420859668 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 2420859668 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44449 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44449 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 23844 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 23844 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68293 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68293 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68293 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68293 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805237 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805237 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955460 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955460 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.857687 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.857687 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.857687 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.857687 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37285.989523 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 37285.989523 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47683.238127 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 47683.238127 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 41329.935944 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 41329.935944 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 41329.935944 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 41329.935944 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1431481 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 66669 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66558 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.484303 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.507272 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9470 # number of writebacks -system.cpu2.l1c.writebacks::total 9470 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35901 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 35901 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22666 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22666 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 58567 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 58567 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 58567 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 58567 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1261304057 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1261304057 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1034981021 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1034981021 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2296285078 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 2296285078 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2296285078 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 2296285078 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 719957534 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 719957534 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 417914602 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 417914602 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1137872136 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1137872136 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806384 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806384 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953234 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953234 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857509 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.857509 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857509 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.857509 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35132.839113 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35132.839113 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45662.270405 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45662.270405 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39207.831680 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39207.831680 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39207.831680 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39207.831680 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9590 # number of writebacks +system.cpu2.l1c.writebacks::total 9590 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35792 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 35792 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22782 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22782 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 58574 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 58574 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 58574 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 58574 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1262960137 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1262960137 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1040755531 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1040755531 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2303715668 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 2303715668 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2303715668 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 2303715668 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 710805276 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 710805276 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 431026471 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 431026471 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1141831747 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1141831747 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805237 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805237 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955460 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955460 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857687 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.857687 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857687 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.857687 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35286.101280 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35286.101280 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45683.238127 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45683.238127 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39330.004234 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39330.004234 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39330.004234 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39330.004234 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1002,114 +1001,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99583 # number of read accesses completed -system.cpu3.num_writes 53448 # number of write accesses completed +system.cpu3.num_reads 98879 # number of read accesses completed +system.cpu3.num_writes 53514 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 22221 # number of replacements -system.cpu3.l1c.tagsinuse 395.683952 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13227 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22614 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.584903 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 22321 # number of replacements +system.cpu3.l1c.tagsinuse 395.059941 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13052 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22702 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.574927 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 395.683952 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.772820 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.772820 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8699 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8699 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1092 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1092 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9791 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9791 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9791 # number of overall hits -system.cpu3.l1c.overall_hits::total 9791 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35935 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35935 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23086 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23086 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 59021 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 59021 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 59021 # number of overall misses -system.cpu3.l1c.overall_misses::total 59021 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1329205475 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1329205475 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1090244238 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1090244238 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 2419449713 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 2419449713 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 2419449713 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 2419449713 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44634 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44634 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24178 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24178 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68812 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68812 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68812 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68812 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805104 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.805104 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954835 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954835 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.857714 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.857714 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.857714 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.857714 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 36989.160289 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 36989.160289 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 47225.341679 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 47225.341679 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 40993.031514 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 40993.031514 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 40993.031514 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 40993.031514 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1431757 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 395.059941 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.771601 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.771601 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8562 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8562 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1034 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1034 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9596 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9596 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9596 # number of overall hits +system.cpu3.l1c.overall_hits::total 9596 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35946 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35946 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 22965 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 22965 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 58911 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 58911 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 58911 # number of overall misses +system.cpu3.l1c.overall_misses::total 58911 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1334193508 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1334193508 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 1085703243 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 1085703243 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 2419896751 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 2419896751 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 2419896751 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 2419896751 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44508 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44508 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 23999 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 23999 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68507 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68507 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68507 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68507 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807630 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.807630 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956915 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.956915 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.859927 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.859927 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.859927 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.859927 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 37116.605686 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 37116.605686 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 47276.431221 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 47276.431221 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 41077.163026 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 41077.163026 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 41077.163026 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 41077.163026 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1431288 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 67125 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66945 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.329713 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.380058 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9875 # number of writebacks -system.cpu3.l1c.writebacks::total 9875 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35935 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35935 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23086 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23086 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 59021 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 59021 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 59021 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 59021 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1257339475 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1257339475 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1044074238 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1044074238 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2301413713 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 2301413713 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2301413713 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 2301413713 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 714868620 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 714868620 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 436247033 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 436247033 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1151115653 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1151115653 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805104 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805104 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954835 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954835 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857714 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.857714 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857714 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.857714 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 34989.271602 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 34989.271602 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45225.428312 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45225.428312 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 38993.133173 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 38993.133173 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 38993.133173 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 38993.133173 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9751 # number of writebacks +system.cpu3.l1c.writebacks::total 9751 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35946 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35946 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22965 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 22965 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 58911 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 58911 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 58911 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 58911 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1262305508 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1262305508 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1039775243 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1039775243 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2302080751 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 2302080751 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2302080751 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 2302080751 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 712475632 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 712475632 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 424398019 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 424398019 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1136873651 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1136873651 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807630 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807630 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956915 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956915 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859927 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.859927 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859927 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.859927 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 35116.716964 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 35116.716964 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45276.518310 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45276.518310 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 39077.264874 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 39077.264874 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 39077.264874 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 39077.264874 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1117,114 +1116,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 53418 # number of write accesses completed +system.cpu4.num_reads 99302 # number of read accesses completed +system.cpu4.num_writes 53818 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22068 # number of replacements -system.cpu4.l1c.tagsinuse 394.143159 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13375 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22471 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.595212 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22353 # number of replacements +system.cpu4.l1c.tagsinuse 396.021323 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13287 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22757 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.583864 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 394.143159 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.769811 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.769811 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8810 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8810 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1141 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1141 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9951 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9951 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9951 # number of overall hits -system.cpu4.l1c.overall_hits::total 9951 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36179 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36179 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 22735 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 22735 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 58914 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 58914 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 58914 # number of overall misses -system.cpu4.l1c.overall_misses::total 58914 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1352891584 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1352891584 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 1067419012 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1067419012 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 2420310596 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 2420310596 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 2420310596 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 2420310596 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44989 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44989 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 23876 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 23876 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68865 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68865 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68865 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68865 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804174 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.804174 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952211 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.952211 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.855500 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.855500 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.855500 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.855500 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 37394.388568 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 37394.388568 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 46950.473367 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 46950.473367 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 41082.095869 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 41082.095869 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 41082.095869 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 41082.095869 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1431267 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 396.021323 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.773479 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.773479 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8768 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8768 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1075 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1075 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9843 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9843 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9843 # number of overall hits +system.cpu4.l1c.overall_hits::total 9843 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36125 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36125 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 22981 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 22981 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59106 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59106 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59106 # number of overall misses +system.cpu4.l1c.overall_misses::total 59106 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1336431585 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1336431585 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 1085022253 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 1085022253 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 2421453838 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 2421453838 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 2421453838 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 2421453838 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44893 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44893 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24056 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24056 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68949 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68949 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68949 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68949 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804691 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.804691 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955313 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.955313 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.857242 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.857242 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.857242 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.857242 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 36994.645952 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 36994.645952 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 47213.883338 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 47213.883338 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 40967.986973 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 40967.986973 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 40967.986973 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 40967.986973 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1430986 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 66934 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 67143 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.383258 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.312512 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9521 # number of writebacks -system.cpu4.l1c.writebacks::total 9521 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36179 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36179 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22735 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 22735 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 58914 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 58914 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 58914 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 58914 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1280533584 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1280533584 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1021953012 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1021953012 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2302486596 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 2302486596 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2302486596 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 2302486596 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 712917081 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 712917081 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 441958565 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 441958565 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1154875646 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1154875646 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804174 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804174 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952211 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952211 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.855500 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.855500 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.855500 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.855500 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 35394.388568 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 35394.388568 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 44950.649307 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 44950.649307 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 39082.163764 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 39082.163764 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 39082.163764 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 39082.163764 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9680 # number of writebacks +system.cpu4.l1c.writebacks::total 9680 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36125 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36125 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22981 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 22981 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59106 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59106 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59106 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59106 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1264183585 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1264183585 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1039060253 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1039060253 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2303243838 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 2303243838 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2303243838 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 2303243838 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 711442657 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 711442657 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 433569420 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 433569420 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1145012077 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1145012077 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804691 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804691 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955313 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955313 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857242 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.857242 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857242 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.857242 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 34994.701315 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 34994.701315 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 45213.883338 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 45213.883338 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 38968.020810 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 38968.020810 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 38968.020810 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 38968.020810 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1232,114 +1231,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99061 # number of read accesses completed -system.cpu5.num_writes 53322 # number of write accesses completed +system.cpu5.num_reads 98038 # number of read accesses completed +system.cpu5.num_writes 52677 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22382 # number of replacements -system.cpu5.l1c.tagsinuse 394.919460 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13094 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22775 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.574929 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 21614 # number of replacements +system.cpu5.l1c.tagsinuse 395.041478 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13218 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22030 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.600000 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 394.919460 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.771327 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.771327 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8623 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8623 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1083 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1083 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9706 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9706 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9706 # number of overall hits -system.cpu5.l1c.overall_hits::total 9706 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 35968 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 35968 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 22960 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 22960 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 58928 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 58928 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 58928 # number of overall misses -system.cpu5.l1c.overall_misses::total 58928 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1339036093 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1339036093 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 1083656826 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1083656826 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 2422692919 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 2422692919 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 2422692919 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 2422692919 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44591 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44591 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24043 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24043 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 68634 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 68634 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 68634 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 68634 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806620 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806620 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954956 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954956 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858583 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858583 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858583 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858583 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37228.539062 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 37228.539062 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47197.596951 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 47197.596951 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 41112.763355 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 41112.763355 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 41112.763355 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 41112.763355 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1432391 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 395.041478 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.771565 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.771565 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8654 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8654 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1143 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1143 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9797 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9797 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9797 # number of overall hits +system.cpu5.l1c.overall_hits::total 9797 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 35607 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 35607 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 22649 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 22649 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 58256 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 58256 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 58256 # number of overall misses +system.cpu5.l1c.overall_misses::total 58256 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1343353904 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1343353904 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 1075550971 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 1075550971 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 2418904875 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 2418904875 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 2418904875 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 2418904875 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44261 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44261 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 23792 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 23792 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68053 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68053 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68053 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68053 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.804478 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.804478 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951959 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.951959 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.856039 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.856039 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.856039 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.856039 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37727.241947 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 37727.241947 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47487.790675 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 47487.790675 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 41521.987006 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 41521.987006 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 41521.987006 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 41521.987006 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1431933 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 66951 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66282 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.394617 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.603648 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9691 # number of writebacks -system.cpu5.l1c.writebacks::total 9691 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35968 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 35968 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22960 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 22960 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 58928 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 58928 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 58928 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 58928 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1267104093 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1267104093 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1037740826 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1037740826 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2304844919 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 2304844919 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2304844919 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 2304844919 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 711626590 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 711626590 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 438340423 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 438340423 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1149967013 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1149967013 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806620 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806620 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954956 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954956 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858583 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858583 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858583 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858583 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35228.650272 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35228.650272 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45197.771167 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45197.771167 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39112.899114 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39112.899114 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39112.899114 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39112.899114 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9279 # number of writebacks +system.cpu5.l1c.writebacks::total 9279 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35607 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 35607 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22649 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 22649 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 58256 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 58256 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 58256 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 58256 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1272141904 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1272141904 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1030256971 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1030256971 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2302398875 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 2302398875 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2302398875 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 2302398875 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 712509152 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 712509152 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 420356599 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 420356599 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1132865751 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1132865751 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.804478 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.804478 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951959 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951959 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.856039 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.856039 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.856039 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.856039 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35727.298116 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35727.298116 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45487.967283 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45487.967283 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39522.089999 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39522.089999 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39522.089999 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39522.089999 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1347,114 +1346,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 98175 # number of read accesses completed -system.cpu6.num_writes 52998 # number of write accesses completed +system.cpu6.num_reads 98486 # number of read accesses completed +system.cpu6.num_writes 53296 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 21915 # number of replacements -system.cpu6.l1c.tagsinuse 395.370816 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13077 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22297 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.586491 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 22107 # number of replacements +system.cpu6.l1c.tagsinuse 394.242179 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13254 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22518 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.588596 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 395.370816 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.772209 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.772209 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8591 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8591 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1078 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1078 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9669 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9669 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9669 # number of overall hits -system.cpu6.l1c.overall_hits::total 9669 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 35673 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 35673 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 22773 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 22773 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 58446 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 58446 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 58446 # number of overall misses -system.cpu6.l1c.overall_misses::total 58446 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1336174857 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1336174857 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1084897863 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1084897863 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 2421072720 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 2421072720 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 2421072720 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 2421072720 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44264 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44264 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 23851 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 23851 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 68115 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 68115 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 68115 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 68115 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805915 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805915 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954803 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954803 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858049 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858049 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858049 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858049 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37456.195358 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 37456.195358 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 47639.654986 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 47639.654986 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 41424.096089 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 41424.096089 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 41424.096089 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 41424.096089 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1432460 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 394.242179 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.770004 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.770004 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8629 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8629 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1104 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1104 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9733 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9733 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9733 # number of overall hits +system.cpu6.l1c.overall_hits::total 9733 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 35833 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 35833 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23033 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23033 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 58866 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 58866 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 58866 # number of overall misses +system.cpu6.l1c.overall_misses::total 58866 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1334639245 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1334639245 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 1095786214 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 1095786214 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 2430425459 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 2430425459 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 2430425459 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 2430425459 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44462 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44462 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24137 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24137 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68599 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68599 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68599 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68599 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805924 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805924 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954261 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954261 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858117 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858117 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858117 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858117 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37246.092847 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 37246.092847 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 47574.619633 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 47574.619633 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 41287.423283 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 41287.423283 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 41287.423283 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 41287.423283 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1431647 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66523 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66759 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.533304 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.445004 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9553 # number of writebacks -system.cpu6.l1c.writebacks::total 9553 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35673 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 35673 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22773 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 22773 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 58446 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 58446 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 58446 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 58446 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1264832857 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1264832857 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1039353863 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1039353863 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2304186720 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 2304186720 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2304186720 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 2304186720 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 711871628 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 711871628 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 446494550 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 446494550 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1158366178 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1158366178 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805915 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805915 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954803 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954803 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858049 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858049 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858049 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858049 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35456.307487 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35456.307487 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 45639.742809 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 45639.742809 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 39424.198748 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 39424.198748 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 39424.198748 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 39424.198748 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9651 # number of writebacks +system.cpu6.l1c.writebacks::total 9651 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35833 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 35833 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23033 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 58866 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 58866 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 58866 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 58866 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1262977245 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1262977245 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1049724214 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1049724214 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2312701459 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 2312701459 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2312701459 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 2312701459 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702275141 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702275141 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 427671023 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 427671023 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1129946164 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1129946164 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805924 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805924 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954261 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954261 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858117 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858117 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858117 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858117 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35246.204476 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35246.204476 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 45574.793297 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 45574.793297 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 39287.559185 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 39287.559185 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 39287.559185 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 39287.559185 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1462,114 +1461,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98453 # number of read accesses completed -system.cpu7.num_writes 53303 # number of write accesses completed +system.cpu7.num_reads 100000 # number of read accesses completed +system.cpu7.num_writes 53815 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22126 # number of replacements -system.cpu7.l1c.tagsinuse 394.997672 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13256 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22544 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.588006 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22563 # number of replacements +system.cpu7.l1c.tagsinuse 397.316418 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13400 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22950 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.583878 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 394.997672 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.771480 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.771480 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8720 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8720 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1098 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1098 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9818 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9818 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9818 # number of overall hits -system.cpu7.l1c.overall_hits::total 9818 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35443 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35443 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23039 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23039 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 58482 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 58482 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 58482 # number of overall misses -system.cpu7.l1c.overall_misses::total 58482 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1325635544 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1325635544 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1095033308 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1095033308 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 2420668852 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 2420668852 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 2420668852 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 2420668852 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44163 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44163 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24137 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24137 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68300 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68300 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68300 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68300 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.802550 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.802550 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954510 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954510 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.856252 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.856252 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.856252 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.856252 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 37401.900065 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 37401.900065 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47529.550241 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 47529.550241 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 41391.690640 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 41391.690640 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 41391.690640 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 41391.690640 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1432038 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 397.316418 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.776009 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.776009 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8738 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8738 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1123 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1123 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9861 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9861 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9861 # number of overall hits +system.cpu7.l1c.overall_hits::total 9861 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36561 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36561 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 22883 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 22883 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59444 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59444 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59444 # number of overall misses +system.cpu7.l1c.overall_misses::total 59444 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1338317183 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1338317183 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1076026419 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1076026419 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 2414343602 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 2414343602 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 2414343602 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 2414343602 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45299 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24006 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24006 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 69305 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 69305 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 69305 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 69305 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807104 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807104 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953220 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953220 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.857716 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.857716 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.857716 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.857716 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 36605.048631 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 36605.048631 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47022.961106 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 47022.961106 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 40615.429682 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 40615.429682 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 40615.429682 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 40615.429682 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1430407 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 66517 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 67553 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.528902 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.174589 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9733 # number of writebacks -system.cpu7.l1c.writebacks::total 9733 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35443 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35443 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23039 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23039 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 58482 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 58482 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 58482 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 58482 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1254751544 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1254751544 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1048957308 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1048957308 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2303708852 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 2303708852 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2303708852 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 2303708852 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 712119692 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 712119692 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 450587409 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 450587409 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1162707101 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1162707101 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.802550 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.802550 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954510 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954510 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.856252 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.856252 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.856252 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.856252 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 35401.956494 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 35401.956494 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45529.637050 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45529.637050 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 39391.759037 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 39391.759037 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 39391.759037 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 39391.759037 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9844 # number of writebacks +system.cpu7.l1c.writebacks::total 9844 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36561 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36561 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22883 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 22883 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59444 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59444 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59444 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59444 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1265201183 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1265201183 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1030262419 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1030262419 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2295463602 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 2295463602 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2295463602 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 2295463602 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 718920000 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 718920000 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 432823408 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 432823408 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1151743408 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1151743408 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807104 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807104 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953220 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953220 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857716 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.857716 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857716 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.857716 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 34605.212740 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 34605.212740 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45023.048508 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45023.048508 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 38615.564262 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 38615.564262 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 38615.564262 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 38615.564262 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt index fd1ec361f..3f17aa9b6 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 31243111314 # Simulator tick rate (ticks/s) -host_mem_usage 230668 # Number of bytes of host memory used -host_seconds 3.20 # Real time elapsed on the host +host_tick_rate 15527580566 # Simulator tick rate (ticks/s) +host_mem_usage 226756 # Number of bytes of host memory used +host_seconds 6.44 # Real time elapsed on the host system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory system.physmem.bytes_read::total 64 # Number of bytes read from this memory system.physmem.bytes_written::cpu 213335552 # Number of bytes written to this memory @@ -151,9 +151,9 @@ system.monitor.readLatencyHist::36864-38911 0 0.00% 100.00% # system.monitor.readLatencyHist::38912-40959 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1 # Read request-response latency system.monitor.writeLatencyHist::samples 3333367 # Write request-response latency -system.monitor.writeLatencyHist::mean 30000 # Write request-response latency -system.monitor.writeLatencyHist::gmean 29999.999984 # Write request-response latency -system.monitor.writeLatencyHist::stdev 0 # Write request-response latency +system.monitor.writeLatencyHist::mean 30000.000098 # Write request-response latency +system.monitor.writeLatencyHist::gmean 30000.000081 # Write request-response latency +system.monitor.writeLatencyHist::stdev 0.179652 # Write request-response latency system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency @@ -204,8 +204,8 @@ system.monitor.ittReadRead::min_value 0 # Re system.monitor.ittReadRead::max_value 0 # Read-to-read inter transaction time system.monitor.ittReadRead::total 0 # Read-to-read inter transaction time system.monitor.ittWriteWrite::samples 3333367 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::mean 29999.695203 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::stdev 539.134360 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::mean 29999.695301 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::stdev 539.310304 # Write-to-write inter transaction time system.monitor.ittWriteWrite::underflows 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::1-5000 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::5001-10000 99 0.00% 0.00% # Write-to-write inter transaction time @@ -229,11 +229,11 @@ system.monitor.ittWriteWrite::90001-95000 0 0.00% 100.00% # W system.monitor.ittWriteWrite::95001-100000 0 0.00% 100.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::overflows 1 0.00% 100.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::min_value 10000 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::max_value 994000 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::max_value 994328 # Write-to-write inter transaction time system.monitor.ittWriteWrite::total 3333367 # Write-to-write inter transaction time system.monitor.ittReqReq::samples 3333368 # Request-to-request inter transaction time system.monitor.ittReqReq::mean 29999.687703 # Request-to-request inter transaction time -system.monitor.ittReqReq::stdev 539.308135 # Request-to-request inter transaction time +system.monitor.ittReqReq::stdev 539.488612 # Request-to-request inter transaction time system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::1-5000 1 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::5001-10000 99 0.00% 0.00% # Request-to-request inter transaction time @@ -256,8 +256,8 @@ system.monitor.ittReqReq::85001-90000 0 0.00% 100.00% # Re system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::overflows 1 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::min_value 5000 # Request-to-request inter transaction time -system.monitor.ittReqReq::max_value 994000 # Request-to-request inter transaction time +system.monitor.ittReqReq::min_value 4672 # Request-to-request inter transaction time +system.monitor.ittReqReq::max_value 994328 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333368 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions system.monitor.outstandingReadsHist::mean 0 # Outstanding read transactions |