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-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini718
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout14
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt613
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini718
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout14
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt607
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini816
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr1
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout14
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt678
12 files changed, 4196 insertions, 0 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
new file mode 100644
index 000000000..13c1420d9
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
@@ -0,0 +1,718 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+eventq_index=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=MinorCPU
+children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=system.cpu.branchPred
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+decodeCycleInput=true
+decodeInputBufferSize=3
+decodeInputWidth=2
+decodeToExecuteForwardDelay=1
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+enableIdling=true
+eventq_index=0
+executeAllowEarlyMemoryIssue=true
+executeBranchDelay=1
+executeCommitLimit=2
+executeCycleInput=true
+executeFuncUnits=system.cpu.executeFuncUnits
+executeInputBufferSize=7
+executeInputWidth=2
+executeIssueLimit=2
+executeLSQMaxStoreBufferStoresPerCycle=2
+executeLSQRequestsQueueSize=1
+executeLSQStoreBufferSize=5
+executeLSQTransfersQueueSize=2
+executeMaxAccessesInMemory=2
+executeMemoryCommitLimit=1
+executeMemoryIssueLimit=1
+executeMemoryWidth=0
+executeSetTraceTimeOnCommit=true
+executeSetTraceTimeOnIssue=false
+fetch1FetchLimit=1
+fetch1LineSnapWidth=0
+fetch1LineWidth=0
+fetch1ToFetch2BackwardDelay=1
+fetch1ToFetch2ForwardDelay=1
+fetch2CycleInput=true
+fetch2InputBufferSize=2
+fetch2ToDecodeForwardDelay=1
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+eventq_index=0
+globalCtrBits=2
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=262144
+
+[system.cpu.dtb]
+type=AlphaTLB
+eventq_index=0
+size=64
+
+[system.cpu.executeFuncUnits]
+type=MinorFUPool
+children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
+eventq_index=0
+funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
+
+[system.cpu.executeFuncUnits.funcUnits0]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
+opLat=3
+timings=system.cpu.executeFuncUnits.funcUnits0.timings
+
+[system.cpu.executeFuncUnits.funcUnits0.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntAlu
+
+[system.cpu.executeFuncUnits.funcUnits0.timings]
+type=MinorFUTiming
+children=opClasses
+description=Int
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits1]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
+opLat=3
+timings=system.cpu.executeFuncUnits.funcUnits1.timings
+
+[system.cpu.executeFuncUnits.funcUnits1.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntAlu
+
+[system.cpu.executeFuncUnits.funcUnits1.timings]
+type=MinorFUTiming
+children=opClasses
+description=Int
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits2]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
+opLat=3
+timings=system.cpu.executeFuncUnits.funcUnits2.timings
+
+[system.cpu.executeFuncUnits.funcUnits2.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntMult
+
+[system.cpu.executeFuncUnits.funcUnits2.timings]
+type=MinorFUTiming
+children=opClasses
+description=Mul
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
+srcRegsRelativeLats=0
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits3]
+type=MinorFU
+children=opClasses
+eventq_index=0
+issueLat=9
+opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
+opLat=9
+timings=
+
+[system.cpu.executeFuncUnits.funcUnits3.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntDiv
+
+[system.cpu.executeFuncUnits.funcUnits4]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
+opLat=6
+timings=system.cpu.executeFuncUnits.funcUnits4.timings
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses]
+type=MinorOpClassSet
+children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatAdd
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
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+opClass=FloatCmp
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
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+opClass=FloatCvt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
+type=MinorOpClass
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+opClass=FloatMult
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
+type=MinorOpClass
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+opClass=FloatDiv
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
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+opClass=FloatSqrt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
+type=MinorOpClass
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+opClass=SimdAdd
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
+type=MinorOpClass
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+opClass=SimdAddAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdAlu
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
+type=MinorOpClass
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+opClass=SimdCmp
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
+type=MinorOpClass
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+opClass=SimdCvt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
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+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
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+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
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+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
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+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
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+
+[system.cpu.executeFuncUnits.funcUnits4.timings]
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+extraCommitLat=0
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+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits5]
+type=MinorFU
+children=opClasses timings
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+opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
+opLat=1
+timings=system.cpu.executeFuncUnits.funcUnits5.timings
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses]
+type=MinorOpClassSet
+children=opClasses0 opClasses1
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+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
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+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
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+
+[system.cpu.executeFuncUnits.funcUnits5.timings]
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+
+[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits6]
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+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
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+timings=
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses]
+type=MinorOpClassSet
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+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
+type=MinorOpClass
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+opClass=IprAccess
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
+type=MinorOpClass
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+opClass=InstPrefetch
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=131072
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=AlphaISA
+eventq_index=0
+system=system
+
+[system.cpu.itb]
+type=AlphaTLB
+eventq_index=0
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
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+max_miss_count=0
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+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
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+size=2097152
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=2097152
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/arm/projectscratch/pd/sysrandd/dist/test-progs/hello/bin/alpha/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+eventq_index=0
+voltage_domain=system.voltage_domain
+
+[system.membus]
+type=CoherentBus
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=DRAMCtrl
+activation_limit=4
+addr_mapping=RoRaBaChCo
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=300000
+tRP=13750
+tRRD=6250
+tWTR=7500
+tXAW=40000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr
new file mode 100644
index 000000000..1a4f96712
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr
@@ -0,0 +1 @@
+warn: Sockets disabled, not accepting gdb connections
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
new file mode 100644
index 000000000..bfafef07d
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
@@ -0,0 +1,14 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled May 7 2014 10:41:53
+gem5 started May 7 2014 10:42:15
+gem5 executing on cz3212c2d7
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 35190500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
new file mode 100644
index 000000000..39aafd883
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -0,0 +1,613 @@
+
+---------- Begin Simulation Statistics ----------
+final_tick 35015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+host_inst_rate 59280 # Simulator instruction rate (inst/s)
+host_mem_usage 248380 # Number of bytes of host memory used
+host_op_rate 59280 # Simulator op (including micro ops) rate (op/s)
+host_seconds 0.11 # Real time elapsed on the host
+host_tick_rate 324332505 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 6400 # Number of instructions simulated
+sim_ops 6400 # Number of ops (including micro ops) simulated
+sim_seconds 0.000035 # Number of seconds simulated
+sim_ticks 35015500 # Number of ticks simulated
+system.clk_domain.clock 1000 # Clock period in ticks
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 24.564797 # BTB Hit Percentage
+system.cpu.branchPred.BTBHits 381 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 1551 # Number of BTB lookups
+system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
+system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect
+system.cpu.branchPred.condPredicted 1201 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 1959 # Number of BP lookups
+system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
+system.cpu.committedInsts 6400 # Number of instructions committed
+system.cpu.committedOps 6400 # Number of ops (including micro ops) committed
+system.cpu.cpi 10.942344 # CPI: cycles per instruction
+system.cpu.dcache.ReadReq_accesses::cpu.inst 1330 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1330 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 78029.411765 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 78029.411765 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 76945.312500 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76945.312500 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits::cpu.inst 1228 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1228 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7959000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 7959000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076692 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.076692 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7386750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 7386750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.072180 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.072180 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69500 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69500 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70147.260274 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70147.260274 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8687500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 8687500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5120750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5120750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2195 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 73332.599119 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73332.599119 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 74008.875740 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74008.875740 # average overall mshr miss latency
+system.cpu.dcache.demand_hits::cpu.inst 1968 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1968 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency::cpu.inst 16646500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 16646500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses
+system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12507500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 12507500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2195 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 73332.599119 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73332.599119 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 74008.875740 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74008.875740 # average overall mshr miss latency
+system.cpu.dcache.overall_hits::cpu.inst 1968 # number of overall hits
+system.cpu.dcache.overall_hits::total 1968 # number of overall hits
+system.cpu.dcache.overall_miss_latency::cpu.inst 16646500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 16646500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses
+system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses
+system.cpu.dcache.overall_misses::total 227 # number of overall misses
+system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12507500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 12507500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
+system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks.
+system.cpu.dcache.tags.data_accesses 4559 # Number of data accesses
+system.cpu.dcache.tags.occ_blocks::cpu.inst 103.870916 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst 0.025359 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.025359 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.tag_accesses 4559 # Number of tag accesses
+system.cpu.dcache.tags.tagsinuse 103.870916 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.discardedOps 1111 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.dtb.data_accesses 2266 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 2252 # DTB hits
+system.cpu.dtb.data_misses 14 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 1379 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 1368 # DTB read hits
+system.cpu.dtb.read_misses 11 # DTB read misses
+system.cpu.dtb.write_accesses 887 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 884 # DTB write hits
+system.cpu.dtb.write_misses 3 # DTB write misses
+system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70238.356164 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 70238.356164 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67805.479452 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67805.479452 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits::cpu.inst 2265 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 2265 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 25637000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 25637000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138783 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.138783 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24749000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 24749000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 2630 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70238.356164 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 70238.356164 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67805.479452 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67805.479452 # average overall mshr miss latency
+system.cpu.icache.demand_hits::cpu.inst 2265 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 2265 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency::cpu.inst 25637000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 25637000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses
+system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24749000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 24749000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses::cpu.inst 2630 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 2630 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70238.356164 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 70238.356164 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67805.479452 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67805.479452 # average overall mshr miss latency
+system.cpu.icache.overall_hits::cpu.inst 2265 # number of overall hits
+system.cpu.icache.overall_hits::total 2265 # number of overall hits
+system.cpu.icache.overall_miss_latency::cpu.inst 25637000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 25637000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses
+system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
+system.cpu.icache.overall_misses::total 365 # number of overall misses
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24749000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 24749000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses
+system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id
+system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks.
+system.cpu.icache.tags.data_accesses 5625 # Number of data accesses
+system.cpu.icache.tags.occ_blocks::cpu.inst 175.902434 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.085890 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.085890 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.replacements 0 # number of replacements
+system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
+system.cpu.icache.tags.tag_accesses 5625 # Number of tag accesses
+system.cpu.icache.tags.tagsinuse 175.902434 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.idleCycles 57521 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.ipc 0.091388 # IPC: instructions per cycle
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 2647 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 2630 # ITB hits
+system.cpu.itb.fetch_misses 17 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69126.712329 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69126.712329 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56544.520548 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56544.520548 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5046250 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 5046250 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst 73 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4127750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4127750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68832.065217 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68832.065217 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56304.891304 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56304.891304 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31662750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 31662750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997831 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 460 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 460 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25900250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25900250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 460 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses::cpu.inst 534 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68872.420263 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68872.420263 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56337.711069 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56337.711069 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency::cpu.inst 36709000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 36709000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses::cpu.inst 533 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30028000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 30028000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses::cpu.inst 534 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68872.420263 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68872.420263 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56337.711069 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56337.711069 # average overall mshr miss latency
+system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1 # number of overall hits
+system.cpu.l2cache.overall_miss_latency::cpu.inst 36709000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 36709000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses
+system.cpu.l2cache.overall_misses::total 533 # number of overall misses
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30028000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 30028000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id
+system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.550813 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007127 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.007127 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.replacements 0 # number of replacements
+system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses
+system.cpu.l2cache.tags.tagsinuse 233.550813 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.numCycles 70031 # number of cpu cycles simulated
+system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.tickCycles 12510 # Number of cycles that the CPU actually ticked
+system.cpu.toL2Bus.data_through_bus 34176 # Total data (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 626500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.throughput 976024903 # Throughput (bytes/s)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
+system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.membus.data_through_bus 34112 # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
+system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4977500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 14.2 # Layer utilization (%)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.throughput 974197141 # Throughput (bytes/s)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 460 # Transaction distribution
+system.membus.trans_dist::ReadResp 460 # Transaction distribution
+system.membus.trans_dist::ReadExReq 73 # Transaction distribution
+system.membus.trans_dist::ReadExResp 73 # Transaction distribution
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgGap 65510.32 # Average gap between requests
+system.physmem.avgMemAccLat 25799.25 # Average memory access latency per DRAM burst
+system.physmem.avgQLat 7049.25 # Average queueing delay per DRAM burst
+system.physmem.avgRdBW 974.20 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 974.20 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
+system.physmem.busUtil 7.61 # Data bus utilization in percentage
+system.physmem.busUtilRead 7.61 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
+system.physmem.bw_inst_read::cpu.inst 665305365 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 665305365 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 974197141 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 974197141 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 974197141 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 974197141 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 369.617978 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 234.259007 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 335.584548 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 22 24.72% 24.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 23 25.84% 50.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 10 11.24% 61.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 8 8.99% 70.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4 4.49% 75.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 6 6.74% 82.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2 2.25% 84.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 4 4.49% 88.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation
+system.physmem.bytesReadDRAM 34112 # Total number of bytes read from DRAM
+system.physmem.bytesReadSys 34112 # Total read bytes from the system interface side
+system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
+system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
+system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
+system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 34112 # Number of bytes read from this memory
+system.physmem.bytes_read::total 34112 # Number of bytes read from this memory
+system.physmem.memoryStateTime::IDLE 15500 # Time in different power states
+system.physmem.memoryStateTime::REF 1040000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 30385500 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
+system.physmem.pageHitRate 81.80 # Row buffer hit rate, read and write combined
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.perBankRdBursts::0 73 # Per bank write bursts
+system.physmem.perBankRdBursts::1 39 # Per bank write bursts
+system.physmem.perBankRdBursts::2 36 # Per bank write bursts
+system.physmem.perBankRdBursts::3 54 # Per bank write bursts
+system.physmem.perBankRdBursts::4 45 # Per bank write bursts
+system.physmem.perBankRdBursts::5 21 # Per bank write bursts
+system.physmem.perBankRdBursts::6 1 # Per bank write bursts
+system.physmem.perBankRdBursts::7 5 # Per bank write bursts
+system.physmem.perBankRdBursts::8 0 # Per bank write bursts
+system.physmem.perBankRdBursts::9 1 # Per bank write bursts
+system.physmem.perBankRdBursts::10 22 # Per bank write bursts
+system.physmem.perBankRdBursts::11 29 # Per bank write bursts
+system.physmem.perBankRdBursts::12 19 # Per bank write bursts
+system.physmem.perBankRdBursts::13 127 # Per bank write bursts
+system.physmem.perBankRdBursts::14 47 # Per bank write bursts
+system.physmem.perBankRdBursts::15 14 # Per bank write bursts
+system.physmem.perBankWrBursts::0 0 # Per bank write bursts
+system.physmem.perBankWrBursts::1 0 # Per bank write bursts
+system.physmem.perBankWrBursts::2 0 # Per bank write bursts
+system.physmem.perBankWrBursts::3 0 # Per bank write bursts
+system.physmem.perBankWrBursts::4 0 # Per bank write bursts
+system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::6 0 # Per bank write bursts
+system.physmem.perBankWrBursts::7 0 # Per bank write bursts
+system.physmem.perBankWrBursts::8 0 # Per bank write bursts
+system.physmem.perBankWrBursts::9 0 # Per bank write bursts
+system.physmem.perBankWrBursts::10 0 # Per bank write bursts
+system.physmem.perBankWrBursts::11 0 # Per bank write bursts
+system.physmem.perBankWrBursts::12 0 # Per bank write bursts
+system.physmem.perBankWrBursts::13 0 # Per bank write bursts
+system.physmem.perBankWrBursts::14 0 # Per bank write bursts
+system.physmem.perBankWrBursts::15 0 # Per bank write bursts
+system.physmem.rdQLenPdf::0 440 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 88 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 533 # Read request sizes (log2)
+system.physmem.readReqs 533 # Number of read requests accepted
+system.physmem.readRowHitRate 81.80 # Row buffer hit rate for reads
+system.physmem.readRowHits 436 # Number of row buffer hits during reads
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
+system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers
+system.physmem.totGap 34917000 # Total gap between requests
+system.physmem.totMemAccLat 13751000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 3757250 # Total ticks spent queuing
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 0 # Write request sizes (log2)
+system.physmem.writeReqs 0 # Number of write requests accepted
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.voltage_domain.voltage 1 # Voltage in Volts
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
new file mode 100644
index 000000000..45336acc0
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
@@ -0,0 +1,718 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+eventq_index=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=MinorCPU
+children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=system.cpu.branchPred
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+decodeCycleInput=true
+decodeInputBufferSize=3
+decodeInputWidth=2
+decodeToExecuteForwardDelay=1
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+enableIdling=true
+eventq_index=0
+executeAllowEarlyMemoryIssue=true
+executeBranchDelay=1
+executeCommitLimit=2
+executeCycleInput=true
+executeFuncUnits=system.cpu.executeFuncUnits
+executeInputBufferSize=7
+executeInputWidth=2
+executeIssueLimit=2
+executeLSQMaxStoreBufferStoresPerCycle=2
+executeLSQRequestsQueueSize=1
+executeLSQStoreBufferSize=5
+executeLSQTransfersQueueSize=2
+executeMaxAccessesInMemory=2
+executeMemoryCommitLimit=1
+executeMemoryIssueLimit=1
+executeMemoryWidth=0
+executeSetTraceTimeOnCommit=true
+executeSetTraceTimeOnIssue=false
+fetch1FetchLimit=1
+fetch1LineSnapWidth=0
+fetch1LineWidth=0
+fetch1ToFetch2BackwardDelay=1
+fetch1ToFetch2ForwardDelay=1
+fetch2CycleInput=true
+fetch2InputBufferSize=2
+fetch2ToDecodeForwardDelay=1
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+eventq_index=0
+globalCtrBits=2
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=262144
+
+[system.cpu.dtb]
+type=AlphaTLB
+eventq_index=0
+size=64
+
+[system.cpu.executeFuncUnits]
+type=MinorFUPool
+children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
+eventq_index=0
+funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
+
+[system.cpu.executeFuncUnits.funcUnits0]
+type=MinorFU
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+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
+opLat=3
+timings=system.cpu.executeFuncUnits.funcUnits0.timings
+
+[system.cpu.executeFuncUnits.funcUnits0.opClasses]
+type=MinorOpClassSet
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+
+[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
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+
+[system.cpu.executeFuncUnits.funcUnits0.timings]
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+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
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+
+[system.cpu.executeFuncUnits.funcUnits1]
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+
+[system.cpu.executeFuncUnits.funcUnits1.opClasses]
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+
+[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
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+
+[system.cpu.executeFuncUnits.funcUnits1.timings]
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+
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+
+[system.cpu.executeFuncUnits.funcUnits3]
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+
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+
+[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
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+
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+
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+eventq_index=0
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
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+
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+
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
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+eventq_index=0
+opClass=SimdAlu
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
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+
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+
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
+[system.cpu.executeFuncUnits.funcUnits4.timings]
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+
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+
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+
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+
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+
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+
+[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
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+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits6]
+type=MinorFU
+children=opClasses
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
+opLat=1
+timings=
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses]
+type=MinorOpClassSet
+children=opClasses0 opClasses1
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
+type=MinorOpClass
+eventq_index=0
+opClass=IprAccess
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
+type=MinorOpClass
+eventq_index=0
+opClass=InstPrefetch
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=131072
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=AlphaISA
+eventq_index=0
+system=system
+
+[system.cpu.itb]
+type=AlphaTLB
+eventq_index=0
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=2097152
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/arm/projectscratch/pd/sysrandd/dist/test-progs/hello/bin/alpha/tru64/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+eventq_index=0
+voltage_domain=system.voltage_domain
+
+[system.membus]
+type=CoherentBus
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=DRAMCtrl
+activation_limit=4
+addr_mapping=RoRaBaChCo
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=300000
+tRP=13750
+tRRD=6250
+tWTR=7500
+tXAW=40000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr
new file mode 100644
index 000000000..32998f270
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout
new file mode 100644
index 000000000..226c0e256
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout
@@ -0,0 +1,14 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled May 7 2014 10:41:53
+gem5 started May 7 2014 15:04:23
+gem5 executing on cz3212c2d7
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 18715000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
new file mode 100644
index 000000000..e8ab0ad04
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
@@ -0,0 +1,607 @@
+
+---------- Begin Simulation Statistics ----------
+final_tick 18662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+host_inst_rate 42585 # Simulator instruction rate (inst/s)
+host_mem_usage 247072 # Number of bytes of host memory used
+host_op_rate 42585 # Simulator op (including micro ops) rate (op/s)
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 307435077 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 2585 # Number of instructions simulated
+sim_ops 2585 # Number of ops (including micro ops) simulated
+sim_seconds 0.000019 # Number of seconds simulated
+sim_ticks 18662000 # Number of ticks simulated
+system.clk_domain.clock 1000 # Clock period in ticks
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 10.394265 # BTB Hit Percentage
+system.cpu.branchPred.BTBHits 58 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 558 # Number of BTB lookups
+system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions.
+system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect
+system.cpu.branchPred.condPredicted 393 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 785 # Number of BP lookups
+system.cpu.branchPred.usedRAS 138 # Number of times the RAS was used to get a target.
+system.cpu.committedInsts 2585 # Number of instructions committed
+system.cpu.committedOps 2585 # Number of ops (including micro ops) committed
+system.cpu.cpi 14.438685 # CPI: cycles per instruction
+system.cpu.dcache.ReadReq_accesses::cpu.inst 497 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 497 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75877.049180 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75877.049180 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74034.482759 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74034.482759 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits::cpu.inst 436 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 436 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4628500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4628500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.122736 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.122736 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::cpu.inst 61 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4294000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4294000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.116700 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116700 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 58 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses::cpu.inst 294 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69872.093023 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69872.093023 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67768.518519 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67768.518519 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits::cpu.inst 251 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3004500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 3004500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.146259 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::cpu.inst 43 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 16 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 16 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1829750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1829750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.091837 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 27 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses::cpu.inst 791 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 791 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 73394.230769 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73394.230769 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72044.117647 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72044.117647 # average overall mshr miss latency
+system.cpu.dcache.demand_hits::cpu.inst 687 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 687 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency::cpu.inst 7633000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7633000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::cpu.inst 0.131479 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.131479 # miss rate for demand accesses
+system.cpu.dcache.demand_misses::cpu.inst 104 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6123750 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6123750 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.107459 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.107459 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses::cpu.inst 85 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses::cpu.inst 791 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 791 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 73394.230769 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73394.230769 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72044.117647 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72044.117647 # average overall mshr miss latency
+system.cpu.dcache.overall_hits::cpu.inst 687 # number of overall hits
+system.cpu.dcache.overall_hits::total 687 # number of overall hits
+system.cpu.dcache.overall_miss_latency::cpu.inst 7633000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7633000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::cpu.inst 0.131479 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.131479 # miss rate for overall accesses
+system.cpu.dcache.overall_misses::cpu.inst 104 # number of overall misses
+system.cpu.dcache.overall_misses::total 104 # number of overall misses
+system.cpu.dcache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 19 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6123750 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6123750 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.107459 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.107459 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses::cpu.inst 85 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id
+system.cpu.dcache.tags.avg_refs 8.082353 # Average number of references to valid blocks.
+system.cpu.dcache.tags.data_accesses 1667 # Number of data accesses
+system.cpu.dcache.tags.occ_blocks::cpu.inst 48.695278 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst 0.011888 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.011888 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.tag_accesses 1667 # Number of tag accesses
+system.cpu.dcache.tags.tagsinuse 48.695278 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 687 # Total number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.discardedOps 631 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.dtb.data_accesses 828 # DTB accesses
+system.cpu.dtb.data_acv 1 # DTB access violations
+system.cpu.dtb.data_hits 815 # DTB hits
+system.cpu.dtb.data_misses 13 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 515 # DTB read accesses
+system.cpu.dtb.read_acv 1 # DTB read access violations
+system.cpu.dtb.read_hits 508 # DTB read hits
+system.cpu.dtb.read_misses 7 # DTB read misses
+system.cpu.dtb.write_accesses 313 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 307 # DTB write hits
+system.cpu.dtb.write_misses 6 # DTB write misses
+system.cpu.icache.ReadReq_accesses::cpu.inst 962 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 962 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69306.053812 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69306.053812 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66882.286996 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66882.286996 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits::cpu.inst 739 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 739 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 15455250 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 15455250 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.231809 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.231809 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14914750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 14914750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231809 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231809 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 223 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses::cpu.inst 962 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 962 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69306.053812 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69306.053812 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66882.286996 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66882.286996 # average overall mshr miss latency
+system.cpu.icache.demand_hits::cpu.inst 739 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 739 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency::cpu.inst 15455250 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 15455250 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::cpu.inst 0.231809 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.231809 # miss rate for demand accesses
+system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14914750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 14914750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231809 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.231809 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses::cpu.inst 223 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses::cpu.inst 962 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 962 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69306.053812 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69306.053812 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66882.286996 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 66882.286996 # average overall mshr miss latency
+system.cpu.icache.overall_hits::cpu.inst 739 # number of overall hits
+system.cpu.icache.overall_hits::total 739 # number of overall hits
+system.cpu.icache.overall_miss_latency::cpu.inst 15455250 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 15455250 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::cpu.inst 0.231809 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.231809 # miss rate for overall accesses
+system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses
+system.cpu.icache.overall_misses::total 223 # number of overall misses
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14914750 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 14914750 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231809 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.231809 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses
+system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id
+system.cpu.icache.tags.avg_refs 3.313901 # Average number of references to valid blocks.
+system.cpu.icache.tags.data_accesses 2147 # Number of data accesses
+system.cpu.icache.tags.occ_blocks::cpu.inst 118.799156 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.058007 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.058007 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.replacements 0 # number of replacements
+system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks.
+system.cpu.icache.tags.tag_accesses 2147 # Number of tag accesses
+system.cpu.icache.tags.tagsinuse 118.799156 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 739 # Total number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.idleCycles 31983 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.ipc 0.069258 # IPC: instructions per cycle
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 974 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 962 # ITB hits
+system.cpu.itb.fetch_misses 12 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst 27 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66750 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66750 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54490.740741 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54490.740741 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 1802250 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 1802250 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst 27 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1471250 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1471250 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 27 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 281 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67356.761566 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67356.761566 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54830.071174 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54830.071174 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18927250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 18927250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 281 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15407250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15407250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses::cpu.inst 308 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 308 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67303.571429 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 67303.571429 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54800.324675 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54800.324675 # average overall mshr miss latency
+system.cpu.l2cache.demand_miss_latency::cpu.inst 20729500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 20729500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses::cpu.inst 308 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 308 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16878500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 16878500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 308 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 308 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses::cpu.inst 308 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 308 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67303.571429 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 67303.571429 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54800.324675 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54800.324675 # average overall mshr miss latency
+system.cpu.l2cache.overall_miss_latency::cpu.inst 20729500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 20729500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses::cpu.inst 308 # number of overall misses
+system.cpu.l2cache.overall_misses::total 308 # number of overall misses
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16878500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 16878500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 308 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id
+system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.968700 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004485 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.004485 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.replacements 0 # number of replacements
+system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses
+system.cpu.l2cache.tags.tagsinuse 146.968700 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.numCycles 37324 # number of cpu cycles simulated
+system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.tickCycles 5341 # Number of cycles that the CPU actually ticked
+system.cpu.toL2Bus.data_through_bus 19712 # Total data (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 381750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 136250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.throughput 1056264066 # Throughput (bytes/s)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
+system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.membus.data_through_bus 19712 # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
+system.membus.reqLayer0.occupancy 362500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2871000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 15.4 # Layer utilization (%)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.throughput 1056264066 # Throughput (bytes/s)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 281 # Transaction distribution
+system.membus.trans_dist::ReadResp 281 # Transaction distribution
+system.membus.trans_dist::ReadExReq 27 # Transaction distribution
+system.membus.trans_dist::ReadExResp 27 # Transaction distribution
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgGap 60324.68 # Average gap between requests
+system.physmem.avgMemAccLat 24109.58 # Average memory access latency per DRAM burst
+system.physmem.avgQLat 5359.58 # Average queueing delay per DRAM burst
+system.physmem.avgRdBW 1056.26 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1056.26 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
+system.physmem.busUtil 8.25 # Data bus utilization in percentage
+system.physmem.busUtilRead 8.25 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
+system.physmem.bw_inst_read::cpu.inst 764762619 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 764762619 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1056264066 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1056264066 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1056264066 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1056264066 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytesPerActivate::samples 44 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 411.636364 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 270.438338 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 322.932860 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 11 25.00% 25.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 7 15.91% 40.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4 9.09% 50.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3 6.82% 56.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 6 13.64% 70.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 5 11.36% 81.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3 6.82% 88.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 2.27% 90.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 4 9.09% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 44 # Bytes accessed per row activation
+system.physmem.bytesReadDRAM 19712 # Total number of bytes read from DRAM
+system.physmem.bytesReadSys 19712 # Total read bytes from the system interface side
+system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
+system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
+system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
+system.physmem.bytes_inst_read::cpu.inst 14272 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 14272 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 19712 # Number of bytes read from this memory
+system.physmem.bytes_read::total 19712 # Number of bytes read from this memory
+system.physmem.memoryStateTime::IDLE 15500 # Time in different power states
+system.physmem.memoryStateTime::REF 520000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 15310750 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.num_reads::cpu.inst 308 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 308 # Number of read requests responded to by this memory
+system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.perBankRdBursts::0 0 # Per bank write bursts
+system.physmem.perBankRdBursts::1 1 # Per bank write bursts
+system.physmem.perBankRdBursts::2 3 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24 # Per bank write bursts
+system.physmem.perBankRdBursts::4 21 # Per bank write bursts
+system.physmem.perBankRdBursts::5 0 # Per bank write bursts
+system.physmem.perBankRdBursts::6 27 # Per bank write bursts
+system.physmem.perBankRdBursts::7 47 # Per bank write bursts
+system.physmem.perBankRdBursts::8 68 # Per bank write bursts
+system.physmem.perBankRdBursts::9 2 # Per bank write bursts
+system.physmem.perBankRdBursts::10 15 # Per bank write bursts
+system.physmem.perBankRdBursts::11 14 # Per bank write bursts
+system.physmem.perBankRdBursts::12 18 # Per bank write bursts
+system.physmem.perBankRdBursts::13 52 # Per bank write bursts
+system.physmem.perBankRdBursts::14 15 # Per bank write bursts
+system.physmem.perBankRdBursts::15 1 # Per bank write bursts
+system.physmem.perBankWrBursts::0 0 # Per bank write bursts
+system.physmem.perBankWrBursts::1 0 # Per bank write bursts
+system.physmem.perBankWrBursts::2 0 # Per bank write bursts
+system.physmem.perBankWrBursts::3 0 # Per bank write bursts
+system.physmem.perBankWrBursts::4 0 # Per bank write bursts
+system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::6 0 # Per bank write bursts
+system.physmem.perBankWrBursts::7 0 # Per bank write bursts
+system.physmem.perBankWrBursts::8 0 # Per bank write bursts
+system.physmem.perBankWrBursts::9 0 # Per bank write bursts
+system.physmem.perBankWrBursts::10 0 # Per bank write bursts
+system.physmem.perBankWrBursts::11 0 # Per bank write bursts
+system.physmem.perBankWrBursts::12 0 # Per bank write bursts
+system.physmem.perBankWrBursts::13 0 # Per bank write bursts
+system.physmem.perBankWrBursts::14 0 # Per bank write bursts
+system.physmem.perBankWrBursts::15 0 # Per bank write bursts
+system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 308 # Read request sizes (log2)
+system.physmem.readReqs 308 # Number of read requests accepted
+system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads
+system.physmem.readRowHits 256 # Number of row buffer hits during reads
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
+system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers
+system.physmem.totGap 18580000 # Total gap between requests
+system.physmem.totMemAccLat 7425750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 1650750 # Total ticks spent queuing
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 0 # Write request sizes (log2)
+system.physmem.writeReqs 0 # Number of write requests accepted
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.voltage_domain.voltage 1 # Voltage in Volts
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
new file mode 100644
index 000000000..75d524231
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
@@ -0,0 +1,816 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+eventq_index=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=MinorCPU
+children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
+branchPred=system.cpu.branchPred
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+decodeCycleInput=true
+decodeInputBufferSize=3
+decodeInputWidth=2
+decodeToExecuteForwardDelay=1
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+enableIdling=true
+eventq_index=0
+executeAllowEarlyMemoryIssue=true
+executeBranchDelay=1
+executeCommitLimit=2
+executeCycleInput=true
+executeFuncUnits=system.cpu.executeFuncUnits
+executeInputBufferSize=7
+executeInputWidth=2
+executeIssueLimit=2
+executeLSQMaxStoreBufferStoresPerCycle=2
+executeLSQRequestsQueueSize=1
+executeLSQStoreBufferSize=5
+executeLSQTransfersQueueSize=2
+executeMaxAccessesInMemory=2
+executeMemoryCommitLimit=1
+executeMemoryIssueLimit=1
+executeMemoryWidth=0
+executeSetTraceTimeOnCommit=true
+executeSetTraceTimeOnIssue=false
+fetch1FetchLimit=1
+fetch1LineSnapWidth=0
+fetch1LineWidth=0
+fetch1ToFetch2BackwardDelay=1
+fetch1ToFetch2ForwardDelay=1
+fetch2CycleInput=true
+fetch2InputBufferSize=2
+fetch2ToDecodeForwardDelay=1
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+eventq_index=0
+globalCtrBits=2
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=262144
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[5]
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.executeFuncUnits]
+type=MinorFUPool
+children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
+eventq_index=0
+funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
+
+[system.cpu.executeFuncUnits.funcUnits0]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
+opLat=3
+timings=system.cpu.executeFuncUnits.funcUnits0.timings
+
+[system.cpu.executeFuncUnits.funcUnits0.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntAlu
+
+[system.cpu.executeFuncUnits.funcUnits0.timings]
+type=MinorFUTiming
+children=opClasses
+description=Int
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits1]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
+opLat=3
+timings=system.cpu.executeFuncUnits.funcUnits1.timings
+
+[system.cpu.executeFuncUnits.funcUnits1.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntAlu
+
+[system.cpu.executeFuncUnits.funcUnits1.timings]
+type=MinorFUTiming
+children=opClasses
+description=Int
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits2]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
+opLat=3
+timings=system.cpu.executeFuncUnits.funcUnits2.timings
+
+[system.cpu.executeFuncUnits.funcUnits2.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntMult
+
+[system.cpu.executeFuncUnits.funcUnits2.timings]
+type=MinorFUTiming
+children=opClasses
+description=Mul
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
+srcRegsRelativeLats=0
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits3]
+type=MinorFU
+children=opClasses
+eventq_index=0
+issueLat=9
+opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
+opLat=9
+timings=
+
+[system.cpu.executeFuncUnits.funcUnits3.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntDiv
+
+[system.cpu.executeFuncUnits.funcUnits4]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
+opLat=6
+timings=system.cpu.executeFuncUnits.funcUnits4.timings
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses]
+type=MinorOpClassSet
+children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatAdd
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatCmp
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatCvt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatMult
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatDiv
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatSqrt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdAdd
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdAddAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdAlu
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdCmp
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdCvt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdMisc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdMult
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdMultAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdShift
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdShiftAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdSqrt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatAdd
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatAlu
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatCmp
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatCvt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatDiv
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatMisc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatMult
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatMultAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatSqrt
+
+[system.cpu.executeFuncUnits.funcUnits4.timings]
+type=MinorFUTiming
+children=opClasses
+description=FloatSimd
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits5]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
+opLat=1
+timings=system.cpu.executeFuncUnits.funcUnits5.timings
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses]
+type=MinorOpClassSet
+children=opClasses0 opClasses1
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
+type=MinorOpClass
+eventq_index=0
+opClass=MemRead
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
+type=MinorOpClass
+eventq_index=0
+opClass=MemWrite
+
+[system.cpu.executeFuncUnits.funcUnits5.timings]
+type=MinorFUTiming
+children=opClasses
+description=Mem
+eventq_index=0
+extraAssumedLat=2
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
+srcRegsRelativeLats=1
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits6]
+type=MinorFU
+children=opClasses
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
+opLat=1
+timings=
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses]
+type=MinorOpClassSet
+children=opClasses0 opClasses1
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
+type=MinorOpClass
+eventq_index=0
+opClass=IprAccess
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
+type=MinorOpClass
+eventq_index=0
+opClass=InstPrefetch
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=131072
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[4]
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=2097152
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/arm/projectscratch/pd/sysrandd/dist/test-progs/hello/bin/arm/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+eventq_index=0
+voltage_domain=system.voltage_domain
+
+[system.membus]
+type=CoherentBus
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=DRAMCtrl
+activation_limit=4
+addr_mapping=RoRaBaChCo
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=300000
+tRP=13750
+tRRD=6250
+tWTR=7500
+tXAW=40000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr
new file mode 100644
index 000000000..1a4f96712
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr
@@ -0,0 +1 @@
+warn: Sockets disabled, not accepting gdb connections
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout
new file mode 100644
index 000000000..ccb773a26
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout
@@ -0,0 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled May 7 2014 10:57:46
+gem5 started May 7 2014 13:43:16
+gem5 executing on cz3211bhr8
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing
+Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu.isa: ISA system set to: 0 0x6c0c360
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Exiting @ tick 28041000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
new file mode 100644
index 000000000..e6065a0ab
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -0,0 +1,678 @@
+
+---------- Begin Simulation Statistics ----------
+final_tick 27963000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+host_inst_rate 75358 # Simulator instruction rate (inst/s)
+host_mem_usage 292860 # Number of bytes of host memory used
+host_op_rate 93985 # Simulator op (including micro ops) rate (op/s)
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 457698243 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 4604 # Number of instructions simulated
+sim_ops 5742 # Number of ops (including micro ops) simulated
+sim_seconds 0.000028 # Number of seconds simulated
+sim_ticks 27963000 # Number of ticks simulated
+system.clk_domain.clock 1000 # Clock period in ticks
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 21.219512 # BTB Hit Percentage
+system.cpu.branchPred.BTBHits 348 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 1640 # Number of BTB lookups
+system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
+system.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect
+system.cpu.branchPred.condPredicted 1370 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 2005 # Number of BP lookups
+system.cpu.branchPred.usedRAS 202 # Number of times the RAS was used to get a target.
+system.cpu.committedInsts 4604 # Number of instructions committed
+system.cpu.committedOps 5742 # Number of ops (including micro ops) committed
+system.cpu.cpi 12.147263 # CPI: cycles per instruction
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses::cpu.inst 1318 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1318 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60367.304348 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60367.304348 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60667.563107 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60667.563107 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits::cpu.inst 1203 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1203 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6942240 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 6942240 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.087253 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.087253 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6248759 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 6248759 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.078149 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.078149 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 103 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.179104 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.179104 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66843.023256 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66843.023256 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4600500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4600500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 24 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2874250 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2874250 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 43 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses::cpu.inst 2231 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2231 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63421.648352 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63421.648352 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62486.363014 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 62486.363014 # average overall mshr miss latency
+system.cpu.dcache.demand_hits::cpu.inst 2049 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2049 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency::cpu.inst 11542740 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 11542740 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::cpu.inst 0.081578 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.081578 # miss rate for demand accesses
+system.cpu.dcache.demand_misses::cpu.inst 182 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9123009 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 9123009 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.065442 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.065442 # mshr miss rate for demand accesses
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+system.cpu.dcache.overall_avg_miss_latency::total 63421.648352 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62486.363014 # average overall mshr miss latency
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+system.cpu.dcache.overall_miss_latency::total 11542740 # number of overall miss cycles
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+system.cpu.dcache.overall_misses::total 182 # number of overall misses
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+system.cpu.dcache.overall_mshr_miss_latency::total 9123009 # number of overall MSHR miss cycles
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+system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
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+system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
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+system.cpu.dtb.inst_hits 0 # ITB inst hits
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+system.cpu.dtb.misses 0 # DTB misses
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+system.cpu.dtb.write_misses 0 # DTB write misses
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+system.cpu.icache.ReadReq_avg_miss_latency::total 66806.250000 # average ReadReq miss latency
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64396.875000 # average ReadReq mshr miss latency
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+system.cpu.icache.ReadReq_hits::total 1987 # number of ReadReq hits
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+system.cpu.icache.ReadReq_miss_latency::total 21378000 # number of ReadReq miss cycles
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+system.cpu.icache.ReadReq_miss_rate::total 0.138708 # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_misses::total 320 # number of ReadReq misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::total 20607000 # number of ReadReq MSHR miss cycles
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+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138708 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 320 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 320 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.icache.demand_avg_miss_latency::total 66806.250000 # average overall miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::total 64396.875000 # average overall mshr miss latency
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+system.cpu.icache.demand_hits::total 1987 # number of demand (read+write) hits
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+system.cpu.icache.demand_miss_rate::total 0.138708 # miss rate for demand accesses
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+system.cpu.icache.demand_misses::total 320 # number of demand (read+write) misses
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+system.cpu.icache.demand_mshr_miss_latency::total 20607000 # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.demand_mshr_miss_rate::total 0.138708 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses::cpu.inst 320 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_avg_miss_latency::total 66806.250000 # average overall miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 64396.875000 # average overall mshr miss latency
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+system.cpu.icache.overall_miss_latency::total 21378000 # number of overall miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total 20607000 # number of overall MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_rate::total 0.138708 # mshr miss rate for overall accesses
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+system.cpu.icache.overall_mshr_misses::total 320 # number of overall MSHR misses
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+system.cpu.icache.tags.avg_refs 6.209375 # Average number of references to valid blocks.
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+system.cpu.icache.tags.sampled_refs 320 # Sample count of references to valid blocks.
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+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
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+system.cpu.itb.misses 0 # DTB misses
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+system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65831.395349 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65831.395349 # average ReadExReq miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53308.139535 # average ReadExReq mshr miss latency
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+system.cpu.l2cache.ReadExReq_miss_latency::total 2830750 # number of ReadExReq miss cycles
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+system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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+system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2292250 # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67507.124352 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55150.530504 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55150.530504 # average ReadReq mshr miss latency
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+system.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits
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+system.cpu.l2cache.ReadReq_miss_latency::total 26057750 # number of ReadReq miss cycles
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+system.cpu.l2cache.ReadReq_miss_rate::total 0.912530 # miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadReq_misses::total 386 # number of ReadReq misses
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+system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791750 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.891253 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.l2cache.demand_accesses::total 466 # number of demand (read+write) accesses
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+system.cpu.l2cache.demand_avg_miss_latency::total 67339.160839 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54961.904762 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54961.904762 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency::cpu.inst 28888500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 28888500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.920601 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.920601 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses::cpu.inst 429 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23084000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 23084000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.901288 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.901288 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses::cpu.inst 466 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 466 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67339.160839 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 67339.160839 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54961.904762 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54961.904762 # average overall mshr miss latency
+system.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits
+system.cpu.l2cache.overall_hits::total 37 # number of overall hits
+system.cpu.l2cache.overall_miss_latency::cpu.inst 28888500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 28888500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.920601 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.920601 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses::cpu.inst 429 # number of overall misses
+system.cpu.l2cache.overall_misses::total 429 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23084000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 23084000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.901288 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.901288 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
+system.cpu.l2cache.tags.avg_refs 0.098143 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.data_accesses 4148 # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.926239 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005979 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.005979 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.replacements 0 # number of replacements
+system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.tag_accesses 4148 # Number of tag accesses
+system.cpu.l2cache.tags.tagsinuse 195.926239 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 37 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.numCycles 55926 # number of cpu cycles simulated
+system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.tickCycles 10946 # Number of cycles that the CPU actually ticked
+system.cpu.toL2Bus.data_through_bus 29824 # Total data (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 640 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 932 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 233000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 545500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 234491 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.throughput 1066552230 # Throughput (bytes/s)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20480 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 29824 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq 423 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 423 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
+system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.membus.data_through_bus 26880 # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes)
+system.membus.reqLayer0.occupancy 485500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3923500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 14.0 # Layer utilization (%)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.throughput 961270250 # Throughput (bytes/s)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 377 # Transaction distribution
+system.membus.trans_dist::ReadResp 377 # Transaction distribution
+system.membus.trans_dist::ReadExReq 43 # Transaction distribution
+system.membus.trans_dist::ReadExResp 43 # Transaction distribution
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgGap 66375.00 # Average gap between requests
+system.physmem.avgMemAccLat 24369.64 # Average memory access latency per DRAM burst
+system.physmem.avgQLat 5619.64 # Average queueing delay per DRAM burst
+system.physmem.avgRdBW 961.27 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 961.27 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
+system.physmem.busUtil 7.51 # Data bus utilization in percentage
+system.physmem.busUtilRead 7.51 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
+system.physmem.bw_inst_read::cpu.inst 695776562 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 695776562 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 961270250 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 961270250 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 961270250 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 961270250 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytesPerActivate::samples 65 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 389.907692 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 267.054058 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 328.238562 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 11 16.92% 16.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17 26.15% 43.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 12 18.46% 61.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7 10.77% 72.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3 4.62% 76.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2 3.08% 80.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3 4.62% 84.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 10 15.38% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation
+system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM
+system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side
+system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
+system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
+system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
+system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory
+system.physmem.bytes_read::total 26880 # Number of bytes read from this memory
+system.physmem.memoryStateTime::IDLE 12000 # Time in different power states
+system.physmem.memoryStateTime::REF 780000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 22869500 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.num_reads::cpu.inst 420 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 420 # Number of read requests responded to by this memory
+system.physmem.pageHitRate 82.62 # Row buffer hit rate, read and write combined
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.perBankRdBursts::0 91 # Per bank write bursts
+system.physmem.perBankRdBursts::1 51 # Per bank write bursts
+system.physmem.perBankRdBursts::2 20 # Per bank write bursts
+system.physmem.perBankRdBursts::3 42 # Per bank write bursts
+system.physmem.perBankRdBursts::4 22 # Per bank write bursts
+system.physmem.perBankRdBursts::5 41 # Per bank write bursts
+system.physmem.perBankRdBursts::6 36 # Per bank write bursts
+system.physmem.perBankRdBursts::7 12 # Per bank write bursts
+system.physmem.perBankRdBursts::8 6 # Per bank write bursts
+system.physmem.perBankRdBursts::9 6 # Per bank write bursts
+system.physmem.perBankRdBursts::10 27 # Per bank write bursts
+system.physmem.perBankRdBursts::11 42 # Per bank write bursts
+system.physmem.perBankRdBursts::12 9 # Per bank write bursts
+system.physmem.perBankRdBursts::13 8 # Per bank write bursts
+system.physmem.perBankRdBursts::14 0 # Per bank write bursts
+system.physmem.perBankRdBursts::15 7 # Per bank write bursts
+system.physmem.perBankWrBursts::0 0 # Per bank write bursts
+system.physmem.perBankWrBursts::1 0 # Per bank write bursts
+system.physmem.perBankWrBursts::2 0 # Per bank write bursts
+system.physmem.perBankWrBursts::3 0 # Per bank write bursts
+system.physmem.perBankWrBursts::4 0 # Per bank write bursts
+system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::6 0 # Per bank write bursts
+system.physmem.perBankWrBursts::7 0 # Per bank write bursts
+system.physmem.perBankWrBursts::8 0 # Per bank write bursts
+system.physmem.perBankWrBursts::9 0 # Per bank write bursts
+system.physmem.perBankWrBursts::10 0 # Per bank write bursts
+system.physmem.perBankWrBursts::11 0 # Per bank write bursts
+system.physmem.perBankWrBursts::12 0 # Per bank write bursts
+system.physmem.perBankWrBursts::13 0 # Per bank write bursts
+system.physmem.perBankWrBursts::14 0 # Per bank write bursts
+system.physmem.perBankWrBursts::15 0 # Per bank write bursts
+system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 65 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 420 # Read request sizes (log2)
+system.physmem.readReqs 420 # Number of read requests accepted
+system.physmem.readRowHitRate 82.62 # Row buffer hit rate for reads
+system.physmem.readRowHits 347 # Number of row buffer hits during reads
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
+system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers
+system.physmem.totGap 27877500 # Total gap between requests
+system.physmem.totMemAccLat 10235250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2360250 # Total ticks spent queuing
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 0 # Write request sizes (log2)
+system.physmem.writeReqs 0 # Number of write requests accepted
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.voltage_domain.voltage 1 # Voltage in Volts
+
+---------- End Simulation Statistics ----------